Vishay SST441NL, U441NL Schematic [ru]

SST441NL/U441NL

New Product

Vishay Siliconix

Monolithic N-Channel JFET Duals

PRODUCT SUMMARY

V

FEATURES BENEFITS APPLICATIONS

D Anti Latchup Capability
D Monolithic Design
D High Slew Rate
D Low Offset/Drift Voltage
D Low Gate Leakage: 1 pA
D Low Noise
D High CMRR: 90 dB

(V) V

GS(off)

-1 to -6 -25 4.5 -1 20

(BR)GSS

Min (V) gfs Min (mS) IG Typ (pA) |V

GS1

- V

D External Substrate Bias—Avoids Latchup
D Tight Differential Match vs. Current
D Improved Op Amp Speed, Settling Time

Accuracy

D High-Speed Performance
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signal

|Max (mV)

GS2

D Wideband Differential Amps
D High-Speed,

Temp-Compensated,
Single-Ended Input Amps

D High Speed Comparators
D Impedance Converters

DESCRIPTION

The SST441NL is a monolithic high-speed dual JFET
mounted in a single SO-8 package. This JFET is an excellent
choice for use as wideband differential amplifiers in
demanding test and measurement applications.

Pins 4 and 8 on the SST441NL and pin 4 on the U441NL part
numbers enable the substrate to be connected to a positive,
external bias (V

SUBSTRATE S

) to avoid latchup.

DD

Narrow Body SOIC

S

1

1

D

2

1

G

3

1

4

Marking Codes:

SST441NL - 441NL

Top View

8
7
6
5

SUBSTRATE
G

2

D

2

2

ABSOLUTE MAXIMUM RATINGS

Gate-Drain, Gate-Source Voltage -25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate Current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead Temperature (

Storage Temperature -55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Junction Temperature -55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .

1

/16” from case for 10 sec.) 300_C. . . . . . . . . . . . . . . . . . .

The U441NL in the hermetically sealed TO-78 package is
available with full military processing.

The SO-8 package provides ease of manufacturing. The
symmetrical pinout prevents improper orientation. The SO-8
package is available with tape-and-reel options for
compatibility with automatic assembly methods.

TO-78

S

1

1

D

1

2

3

G

1

Power Dissipation : Per Side

Notes
a. Derate 2.4 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C

4

CASE, SUBSTRATE

Top View

U441NL

Total

G

2

7

D

2

6

5

S

2

a

b

300 mW. . . . . . . . . . . . . . . . . . . . . . . .

500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .

For applications information see AN102.

Document Number: 72056
S-22526–Rev. A, 17-Feb-03

www.vishay.com

7-1

SST441NL/U441NL

S

V

DS

= 10 V, ID = 5 mA

S

VDS = 10 V, ID = 5 mA

S

VDS = 10 V, ID = 5 mA

Vishay Siliconix

New Product

SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)

Limits

Parameter Symbol

Test Conditions

Min Typ

Static

Gate-Source Breakdown Voltage V
Gate-Source Cutoff Voltage V
Saturation Drain Current

Gate Reverse Current I

Gate Operating Current I

Gate-Source Forward Voltage V

b

(BR)GSS

GS(off)

I

DSS

GSS

G

GS(F)

IG = -1 mA, VDS = 0 V
VDS = 10 V, ID = 1 nA -1 -3.5 -6

VDS = 10 V, VGS = 0 V 6 15 30 mA

VGS = -15 V, VDS = 0 V -1 -500 pA

TA = 125_C

VDG = 10 V, ID = 5 mA -1 -500 pA

TA = 125_C

IG = 1 mA , VDS = 0 V 0.7 V

-25 -35

Dynamic

Common-Source
Forward Transconductance

Common-Source
Output Conductance

Common-Source
Forward Transconductance

Common-Source
Output Conductance

Common-Source
Input Capacitance

Common-Source
Reverse Transfer Capacitance

Equivalent Input Noise Voltage e

g

fs

g

os

g

fs

g

os

C

iss

C

rss

n

V

= 10 V, I

D

V

= 10 V, ID = 5 mA

D

V

= 10 V, ID = 5 mA

D

VDS = 10 V, ID = 5 mA

= 5 mA

D

f = 1 kHz

f = 100 MHz

f = 1 MHz

f = 10 kHz

4.5 6 9 mS

Matching

Differential Gate-Source Voltage

Gate-Source Voltage Differential
Change with Temperature

Saturation Drain Current Ratio

Transconductance Ratio

Common Mode Rejection Ratio CMRR VDG = 10 to 15 V, ID = 5 mA 90 dB

Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NNZ
b. Pulse test: PW v300 ms duty cycle v3%.
c. Assumes smaller value in the numerator.

c

c

|

V

GS1–VGS2

|

D

V

GS1–VGS2

DT

I

DSS1

I

DSS2

g
g

fs1
fs2

|

|

VDG = 10 V, ID = 5 mA 7 20 mV

VDG = 10 V, ID = 5 mA

T

= -55 to 125_C

A

VDS = 10 V, VGS = 0 V 0.98

VDS = 10 V, ID = 5 mA

f = 1 kHz

a

Max Unit

-0.2 nA

-0.2 nA

20 200

5.5 mS

30

3.5

1

4

10

0.98

√Hz

mV/_C

V

mS

mS

pF

nV⁄

www.vishay.com

7-2

Document Number: 72056

S-22526–Rev. A, 17-Feb-03