Vishay SST3958NL, U3958NL Schematic [ru]

SST3958NL/U3958NL

New Product

Vishay Siliconix

Monolithic N-Channel JFET Dual

PRODUCT SUMMARY

V

FEATURES BENEFITS APPLICATIONS

D Anti Latchup Capability
D Monolithic Design
D High Slew Rate
D Low Offset/Drift Voltage
D Low Gate Leakage: 5 pA
D Low Noise: 9
D High CMRR: 100 dB

(V) V

GS(off)

-1.0 to -4.5 -50 1 -50 25

(BR)GSS

Min (V) gfs Min (mS) IG Max (pA) jV

GS1

- V

GS2

D External Substrate Bias—Avoids Latchup
D Tight Differential Match vs. Current
D Improved Op Amp Speed, Settling Time

Accuracy

D Minimum Input Error/Trimming Requirement

nV⁄√Hz

D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signal

j Max (mV)

D Wideband Differential Amps
D High-Speed,

Temp-Compensated,
Single-Ended Input Amps

D High Speed Comparators
D Impedance Converters

DESCRIPTION

The low cost SST3958NL and U3958NL JFET duals are
designed for high-performance differential amplification for a
wide range of precision test instrumentation applications. This
series features tightly matched specs, low gate leakage for
accuracy, and wide dynamic range with IG guaranteed at
VDG = 20 V.

Pins 4 and 8 on the SST3958NL and pin 4 on the U3958NL part
numbers enable the substrate to be connected to a positive,
external bias (V

SUBSTRATE S

) to avoid latchup.

DD

Narrow Body SOIC

S

1

1

D

2

1

G

3

1

4

Top View

Marking Codes:

SST3958NL - 3958NL

8
7
6
5

SUBSTRATE
G

2

D

2

2

The U3958NL in the hermetically-sealed TO-78 package is
available with full military processing.

The SST3958NL in the SO-8 package provides ease of
manufacturing. The symmetrical pinout prevents improper
orientation. The SST3958NL is available with tape-and-reel
options for compatibility with automatic assembly methods.

TO-78

TO-78

S

S

1

1

1

1

D

D

1

1

2

2

3

3

G

G

1

1

4

4

CASE, SUBSTRATE

CASE, SUBSTRATE

Top View
U3958NL

G

G

2

2

7

7

D

D

2

2

6

6

5

5

S

S

2

2

ABSOLUTE MAXIMUM RATINGS

Gate-Drain, Gate-Source Voltage -50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate Current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead Temperature (1/16” from case for 10 sec.) 300 _C. . . . . . . . . . . . . . . . . .

Storage Temperature -65 to 200_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Junction Temperature -55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .

Document Number: 72157
S-22527—Rev. A, 17-Feb-03

Power Dissipation : Per Side

Notes
a. Derate 2 mW/_C above 85_C
b. Derate 4 mW/_C above 85_C

Total

b

a

250 mW. . . . . . . . . . . . . . . . . . . . . . . .

500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .

www.vishay.com

7-1

SST3958NL/U3958NL

V

f = 1 kH

S

VDS = 20 V, ID = 200 mA

Vishay Siliconix

New Product

SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)

Parameter Symbol Test Conditions Min Typ

Static

Gate-Source Breakdown Voltage V
Gate-Source Cutoff Voltage V
Saturation Drain Current

Gate Reverse Current I

Gate Operating Current I

Gate-Source Voltage V

Gate-Source Forward Voltage V

b

(BR)GSS

GS(off)

I

DSS

GSS

GS(F)

Dynamic

Common-Source
Forward Transconductance

Common-Source Output Conductance g
Common-Source Input Capacitance C
Common-Source

Reverse Transfer Capacitance
Drain-Gate Capacitance C

Equivalent Input Noise Voltage e

Noise Figure NF

g

C

Matching

G

GS

fs

os
iss

rss

dg

n

IG = -1 mA, VDS = 0 V
VDS = 20 V, ID = 1 nA -1.0 -3 -4.5

VDS = 20 V, VGS = 0 V 0.5 5 8 mA

VGS = -30 V, VDS = 0 V -10 -100 pA

VDG = 20 V, ID = 200 mA

VDG = 20 V, ID = 200 mA

IG = 1 mA, VDS = 0 V 2

VDS = 20 V, VGS = 0 V

VDS = 20 V, VGS = 0 V

VDG = 10 V, IS = 0 , f = 1 MHz 1.5

VDS = 20 V, VGS = 0 V, f = 1 kHz 11

VDS = 20 V, VGS = 0 V

f = 100 Hz, R

f = 1 MHz

G

z

= 10 MW

TA = 150_C

TA =125_C

ID = 50 mA

Limits

a

Max Unit

-50 -57

-20 -500 nA

-5 -50 pA

-0.8 -250 nA

-0.5 -2.5 -4

-4.2

1 3.0 3.6 mS

8 35
3 4

1 1.2

0.5 dB

V

mS

pF

nV⁄

√Hz

Differential Gate-Source Voltage

Gate-Source Voltage Differential Change with
Temperature

Saturation Drain Current Ratio

Transconductance Ratio

Differential Output Conductance

Differential Gate Current

Common Mode Rejection Ratio CMRR

Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NQP
b. Pulse test: PW v300 ms duty cycle v3%.

www.vishay.com

7-2

|

V

GS1–VGS2

|

D

V

GS1–VGS2

|

g

os1–gos2

|

I

G1–IG2

DT

I

DSS1

I

DSS2

g
g

fs1
fs2

|

|

|

|

VDG = 20 V, ID = 200 mA

VDG = 20 V, ID = 200 mA

T

= -55 to 125_C

A

VDS = 20 V, VGS = 0 V 0.85 0.97 1

0.85 0.97 1

V

= 20 V, ID = 200 mA

D

f = 1 kHz

VDG = 20 V, ID = 200 mA

T

= 125_C

A

VDG = 10 to 20 V, ID = 200 mA

15 25 mV

20 100

0.1

0.1 10 nA

100 dB

Document Number: 72157

S-22527—Rev. A, 17-Feb-03

mV/_C

mS