VISHAY TFDU8108 Technical data

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TFDU8108

Vishay Semiconductors

Very Fast Infrared Transceiver Module (VFIR, 16 Mbit/s), Serial
Interface Compatible, 2.7 V to 5.5 V Supply Voltage Range

Description

The TFDU8108 transceiver is part of a family of low­power consumption infrared transceiver modules
compliant to the IrDA physical layer standard for VFIR
infrared data communication, supporting IrDA speeds
up to 16 Mbit/s (VFIR) and carrier based remote con­trol modes up to 2 MHz. Integrated within the trans­ceiver module are a PIN photodiode, an infrared
emitter (IRED), and a low-power BiCMOS control IC
to provide a total front-end solution in a single pack­age.

Vishay Semiconductors VFIR transceivers are avail­able in the BabyFace package. This provides flexibil­ity for a variety of applications and space constraints.
The transceivers are capable of directly interfacing
with a wide variety of I/O devices, which perform the
modulation/ demodulation function. At a minimum, a
V

bypass capacitor is the only external component

CC

required implementing a complete solution. For limit­ing the transceiver internal power dissipation one
additional resistor might be necessary. The trans­ceiver can be operated with logic I/O voltages as low
as 1.5 V. The functionality of the device is equivalent
to the TFDU6108 with the VFIR functionality added.
The IRED current is programmable to different levels,
no external current limiting resistor is necessary.

Features

• Compliant to the latest IrDA physical layer stan­dard (Up to 16 Mbit/s) and TV Remote Control

• Compliant to the IrDA "Serial Interface
Specification for Transceivers"

• For 3.0 V and 5.0 V Applications, fully specified

2.7 V to 5.5 V

• Compliant to all logic levels between 1.5 V and 5 V

• Low Power Consumption
(typ. 2.0 mA Supply Current)

• Power Shutdown Mode

(< 1 µA Shutdown Current)

• Surface Mount Package Options

- Universal (L 9.7 mm × W 4.7 mm × H 4.0 mm)

- Side and Top View

• Tri-State-Receiver Output, Weak Pull-up when in
Shutdown Mode

• High Efficiency Emitter

• Baby Face (Universal) Package Capable of
Surface Mount Soldering to Side and Top
View Orientation

• Eye safety class 1 (IEC60825-1, ed. 2001), limited
LED on-time, LED current is controlled, no single
fault to be considered

• Built - In EMI Protection including GSM bands. ­EMI Immunity in GSM Bands > 300 V/m verified
No External Shielding Necessary

• Few External Components Required

• Pin to Pin Compatible to Legacy Vishay Semicon­ductors SIR and FIR Infrared Transceivers

• Split power supply, transmitter and receiver can be
operated from two power supplies with relaxed
requirements saving costs,
US Patent No. 6,157,476

• Compliant with IrDA EMI and Background Light
Specification

• TV Remote Control Support

• Lead (Pb)-free device

• Device in accordance to RoHS 2002/95/EC and
WEEE 2002/96/EC

Document Number 82558

Rev. 1.6, 12-Aug-04

www.vishay.com

1

TFDU8108

Vishay Semiconductors

Applications

• Notebook Computers, Desktop PCs, Palmtop
Computers (Win CE, Palm PC), PDAs

• Printers, Fax Machines, Photocopiers,
Screen Projectors

• Telecommunication Products
(Cellular Phones, Pagers)

• Internet TV Boxes, Video Conferencing Systems

• External Infrared Adapters (Dongles)

• Medical and Industrial Data Collection Devices

• Digital Still and Video Cameras

• MP3 Players

Parts Table

Part Description Qty / Reel

TFDU8108-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs

TFDU8108-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs

Functional Block Diagram

V

logic

Driver

Current controlled
driver

200

Rxd

Ω

IRED Anode
V

IRED Cathode

CC2

17086

SCLK

Txd

Amplifier

AGC
Logic

V

CC1

Comparator

GND

Pin Description

Pin Number Function Description I/O Active

1 IRED Anode Connect IRED anode directly to V

power supply separated can be used at this pin.

2 IRED Cathode IRED cathode, internally connected to driver transistor

3 Txd Transmit Data Input, dynamically loaded I HIGH

4 Rxd Received Data Output, push-pull CMOS driver output capable of

driving a standard CMOS or TTL load. No external pull-up or pull-

down resistor is required. Pin is current limited for protection against
programming errors. The output is loaded with a weak 500 kΩ pull-

up when in SD mode

5 SCLK Serial Clock, dynamically loaded I HIGH

. An unregulated separate

CC2

OLOW

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Document Number 82558

Rev. 1.6, 12-Aug-04

TFDU8108

Vishay Semiconductors

Pin Number Function Description I/O Active

6V

7V

8 GND Ground

CC

logic

Supply voltage for digital part, 1.5 V to 5.5 V, defines logic swing for

Supply Voltage

Txd, SCLK, and Rxd

Pinout

TFDU8108
weight 200 mg

17087

"U" Option BabyFace

(Universal)

IRED Detector

12345678

Definitions:

In the Vishay transceiver data sheets the following nomenclature is

used for defining the IrDA operating modes:

SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared

standard with the physical layer version IrPhy 1.0

MIR 576 kbit/s to 1152 kbit/s

FIR 4 Mbit/s

VFIR 16 Mbit/s

MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy

1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the

Low Power Option to MIR and FIR and VFIR was added with IrPhy

1.4. A new version of the standard in any case obsoletes the former

version.

Remark:

Throughout the documentation the not correct term LED (Light

Emitting Diode) is used for Infrared Emitting Diode (IRED). We are

following the trend to use the term light for infrared radiation, which

is wrong but common usage.

Document Number 82558

Rev. 1.6, 12-Aug-04

www.vishay.com

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TFDU8108

Vishay Semiconductors

Absolute Maximum Ratings

Reference point Ground (pin 8) unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Typ . Max Unit

Supply voltage range,
transceiver

Supply voltage range,
transmitter

Supply voltage range,
transceiver logic

Input currents for all pins, except IRED anode

Output sinking current 25 mA

Junction temperature T

Power dissipation see derating curve, figure 4 P

Ambient temperature range
(operating)

Storage temperature range T

Soldering temperature see recommended solder profile

Average output current I

Repetitive pulse output current < 90 µs, t

IRED anode voltage V

Transmitter data input voltage V

Receiver data output voltage V

Virtual source size Method: (1 - 1/e) encircled

Maximum Intensity for Class 1
Operation of IEC825-1 or
EN60825-1, edition Jan. 2001*)

IrDA specified maximum limit 500 mW/sr

Due to the internal measures the device is a "class1" device. It will not exceed the IrDA intensity limit of 500 mW/sr.

*)

With the amendment 2 of IEC 60825 - 1 this value

0 V < V

0 V < V

0 V < V

< 6 V V

CC2

< 6 V V

CC1

< 6 V V

CC1

pin

(see figure 3)

< 20 % I

on

energy

unidirectional operation, worst
case IrDA FIR pulse pattern

CC1

CC2

logic

- 0.5 + 6 V

- 0.5 + 6 V

- 0.5 + 6 V

10 mA

J

D

T

amb

stg

- 25 + 85 °C

- 40 + 100 °C

125 °C

350 mW

240 °C

(DC) 130 mA

IRED

(RP) 600 mA

IRED

IREDA

Txd

Rxd

- 0.5 + 6 V

- 0.5 V

- 0.5 V

+ 0.5 V

logic

+ 0.5 V

logic

d2.52.8 mm

Internally
limited to

class 1

www.vishay.com

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Document Number 82558

Rev. 1.6, 12-Aug-04

TFDU8108

Vishay Semiconductors

Electrical Characteristics

Transceiver

T

= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.

amb

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Typ . Max Unit

Supply voltage V

Dynamic supply current

1)

T = - 25 °C to 85 °C
active, no signal E

= 0 klx

e

T = - 25 °C to 85 °C
active, no signal E

= 0 klx, SIR

e

V

I

CC1

I

CC1

CC1

logic

only

T = - 25 °C to 85 °C idle

I

logic

active, no load Ee = 0 klx

T = - 25 °C to 85 °C

I

logic

Ee = 1 klx2) receive mode,

E

= 100 mW/m2

Eo

(9.6 kbit/s to 4.0 Mbit/s),

= 10 kΩ to V

R

L

C

= 15 pF

L

Shutdown supply current inactive, set to shutdown mode

T = 25 °C, E

inactive, set to shutdown mode

T = 25 °C, Ee = 1 klx

shutdown mode, T = 85 °C,

logic

= 0 klx

e

= 5 V,

2)

I

SD

I

SD

I

SD

not ambient light sensitive

Operating temperature range T

Output voltage low C

Output voltage high C

Input voltage low (Txd, SCLK)

Input voltage high (Txd, SCLK)

= 15 pF, V

load

= 15 pF, V

load

CMOS level

CMOS level

= 5 V V

logic

= 5 V V

logic

3)

3)

Input leakage current (Txd,

A

OL

OH

V

IL

V

IH

I

L

SCLK)

Input capacitance C

1)

Receive mode only. In transmit mode, add the averaged programmed current of IRED current as I

2)

Standard Illuminant A

3)

The typical threshold level is between 0.5 x V

logic

/2 (V

logic

= 3 V) and 0.4 x V

IN

tight levels than the specified min/ max values. However, it is recommended to use the specified min/max values to avoid increased oper­ating/standby supply currents.

2.7 5.5 V

1.5 5.5 V

3.0 10 mA

1.6 2.5 mA

- 25 + 85 °C

0.5 0.8 V

V

- 0.5 V

logic

0.15 x V

0.9 x V

logic

- 10 + 10 µA

CC2

(V

logic

= 5.5 V).With that the device will work with less

logic

5 µA

1mA

1 µA

1.5 µA

5 µA

logic

V

V

5pF

Document Number 82558

Rev. 1.6, 12-Aug-04

www.vishay.com

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TFDU8108

Vishay Semiconductors

Optoelectronic Characteristics

Receiver

T

= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.

amb

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Typ . Max Unit

Minimum detection threshold
irradiance, SIR mode

Minimum detection threshold
irradiance, MIR mode

Minimum detection threshold
irradiance, FIR mode

Minimum detection threshold
irradiance, VFIR mode

Maximum detection threshold
irradiance

Logic LOW receiver input
irradiance

Rise time of output signal 10 % to 90 %, 15 pF t

Fall time of output signal 90 % to 10 %, 15 pF t

Rxd pulse width of output signal,
50 % SIR mode

Jitter, leading edge, SIR mode

Rxd pulse width of output signal,
50 % FIR mode

Jitter, leading edge, FIR mode

Rxd pulse width of output signal,
50 %

Jitter, leading edge

Latency t

9.6 kbit/s to 115.2 kbit/s
λ = 850 nm to 900 nm

1.152 Mbit/s
λ = 850 nm to 900 nm

4 Mbit/s
λ = 850 nm to 900 nm

16 Mbit/s
λ = 850 nm to 900 nm

λ = 850 nm to 900 nm E

optical ambient noise
suppression up to this level for
e.g. fluorescent light tolerance

equivalent to the IrDA

®

"Background Light and
Electromagnetic Field"
specification

r (Rxd)

f (Rxd)

input pulse length 20 µs,

9.6 kbit/s

input pulse length 1.41 µs,

115.2 kbit/s

input irradiance = 100 mW/m

2

,

115.2 kbit/s

input pulse length 125 ns,

4.0 Mbit/s

input pulse length 250 ns,

4.0 Mbit/s

2

input irradiance = 100 mW/m

,

4 Mbit/s

input pulse length 16 Mbit/s,
VFIR

39.5 ns < P

input irradiance = 100 mW/m

wopt

< 43 ns

2

,

16 Mbit/s, VFIR mode

t

t

t

t

t

E

E

E

E

E

PW

PW

PW

PW

PW

e

e

e

e

e

e

510

4

1.2 2 3 µs

1.2 3 µs

115 125 135 ns

230 270 ns

34 42 50 ns

L

25 40

conditionally supported

85 90

100

57ns

mW/m

mW/m

mW/m

mW/m

kW/m

mW/m

15 ns

15 ns

350 ns

20 ns

100 µs

2

2

2

2

2

2

www.vishay.com

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Document Number 82558

Rev. 1.6, 12-Aug-04

TFDU8108

Vishay Semiconductors

Transmitter

T

= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.

amb

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Typ . Max Unit

IRED operating current
internally controlled,
programmable using the "serial
interface" programming
sequence, see Appendix

Max. output radiant intensity V

Output radiant intensity V

Output radiant intensity, angle of
half intensity

Peak - emission wavelength λ

Spectral bandwidth ∆λ 40 nm

Optical rise time, fall time t

Optical overshoot 15 %

= 3.3 V, the maximum

V

CC1

current is limited internally. An
external resistor can be used to
reduce the power dissipation at
higher operating voltages, see
derating curve.

= 3.3 V, α = 0 °,

CC1

15 ° Txd = High, R1 = 0 Ω
programmed to max. power
level

= 5.0 V, α = 0 °,

CC1

15 ° Txd = Low, programmed to
shutdown mode

I

D

I

e

I

e

α ± 24 °

880 900 nm

10 40 ns

ropt

p

, t

fopt

8
15
30
60

110
220
500 600

0.3 mW/sr/mA

0.04 mW/sr

mA

Document Number 82558

Rev. 1.6, 12-Aug-04

www.vishay.com

7

TFDU8108

Vishay Semiconductors

Recommended Circuit Diagram

Operated with a low impedance power supply the
TFDU8108 needs no external components. However,
depending on the entire system design and board lay­out, additional components may be required (see fig­ure 1).

V

CC2

V

CC1

Rxd

GND

V

logic

SCLK

Txd

Vishay Semiconductors transceivers integrate a sen­sitive receiver and a built-in power driver. The combi­nation of both needs a careful circuit board layout.
The use of thin, long, resistive and inductive wiring
should be avoided. The inputs (Txd, SCLK) and the
output Rxd should be directly (DC) coupled to the I/O
circuit.

R1 is used for controlling the maximum current
through the IR emitter. This one is necessary when
operating over the full range of operating temperature
and V

CC1

max. output power of the IRED, the value of the resis­tor should be reduced. It should be dimensioned to
keep the IRED anode voltage below 4 V for using the
full temperature range. For device and eye protection
the pulse duration and current are internally limited.

R2, C1 and C2 are optional and dependent on the
quality of the supply voltage V
An unstable power supply with dropping voltage dur­ing transmission may reduce sensitivity (and trans­mission range) of the transceiver.

The placement of these parts is critical. It is strongly
recommended to position C2 close to the transceiver
power supply pins. An electrolytic capacitor should be
used for C1 while a ceramic capacitor is used for C2.

R1

IRED

R2

Figure 1. Recommended Application Circuit

All external components (R, C) are optional

Cathode

Rxd

Vcc

C2C1

GND

IRED

Anode

Txd

SCLK

V

logic

17089

- voltages above 4 V. For increasing the

and injected noise.

CC1

Recommended Application Circuit Com­ponents

Component Recommended Value

C1 4.7 µF, 16 V

C2 0.1 µF, Ceramic, 16 V

R1 Recommended for V

Depending on current limit

R2 4.7 Ω, 0.125 W

CC1

≥ 4 V

I/O and Software

For operating the device from a Controller I/O a driver
software must be implemented.

Mode Switching

The generic IrDA "Serial Interface programming"
needs no special settings for the device. Only the cur­rent control table must be taken into account. For the
description see the Appendix and the IrDA "Serial
Interface specification for transceivers"

www.vishay.com

8

Document Number 82558

Rev. 1.6, 12-Aug-04

TFDU8108

Vishay Semiconductors

Recommended Solder Profile

Solder Profile for Sn/Pb soldering

240

220

14874

200

180

160

140

120

100

80

60

Temperature (°C)

40

20

0

2°C-4°C/s

0 50 100 150 200 250 300 350

Figure 2. Recommended Solder Profile

280

260

240

220

200

180

160

140

120

Temperature/° C

100

80

60

40

20

0

0 50 100 150 200 250 300 350

2°C-4°C/s

90 s max120 s - 180 s

Time(s)

T = 250°C for 10 s....40 s

T = 217°C for 70 s max

2°C...3°C/s

10 s max.

@ 230 °C

90 s...120 s

Lead-Free, Recommended Solder Profile

This device is a lead-free transceiver and qualified for
lead-free processing. For lead-free solder paste like
Sn

(3.0 - 4.0)Ag(0.5 - 0.9)

reflow profiles: Ramp-Soak-Spike (RSS) and Ramp­To-Spike (RTS). The Ramp-Soak-Spike profile was
developed primarily for reflow ovens heated by infra­red radiation. With widespread use of forced convec­tion reflow ovens the Ramp-To-Spike profile is used
increasingly. Shown below in figure 3 and figure 4 are
Vishay’s recommended profile for use with this trans­ceiver type. For more details please refer to Applica­tion note: SMD Assembly Instruction

40 s max.

70 s max.

Time/s

Cu, there are two standard

.

T

= 260°C max.

peak

2°C...4°C/s

Document Number 82558

Rev. 1.6, 12-Aug-04

Figure 3. Solder Profile, RSS Recommendation

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