VISHAY TFDU6102E, TFDS6402, TFDS6502E, TFDT6502E Technical data

查询TFDS6402供应商
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Fast Infrared Transceiver Module Family (FIR, 4 Mbit/s) for 2.6 V to 5.5 V Operation
Description
Vishay Telefunken’s FIR transceivers are available in four package options, including our Baby Face package (TFDU610xE), the standard setting, once
smallest FIR transceiver available on the market. This wide selection provides flexibility for a variety of applications and space constraints. The transceivers are capable of directly interfacing with a wide variety of I/O devices which perform the modulation/ demodulation function, including National Semiconductor’s PC87338, PC87108 and PC87109, SMC’s FDC37C669, FDC37N769 and CAM35C44, and Hitachi’s SH3. At a minimum, a current–limiting resistor in series with the infrared emitter and a VCC bypass capacitor are the only external components required implementing a complete solution.
Vishay Semiconductor
Features
Compliant to the IrDA physical layer specification
(Up to 4 Mbit/s), HP–SIR, Sharp ASK and TV Remote Control
For 3.0 V and 5.0 V ApplicationsOperates from 2.6 V to 5.5 V within specification,
operational down to 2.4 V
Low Power Consumption (3 mA Supply Current)Power Shutdown Mode (1 A Shutdown Current)Four Surface Mount Package Options
Universal (9.7 × 4.7 × 4.0 mm) – Side View (13.0 × 5.95 × 5.3 mm) – Top View (13.0 × 7.6 × 5.95 mm) – Dracula (11.2 × 5.6 × 2.2 mm)
Push-Pull-Receiver Output, grounded in
shutdown mode
Applications
Notebook Computers, Desktop PCs,
Palmtop Computers (Win CE, Palm PC), PDAs
Digital Still and Video CamerasPrinters, Fax Machines, Photocopiers,
Screen Projectors
High Efficiency EmitterBaby Face (Universal) Package Capable of
Surface Mount Soldering to Side and Top View Orientation
Directly Interfaces with Various Super I/O and
Controller Devices
Built–In EMI Protection – No External Shielding
Necessary
Few External Components RequiredBackward Pin to Pin Compatible to all Vishay
Telefunken SIR and FIR Infrared Transceivers
Split power supply , transmitter and receiver can be
operated from two power supplies with relaxed requirements, thus saving costs
Telecommunication Products
(Cellular Phones, Pagers)
Internet TV Boxes, Video Conferencing SystemsExternal Infrared Adapters (Dongles)Medical and Industrial Data Collection Devices
Document Number 82526 Rev. B1.6, 02–Nov–00 1
www.vishay.com
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Package Options
TFDU6102E
Baby Face (Universal)
weight 0.20 g
TFDS6402
Dracula Side View
weight 0.30 g
TFDS6502E
Side View
weight 0.39 g
TFDT6502E
Top View
weight 0.39 g
Ordering Information
Part Number Qty / Reel Description TFDU6102E–TR3 1000 pcs Oriented in carrier tape for side view surface mounting TFDU6102E–TT3 1000 pcs Oriented in carrier tape for top view surface mounting TFDS6402–TR3 1000 pcs Side View TFDS6502E–TR3 750 pcs Side View TFDT6502E–TR3 750 pcs Top View
Functional Block Diagram
Amplifier
SD/Mode
Txd
AGC Logic
Open Drain Driver
V
CC
Comparator
GND
Figure 1. Functional Block Diagram
Driver
Rxd
IRED Anode
IRED Cathode
www.vishay.com Document Number 82526
Rev. B1.6, 02–Nov–002
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Function
Descri tion
I/O
Active
Pin Description
Pin Number Function Description I/O Active
“U” and “T” Option “S” Option
1 8 IRED Anode IRED anode, to be externally connected
2 1 IRED Cathode IRED cathode, internally connected to
3 7 Txd Transmit Data Input I HIGH 4 2 Rxd Received Data Output, push-pull CMOS
5 6 SD/Mode Shutdown/ Mode I HIGH 6 3 V 7 5 Mode HIGH: High speed mode;
8 4 GND Ground
CC
Vishay Semiconductor
to V
through a current control resistor.
CC
This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled V
driver transistor
driver output capable of driving a stan­dard CMOS or TTL load. No external pull-up or pull-down resistor is required.
Pin is floating when device is in shutdown mode
Supply Voltage
LOW: Low speed mode, SIR only (see chapter “Mode Switching”)
supply
CC
O LOW
I
“U” Option Baby Face (Universal)
and Dracula
IRED Detector
14885
“S” Option Side View “T” Option Top View
IRED Detector
IRED Detector
Figure 2. Pinnings
Document Number 82526 Rev. B1.6, 02–Nov–00 3
www.vishay.com
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Absolute Maximum Ratings
Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters Test Conditions Symbol Min. Typ. Max. Unit
Supply Voltage Range, Transceiver
Supply Voltage Range, Transmitter
Input Currents For all Pins, Except IRED
Output Sinking Current 25 mA Power Dissipation See Derating Curve P Junction Temperature T Ambient Temperature
Range (Operating) Storage Temperature
Range Soldering Temperature See Recommended Solder
Average Output Current I Repetitive Pulsed Output
Current IRED Anode Voltage V Transmitter Data Input
Voltage Receiver Data Output
Voltage Virtual Source Size Method:
Maximum Intensity for Class 1 Operation of IEC825–1 or EN60825–1 (worst case IrDA FIR pulse pattern)
0 V <V
0 V <V
<6 V V
CC2
<6 V V
CC1
Anode Pin
Profile (see Figure 11)
<90 µs, ton <20% I
(1–1/e) encircled energy EN60825, 1997,
unidirectional operation, worst case test mode
CC1
CC2
– 0.5 6 V
– 0.5 6 V
10 mA
350 mW 125 °C
T
amb
T
stg
D
J
–25 +85 °C
–25 +85 °C
240 °C
(DC) 130 mA
IRED
(RP) 600 mA
IRED
IREDA
V
Txd
V
Rxd
– 0.5 6 V – 0.5 V
– 0.5 V
+0.5 V
CC1
+0.5 V
CC1
d 2.5 2.8 mm
320 mW/sr
www.vishay.com Document Number 82526
Rev. B1.6, 02–Nov–004
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Mode Floating, In ut Voltage High
Vishay Semiconductor
Electrical Characteristics
T
= 25_C, VCC = 2.6V to 5.5 V unless otherwise noted.
amb
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit
Transceiver
Supply Voltage V Dynamic Supply Current Receive mode only.
In transmit mode, add additional 85 mA (typ) for IRED current SD = Low, Ee = 0 klx I SD = Low, Ee = 1 klx *) I
Standby Supply Current SD = High,
Mode = Floating,
I
T = 25°C, Ee = 0 klx T = 25°C, Ee = 1 klx *)
SD = High, T = 85°C,
I Mode = Floating, Not Ambient Light Sensitive
Operating Temperature
T
Range Output Voltage Low R
Output Voltage High R
Input Voltage Low
load
C
load load
C
load
= 2.2 kW, = 15 pF
= 2.2 kW, = 15 pF
V
V
V
(Txd, SD/ Mode, Mode) Input Voltage High CMOS level **) V
(Txd, SD/ Mode, Mode)
TTL level, VCC 4.5 V V
Input Leakage Current (Txd, SD/ Mode)
Input Leakage Current, Mode
Input Capacitance C
CC
CC CC SD
SD
OL
OH
I
I
A
IL
IH IH L
L
I
2.6 5.5 V
3 4.5 mA 3 4.5 mA
–25 +85 °C
0.5 0.8 V
VCC–0.5 V
0 0.8 V
0.9 x V
CC
2.4 V
–10 +10 µA
–80 +80 µA
1
1.5 5 µA
5 pF
µA µA
V
*) Standard Illuminant A **) The typical threshold level is between 0.5 x V
Document Number 82526 Rev. B1.6, 02–Nov–00 5
(VCC = 3 V) and 0.4 x VCC (VCC = 5.5 V) .
CC/2
It is recommended to use the specified min/ max values to avoid increased operating current.
www.vishay.com
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
SIR Mode
MIR Mode
FIR Mode Rxd Pulse Width of
O
50%
Vishay Semiconductor
Optoelectronic Characteristics
T
= 25_C, VCC = 2.6 V to 5.5 V unless otherwise noted.
amb
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters Test Conditions Symbol Min. Typ. Max. Unit
Receiver
Minimum Detection Threshold Irradiance, SIR Mode
Minimum Detection Threshold Irradiance, MIR Mode
Minimum Detection Threshold Irradiance, FIR Mode
Maximum Detection Threshold Irradiance
Logic LOW Receiver Input Irradiance
Rise Time of Output Signal––,,,,klll
Fall Time of Output Signal
Rxd Pulse Width of Input pulse length 20 µs, 9.6 kbit/s t Output Signal, 50% SIR Mode
Rxd Pulse Width of Output Signal, 50% MIR Mode
Rxd Pulse Width ofpInput pulse length 125 ns, 4.0 Mbit/s t
utput Signal,
FIR Mode Stochastic Jitter,
Leading Edge, FIR Mode
Latency t
TFDS6502E/ TFDT6502E
9.6 kbit/s to 115.2 kbit/s l = 850 nm to 900 nm
TFDU6102E, TFDS6402
9.6 kbit/s to 115.2 kbit/s l = 850 nm to 900 nm
TFDS6502E/ TFDT6502E
1.152 Mbit/s l = 850 nm to 900 nm
TFDU6102E, TFDS6402
1.152 Mbit/s l = 850 nm to 900 nm
TFDS6502E/ TFDT6502E
4.0 Mbit/s l = 850 nm to 900 nm
TFDU6102E, TFDS6402
4.0 Mbit/s
l = 850 nm to 900 nm l = 850 nm to 900 nm E
10% to 90%, @2.2 k, 15 pF t
90% to 10%, @2.2 k, 15 pF t
Input pulse length 1.41 ms,
r (Rxd)
f (Rxd)
t
115.2 kbit/s Input pulse length 217 ns,
t
1.152 Mbit/s
Input pulse length 250 ns, 4.0 Mbit/s t Input Irradiance = 100 mW/m2,
4.0 Mbit/s
E
E
E
E
E
E
E
PW PW
PW
PW PW
e
e
e
e
e
e
e
e
5 10 kW/m
4 mW/m
20 35 mW/m
25 40 mW/m
50 mW/m
65 mW/m
65 100 mW/m
85 100 mW/m
10 40 ns
10 40 ns
1.2 10 20 µs
1.2 1/2 bit length
110 260 ns
100 160 ns 200 290 ns
±10 ns
L
120 300 µs
2
2
2
2
2
2
2
2
µs
www.vishay.com Document Number 82526
Rev. B1.6, 02–Nov–006
Loading...
+ 11 hidden pages