VISHAY TFDU5037 Technical data

TFDU5307
Vishay Semiconductors
Fast Low Profile (2.5 mm) Infrared Transceiver Module (MIR, 1.152 Mbit/s) for IrDA
Description
The TFDU5307 is an infrared transceiver module compliant to the latest IrDA physical layer standard, supporting IrDA speeds up to 1.152 Mbit/s (MIR) and carrier based remote control modes up to 2 MHz. Inte­grated within the transceiver module are a PIN photo­diode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a sin­gle package.
This Vishay MIR transceiver is built in a low profile package using the experiences of the lead frame babyface technology. The transceivers are capable of directly interfacing with a wide variety of I/O devices, which perform the modulation/ demodulation function. At a minimum, a V
bypass capacitor and a serial
CC
Applications
resistor for current control are the only external com­ponents required implementing a complete solution. TFDU5307 has a tri-state output and is floating in shutdown mode with a weak pull-up.
Features
• Compliant to the latest IrDA physical layer specification (up to 1.152 Mbit/s) and TV Remote Control, bi-directional operation included.
• Sensitivity covers full IrDA range. Recommended operating range is from nose to nose to 70 cm
• Operates from
2.7 V to 5.5 V within specification
• Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal)
• Power shutdown mode (< 5 µA Shutdown Current in Full Temperature Range, up to 85 °C)
• Surface mount package, low profile universal (L 8.5 mm x W 2.9 mm x H 2.5 mm) Capable of surface mount soldering to Side and top view orientation
• Backward pin compatible to Vishay Semiconductors SIR and MIR infrared transceivers
e3
Applications
• Telecommunication products (cellular phones, pagers)
• Digital still and video cameras
• Printers, fax machines, photocopiers, screen pro­jectors
• Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal)
• High efficiency emitter
• Directly interfaces with various super I/O and con­troller devices
• Tri-state-receiver output, floating in shut down with a weak pull-up
• Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US Patent No. 6,157,476
• Logic voltage 1.5 V to 5.5 V is independent of IRED driver and analog supply voltage
• Only one external component required
• TV remote control supported
• Transmitter intensity can be adjusted by an external resistor for extended range (> 0.7 m) or minimum low power (> 0.2 m) IrDA compliance.
• Lead (Pb)-free device
• Device in accordance to RoHS 2002/95/EC and WEEE 2002/96EC
• Medical and industrial data collection
• Notebook computers, desktop PCs, Palmtop Computers (Win CE, Palm PC), PDAs
• Internet TV boxes, video conferencing systems
• External infrared adapters (dongles)
• Kiosks, POS, Point and Pay devices including IrFM - applications
Document Number 82616
Rev. 1.5, 07-Apr-06
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1
TFDU5307
Vishay Semiconductors
Parts Table
Part Description Qty / Reel
TFDU5307-TR1 Oriented in carrier tape for side view surface mounting 750 pcs
TFDU5307-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs
TFDU5307-TT1 Oriented in carrier tape for top view surface mounting 750 pcs
TFDU5307-TT3 Oriented in carrier tape for top view surface mounting 2500 pcs
Functional Block Diagram
V
logic
Tri-State
Amplifier
Comparator
Driver
RXD
Vcc2
18509
SD
TXD
Logic &
Control
IRED Driver
IRED C
GND
Pin Description
Pin Number Function Description I/O Active
1 IRED
Anode
2 IRED
Connect IRED anode to the V
limiting resistor. A separate unregulated power supply can be used at this pin.
IRED Cathode, internally connected to the driver transistor
Cathode
3 TXD This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-
chip protection circuit disables the LED driver if the TXD pin is asserted for longer
than 80 μs. When used in conjunction with the SD pin, this pin is also used to
control receiver output pulse duration. The input threshold voltage adapts to and
follows the logic voltage reference applied to the V
4 RXD Received Data Output, push-pull CMOS driver output capable of driving standard
CMOS or TTL loads. No external pull-up or pull-down resistor is required. Floating
with a weak pull-up of 500 kΩ (typ.) in shutdown mode. The voltage swing is
defined by the applied V
5 SD Shutdown. Also used for setting the output pulse duration. Setting this pin active
for more than 1.5 ms places the module into shutdown mode. Before that (t < 0.7 ms) on the falling edge of this signal, the state of the TXD pin is sampled and used
to set the receiver output to long pulse duration (2 µs) or to short pulse duration
(0.4 μs) mode. The input threshold voltage adapts to and follows the logic voltage
reference applied to the V
6V
7V
CC1
logic
V
defines the logic voltage levels for input and output. The RXD output range
logic
is from 0 V to V
, for optimum noise suppression the inputs’ logic decision level
logic
8 GND Ground
power supply through an external current
CC2
pin (pin 7).
logic
voltage
logic
pin (pin 7).
logic
Supply Voltage
is 0.5 x V
logic
IHIGH
OLOW
IHIGH
I
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Document Number 82616
Rev. 1.5, 07-Apr-06
TFDU5307
Vishay Semiconductors
Pinout
TFDU5307 weight 75 mg
Definitions:
In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes:
SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0
MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s
MIR and FIR were implemented with IrPhy 1.1, fol­lowed by IrPhy 1.2, adding the SIR Low Power Stan­dard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A
18101
1234
IRED A
IRED C
TXD
56
RXD SD Vcc
7
Vlog
8
GND
new version of the standard in any case obsoletes the former version.
With introducing the updated versions the old ver­sions are obsolete. Therefore the only valid IrDA stan­dard is the actual version IrPhy 1.4 (in Oct. 2002).
Absolute Maximum Ratings
Reference point Ground (pin 8) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameter Test Conditions Symbol Min Ty p. Max Unit
Supply voltage range, transceiver
Supply voltage range, transmitter
Supply voltage range, V
Input current for all pins, except IRED anode
Output sinking current 25 mA
Power dissipation see derating curve, figure 4 P
Junction temperature T
Ambient temperature range (operating)
Storage temperature range T
Soldering temperature see recommended solder profile
Average output current, pin 1 I
Repetitive pulsed output current, pin 1 to pin 2
IRED anode voltage, pin 1 V
Voltage at all inputs and outputs V
Load at mode pin when used as mode indicator
logic
- 0.3 V < V
- 0.5 V < V
- 0.5 V < V
- 0.5 V < V
- 0.5 V < V
- 0.3 V < V
pin
(figure 3)
t < 90 µs, t
< V
in
< 6 V
CC2
< 5.5 V
logic
< 6 V
CC1
< 5.5 V
logic
< 6 V
CC1
< 6.5 V
CC2
< 20 % I
on
is allowed V
CC1
V
CC1
V
CC2
V
logic
D
J
T
amb
stg
IRED(DC)
IRED(RP)
IREDA
in
- 0.3 + 6.0 V
- 0.3 + 6.5 V
- 0.3 + 5.5 V
10 mA
500 mW
125 °C
- 25 + 85 °C
- 25 + 85 °C
260 °C
125 mA
600 mA
- 0.5 + 6.5 V
- 0.5 + 5.5 V
50 pF
Document Number 82616
Rev. 1.5, 07-Apr-06
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3
TFDU5307
Vishay Semiconductors
Eye safety information
Parameter Test Conditions Symbol Min Ty p. Max Unit
Virtual source size Method: (1-1/e) encircled
energy
Maximum intensity for class 1 IEC60825-1 or EN60825-1,
edition Jan. 2001, operating below the absolute maximum ratings
*)
Due to the internal limitation measures the device is a "class 1" device.
**)
IrDA specifies the max. intensity with 500 mW/sr.
Electrical Characteristics
Transceiver
T
= 25 °C, V
amb
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Supply voltage V
Idle supply current SD = Low, E
Average dynamic supply current, transmitting
Shutdown supply current SD = High, T = 25 °C, E
Standby supply current SD = High, T = 85 °C, not
Operating temperature range T
Output voltage low, RXD C
Output voltage high, RXD I
RXD to V
CC1
Input voltage low (TXD, SD) V
Input voltage high (TXD, SD)
Input leakage current (TXD, SD) V
Controlled pull down current SD, TXD = "0" to "1",
Input capacitance (TXD, SD) C
*)
Standard illuminant A
**)
The typical threshold level is 0.5 x V The inputs in low state are actively loaded for noise protection. See for that the "Controlled pull down current" spec. Equivalently a pull up current stabilizes the state when the inputs are in high state.
= V
CC1
= 2.7 V to 5.5 V unless otherwise noted.
CC2
Parameter Test Conditions Symbol Min Ty p. Max Unit
= 1 klx I
e
I
= 500 mA, 25 % Duty
IRED
Cycle
= 0 klx I
e
SD = High, T = 25 °C,
= 1 klx
e
*)
E
ambient light sensitive
= 15 pF, IOL = 1 mA V
Load
= - 500 µA V
OH
I
= - 250 µA, C
OH
= 15 pF V
Load
impedance R
< 0.15 V
in
**)
logic
logic
CMOS level
= 0.9 x V
in
0 < V
SD, TXD = "0" to "1", V
> 0.7 V
in
logic
. It is recommended to use the specified min/max values to avoid increased operating current.
logic
d1.82.0 mm
(500)
*) **)
mW/sr
A
2.5 µA
A
0.4 V
V
V
+ 0.5 V
logic
+ 150 µA
5pF
I
I
I
I
e
CC1
CC1
I
CC
SD
I
SD
I
SD
OL
OH
OH
RXD
IL
V
IH
ICH
IRTx
IRTx
IN
2.7 5.5 V
550 900 µA
1100 1500 µA
A
- 25 + 85 °C
0.8 x V
logic
0.9 x V
logic
400 500 600 kΩ
- 0.5 0.5 V
V
- 0.5 V
logic
- 2 + 2 µA
- 1 0 1 µA
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Document Number 82616
Rev. 1.5, 07-Apr-06
TFDU5307
Vishay Semiconductors
Optoelectronic Characteristics
Receiver
T
= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.
amb
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameter Test Conditions Symbol Min Ty p. Max Unit
Minimum detection threshold irradiance
Maximum detection threshold irradiance
No detection receiver input irradiance
9.6 kbit/s to 1.152 Mbit/s
λ = 850 nm - 900 nm
λ = 850 nm - 900 nm E
Threshold! No RXD output below this irradiance value
E
e
40 (4)
e
5
(500)
E
e
4
(0.4)
90 (9)
allowed
Rise time of output signal 10 % to 90 %, CL = 15 pF,
= V
V
logic
CC
Fall time of output signal 90 % to 10 %, C
= V
V
logic
RXD pulse width of output signal, default mode after power on or reset
SIR ENDEC compatibility
*)
mode
: RXD pulse width of
output signal
Stochastic jitter, leading edge
input pulse length P
> 200 ns
Wopt
input pulse length P
> 200 ns, see chapter
Wopt
"Programming"
input irradiance = 100 mW/m
CC
= 15 pF,
L
2
,
t
r(RXD)
t
f(RXD)
t
PW
t
PW
20 60 ns
20 60 ns
300 400 500 ns
1.7 2.0 2.9 µs
80 ns
1.152 Mbit/s, 576 kbit/s
input irradiance = 100 mW/m
2
,
350 ns
115.2 kbit/s
Standby /Shutdown delay after shutdown active or (SD low
0.6 1.5 ms
to high transition)
Shutdown active time window for programming
During this time the pulse duration of the output can be
600 µs
programmed to the application mode. see chapter "Programming"
Receiver start up time power on delay shutdown recovery delay
after shutdown inactive (SD high to low transition) and after
300 µs
power-on
Latency t
*)
Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore this additional mode was added in TFDU5307.
L
200 µs
TFDU5307 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (SD must have been longer active than 1.5 ms). For mode changing see the chapter "Programming"
2
mW/m
(µW/cm
2
kW/m
(mW/cm2)
2
mW/m
(µW/cm
2)
2)
Document Number 82616
Rev. 1.5, 07-Apr-06
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TFDU5307
Vishay Semiconductors
Transmitter
T
= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.
amb
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameter Test Conditions Symbol Min Ty p. Max Unit
V
IRED operating current, recommended serial resistor for MIR applications
Output leakage IRED current TXD = 0 V, 0 < V
Output radiant intensity recommended application circuit, see figure 1
Output radiant intensity V
= 3.3 V: RS = 2.0 Ω
CC2
= 5.0 V: RS = 5.6 Ω
V
CC2
< 5.5 V I
CC1
α = 0 °, I
=420 mA
f
TXD = High, SD = Low
α = 0 °, 15 °, I
=420 mA
f
TXD = High, SD = Low
= 5.0 V, α = 0 °, 15 °
CC1
**)
**)
TXD = Low or SD = High (Receiver is inactive as long as SD = High)
Output radiant intensity, angle of half intensity
Peak - emission wavelength
*)
Spectral bandwidth Δλ 45 nm
Optical rise time, fall time t
Optical output pulse duration input pulse width 217 ns,
1.152 Mbit/s Note: IrDA specification for MIR
input pulse width t
input pulse width t
< 80 µs t
TXD
80 µs t
TXD
Optical overshoot 25 %
*)
Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6 ditions (>120 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used.
**)
Typ. conditions for If = 420 mA, V
= 3.3 V, Rs = 2.3 Ω, V
CC2
= 5.0 V, Rs = 6.4 Ω
CC2
I
D
IRED
I
e
I
e
I
e
- 1 1 µA
110 500 mW/sr
70 120 500 mW/sr
450 500 mA
0.04 mW/sr
α ± 24 °
λ
p
, t
ropt
fopt
t
opt
opt
opt
®
or RECS 80. When operated under IrDA full range con-
880 900 nm
640ns
190
(147.6)
20 t
217 240
(260)
TXD
20 85 µs
ns ns
µs
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Document Number 82616
Rev. 1.5, 07-Apr-06
TFDU5307
Vishay Semiconductors
Recommended Circuit Diagram
Used with a clean low impedance power supply the TFDU5307 only needs an external series current lim­iting resistor. However, depending on the entire sys­tem design and board layout, additional components may be required (see figure 1).
V
IRED
V
cc
GND
V
logic
SD
TXD
RXD
18147
Figure 1. Recommended Application Circuit
The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is the current limiting resistor and this is supply voltage dependent, see derating curve in fig­ure 4, to avoid too high internal power dissipation. Vishay’s transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided.
C1
R1
R2
C2
IRED Anode
V
cc
Ground
V
logic
SD
TXD
RXD
IRED Cathode
The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and trans­mission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. A Tantalum capac­itor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at V
. Often some power supplies are not apply to
CC2
follow the fast current rise time. In that case another
4.7 µF (type, see table under C1) at V
will be help-
CC2
ful. Under extreme EMI conditions as placing an RF­transmitter antenna on top of the transceiver, we rec­ommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port. Keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termi­nation. See e.g. "The Art of Electronics" Paul Horow­itz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957.
Table 1. Recommended Application Circuit Components
Component Recommended Value Vishay Part Number
C1 4.7 µF, 16 V, Tantalum 293D 475X9 016B
C2 0.1 µF, Ceramic VJ 1206 Y 104 J XXMT
R1 5 V supply voltage: 5.6 Ω s. text 0.25 W (recommended
using two 2.8 Ω, 0.125 W resistors in series).
3.3 V supply voltage: 2.0 Ω s. text 0.25 W
R2 47 Ω, 0.125 W CRCW-1206-47R0-F-RT1
Document Number 82616
Rev. 1.5, 07-Apr-06
e.g. 2 x CRCW-1206-2R0-F-RT1 for 3.3 V supply voltage
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TFDU5307
Vishay Semiconductors
I/O and Software
In the description, already different I/Os are men­tioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application.
Programming Pulse duration Switching
After Power-on the TFDU5307 is in the default short RXD pulse duration mode. Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore an additional mode with extended pulse duration (same as in standard SIR transceivers) is added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, and after recovering from the shutdown mode (SD being active longer than 1.5 ms). To switch the transceivers from the short RXD pulse duration mode to the long pulse duration mode and vice versa, follow the procedure described below.
3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting).
4. After waiting t
200 ns TXD can be set to logic
h
"LOW". The hold time of TXD is limited by the maxi­mum allowed pulse length.
After that TXD is now enabled as normal TXD input and the RXD output is set for the short RXD - pulse duration mode. The timing of the pulse duration changing procedure is quite uncritical. However, the whole change must not take more than 600 µs. See in the spec. "Shut­down Active Time Window for Programming"
SD 50 %
t
s
TXD 50 % 50 %
t
h
High:
Low:
400 ns
2 µs
Setting to the ENDEC compatibility mode with an RXD pulse duration of 2 µs
1. Set SD input to logic "HIGH".
2. Set TXD input to logic "LOW". Wait t
200 ns.
s
3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting).
4. After waiting t
200 ns.
h
After that TXD is enabled as normal TXD input and the RXD output is set for the longer RXD - pulse dura­tion mode.
Setting back to the default mode with a 400 ns pulse duration
1. Set SD input to logic "HIGH".
2. Set TXD input to logic "HIGH". Wait t
200 ns.
s
18150
Figure 2. Timing Diagram for changing the output pulse duration
Simplified Method
Setting the device to the long pulse duration is simply applying a short active (less than 600 µs) pulse to SD. In any case a short SD pulse will force the device to leave the default mode and go the compatibility mode. Vice versa applying a 1.5 ms (minimum) pulse at SD will cause the device to go back to the default mode by activating a power-on-reset and setting the device to the default short pulse mode. This simplified method takes more time but may be easier to handle.
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Document Number 82616
Rev. 1.5, 07-Apr-06
Table 2. Truth table
Inputs Outputs Remark
SD TXD
high
< 600 µs
high
> 1.5 ms
low high x low (active) I
x x weakly pulled
x x weakly pulled
high
> 80 ms
low < 4 high inactive 0 Ignoring low signals below the IrDA
low > Minimum irradiance E
low > Maximum irradiance E
Optical input Irradiance mW/m
x high inactive 0 Protection is active
< Maximum irradiance E
2
e
e
e
RXD Transmitte
(500 kΩ) to V
(500 kΩ) to V
low (active) 0 Response to an IrDA compliant
undefined 0 Overload conditions can cause
CC1
CC1
TFDU5307
Vishay Semiconductors
r
0 Time window for pulse duration
0 Shutdown
e
Operation
setting
Transmitting
defined threshold for noise
immunity
optical input signal
unexpected outputs
Document Number 82616
Rev. 1.5, 07-Apr-06
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TFDU5307
Time/s
/
C
10 s max. at 230 °C
120 s...180 s
240 °C max.
20 s
2 °C...4 °C/s
2 °C...4 °C/s
90 s...120 s
T ≥ 217 °C for 50 s max
T ≥ 255 °C for 20 s max
Vishay Semiconductors
Recommended Solder Profile
Solder Profile for Sn/Pb soldering
260
240
220
200
°
180
160
140
120
100
80
Tem perat u re
60
40
20
0
2...4 °C/s
0 50 100 150 200 250 300 350
160 °C max.
Figure 3. Recommended Solder Profile for Sn/Pb soldering
2...4 °C/s
90 s max.
19431_1
Lead-Free, Recommended Solder Profile
The lead-frame based transceivers (all types with the name TFDUxxxx) are lead (Pb)-free and qualified for lead (Pb)-free and lead - bearing processing. In case of using a lead-bearing process we recom­mend a solder profile as shown in figure 4. For lead (Pb)-free solder paste like Sn-(3.0-4.0)Ag­(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-Soak-Spike (RSS) and Ramp-To-Spike (RTS). The Ramp-Soak-Spike profile was developed prima­rily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-To-Spike profile is used increasingly. Shown below in figure 5 and figure 6 are VISHAY’s recom­mende profiles for use with the TFDUxxxx transceiv­ers for lead (Pb)-free processing.
280
T
= 260 °C max.
260
240
220
200
180
160
140
120
Temperature/°C
100
80
60
40
20
0
0 50 100 150 200 250 300 350
19261
Time/s
50 s max.
peak
Figure 4. Solder Profile, RSS Recommendation
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Document Number 82616
Rev. 1.5, 07-Apr-06
Figure 5. Solder Profile, RTS Recommendation
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
0 50 100 150 200 250 300
Time/s
Tempe ratur e/°C
< 4 °C/s
1.3 °C/s
Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature T
peak
= 260 °C
< 2 °C/s
T
peak
= 260 °C max
TFDU5307
Vishay Semiconductors
A ramp-up rate less than 0.9 °C/s is not recom­mended. Ramp-up rates faster than 1.3 °C/s damage an optical part because the thermal conductivity is less than compared to a standard IC.
Current Derating Diagram
Figure 6 shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 Ω is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too.
90
85
80
75
70
65
60
Ambient Temperature (°C)
55
50
2.0 2.5 3.0 3.5 4.0
18097
Operating Voltage [V] at duty cycle 20 %
4.5
5.0 5.5 6.0
Document Number 82616
Rev. 1.5, 07-Apr-06
Figure 6. Temperature Derating Diagram
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TFDU5307
Vishay Semiconductors
TFDU5307 - TinyFace (Universal) Package (Dimensions in mm)
(Mechanical Dimensions)
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18100
Document Number 82616
Rev. 1.5, 07-Apr-06
Reel Dimensions
TFDU5307
Vishay Semiconductors
14017
Tape Width A max. N W1 min. W2 max. W3 min. W3 max.
mm mm mm mm mm mm mm
16 330 50 16.4 22.4 15.9 19.4
Document Number 82616
Rev. 1.5, 07-Apr-06
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TFDU5307
Vishay Semiconductors
Tape Dimensions in mm
Drawing-No.: 9.700-5280.01-4 Issue: 1; 03.11.03
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14
19855
Figure 7. Tape drawing, TFDU5307 for top view mounting
Document Number 82616
Rev. 1.5, 07-Apr-06
TFDU5307
Vishay Semiconductors
Drawing-No.: 9.700-5279.01-4 Issue: 1; 08.12.04
Document Number 82616
Rev. 1.5, 07-Apr-06
19856
Figure 8. Tape drawing, TFDU5307 for side view mounting
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TFDU5307
Vishay Semiconductors
Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating
systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.
Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments
respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design
and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each
customer application by the customer. Should the buyer use Vishay Semiconductors products for any
unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all
claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal
damage, injury or death associated with such unintended or unauthorized use.
Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
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Document Number 82616
Rev. 1.5, 07-Apr-06
Legal Disclaimer Notice
Vishay
Document Number: 91000 www.vishay.com Revision: 08-Apr-05 1
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
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