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SiP41109/41110
New Product
Vishay Siliconix
Half-Bridge N-Channel MOSFET Driver for DC/DC Conversion
FEATURES APPLICATIONS
D PWM With Tri-State Enable
D 12-V Low-Side Gate Drive (SiP41109)
D 8-V Low-Side Gate Drive (SiP41110)
D Undervoltage Lockout
D Internal Bootstrap Diode
D Switching Frequency Up to 1 MHz
D 30-ns Max Propagation Delay
D Drive MOSFETs In 5- to 48-V Systems
D Adaptive Shoot-Through Protection
DESCRIPTION
The SiP41109 and SiP41110 are high-speed half-bridge
MOSFET drivers for use in high frequency, high current,
multiphase dc-to-dc synchronous rectifier buck power
supplies. They are designed to operate at switching
frequencies up to 1 MHz. The high-side driver is bootstrapped
to allow driving n-channel MOSFETs.
They feature adaptive shoot-through protection to prevent
simultaneous conduction of the external MOSFETs. There are
two options available for the voltage of the high-side and
D Multi-Phase DC/DC Conversion
D High Current Low Voltage DC/DC Converters
D High Frequency DC/DC Converters
D Mobile and Desktop Computer DC/DC Converters
D Core Voltage Supplies for PC Micro-Processors
low-side drivers. In the SiP41109, the regulator supplies gate
drive voltage to the high-side driver and V
CC
low-side driver. in the SiP41110, the regulator supplies the
high- and low-side gate drive voltage.
The SiP41109 and SiP41110 are assembled in a
lead (Pb)-free 8-pin SOIC package for operation over the
industrial operating range (−40 _C to 85 _C).
supplies the
TYPICAL APPLICATION CIRCUIT
+5 to 48 V
+12 V
Controller
PVcc
SiP41109/41110
PWM
(Tri-State)
V
CC
GND
BOOT
UGATE
PHASE
LGATE
V
OUT
GND
Document Number: 73023
S-51104—Rev. A, 13-Jun-05
GND
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1
SiP41109/41110
mA
V
High-Side Drive C
c
V
− V
= 8 V
V
= 8 V
SiP4111 0
A
V
= 12 V
SiP41109
Vishay Siliconix
New Product
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
V CC, PV
CC
BOOT, PHASE −0.3 to 55 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3 to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Impedance (Q
SO-8 130_C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to PHASE −0.3 to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature −40 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature 125_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation
a
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.7 mW/_C
SO-8 770 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
b
)
JA
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
V
CC
V
LX
C
BOOT
10.8 to 13.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.48 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to PHASE . 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range −40 to 85_C. . . . . . . . . . . . . . . . . . . . . . . . . . .
.100 nF to 1 mF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONS
a
Parameter Symbol
Power Supplies
Supply Voltage V
Quiescent Current I
Supply Current I
Tristate (Shutdown) Current I
Reference Voltage
Break-Before-Make V
PWM Input
Input High V
Input Low V
Bias Current I
Tristate Threshold
Tristate Holdoff Timeout
High V
Low V
c
Bootstrap Diode
Forward Voltage V
MOSFET Drivers
I
-
urrent
Low-Side Drive Current
c
c
PKH(source)
I
PKH(sink)
I
PKL(source)
I
PKL(sink)
I
PKL(source)
I
PKL(sink)
CCQ
CCT
BBM
TSH
t
TST
CC
DD
IH
IL
B
TSL
Test Conditions Unless Specified
VCC = 12 V, V
− V
BOOT
PHASE
TA = −40 to 85_C
= 8 V
Min
Limits
a
TypbMaxaUnit
10.8 13.2 V
PWM Non-Switching 5.6 9.5
f
= 100 kHz, C
PWM
LOAD
= 3 nF
SiP41109 12.5
SiP41110 11.0
mA
PWM = Open 850 1200 mA
2.5 V
4.0 V
CC
1.0
PWM 5 V or 0 V "600 "1000 mA
3.0
2.0
V
240 ns
F
IF = 40 mA, TA = 25_C 0.70 0.85 1.0 V
0.8
1.0
0.9
1.2
1.4
1.8
PVCC
PVCC
BOOT
−
PHASE
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Document Number: 73023
S-51104—Rev. A, 13-Jun-05
SiP41109/41110
10% − 90%, V
− V
= 8 V, C
= 3 nF
10% − 90%, V
− V
= 12 V, C
= 3 nF
ns
V
V
_C
SPECIFICATIONS
Parameter UnitMax
New Product
a
Test Conditions Unless Specified
Test Conditions Unless Specified
Symbol
VCC = 12 V, V
VCC = 12 V, V
− V
− V
BOOT
BOOT
T
T
= −40 to 85_C
= −40 to 85_C
A
A
PHASE
PHASE
= 8 V
= 8 V
Vishay Siliconix
Limits
Min
a
Typ
b
a
MOSFET Drivers
R
High-Side Driver Impedance
Low-Side Driver Impedance
DH(source)
R
R
DL(source)
R
R
DL(source)
R
High-Side Rise Time t
High-Side Fall Time t
High-Side Rise Time Bypass
High-Side Fall Time Bypass
High-Side Propagation Delay
c
Low-Side Rise Time t
Low-Side Fall Time t
Low-Side Propagation Delay
DH(sink)
DL(sink)
DL(sink)
rH
fH
t
d(off)H
t
d(on)H
rL
fL
t
d(off)L
t
d(on)L
V
BOOT
V
−
−
10% − 90%, V
10% − 90%, V
10% − 90%, V
10% − 90%, V
C
C
C
C
V
PVCC
PVCC
− V
= 8 V, PHASE = GND
PHASE
= 8 V SiP41110
= 12 V SiP41109
−
BOOT
PHASE
−
BOOT
PHASE
See Timing Waveforms
BOOT
LOAD
BOOT
LOAD
BOOT
LOAD
BOOT
LOAD
− V
= 3 nF
− V
= 3 nF
− V
= 3 nF
− V
= 3 nF
PHASE
PHASE
PHASE
PHASE
= 8 V
= 12 V
= 8 V
= 12 V
See Timing Waveforms
LOAD
LOAD
SiP41110 40
SiP41109 40
SiP41110 30
SiP41109 30
2.3 4.2
1.9 3.5
2.9 5.2
1.3 2.4
2.4 4.3
1.2 2.2
45
35
45
35
15
15
15
15
PHASE Timer
PHASE Falling Timeout
c
t
PHASE
380 ns
PVCC Regulator
Output Voltage PV
Output Current I
Current Limit I
CC
PVCC
LIM
V
= 0 V 120 200 280
DRV
Line Regulation LNR VCC = 10.8 V to 13.2 V 0.05 0.5 %/V
Load Regulation LDR 5 mA to 80 mA 0.1 1.0 %
7.6 8 8.4 V
80 100
PVCC Regulator UVLO
PVCC Rising
PV
Falling
CC
UVLO2
Hysteresis Hyst 100 300 500 mV
6.7 7.2
6.4 6.9
High-Side Undervoltage Lockout
Threshold V
V
Undervoltage Lockout
CC
Threshold V
UVHS
UVLO1
Power on Reset Time POR 2.5 ms
Rising or Falling 2.5 3.35 4.0 V
5.0 5.3 5.6 V
Thermal Shutdown
Temperature T
Hysteresis T
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at V
SD
H
Temperature Rising 165
Temperature Falling 25
= 12 V unless otherwise noted.
CC
W
ns
mA
_
Document Number: 73023
S-51104—Rev. A, 13-Jun-05
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SiP41109/41110
_C
_C
Vishay Siliconix
New Product
TIMING WAVEFORMS
PWM
50%
UGate
LGate
Phase
t
d(off)H
90%
10%
t
fH
2.5 V
90%
10%
t
d(on)L
PIN CONFIGURATION AND TRUTH TABLE
SO-8
UGATE PHASE
BOOT
PWM
GND
1
2
3
4
SiP41109
SiP41110
8
PV
7
CC
V
6
CC
LGATE
5
50%
90%
10%
t
t
d(on)H
rH
90%
10%
t
rL
t
d(off)L
t
fL
TRUTH TABLE
PWM UGATE LGATE
L L H
H H L
Tri-State L L
Top View
ORDERING INFORMATION
Part Number Temperature Range Marking
SiP41109DY-T1—E3
SiP41110DY-T1—E3
−
−40 to 85
_
Eval Kit Temperature Range
SiP41109DB
SiP41110DB
−
−40 to 85
_
PIN DESCRIPTION
Pin Number Name Function
1 UGATE 8-V high-side MOSFET gate drive
2 BOOT Bootstrap supply for high-side driver. The bootstap capacitor is connected between BOOT and PHASE.
3 PWM Input signal for the MOSFET drivers and tri-state enable
4 GND Ground
5 LGATE Synchronous or low-side MOSFET gate drive
6 V
7 PV
8 PHASE Connection to source of high-side MOSFET, drain of the low-side MOSFET, and the inductor
CC
CC
12-V supply. Connect a bypass capacitor w1 mF from here to ground
8-V Voltage Regulator Output. Connect a bypass capacitor w1 mF from here to ground
41109
41110
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Document Number: 73023
S-51104—Rev. A, 13-Jun-05
SiP41109/41110
FUNCTIONAL BLOCK DIAGRAM
V
CC
UVLO
OTP
Linear
Regulator
+5 V
Tri-State
Detect
PWM
GND
New Product
+8-V Linear
Regulator
PV
CC
SiP41109 − V
SiP41110 − V
= VCC (12 V)
DRL
= PVCC (8 V)
DRL
Vishay Siliconix
BOOT
UGATE
UVLO
PHASE
−
V
+
BBM
(2.5 V)
V
DRL
LGATE
DETAILED OPERATION
PWM/Tri-State Enable
The PWM pin controls the switching of the external MOSFETs.
The driver logic operates in a noninverting configuration. The
PWM input stage should be driven by a signal with fast
transition times, like those provided by a PWM controller or
logic gate, (<200 ns). The PWM input functions as a logic input
and is not intended for applications where a slow changing
input voltage is used to generate a switching output when the
input switching threshold voltage is reached.
Shutdown
The SiP41109/41110 enters shutdown mode when the signal
driving PWM enters the tri-state window for more than 240 ns.
The shutdown state is removed when the PWM signal moves
outside the tri-state window. If the PWM is left open, the pin is
held to 2.5 V by an internal voltage divider, thus forcing the
tri-state condition.
Low-Side Driver
In the SiP41109, the low-side driver voltage is supplied by V
In the SiP41110, the low-side driver voltage is supplied by
PVCC. During shutdown, LGATE is held low.
High-Side Driver
The high-side driver is isolated from the substrate to create a
floating high-side driver so that an n-channel MOSFET can be
CC
Figure 1.
used for the high-side switch. The high-side driver voltage is
supplied by PV
. The voltage is maintained by a floating
CC
bootstrap capacitor, which is continually recharged by the
switching action of the output. During shutdown UGATE is
held low.
Gate Drive Voltage (PV
) Regulator
CC
An integrated 80-mA, 8-V regulator supplies voltage to the
PV
pin and it current limits at 200 mA typical when the
CC
output is shorted to ground. A capacitor (1 mF minimum) must
be connected to the PV
The voltage on PV
diode. PV
is used to recharge the bootstrap capacitor and
CC
powers the SiP41110 low-side driver. PV
externally connected to V
pin to stabilize the regulator output.
CC
is supplied to the integrated bootstrap
CC
to bypass the 8-V regulator and
CC
CC
increase high-side gate drive to 12 V. If the PV
connected to V
the system voltage should not exceed 43V.
CC
Bootstrap Circuit
The internal bootstrap diode and an external bootstrap
.
capacitor supply voltage to the BOOT pin. An integrated
bootstrap diode replaces the external diode normally needed
for the bootstrap circuit; only a capacitor is necessary to
complete the bootstrap circuit. The bootstrap capacitor is
sized according to,
C
BOOT
= (Q
GATE
/(DV
BOOT
− V
PHASE
pin can be
pin is
CC
)) x 10
Document Number: 73023
S-51104—Rev. A, 13-Jun-05
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5
SiP41109/41110
Vishay Siliconix
where Q
high-side MOSFET and DV
is the gate charge needed to turn on the
GATE
− PHASE is the amount of
BOOT
New Product
droop allowed in the bootstrapped supply voltage when the
high-side MOSFET is driven high. The bootstrap capacitor
value is typically 0.1 mF to 1 mF. The bootstrap capacitor
voltage rating must be greater than VCC + 12 V to withstand
transient spikes and ringing.
Shoot-Through Protection
The external MOSFETs are prevented from conducting at the
same time during transitions. Break-before-make circuits
monitor the voltages on the PHASE pin and the LGATE pin and
control the switching as follows: When the signal on PWM goes
low, UGATE will go low after an internal propagation delay.
After the voltage on PHASE falls below 2.5 V by the inductor
action, the low-side driver is enabled and LGATE goes high
after some delay. When the signal on PWM goes high, LGATE
will go low after an internal propagation delay. After the voltage
on LGATE drops below 2.5 V the high-side driver is enabled
and UGATE will go high after an internal propagation delay. If
PHASE does not drop below 2.5 V within 380 ns after UGATE
goes low, LGATE is forced high until the next PWM transition.
Bypass Capacitor
V
CC
MOSFET drivers draw large peak currents from the supplies
when they switch. A local bypass capacitor is required to
supply this current and reduce power supply noise. Connect
a 1-mF ceramic capacitor as close as practical between the
V
and GND pins.
CC
Undervoltage Lockout
Undervoltage lockout prevents control of the circuit until the
supply voltages reach valid operating levels. The UVLO circuit
forces LGATE and UGATE to low when VCC is below its
specified voltage. A separate UVLO forces UGATE low when
the voltage between BOOT and PHASE is below the specified
voltage.
Thermal Protection
If the die temperature rises above 165_C, the thermal
protection disables the drivers. The drivers are re-enabled
after the die temperature has decreased below 140_C.
TYPICAL CHARACTERISTICS
(mA)
CC
I
105
ICC vs. C
95
85
75
65
55
45
35
25
15
VCC = 12 V VCC = 12 V
5
012345
vs. Frequency (SiP41109)
LOAD
1 MHz
C
(nF)
LOAD
500 kHz
200 kHz
(mA)
CC
I
100
ICC vs. C
90
80
70
60
50
40
30
20
10
0
012345
vs. Frequency (SiP41110)
LOAD
1 MHz
C
LOAD
500 kHz
(nF)
200 kHz
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Document Number: 73023
S-51104—Rev. A, 13-Jun-05
SiP41109/41110
TYPICAL WAVEFORMS
Figure 2. PWM Signal vs. HS Gate, LS Gate
and PHASE (Rising)
40 ns/div
New Product
PWM
5 V/div
UGate
20 V/div
LGate
10 V/div
V
PHASE
10 V/div
Vishay Siliconix
Figure 3. PWM Signal vs. HS Gate, LS Gate
and PHASE (Falling)
40 ns/div
PWM
5 V/div
UGate
20 V/div
LGate
10 V/div
V
PHASE
10 V/div
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified loc ations. Reliability data for Silicon Technology and
Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see
http://www.vishay.com/ppg?73023.
Document Number: 73023
S-51104—Rev. A, 13-Jun-05
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