VISHAY SiC634 Datasheet

www.vishay.com

50 A VRPower® Integrated Power Stage

SiC634

Vishay Siliconix

DESCRIPTION

The SiC634 is integrated power stage solutions optimized
for synchronous buck applications to offer high current, high
efficiency, and high power density performance. Packaged
in Vishay’s proprietary

5 mm x 5 mm
enables voltage regulator designs to deliver up to 50 A
continuous current per phase.

The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET® technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.

The SiC634 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
and zero current detection to improve light load efficiency.
The driver is also compatible with a wide range of PWM
controllers, supports tri-state PWM, and 5 V PWM logic.

A user selectable diode emulation mode (ZCD_EN#) is
included to improve the light load performance. The device
also supports PS4 mode to reduce power consumption
when system operates in standby state.

MLP package, SiC634

FEATURES

• Thermally enhanced PowerPAK® MLP55-31L
package

• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode

• Delivers in excess of 50 A continuous current, 55 A at
10 ms peak current

• High efficiency performance

• High frequency operation up to 2 MHz

• Power MOSFETs optimized for 19 V input stage

• 5 V PWM logic with tri-state and hold-off

• Supports PS4 mode light load requirement for IMVP8 with
low shutdown supply current (5 V, 3 μA)

• Under voltage lockout for V

CIN

• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

APPLICATIONS

• Multi-phase VRDs for computing, graphics card and
memory

• Intel IMVP-8 VRPower delivery

- V

- V

• Up to 24 V rail input DC/DC VR modules

CORE

, V

GRAPHICS

, V

platforms

for Apollo Lake platforms

CCGI

SYSTEM AGENT

Skylake, Kabylake



TYPICAL APPLICATION DIAGRAM

5V V

V

DRV

V

CIN

ZCD_EN#

PWM

controller

S20-0485-Rev. C, 29-Jun-2020

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

PWM

Fig. 1 - SiC634 Typical Application Diagram

For technical questions, contact: [e-mail]

Gate

driver

GL

C

GND

V

IN

BOOT

PHASE

V

SWH

P

GND

1

Document Number: 76784

IN

V

OUT

www.vishay.com

P

GND

N.C.

BOOT

PHASE

V

IN

P

GNDPGNDPGNDPGND

VINVINV

IN

N.C.

GL

V

DRV

N.C.

N.C.

PWM

ZCD_EN#

V

CIN

PGND

VIN

CGND

GL

P

GND

N.C.

BOOT

PHASE

V

IN

P

GND

P

GND

P

GNDPGND

VINVINV

IN

N.C.

GL

V

DRV

N.C.

N.C.

PWM

ZCD_EN#

V

CIN

35

P

GND

34

V

IN

32

C

GND

GL

2

1

4

3

6

5

8

7

2425262728293031

1514131211109

2

1

4

3

6

5

8

7

15 14 13 12 11 10 9

24 25 26 27 28 29 30 31

V

SWH

23

V

SWHVSWHVSWH

V

SWHVSWH

V

SWH

33
GL

V

SWH

22

V

SWH

21

V

SWH

20

V

SWH

19

V

SWH

18

V

SWH

17

V

SWH

16

23 V

SWH

22 V

SWH

21 V

SWH

20 V

SWH

19 V

SWH

16 V

SWH

18 V

SWH

17 V

SWH

PINOUT CONFIGURATION

SiC634

Vishay Siliconix

Fig. 2 - SiC634 Pin Configuration

PIN CONFIGURATION

PIN NUMBER NAME FUNCTION

1 PWM PWM input logic

The ZCD_EN# pin enables or disables diode emulation. When ZCD_EN# is LOW, diode emulation is

2 ZCD_EN#

3V

CIN

5 BOOT High-side driver bootstrap voltage

4, 6, 30, 31 N.C.

7 PHASE Return path of high-side gate driver

8 to 11, 34 V

12 to 15, 28, 35 P

27, 33 GL Low-side MOSFET gate signal

16 to 26 V

29 V

S20-0485-Rev. C, 29-Jun-2020

32 C

ORDERING INFORMATION

PART NUMBER PACKAGE MARKING CODE OPTION

SiC634CD-T1-GE3 PowerPAK MLP55-31L SiC634 5 V PWM optimized

SiC634DB Reference board

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

IN

GND

SWH

DRV

GND

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

allowed. When ZCD_EN# is HIGH, continuous conduction mode is forced.
ZCD_EN# can also be put in a high impedance mode by floating the pin. If both ZCD_EN# and PWM
are floating, the device shuts down and consumes typically 3 μA (9 μA max.) current

Supply voltage for internal logic circuitry

Pin 4 can be either left floating or connected to C
connected to GND or not internally connected depending on manufacturing
location.

Factory code “G” on line 3, pin 4 = C
Factory code “T” on line 3, pin 4 = not internally connected

GND



. Internally it is either

GND

P/N

LL

G Y W W

Power stage input voltage. Drain of high-side MOSFET

Power ground

Phase node of the power stage

Supply voltage for internal gate driver

Signal ground

2

Document Number: 76784

For technical questions, contact: [e-mail]

P/N

LL

T Y W W

SiC634

www.vishay.com

PART MARKING INFORMATION

= pin 1 indicator

= part number code

P/N

P/N

LL

F Y W W

= Siliconix logo

= ESD symbol

= assembly factory code

F

= year code

Y

WW

= week code

LL

= lot code

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT

Input voltage V

Control logic supply voltage V

Drive supply voltage V

Switch node (DC voltage)

Switch node (AC voltage)

BOOT voltage (DC voltage)

BOOT voltage (AC voltage)

BOOT to PHASE (DC voltage)

BOOT to PHASE (AC voltage)

All lo gic i npu ts an d o utpu ts
(PWM, ZCD_EN#)

Max. operating junction temperature T

Storage temperature T

Electrostatic discharge protection

Notes

• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

(1)

The specification values indicated “AC” is V

(2)

The specification value indicates “AC voltage” is V

(3)

The specification value indicates “AC voltage” is V

(1)

(2)

(3)

Human body model, JESD22-A114 2000

Charged device model, JESD22-C101 1000

to P

SWH

-8 V (< 20 ns, 10 μJ), min. and 35 V (< 50 ns), max.

GND

to P

BOOT

to V

BOOT

IN

CIN

DRV

V

SWH

V

BOOT

V

BOOT-PHASE

J

A

stg

, 40 V (< 50 ns) max.

GND

, 8 V (< 50 ns) max.

PHASE

-0.3 to +28

-0.3 to +7

-0.3 to +7

-0.3 to +28

-7 to +35

-0.3 to +7

-0.3 to +8

-0.3 to V

150

-40 to +125

-65 to +150

Vishay Siliconix

33

40

+0.3

CIN

V

°CAmbient temperature T

V

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT

Input voltage (V

Drive supply voltage (V

Control logic supply voltage (V

BOOT to PHASE (V

Thermal resistance from junction to ambient - 10.6 -

Thermal resistance from junction to case - 1.6 -

S20-0485-Rev. C, 29-Jun-2020

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

)4.5-24

IN

) 4.555.5

DRV

) 4.555.5

CIN

BOOT-PHASE

, DC voltage) 4 4.5 5.5

3

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 76784

V

°C/W

www.vishay.com

Vishay Siliconix

ELECTRICAL SPECIFICATIONS

(ZCD_EN# = 5 V, V

PARAMETER SYMBOL TEST CONDITION

POWER SUPPLY

Control logic supply current I

Drive supply current I

PS4 mode supply current I

BOOTSTRAP SUPPLY

Bootstrap diode forward voltage V

PWM CONTROL INPUT

Rising threshold V

Falling threshold V

Tri-state voltage V

Tri-state rising threshold V

Tri-state falling threshold V

Tri-state rising threshold hysteresis V

Tri-state falling threshold hysteresis V

PWM input current I

ZCD_EN# CONTROL INPUT

Rising threshold V

Falling threshold V

Tri-state voltage V

Tri-state rising threshold V

Tri-state falling threshold V

Tri-state rising threshold hysteresis V

Tri-state falling threshold hysteresis V

ZCD_EN# input current I

PS4 exit latency t

TIMING SPECIFICATIONS

Tri-state to GH/GL rising
propagation delay

Tri-state hold-off time t

GH - turn off propagation delay t

GH - turn on propagation delay
(dead time rising)

GL - turn off propagation delay t

GL - turn on propagation delay
(dead time falling)

PWM minimum on-time t

PROTECTION

Under voltage lockout V

Under voltage lockout hysteresis V

Notes

(1)

Typical limits are established by characterization and are not production tested

(2)

Guaranteed by design

S20-0485-Rev. C, 29-Jun-2020

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

= 12 V, V

IN

DRV

and V

= 5 V, TA = 25 °C, unless otherwise stated)

CIN

LIMITS

MIN. TYP. MAX.

V

= FLOAT - 80 -

PWM

VCIN

VDRV

+ I

VCIN

VDRV

F

TH_PWM_R

TH_PWM_F

TRI

TRI_TH_R

TRI_TH_F

HYS_TRI_R

HYS_TRI_F

PWM

TH_ZCD_EN#_R

TH_ZCD_EN#_F

TRI_ZCD_EN#

TRI_ZCD_EN#_R

TRI_ZCD_EN#_F

HYS_TRI_ZCD#_R

HYS_TRI_ZCD#_F

ZCD_EN#

PS4EXIT

t

PD_TRI_R

TSHO

PD_OFF_GH

t

PD_ON_GH

PD_OFF_GL

t

PD_ON_GL

PWM_ON_MIN.

UVLO

UVLO_HYST

= FLOAT, V

PWM

f

= 300 kHz, D = 0.1 - 300 -

S

fS = 300 kHz, D = 0.1 - 10 20

= 1 MHz, D = 0.1 - 30 -

f

S

V

= V

PWM

ZCD_EN#

T

= -10 °C to +100 °C

A

IF = 2 mA - - 0.65 V

V

= FLOAT - 2.5 -

PWM

V

= 5 V - - 350

PWM

= 0 V - - -350

V

PWM

V

= FLOAT - 2.5 -

ZCD_EN#

V

ZCD_EN#

V

ZCD_EN#

No load, see Fig. 4

V

rising, on threshold - 3.4 3.9

CIN

falling, off threshold 2.4 2.9 -

V

CIN

= 0 V - 120 -

ZCD_EN#

= FLOAT,

-39μA

3.6 3.9 4.2

0.72 1 1.3

1.11.351.6

3.4 3.7 4

- 325 -

- 250 -

3.3 3.6 3.9

1.1 1.4 1.7

1.5 1.8 2.1

2.93.153.4

- 375 -

- 450 -

= 5 V - - 100

= 0 V - - -100

--5μs

-20-

- 150 -

-20-

-15-

-20-

-20-

30 - -

- 500 - mV

4

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 76784

SiC634

UNIT

μAV

mA

V

mV

μA

V

mV

μA

ns

V

www.vishay.com

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-State Function

The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V

PWM_TH_R

turned on. When PWM input is driven below V
high-side is turned off and the low-side is turned on. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is an third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC634 to
pull the PWM input into the tri-state region (see definition of
PWM logic and tri-state, Fig. 4). If the PWM input stays in
this region for the tri-state hold-off period, t
high-side and low-side MOSFETs are turned off. The
function allows the VR phase to be disabled without
negative output voltage swing caused by inductor ringing
and saves a Schottky diode clamp. The PWM and tri-state
regions are separated by hysteresis to prevent false
triggering. The SiC634 incorporates PWM voltage
thresholds that are compatible with 5 V.

Diode Emulation Mode and PS4 Mode (ZCD_EN#)

The ZCD_EN# pin enables or disables diode emulation
mode. When ZCD_EN# is driven below V
emulation is allowed. When ZCD_EN# is driven above
V

TH_ZCD_EN#_R

Diode emulation mode allows for higher converter efficiency
under light load situations. With diode emulation active, the
SiC634 will detect the zero current crossing of the output
inductor and turn off the low-side MOSFET. This ensures
that discontinuous conduction mode (DCM) is achieved.
Diode emulation is asynchronous to the PWM signal,
therefore, the SiC634 will respond to the ZCD_EN# input
immediately after it changes state.

The ZCD_EN# pin can be floated resulting in a high
impedance state. High impedance on the input of ZCD_EN#
combined with a tri-stated PWM output will shut down the
SiC634, reducing current consumption to typically 5 μA.
This is an important feature in achieving the low standby
current requirements required in the PS4 state in ultrabooks
and notebooks.

Voltage Input (V

This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.






the low-side is turned on and the high-side is

TSHO

the

, both

, diode

PWM_TH_F

TH_ZCD_EN#_F

, continuous conduction mode is forced.

)

IN

SiC634

Vishay Siliconix

Switch Node (V

The switch node, V
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node V
is to be used exclusively as the return pin for the BOOT
capacitor.

Ground Connections (C

P

(power ground) should be externally connected

GND

to C

(control signal ground). The layout of the printed

GND

circuit board should be such that the inductance separating

and P

C

GND

GND

inductance effects between these two pins should not
exceed 0.5 V

Control and Drive Supply Voltage Input (V

V

is the bias supply for the gate drive control IC. V

CIN

the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.

Bootstrap Circuit (BOOT)

The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC634 has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the one
turning on from tuning on until the other's gate voltage is
sufficiently low (< 1 V). Built in delays also ensure that one
power MOS is completely off, before the other can be turned
on. This feature helps to adjust dead time as gate transitions
change with respect to output current and temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate
drive holding high-side and low-side MOSFET gates low
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC634 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device.

and PHASE)

SWH

, is the circuit power stage output.

SWH

. This pin

SWH

GND

and P

GND

)

is minimized. Transient differences due to

, V

CIN

)

DRV

DRV

is

S20-0485-Rev. C, 29-Jun-2020

For technical questions, contact: [e-mail]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

5

Document Number: 76784

www.vishay.com

ZCD_EN#

V

SWH

GL

+

-

GL

+

-

UVLO

V

CIN

PWM logic

control &

state

machine

Anti-cross

conduction

control

logic

BOOT

V

IN

PWM

C

GND

V

CIN

P

GND

PHASE

V

DRV

V

DRV

FUNCTIONAL BLOCK DIAGRAM

SiC634

Vishay Siliconix

Fig. 3 - SiC634 Functional Block Diagram

DEVICE TRUTH TABLE

ZCD_EN# PWM GH GL

Tri-state X L L

LLL

LHHL

L Tri-state L L

HLLH

HHHL

H Tri-state L L

S20-0485-Rev. C, 29-Jun-2020

6

For technical questions, contact: [e-mail]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

H, I
L, I

Document Number: 76784

> 0 A

L

< 0 A

L