Vishay SiC632, SiC632A Datasheet

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50 A VRPower® Integrated Power Stage

SiC632, SiC632A

Vishay Siliconix

DESCRIPTION

The SiC632 and SiC632A are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power density
performance. Packaged in Vishay’s proprietary
MLP package, SiC632 and SiC632A enables voltage
regulator designs to deliver up to 50 A continuous current
per phase.

The internal power MOSFETs utilizes Vishay’s

®

state-of-the-art Gen IV TrenchFET

technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.

The SiC632 and SiC632A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
zero current detection to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC632A), 5 V
(SiC632) PWM logic.

5 mm x 5 mm

FEATURES

• Thermally enhanced PowerPAK® MLP55-31L
package

• Vishay’s Gen IV MOSFET technology and a low
side MOSFET with integrated Schottky diode

• Delivers up to 50 A continuous current

• High efficiency performance

• High frequency operation up to 1.5 MHz

• Power MOSFETs optimized for 19 V input stage

• 3.3 V (SiC632A), 5 V (SiC632) PWM logic with tri-state and
hold-off

• Zero current detect control for light load efficiency
improvement

• Low PWM propagation delay (< 20 ns)

• Faster disable

• Thermal monitor flag

• Under voltage lockout for V

CIN

• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

APPLICATIONS

• Multi-phase VRDs for computing, graphics card and
memory

• Intel IMVP-8 VRPower delivery

- V

- V

• Up to 24 V rail input DC/DC VR modules

CORE

, V

GRAPHICS

, V

platforms

for Apollo Lake platforms

CCGI

SYSTEM AGENT

Skylake, Kabylake

TYPICAL APPLICATION DIAGRAM

5V V

V

DRV

V

CIN

ZCD_EN#

PWM

controller

S20-0486-Rev. E, 29-Jun-2020

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

DSBL#

PWM

THWn

Fig. 1 - SiC632 and SiC632A Typical Application Diagram

For technical questions, contact: [e-mail]

Gate

driver

GL

C

GND

V

IN

BOOT

PHASE

V

SWH

P

GND

1

Document Number: 62992

IN

V

OUT

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P

GND

C

GND

BOOT

PHASE

V

IN

P

GNDPGNDPGNDPGND

VINVINV

IN

N.C.

GL

V

DRV

THWn

DSBL#

PWM

ZCD_EN#

V

CIN

PGND

VIN

CGND

GL

Top view Bottom view

P

GND

C

GND

BOOT

PHASE

V

IN

P

GNDPGNDPGNDPGND

VINV

INVIN

N.C.

GL

V

DRV

THWn

DSBL#

PWM

ZCD_EN#

V

CIN

35

P

GND

34

V

IN

32

C

GND

GL

2

1

4

3

6

5

8

7

2425262728293031

1514131211109

2

1

4

3

6

5

8

7

15 14 13 12 11 10 9

24 25 26 27 28 29 30 31

V

SWH

23

V

SWHVSWH

V

SWH

V

SWHVSWH

V

SWH

33
GL

V

SWH

22

V

SWH

21

V

SWH

20

V

SWH

19

V

SWH

18

V

SWH

17

V

SWH

16

23 V

SWH

22 V

SWH

21 V

SWH

20 V

SWH

19 V

SWH

16 V

SWH

18 V

SWH

17 V

SWH

PINOUT CONFIGURATION

SiC632, SiC632A

Vishay Siliconix

PIN CONFIGURATION

PIN NUMBER NAME FUNCTION

1 PWM PWM input logic

2 ZCD_EN# ZCD control. Active low

3V

4, 32 C

5 BOOT High side driver bootstrap voltage

6 N.C. Not connected internally, can be left floating or connected to ground

7 PHASE Return path of high side gate driver

8 to 11, 34 V

12 to 15, 28, 35 P

16 to 26 V

27, 33 GL Low side MOSFET gate signal

29 V

30 THWn Thermal warning open drain output

31 DSBL# Disable pin. Active low

ORDERING INFORMATION

PART NUMBER PACKAGE MARKING CODE OPTION

SiC632CD-T1-GE3 PowerPAK MLP55-31L SiC632 5 V PWM optimized

SiC632ACD-T1-GE3 PowerPAK MLP55-31L SiC632A 3.3 V PWM optimized

SiC632DB / SiC632ADB Reference board

S20-0486-Rev. E, 29-Jun-2020

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Fig. 2 - SiC632 and SiC632A Pin Configuration

CIN

GND

IN

GND

SWH

DRV

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Supply voltage for internal logic circuitry

Signal ground

Power stage input voltage. Drain of high side MOSFET

Power ground

Phase node of the power stage

Supply voltage for internal gate driver

2

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Document Number: 62992

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PART MARKING INFORMATION

P/N

SiC632, SiC632A

Vishay Siliconix

= Pin 1 Indicator

P/N = Part Number Code

= Siliconix Logo

LL

= ESD Symbol

F = Assembly Factory Code

F Y W W

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT

Input voltage V

Control logic supply voltage V

Drive supply voltage V

Switch node (DC voltage)

Switch node (AC voltage)

BOOT voltage (DC voltage)

BOOT voltage (AC voltage)

BOOT to PHASE (DC voltage)

BOOT to PHASE (AC voltage)

All lo gic i npu ts an d o utpu ts
(PWM, DSBL#, and THWn)

Max. operating junction temperature T

Storage temperature T

Electrostatic discharge protection

Notes

• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

(1)

The specification values indicated “AC” is V

(2)

The specification value indicates “AC voltage” is V

(3)

The specification value indicates “AC voltage” is V

(1)

(2)

(3)

Human body model, JESD22-A114 3000

Charged device model, JESD22-C101 1000

to P

SWH

GND

BOOT

BOOT

V

V

BOOT

V

BOOT-PHASE

-8 V (< 20 ns, 10 μJ), min. and 33 V (< 50 ns), max.

to P

, 40 V (< 50 ns) max.

GND

to V

PHASE

Y = Year Code

WW = Week Code

LL = Lot Code

IN

CIN

DRV

SWH

J

A

stg

, 8 V (< 20 ns) max.

-0.3 to +28

-0.3 to +7

-0.3 to +7

-0.3 to +28

-7 to +33

-0.3 to +7

-0.3 to +8

-0.3 to V

-40 to +125

-65 to +150

35

40

150

CIN

V

+ 0.3

°CAmbient temperature T

V

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT

Input voltage (V

Drive supply voltage (V

Control logic supply voltage (V

BOOT to PHASE (V

Thermal resistance from junction to ambient - 10.6 -

Thermal resistance from junction to case - 1.6 -

S20-0486-Rev. E, 29-Jun-2020

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)4.5-24

IN

) 4.555.5

DRV

) 4.555.5

CIN

BOOT-PHASE

, DC voltage) 4 4.5 5.5

3

For technical questions, contact: [e-mail]

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Document Number: 62992

V

°C/W

SiC632, SiC632A

www.vishay.com

ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V

PARAMETER SYMBOL TEST CONDITION

POWER SUPPLY

Control logic supply current I

Drive supply current I

BOOTSTRAP SUPPLY

Bootstrap diode forward voltage V

PWM CONTROL INPUT (SiC632)

Rising threshold V

Falling threshold V

Tri-state voltage V

Tri-state rising threshold V

Tri-state falling threshold V

Tri-state rising threshold hysteresis V

Tri-state falling threshold hysteresis V

PWM input current I

PWM CONTROL INPUT (SiC632A)

Rising threshold V

Falling threshold V

Tri-state Voltage V

Tri-state rising threshold V

Tri-state falling threshold V

Tri-state rising threshold hysteresis V

Tri-state falling threshold hysteresis V

PWM input current I

TIMING SPECIFICATIONS

Tri-state to GH/GL rising
propagation delay

Tri-state hold-off time t

GH - turn off propagation delay t

GH - turn on propagation delay
(dead time rising)

GL - turn off propagation delay t

GL - turn on propagation delay
(dead time falling)

DSBL# Lo to GH/GL falling
propagation delay

PWM minimum on-time t

= 12 V, V

IN

VDRV

TH_PWM_R

TH_PWM_F

TRI_TH_R

TRI_TH_F

HYS_TRI_R

HYS_TRI_F

PWM

TH_PWM_R

TH_PWM_F

TRI_TH_R

TRI_TH_F

HYS_TRI_R

HYS_TRI_F

PWM

t

PD_TRI_R

TSHO

PD_OFF_GH

t

PD_ON_GH

PD_OFF_GL

t

PD_ON_GL

t

PD_DSBL#_F

PWM_ON_MIN

VCIN

F

TRI

TRI

DRV

and V

V

DSBL#

DSBL#

= 5 V, TA = 25 °C)

CIN

= 0 V, no switching, V

= 5 V, no switching, V

V

= 5 V, fS = 300 kHz, D = 0.1 - 525 -

DSBL#

fS = 300 kHz, D = 0.1 - 10 15

f

S

V

DSBL#

V

DSBL#

No load, see Fig. 4

MIN. TYP. MAX.

= FLOAT - 10 -

PWM

= FLOAT - 300 -

PWM

= 1 MHz, D = 0.1 - 35 -

= 0 V, no switching - 15 -

= 5 V, no switching - 55 -

IF = 2 mA 0.4 V

3.4 3.8 4.2

0.72 0.9 1.1

V

= FLOAT - 2.3 -

PWM

0.9 1.15 1.38

33.33.6

- 225 -

- 325 -

V

= 5 V - - 350

PWM

= 0 V - - -350

V

PWM

2.3 2.45 2.7

0.72 0.9 1.1

V

= FLOAT - 1.8 -

PWM

0.9 1.15 1.38

1.95 2.2 2.45

- 250 -

- 300 -

V

= 3.3 V - - 225

PWM

= 0 V - - -225

V

PWM

-30-

- 130 -

-15-

-10-

-13-

-10-

Fig. 5 - 15 -

30 - -

Vishay Siliconix

LIMITS

UNIT

μAV

mA

μA

V

mV

μA

V

mV

μA

ns

S20-0486-Rev. E, 29-Jun-2020

4

Document Number: 62992

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ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V

PARAMETER SYMBOL TEST CONDITION

DSBL# ZCD_EN# INPUT

DSBL# logic input voltage

ZCD_EN# logic input voltage

PROTECTION

Under voltage lockout V

Under voltage lockout hysteresis V
THWn flag set

THWn flag hysteresis
THWn output low V

Notes

(1)

Typical limits are established by characterization and are not production tested

(2)

Guaranteed by design

(2)

(2)

(2)

= 12 V, V

IN

V

IH_DSBL#

V

IL_DSBL#

V

IH_ZCD_EN#

V

IL_ZCD_EN#

UVLO_HYST

T

THWn_SET

T

THWn_CLEAR

T

THWn_HYST

OL_THWn

UVLO

DRV

and V

= 5 V, TA = 25 °C)

CIN

MIN. TYP. MAX.

Input logic high 2 - -

Input logic low - - 0.8

Input logic high 2 - -

Input logic low - - 0.8

V

rising, on threshold - 3.7 4.1

CIN

V

falling, off threshold 2.7 3.1 -

CIN

I

= 2 mA - 0.02 - V

THWn

SiC632, SiC632A

Vishay Siliconix

LIMITS

- 575 - mV

- 160 -

- 135 -

-25-

UNIT

V

V

°CTHWn flag clear

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-State Function

The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V

PWM_TH_R

turned on. When PWM input is driven below V
high side is turned off and the low side is turned on. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shutdown. The high impedance
state of the controller’s PWM output allows the SiC632 and
SiC632A to pull the PWM input into the tri-state region (see
definition of PWM logic and tri-state, Fig. 4). If the PWM
input stays in this region for the tri-state hold-off period,
tTSHO, both high side and low side MOSFETs are turned
off. The function allows the VR phase to be disabled without
negative output voltage swing caused by inductor ringing
and saves a Schottky diode clamp. The PWM and tri-state
regions are separated by hysteresis to prevent false
triggering. The SiC632A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC632 thresholds are compatible with 5 V logic.

Disable (DSBL#)

In the low state, the DSBL# pin shuts down the driver IC and
disables both high side and low side MOSFETs. In this state,
standby current is minimized. If DSBL# is left unconnected,
an internal pull-down resistor will pull the pin to C
shut down the IC.

the low side is turned off and the high side is

GND

the

and

PWM_TH_F

Diode Emulation Mode (ZCD_EN#)

When ZCD_EN# pin is driven below V

IL_ZCD_EN#

. diode
emulation mode is enabled. If the PWM signal switches
below V

TH_PWM_F

then the LS MOSFET is under control of
the ZCD (zero crossing detect) comparator. If, after the
internal blanking delay, the inductor current becomes less
than or = 0 the low side is turned off. Light load efficiency is
improved by avoiding discharge of output capacitors. If both
high side and low side MOSFETs are required to be turned
off, regardless of inductor current, the PWM input should be
tri-stated.

Thermal Shutdown Warning (THWn)

The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 k, to V

. An internal temperature sensor

CIN

detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC632 and SiC632A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.

Voltage Input (V

)

IN

This is the power input to the drain of the high side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.



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DISB#

20K

V

SWH

V

SWH

GL

+

-

GL

+

-

ZCD_EN#

Thermal monitor

& warning

UVLO

V

CIN

PWM logic

control &

state

machine

Anti-cross

conduction

control

logic

BOOT

THWn

V

IN

PWM

C

GND

V

CIN

V

ref

= 1 V

V

ref

= 1 V

P

GND

PHASE

V

DRV

V

DRV

P

GND

SiC632, SiC632A

Vishay Siliconix

Switch Node (V

The switch node, V

and PHASE)

SWH

, is the circuit power stage output.

SWH

This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node V

SWH

. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 k resistor is connected between GH
(the high side gate) and PHASE to provide a discharge path
for the HS MOSFET in the event that V

goes to zero while

CIN

VIN is still applied.

Ground Connections (C

P

(power ground) should be externally connected

GND

to C

(signal ground). The layout of the printed circuit

GND

board should be such that the inductance separating C
and P

is minimized. Transient differences due to

GND

GND

and P

GND

)

GND

inductance effects between these two pins should not
exceed 0.5 V

, V

Control and Drive Supply Voltage Input (V

V

is the bias supply for the gate drive control IC. V

CIN

DRV

CIN

)

DRV

is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.









FUNCTIONAL BLOCK DIAGRAM

Bootstrap Circuit (BOOT)

The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC632 and SiC632A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high side and low side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The high side and low
side gate voltages are monitored to prevent the MOSFET
turning on from tuning on until the other MOSFET's gate
voltage is sufficiently low (< 1 V). Built in delays also ensure
that one power MOSFET is completely off, before the other
can be turned ON. This feature helps to adjust dead time as
gate transitions change with respect to output current and
temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate
drive holding high side and low side MOSFET gates low
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC632,
SiC632A also incorporates logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH (the high side gate) and
PHASE to provide a discharge path for the HS MOSFET.

Fig. 3 - SiC632 and SiC632A Functional Block Diagram

S20-0486-Rev. E, 29-Jun-2020

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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6

Document Number: 62992