D Low 105-mV Dropout at 250-mA Load
D Guaranteed 250-mA Output Current
D 500-mA Peak Output Current Capability
D Uses Low ESR Ceramic Output Capacitor
D Fast Load and Line Transient Response
D Only 100-mV(rms) Noise With Noise Bypass
Capacitor
D 1-mA Maximum Shutdown Current
D Built-in Short Circuit and Thermal Protection
D Out-Of-Regulation Error Flag (Power Good or POR)
DESCRIPTION
Available
Si9182
Vishay Siliconix
D Fixed 1.215-V, 1.5-V, 1.8-V, 2.5-V, 2.8-V, 2.9-V,
3.0-V, 3.3-V, 5.0-V, or Adjustable Output Voltage
Options
D Other Output Voltages Available by Special Order
APPLICATIONS
D Cellular Phones
D Laptop and Palm Computers
D PDA, Digital Still Cameras
The Si9182 is a 250-mA CMOS LDO (low dropout) voltage
regulator. The device features ultra low ground current and
dropout voltage to prolong battery life in portable electronics.
The Si9182 offers line/load transient response and ripple
rejection superior to that of bipolar or BiCMOS LDO regulators.
The device is designed to maintain regulation while delivering
500-mA peak current. This is useful for systems that have high
surge current upon turn-on. The Si9182 is designed to drive
the lower cost ceramic, as well as tantalum, output capacitors.
The device is guaranteed stable from maximum load current
down to 0-mA load. In addition, an external noise bypass
capacitor connected to the device’s C
pin will lower the
NOISE
TYPICAL APPLICATIONS CIRCUITS
18
C
NOISE
27
DELAYERROR
36
GND SENSE/ADJ
45
V
IN
2.2 mF2.2 mF
GND
V
IN
Si9182
FIGURE 1. Fixed OutputFIGURE 2. Adjustable Output
SD
V
OUT
V
OUT
LDO’s output noise for low noise applications.
The Si9182 also includes an out-of-regulation error flag. When
the output voltage is 5% below its nominal output voltage, the
error flag output goes low. If a capacitor is connected to the
device’s delay pin, the error flag output pin will generate a
delayed power-on-reset signal.
The Si9182 is available in both standard and lead (Pb)-free
MSOP-8 packages and is specified to operate over the
industrial temperature range of −40 _C to 85 _C.
18
C
NOISE
27
DELAYERROR
36
GND SENSE/ADJ
45
V
IN
2.2 mF2.2 mF
GND
V
IN
Si9182
SD
V
OUT
V
OUT
Document Number: 71150
S-50955—Rev. H, 16-May-05
18
C
NOISE
27
0.1 mF
V
IN
2.2 mF2.2 mF
GND
0.1 mF
DELAYERROR
36
GND SENSE/ADJ
45
V
IN
Si9182
SD
V
OUT
FIGURE 3. Low Noise, Full Features Application
1 MW
ON/OFF
POR
V
OUT
www.vishay.com
1
Si9182
y
Output Voltage Accuracy
OUT
%/V
Dropout Voltage
d
INOUT
(@
)
(@V
t 2 V, VIN w 2 V)
GND
m
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Input Voltage, V
SD Input Voltage, V
Output Current, I
Output Voltage, V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
Notes
a. Room = 25_C, Full = −40 to 85_C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at V
V
= 3.3 V, while typical values for dropout voltage at V
OUT
d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V
differential, provided that V
e. The device’s shutdown pin includes a typical 6-MW internal pull-down resistor connected to ground.
f.V
g. The Error Output (Low) function is guaranteed from V
h. The Power_Good trip threshold function is guaranteed from V
is defined as the output voltage of the DUT at 1 mA.
OUT
does not not drop below 2.0 V.
IN
OFF
V
V
V
HYST
DELAY
OL
TH
OUT
ERROR= V
I
= 2 mAFull0.4
SINK
< 2 V are measured at V
OUT
= 2.0 V to V
OUT
= 5.0 V.
OUT
= 1.5 V to V
OUT(nom)
= 1.8 V.
OUT
= 5.0 V and VIN w 2.0 V.
OUT
Full0.012mA
Full
Room
0.93 x
V
OUT
0.95 x
V
OUT
2% x
V
OUT
0.97 x
V
OUT
Room1.22.23.0mA
w 2 V are measured at
OUT
mV (rms)
dB
mV
_
_C
V
mA
V
Document Number: 71150
S-50955—Rev. H, 16-May-05
www.vishay.com
3
TIMING WAVEFORMS
V
IN
t
ON
0.95 V
NOM
V
OUTVOUT
ERROR
t
DELAY
FIGURE 4. Timing Diagram for Power-Up
V
Si9182
Vishay Siliconix
NOM
PIN CONFIGURATION
MSOP-8
C
NOISE
DELAYERROR
1
2
GNDSENSE or ADJ
3
V
4
IN
Top View
8
SD
7
6
V
5
OUT
PIN DESCRIPTION
Pin NumberNameFunction
1C
2DELAY
3GNDGround pin. Local ground for C
4V
5V
6SENSE or ADJ
7ERROR
8SDBy applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused.
NOISE
IN
OUT
Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected from this pin
to ground.
Capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (Pin 7) output.
Refer to Figure 4.
and C
NOISE
Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground.
Output voltage. Connect C
For fixed output voltage versions, this pin should be connected to V
this voltage feedback pin sets the output voltage via an external resistor divider.
This open drain output is an error flag output which goes low when V
also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.
between this pin and ground.
OUT
OUT
.
(Pin 5). For adjustable output voltage version,
OUT
drops 5% below its nominal voltage. This pin
OUT
www.vishay.com
4
Document Number: 71150
S-50955—Rev. H, 16-May-05
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