Vishay Si4160DY Datasheet
www.vishay.com
SPICE Device Model Si4160DY
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
DESCRIPTION
The attached SPICE model describes the typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to 125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used
to model the gate charge characteristics while avoiding
convergence difficulties of the switched C
model. All
gd
model parameter values are optimized to provide a best fit
to the measured electrical data and are not intended as an
exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
CHARACTERISTICS
•N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
•Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
D
C
GD
M
2
Gy
–
G
R
G
Note
• This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer
to the appropriate datasheet of the same number for guaranteed specification limits.
+
ETCV
Gx
C
GS
R
1
3
M
1
S
DBD
S12-2653-Rev. B, 05-Nov-12
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1
Document Number: 64670
SPICE Device Model Si4160DY
www.vishay.com
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS
Static
Gate Threshold Voltage V
Drain-Source On-State Resistance
Forward Transconductance
a
R
a
Diode Forward Voltage V
Dynamic
b
Input Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
GS(th)
DS(on)
g
fs
SD
iss
420 406
oss
171 168
rss
g
Gate-Source Charge Qgs 5.1 5.1
Gate-Drain Charge Q
5.2 5.2
gd
VDS = VGS, ID = 250 μA 1.2 V
= 10 V, ID = 15 A 0.0041 0.0040
V
GS
V
= 4.5 V, ID = 10 A 0.0051 0.0051
GS
VDS = 15 V, ID = 15 A 80 60 S
IS = 3 A 0.73 0.73 V
= 15 V, VGS = 0 V, f = 1 MHz
V
DS
= 15 V, VGS = 10 V, ID = 10 A 33 36
V
DS
V
= 15 V, VGS = 4.5 V, ID = 10 A
DS
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
SIMULATED
DATA
2050 2071
17 16.8
Vishay Siliconix
MEASURED
DATA
UNIT
pF Output Capacitance C
nC
S12-2653-Rev. B, 05-Nov-12
2
Document Number: 64670
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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