Datasheet Si3456BDV Datasheet (Vishay) [ru]

N-Channel 30-V (D-S) MOSFET

T

Si3456BDV

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

30

0.035 at V

0.052 at V

TSOP-6

Top View

1

3 mm

Ordering Information: Si3456BDV-T1-E3 (Lead (Pb)-free)

Marking Code:

2

3

2.85 mm

Si3456BDV-T1-GE3 (Lead (Pb)-free and Halogen-free)

6Bxxx

(Ω)I

DS(on)

= 10 V

GS

= 4.5 V

GS

6

5

4

D

(A)

6.0

4.9

FEATURES

• Halogen free According to IEC 61249-2-21
Definition

• TrenchFET

• 100 % R

• Compliant to RoHS Directive 2002/95/EC

®

Power MOSFET

Tested

g

(3) G

(1, 2, 5, 6) D

(4) S

N-Channel MOSFE

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 5 s Steady State Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

J

a

Pulsed Drain Current

Continuous Source Current (Diode Conduction)

Maximum Power Dissipation

a

a

Operating Junction and Storage Temperature Range

TA = 25 °C

= 70 °C

T

A

TA = 25 °C

= 70 °C

T

A

V

DS

V

GS

I

D

I

DM

I

S

P

D

, T

T

J

stg

6.0 4.5

4.8 3.6

1.7 0.9

2.0 1.1

1.3 0.7

30

± 20

± 30

W

- 55 to 150 °C

V

A

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

a

t ≤ 5 s

Steady State 92 110

Maximum Junction-to-Foot (Drain) Steady State

Notes:
a. Surface Mounted on 1" x 1" FR4 board.

Document Number: 72544
S09-0530-Rev. D, 06-Apr-09

R

thJA

R

thJF

55 62.5

°C/W

28 40

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Si3456BDV

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

V

Gate Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

a

Drain-Source On-State Resistance

Forward Transconductance

Diode Forward Voltage

Dynamic

b

a

a

Total Gate Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n D el a y T im e

Rise Time

Turn-Off Delay Time

Fall Time

Source-Drain Reverse Recovery Time

V

GS(th)

I

GSS

I

DSS

I

V

D(on)

a

R

DS(on)

g

fs

V

SD

Q

g

Q

gs

Q

gd

R

g

t

d(on)

t

r

t

d(off)

t

f

t

rr

V

VDS = 15 V, V

I

Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functiona l operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

= VGS, ID = 250 µA

DS

VDS = 0 V, VGS = ± 20 V

V

= 30 V, V

DS

= 30 V, V

DS

GS

≥ 5 V, V

DS

V

= 10 V, ID = 6 A

GS

V

= 4.5 V, ID = 4.9 A

GS

= 0 V

GS

= 0 V, TJ = 55 °C

= 10 V

GS

VDS = 15 V, ID = 6 A

IS = 1.7 A, V

= 0 V

GS

= 10 V, ID = 6 A

GS

f = 1 MHz 1.4 2.8 4.8 Ω

V

= 15 V, RL = 15 Ω

DD

≅ 1 A, V

D

= 10 V, Rg = 6 Ω

GEN

IF = 1.7 A, dI/dt = 100 A/µs

1.0 3.0 V

± 100 nA

1

5

30 A

0.028 0.035

0.041 0.052

12 S

0.8 1.2 V

8.6 13

1.8

nCGate-Source Charge

1.5

10 15

15 25

25 40

10 15

20 40

µA

Ω

ns

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

40

35

30

25

20

15

- Drain Current (A)I

D

10

5

0

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2

012345

VGS = 10 V thru 6 V

- Drain-to-Source Voltage (V)

V

DS

Output Characteristics

5 V

4 V

3 V

40

35

30

25

20

15

- Drain Current (A)I

D

10

5

0

0123456

- Gate-to-Source Voltage (V)

V

GS

TC = - 55 °C

25 °C

Transfer Characteristics

Document Number: 72544

S09-0530-Rev. D, 06-Apr-09

125 °C

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si3456BDV

Vishay Siliconix

- On-Resistance (Ω)R

DS(on)

0.10

0.08

0.06

VGS = 4.5 V

0.04

0.02

0.00
0 5 10 15 20 25 30 35 40

ID - Drain Current (A)

VGS = 10 V

On-Resistance vs. Drain Current

10

VDS = 15 V
I

= 6 A

D

8

6

800

700

600

500

400

300

C - Capacitance (pF)

200

100

C

rss

0

0 5 10 15 20 25 30

1.6

VGS = 10 V
I

1.4

1.2

C

iss

C

oss

V - Drain-to-Source Voltage (V)

DS

Capacitance

= 6 A

D

- Gate-to-Source Voltage (V)

GS

V

- Source Current (A)I

S

4

2

0

0246810

Qg - Total Gate Charge (nC)

Gate Charge

40

TJ = 150 °C

10

TJ = 25 °C

1

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

VSD - Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

- On-Resistance

1.0

(Normalized)

DS(on)

R

0.8

0.6

- 50 - 25 0 25 50 75 100 125 150

0.10

0.08

0.06

0.04

- On-Resistance (Ω)R

DS(on)

0.02

0.00
024681

-

T

Junction Temperature (°C)

J

On-Resistance vs. Junction Temperature

ID = 6 A

VGS - Gate-to-Source Voltage (V)

On-Resistance vs. Gate-to-Source Voltage

0

Document Number: 72544
S09-0530-Rev. D, 06-Apr-09

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Si3456BDV

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.4

0.2

ID = 250 µA

0.0

- 0.2

Variance (V)V

GS(th)

- 0.4

- 0.6

- 0.8

- 50 - 25 0 25 50 75 100 125 150

TJ - Temperature ( °C)

Threshold Voltage

100

- Drain Current (A)

D

I

0.01

50

40

30

Power (W)

20

10

0

-

3

10

IDMLimited

P(t) = 0.0001 s

P(t) = 0.001 s

P(t) = 0.01 s

P(t) = 0.1 s
P(t) = 1 s

P(t) = 10 s
DC

Limited by R

10

1

0.1

I

D(on)

Limited

TA = 25 °C

Single Pulse

DS(on)

10

*

BVDSS Limited

0.1 1 10 100

VDS- Drain-to-Source Voltage (V)

> minimum VGSat which R

*V

GS

DS(on)

is specified

Safe Operating Area

-

-

2

1

Single Pulse Power

1 100 6001010

Time (s)

0.1

Thermal Impedance

Normalized Effective Transient

0.01

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4

2

1

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

-

4

10

Single Pulse

-

3

10

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

- TA = PDMZ

JM

4. Surface Mounted

-

2

10

-

1

1 10 60010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

t

1

t

2

t

1

t

2

= 92 °C/W

thJA

(t)

thJA

100

Document Number: 72544

S09-0530-Rev. D, 06-Apr-09

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

2

1

Duty Cycle = 0.5

0.2

0.1

0.1

Thermal Impedance

Normalized Effective Transient

0.05

0.02

Si3456BDV

Vishay Siliconix

0.01

Single Pulse

4

-

10

- 3

10

- 2

10

Square Wave Pulse Duration (s)

-1

11010

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72544

Document Number: 72544

.

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S09-0530-Rev. D, 06-Apr-09

5

TSOP: 5/6−LEAD

JEDEC Part Number: MO-193C

Package Information

Vishay Siliconix

e1

5 4

1

2

e

b

E 1 E

3

-B-

C 0.15 M B A

6 5 4

1

5-LEAD TSOP 6-LEAD TSOP

4x

R

4x

-C-

-A-

A 2 A

A

1

R

Seating Plane

D

C 0.08

e1

E 1 E

2

e

1

1

b

(L 1 )

3

-B-

C 0.15 M B A

0.17 Ref
c

L

2

Gauge Plane

Seating Plane

L

Document Number: 71200
18-Dec-06

MILLIMETERS INCHES

Dim Min Nom Max Min Nom Max

0.91 - 1.10 0.036 - 0.043

A

0.01 - 0.10 0.0004 - 0.004

A

1

0.90 - 1.00 0.035 0.038 0.039

A

2

0.30 0.32 0.45 0.012 0.013 0.018

b

0.10 0.15 0.20 0.004 0.006 0.008

c

2.95 3.05 3.10 0.116 0.120 0.122

D

2.70 2.85 2.98 0.106 0.112 0.117

E

1.55 1.65 1.70 0.061 0.065 0.067

E

1

e

e

1

L

L

1

L

2

R

1

ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540

0.95 BSC 0.0374 BSC

1.80 1.90 2.00 0.071 0.075 0.079

0.32 - 0.50 0.012 - 0.020

0.60 Ref 0.024 Ref

0.25 BSC 0.010 BSC

0.10 - - 0.004 - -

0 4 8 0 4 8

7 Nom 7 Nom

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Vishay Siliconix

Mounting LITTLE FOOTR TSOP-6 Power MOSFETs

AN823

Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.

The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see

http://www.vishay.com/doc?72610 for the minimum pad footprint.

In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.

In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are

0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.

Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.

Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.

0.167

4.25

0.074

0.010

0.25

1.875

0.122

3.1

0.014

0.35

0.026

0.65

0.049

0.049

1.25

1.25

FIGURE 1. Recommended Copper Spreading Footprint

Document Number: 71743
27-Feb-04

Ramp-Up Rate

Temperature @ 155 " 15_C

Temperature Above 180_C

Maximum Temperature

Time at Maximum Temperature 20 − 40 Seconds

Ramp-Down Rate

FIGURE 2. Solder Reflow Temperature Profile

+6_C/Second Maximum

120 Seconds Maximum

70 − 180 Seconds

240 +5/−0_C

+6_C/Second Maximum

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AN823

Vishay Siliconix

10 s (max)

255 − 260_C

1X4_C/s (max) 3-6_C/s (max)

140 − 170_C

3_C/s (max)

Maximum peak temperature at 240_C is allowed.

60-120 s (min)

Pre-Heating Zone

FIGURE 3. Solder Reflow Temperature and Time Durations

THERMAL PERFORMANCE

A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rq

, or the

jc

junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.

TABLE 1.

Equivalent Steady State Performance—TSOP-6

Thermal Resistance Rq

jf

30_C/W

1.6

1.4

1.2

− On-Resiistance

1.0

(Normalized)

DS(on)

r

0.8

217_C

60 s (max)

Reflow Zone

On-Resistance vs. Junction Temperature

VGS = 4.5 V

= 6.1 A

I

D

SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6

In any design, one must take into account the change in
MOSFET r

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2

with temperature (Figure 4).

DS(on)

0.6

−50 −25 0 25 50 75 100 125 150

T

− Junction Temperature (_C)

J

FIGURE 4. Si3434DV

Document Number: 71743

27-Feb-04

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR TSOP-6

0.099

(2.510)

Return to Index

Return to Index

0.119
(3.023)

0.039

(1.001)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.020

(0.508)

0.019

(0.493)

0.064

0.028

(1.626)

(0.699)

APPLICATION NOTE

www.vishay.com Document Number: 72610
26 Revision: 21-Jan-08

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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12

1

Document Number: 91000