Vishay IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L Data Sheet

N-Channel MOSFET

G

D

S

D2PAK (TO-263)

G

D

S

I2PAK (TO-262)

G

D

S

IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 60

()V

R

DS(on)

Q

(Max.) (nC) 35

g

Q

(nC) 7.1

gs

Q

(nC) 25

gd

Configuration Single

= 5 V 0.05

GS

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Advanced Process Technology

• Surface Mount (IRLZ34S, SiHLZ34S)

• Low-Profile Through-Hole (IRLZ34L, SiHLZ34L)

• 175 °C Operating Temperature

•Fast Switching

• Fully Avalanche Rated

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation Power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast swichting speed and ruggedized device design that
Power MOSFETs are known for, provides the designer with
an extremely efficient and reliable device for use in a wide
variety of applications.

2

The D

PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The

2

D

PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0 W in a typical surface mount application.
The through-hole version (IRLZ34L, SiHLZ34L) is available
for low-profile applications.

ORDERING INFORMATION

Package D2PAK (TO-263) I2PAK (TO-262)
Lead (Pb) free and Halogen-free SiHLZ34S-GE3 -

Lead (Pb) free

- IRLZ34LPbF

- SiHLZ34L-E3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V
Gate-Source Voltage V

= 25 °C

T

Continuous Drain Current V

Pulsed Drain Current
Linear Derating Factor 0.59 W/°C
Single Pulse Avalanche Energy
Maximum Power Dissipation T
Maximum Power Dissipation (PCB Mount)
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Recommendations (Peak Temperature) for 10 s 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

= 25 V, Starting TJ = 25 °C, L = 285 μH, Rg = 25 , IAS = 30 A (see fig. 12).

b. V

DD

 30 A, dI/dt  200 A/μs, VDD  VDS, TJ  175 °C.

c. I

SD

d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).

a

b

e

c

GS

at 5 V

C

= 100 °C 21

C

= 25 °C

C

TA = 25 °C 3.7

DS

± 10

GS

I

D

IDM 110

E

AS

P

D

dV/dt 4.5 V/ns

, T

J

stg

60

30

128 mJ

88

- 55 to + 175

d

V

AT

W

°C

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 90418
S11-1044-Rev. D, 30-May-11 1

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com

www.vishay.com/doc?91000

S

D

G

IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Maximum Junction-to-Ambient
(PCB Mount)

a

Maximum Junction-to-Case (Drain) R

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.07 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Source Inductance L

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

a

R

thJA

thJC

DS

GS(th)

V

GSS

--40
°C/W

--1.7

VGS = 0, ID = 250 μA 60 - - V

VDS = VGS, ID = 250 μA 1.0 - 2.0 V

= ± 10 V - - ± 100 nA

GS

VDS = 60 V, VGS = 0 V - - 25

DSS

DS(on)

fs

iss

- 660 -

oss

- 170 -

rss

g

--7.1

gs

--25

gd

d(on)

r

-30-

d(off)

-56-

f

S

S

I

SM

SD

rr

rr

on

V

= 48 V, VGS = 0 V, TJ = 150 °C - - 250

DS

= 5 V ID = 18 A

V

GS

V

= 4 V ID = 15 A

GS

b

b

- - 0.05

- - 0.07

VDS = 25 V, ID = 18 A 12 - - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

- 1600 -

--35

= 30 A, VDS = 48 V,

I

V

GS

= 5 V

D

see fig. 6 and 13

b

-14-

= 30 V, ID = 30 A,

V

DD

R

= 6 , RD = 1 , see fig. 10

g

Between lead,

and center of die contact

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IS = 30 A, VGS = 0 V

TJ = 25 °C, IF = 30 A, dI/dt = 100 A/μs

b

b

- 170 -

-7.5-nH

--30

- - 110

--1.6V

- 120 180 ns

b

- 700 1300 nC

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

μA



pFOutput Capacitance C

nC Gate-Source Charge Q

ns

A

www.vishay.com Document Number: 90418
2 S11-1044-Rev. D, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 - Typical Output Characteristics, T

= 175 °C

C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 90418 www.vishay.com
S11-1044-Rev. D, 30-May-11 3

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

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V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

g

5 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveforms

Document Number: 90418 www.vishay.com
S11-1044-Rev. D, 30-May-11 5

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

R

g

I

AS

0.01 W

t

p

D.U.T.

L

V

DS

+

-

V

DD

5 V

Var y t

p

to obtain

required I

AS

Q

GS

Q

GD

Q

G

V

G

Charge

5 V

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L

Vishay Siliconix

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

V

DS

t

p

V

DS

I

AS

V

DD

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

www.vishay.com Document Number: 90418
6 S11-1044-Rev. D, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L

Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

• dV/dt controlled by R

• Driver same type as D.U.T.

I

controlled by duty factor “D”

•

SD

• D.U.T. - device under test

-

D =

g

Period

P.W.

+

+

V

DD

-

= 10 Va

V

GS

D.U.T. l

Reverse
recovery
current

D.U.T. V

Re-applied
voltage

Inductor current

Note

a. V

waveform

SD

Body diode forward

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

current

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90418

.

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This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12

1

Document Number: 91000