Vishay IRFPS40N60K, SiHFPS40N60K Data Sheet

IRFPS40N60K, SiHFPS40N60K
N-Channel MOSFET
G
D
S
Available
RoHS*
COMPLIANT
Power MOSFET
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) 600
()V
R
DS(on)
Q
(Max.) (nC) 330
g
Q
(nC) 84
gs
Q
(nC) 150
gd
Configuration Single
= 10 V 0.110
GS
FEATURES
• Low Gate Charge Qg Results in Simple Drive Requirement
• Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage and Current
• Enhanced Body Diode dV/dt Capability
• Compliant to RoHS Directive 2002/95/EC
Super-247
APPLICATIONS
• Hard Switching Primary or PFC Switch
• Switch Mode Power Supply (SMPS)
S
D
G
• Uninterruptible Power Supply
• High Speed Power Switching
• Motor Drive
ORDERING INFORMATION
Package Super-247
Lead (Pb)-free
SnPb
IRFPS40N60KPbF
SiHFPS40N60K-E3
IRFPS40N60K
SiHFPS40N60K
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage V
T
= 25 °C
Continuous Drain Current V
Pulsed Drain Current
a
at 10 V
GS
C
= 100 °C 24
C
DS
± 30
GS
I
D
IDM 160
Linear Derating Factor 4.5 W/°C
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Peak Diode Recovery dV/dt
b
a
a
= 25 °C P
c
C
Operating Junction and Storage Temperature Range T
E
AS
I
AR
E
AR
D
dV/dt 7.5 V/ns
, T
J
stg
Soldering Recommendations (Peak Temperature) for 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting T c. I
SD
d. 1.6 mm from case.
= 25 °C, L = 0.84 mH, Rg = 25 , IAS = 38 A, dV/dt = 5.5 V/ns (see fig. 12a).
J
38 A, dI/dt 150 A/μs, VDD VDS, TJ 150 °C.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91261 www.vishay.com S11-0112-Rev. B, 31-Jan-11 1
600
40
600 mJ
40 A
57 mJ
570 W
- 55 to + 150
d
V
AT
°C
IRFPS40N60K, SiHFPS40N60K
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient R
Maximum Junction-to-Case (Drain) R
thJA
thCS
thJC
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
V
Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.63 - V/°C
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
Dynamic
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Output Capacitance C
Effective Output Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
a
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
Body Diode Recovery Current I
Forward Turn-On Time t
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. c. C
eff. is a fixed capacitance that gives the same charging time as C
oss
DS
GS(th)
V
GSS
DSS
VGS = 10 V ID = 24 A
DS(on)
fs
iss
- 750 -
oss
-75-
rss
oss
eff. VDS = 0 V to 480 V
oss
g
--84
gs
- - 150
gd
d(on)
r
-97-
d(off)
-60-
f
S
V
V
GS
V
GS
MOSFET symbol showing the integral reverse
I
SM
SD
rr
RRM
on
rr
p - n junction diode
TJ = 25 °C
T
= 125 °C - 730 1090
J
TJ = 25 °C - 14 20
T
= 125 °C - 17 25
J
-40
0.24 -
°C/WCase-to-Sink, Flat, Greased Surface R
-0.22
VGS = 0 V, ID = 250 μA 600 - - V
VDS = VGS, ID = 250 μA 3.0 - 5.0 V
= ± 30 V - - ± 100 nA
GS
VDS = 600 V, VGS = 0 V - - 50
= 480 V, VGS = 0 V, TJ = 125 °C - - 250
DS
VDS = 50 V, ID = 24 A
VGS = 0 V,
V
= 25 V,
DS
f = 1.0 MHz, see fig. 5
V
DS
= 0 V
V
DS
= 1.0 V , f = 1.0 MHz - 9440 -
= 480 V , f = 1.0 MHz - 200 -
b
b
- 0.110 0.130
21 - - S
- 7970 -
c
- 260 -
- - 330
I
= 38 A, VDS = 480 V,
D
see fig. 6 and 13
= 10 V
= 300 V, ID = 38 A,
V
DD
R
= 4.3 , see fig. 10
G
TJ = 25 °C, IS = 38 A, VGS = 0 V
b
-47-
- 110 -
b
D
G
S
b
--40
- - 160
--1.5V
- 630 950
= 38 A, dI/dt = 100
I
F
A/μs
TJ = 25 °C - 39 58 A
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
while VDS is rising from 0 % to 80 % VDS.
oss
μA
pF
nC Gate-Source Charge Q
ns
A
ns
μC
www.vishay.com Document Number: 91261 2 S11-0112-Rev. B, 31-Jan-11
IRFPS40N60K, SiHFPS40N60K
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.001
0.01
0.1
1
10
100
1000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
4.5V
20μs PULSE WIDTH Tj = 25°C
VGS TOP 15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V BOTTOM 4.5V
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
4.5V
20μs PULSE WIDTH Tj = 150°C
VGS TOP 15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V BOTTOM 4.5V
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Vishay Siliconix
1000
Fig. 1 - Typical Output Characteristics
100
10
1
0.1
D
I , Drain-to-Source Current (A)
0.01 4 6 8 10 11 13 15
°
T = 150 C
J
°
T = 25 C
J
V , Gate-to-Source Voltage (V)
GS
V = 50V
DS
20μs PULSE WIDT H
Fig. 3 - Typical Transfer Characteristics
3.5
38A
I =
D
3.0
2.5
2.0
Fig. 2 - Typical Output Characteristics
Document Number: 91261 www.vishay.com S11-0112-Rev. B, 31-Jan-11 3
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
V =
GS
°
Fig. 4 - Normalized On-Resistance vs. Temperature
10V
IRFPS40N60K, SiHFPS40N60K
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
100000
C
,
C
a
p
a
c
i
t
a
n
c
e
(
p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ C
iss
= C
gs
+ Cgd, C
ds
SHORTED
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
0 50 100 150 200 250
0
2
5
7
10
12
Q , Total Gate Charge ( nC)
V , Gate-to-Source Voltage (V)
G
GS
I =
D
38A
V = 120V
DS
V = 300V
DS
V = 480V
DS
0.1
1
10
100
1000
0.2 0.6 0.9 1.3 1.6
V ,Source- to-Drain Vol tage ( V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 150 C
J
°
T = 25 C
J
°
1 10 100 1000 10000
VDS, Drain-toSource Voltage (V)
0.1
1
10
100
1000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
Tc = 25°C Tj = 150°C Single Pulse
1msec
10msec
OPERATION IN THIS AREA LIMITED BY RDS(on)
100μsec
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
www.vishay.com Document Number: 91261 4 S11-0112-Rev. B, 31-Jan-11
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
IRFPS40N60K, SiHFPS40N60K
25 50 75 100 125 150
0
10
20
30
40
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
0.001
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
J DM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
Vishay Siliconix
R
D.U.T.
D
+
V
-
DD
V
DS
V
GS
R
G
10 V
Pulse width 1 µs Duty factor 0.1 %
Fig. 10a - Switching Time Test Circuit
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91261 www.vishay.com S11-0112-Rev. B, 31-Jan-11 5
IRFPS40N60K, SiHFPS40N60K
A
R
G
I
AS
0.01 Ω
t
p
D.U.T.
L
V
DS
+
-
V
DD
Driver
15 V
20 V
25 50 75 100 125 150
0
240
480
720
960
1200
Starti ng Tj , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
AS
°
I
D
TOP
BOTTOM
17A
24A
38A
-75 -50 -25 0 25 50 75 100 125 150
TJ , Temperature ( °C )
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
G
S
(
t
h
)
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
ID= 250μA
Q
GS
Q
GD
Q
G
V
G
Charge
V
GS
V
D.U.T.
3 mA
V
GS
V
DS
I
G
I
D
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Vishay Siliconix
Fig. 12a - Unclamped Inductive Test Circuit
V
DS
t
p
Fig. 12d - Threshold Voltage vs. Temperature
I
AS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
www.vishay.com Document Number: 91261 6 S11-0112-Rev. B, 31-Jan-11
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
P.W.
Period
dI/dt
Diode recovery
dV/dt
Ripple 5 %
Body diode forward drop
Re-applied voltage
Reverse recovery current
Body diode forward
current
V
GS
= 10 Va
I
SD
Driver gate drive
D.U.T. l
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D =
P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
V
DD
dV/dt controlled by R
g
Driver same type as D.U.T.
I
SD
controlled by duty factor “D”
D.U.T. - device under test
D.U.T.
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
R
g
Note
a. V
GS
= 5 V for logic level devices
V
DD
IRFPS40N60K, SiHFPS40N60K
Vishay Siliconix
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91261
Document Number: 91261 www.vishay.com S11-0112-Rev. B, 31-Jan-11 7
.
Fig. 14 - For N-Channel
TO-274AA (HIGH VOLTAGE)
B
E4
E
R
Package Information
Vishay Siliconix
A
A
A1
E1
D2
D
L1
L
e
10°
Detail “A”
b
0.10 (0.25)
Lead Tip
MM
B A
C
A2
b2
Detail “A”
Scale: 2:1
b4
D1
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.70 5.30 0.185 0.209 D1 15.50 16.10 0.610 0.634
A1 1.50 2.50 0.059 0.098 D2 0.70 1.30 0.028 0.051
A2 2.25 2.65 0.089 0.104 E 15.10 16.10 0.594 0.634
b 1.30 1.60 0.051 0.063 E1 13.30 13.90 0.524 0.547
b2 1.80 2.20 0.071 0.087 e 5.45 BSC 0.215 BSC
b4 3.00 3.25 0.118 0.128 L 13.70 14.70 0.539 0.579
c 0.80 1.20 0.031 0.047 L1 1.00 1.60 0.039 0.063
D 19.80 20.80 0.780 0.819 R 2.00 3.00 0.079 0.118
ECN: S-82247-Rev. A, 06-Oct-08 DWG: 5975
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outer extremes of the plastic body.
3. Outline conforms to JEDEC outline to TO-274AA.
Document Number: 91365 www.vishay.com Revision: 06-Oct-08 1
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Vishay
Disclaimer
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Revision: 13-Jun-16
1
Document Number: 91000
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