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DG536
Technical data
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VISHAY DG535, DG536 Technical data

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Vishay Siliconix
16-Channel Wideband Video Multiplexers
FEATURES BENEFITS APPLICATIONS
DG535/536
DS(on)
: 50
D On-Board Address Latches
D High Video Quality D Reduced Insertion Loss D Reduced Input Buffer
Requirements
D Minimizes Power Consumption D Simplifies Bus Interface
D Disable Output
DESCRIPTION
The DG535/536 are 16-channel multiplexers designed for routing one of 16 wideband analog or digital input signals to a single output. T hey f eature l ow i nput and output c apacitance, l ow on-resistance, and n-channel DMOS “T” switches, resulting in wide bandwidth, low crosstalk and high “off” isolation. In the on state, the sw itches p ass s ignals i n e ither d irection, a llowing t hem to be used as multiplexers or as demultiplexers.
On-chip address latches and decode logic simplify microprocessor interface. Chip Select and Enable inputs simplify addressing in large matrices. Single-supply operation
D Video Switching/Routing D High Speed Data Routing D RF Signal Multiplexing D Precision Data Acquisition D Crosspoint Arrays D FLIR Systems
and a low 75-W power consumption vastly reduces power supply requirements.
Theses devices are built on a proprietary D/CMOS process which creates low-capacitance DMOS FETs and high-speed, low-power CMOS logic on the same substrate.
For more information please refer to Vishay Siliconix Application Note AN501 (FaxBack document number 70608).
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
GND S
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
DIS V+
CS CS A EN A
A
0
DG535
1 2 3 4 5 6 7 8
920 10 19 11 12 13 16 14 15
Latches/Decoders/Drivers
Top View
Dual-In-Line
28
9
S
27
10
S
26
11
S
25
12
S
24
13
S
23
14
S
22
15
S
21
16
D
ST
18 17
3
2
A
1
DIS S
7
CS GND
8
CS S
9
EN GND
10
A
11
0
A
12
1
A
13
2
A
14
3
ST S
15
V+ GND
16
DS
17
DG536
PLCC/Cerquad
1
2
3
4
GNDGND
S
GNDGND
S15GNDGND
S14GNDGND
6 5 4 3 2 1 44 43 42 41 40
Latches/
Decoders/
Drivers
18 19 20 21 22 23 24 25 26 27 28
16
S
S
S
Top View
S13GNDGND
S
5
S12GNDGND
S
39
6
38 37
7
36
S
35
8
GND
34
S
33
9
GND
32 31
10
30 29
11
Document Number: 70070 S-02315—Rev. D, 05-Oct-00
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5-1
DG535/536
–55 to 125 C
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION
ORDERING INFORMATION
Temperature Range Package Part Number
_
–40 to 85_C
–55 to 125_C
EN CS CS ST
0 X X X 0 X X X 1
1 1 0 1
X X X 0 X X X X
Notes: a. Strobe input (ST) is level triggered. b. Low Z, High Z = impedance of Disable Output to GND. Disable output
sinks current when any channel is selected.
a
1 X X X X None High Z
A
3
0 0 0 0 S 0 0 0 1 S 0 0 1 0 S 0 0 1 1 S 0 1 0 0 S 0 1 0 1 S 0 1 1 0 S 0 1 1 1 S 1 0 0 0 S 1 0 0 1 S 1 0 1 0 S 1 0 1 1 S 1 1 0 0 S 1 1 0 1 S 1 1 1 0 S 1 1 1 1 S
28-Pin Plastic DIP DG535DJ
44-Pin PLCC DG536DN
28-Pin Sidebraze
44-Pin Cerquad DG536AM/883
TRUTH TABLE
A
2
Logic “0” = V
Logic “1” = V
X = Don’t Care
v 4.5 V
AL
w 10.5 V
AH
A
1
DG535AP DG535AP/883
A
0
Channel
Selected
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
Maintains previous
switch condition
Disable
Low Z
High Z
or
Low Z
b
ABSOLUTE MAXIMUM RATINGS
V+ to GND –0.3 V to +18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputs (GND – 0.3 V) to (V+ plus 2 V ) or. . . . . . . . . . . . . . . . . . . . . . . .
, V
V
S
D
Current (any terminal) Continuous 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current (S or D) Pulsed 1 ms 10% duty cycle 40 mA. . . . . . . . . . . . . . . . . . . .
Storage Temperature (A Suffix) –65 to 150_C. . . . . . . . . . . . . . . . . . . .
Power Dissipation (Package) 28-Pin Plastic DIP
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b
(D Suffix) –65 to 125_C. . . . . . . . . . . . . . . . . . . .
a
5-2
20 mA, whichever occurs first
(GND – 0.3 V) to V+ plus 2 V) or. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 mA, whichever occurs first
28-Pin Sidebraze 44-Pin PLCC 44-Pin Cerquad
Notes: a. All leads soldered or welded to PC board. b. Derate 8.6 mW/_C above 75_C. c. Derate 16 mW/_C above 75_C.
625 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
d. Derate 6 mW/_C above 75_C. e. Derate 11 mW/_C above 75_C.
c
d
e
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
1200 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
825 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG535/536
RIN = 75
R
= R
= 75
Vishay Siliconix
SPECIFICATIONS
Parameter Symbol
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, ST, CS = 10.5 V
= 4.5 V, VA = 4.5 or 10.5 V
CS
f
TempbTypcMincMaxcMincMaxcUnit
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
Analog Switch
Analog Signal Range Drain-Source
On-Resistance Resistance Match Source Off
Leakage Current Drain On
Leakage Current Disable Output R
e
V
ANALOG
r
DS(on)
r
DS(on)
I
S(off)
I
D(on)
DISABLE
IS = –1 mA, VD = 3 V
EN = 10.5 V
EN = 10.5 V
Sequence Each Switch On
VS = 3 V, VD = 0 V, EN = 4.5 V
VS = VD = 3 V, EN = 10.5 V
I
= 1 mA, EN = 10.5 V
DISABLE
Full 0 10 0 10 V
Room
Full
55 90
120
90
120 Room 9 9 Room
Full
Room
Full
Room
Full
100 200
–10
–10010100
–10
–1000101000
250
–10
–10010100
–10
–100
–10
–100
200
250
nA
Digital Control
Input Voltage High V Input Voltage Low V
Address Input Current I
Address Input Capacitance
AIH AIL
AI
C
A
VA = GND or V+
Full 10.5 10.5 V Full 4.5 4.5
Room
Full
<0.01 –1
–1001100–1–1001100
Full 5 pF
A
Dynamic Characteristics
PLCC Room 32 45 45
On State Input Capacitance
Capacitance
Off State Input Capacitance
Capacitance
Off State Output Capacitance
Capacitance
e
e
e
e
e
e
Multiplexer Switching Time t Break-Before-Make
Interval EN, CS, CS, ST, t EN, CS, CS, ST, t
ON OFF
C
S(on)
S(on) D S
C
S(off)
S(off) S
C
D(off)
D(off) D
TRANS
t
OPEN
t
ON
t
OFF
VD = VS = 3 V
VS = 3 V
VD = 3 V
See Figure 4
See Figure 2 and 3 Full 300 300
See Figure 2 Full 150 150
Charge Injection Q See Figure 5 Room –35 pC
Single-Channel Crosstalk X
Chip Disabled Crosstalk X
TALK(SC)
TALK(SC)
TALK(CD)
TALK(CD)
RIN = 75
RL = 75
f = 5 MHz
f = 5 MHz
See Figure 9
R
IN
IN
f = 5 MHz
EN = 4.5 V
EN = 4.5 V
See Figure 8
= RL = 75
L
Cerquad Room 35
DIP Room 40 55 55
PLCC Room 2 8 8
Cerquad Room 5
DIP Room 3
PLCC Room 8 20 20
Cerquad Room 12
DIP Room 9
Full 300 300
Full 25 25
PLCC Room –100
Cerquad Room –93
DIP Room –60
PLCC Room –85
Cerquad Room –84
DIP Room –60
pF
ns
dB
Document Number: 70070 S-02315—Rev. D, 05-Oct-00
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5-3
DG535/536
RIN = 10
RIN = 10
Vishay Siliconix
SPECIFICATIONS
Parameter Symbol
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, ST, CS = 10.5 V
= 4.5 V, VA = 4.5 or 10.5 V
CS
f
TempbTypcMincMaxcMincMaxcUnit
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
Dynamic Characteristics (Cont’d)
PLCC Room –92
Cerquad Room –87
DIP Room –72
PLCC Room –74 –60 –60
Cerquad Room –74
DIP Room –60
Room 500 MHz
Adjacent Input Crosstalk X
All Hostile Crosstalk
Bandwidth BW
e
TALK(AI)
TALK(AI)
X
TALK(AH)
TALK(AH)
RIN = 10 RL = 10 k
f = 5 MHz
f = 5 MHz
See Figure 10
RIN = 10 RL = 10 k
f = 5 MHz
f = 5 MHz
See Figure 7
RL = 50 , See Figure 6
Power Supplies
Positive Supply Current I+ Supply Voltage Range V+ Full 10 16.5 10 16.5 V
Any One Channgel Selected with
All Logic Inputs at GND or V+
Room
Full
5 50
100
50
100
Minimum Input Timing Requirements
Strobe Pulse Width t A0, A1, A2, A3 CS, CS, EN
Data Valid to Strobe A0, A1, A2, A3 CS, CS, EN
Data Valid after Strobe
SW
t
DW
t
WD
See Figure 1
Full 200 200 Full 100 100
Full 50 50
dB
A
ns
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V
= input voltage to perform proper function.
A
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
r
vs. VD and Temperature r
400
)
360 320 280 240 200 160 120
80
– Drain-Source On-Resistance (
40
DS(on)
r
0
010
DS(on)
V+ = +15 V GND = 0 V
300
)
270 240 210
125_C
25_C
–55_C
8642
VD – Drain Voltage (V) VD – Drain Voltage (V)
180 150 120
90 60
– Drain-Source On-Resistance (
30
DS(on)
r
0
010
vs. VD and Power Supply Voltage
DS(on)
GND = 0 V T
= 25_C
A
8 V
12 V
15 V
8642
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5-4
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
DG535/536
Vishay Siliconix
(V)
th
V
– LeakageI
D(on)
 
100 nA
10 nA
1 nA
100 pA
10
9 8 7 6 5 4 3 2 1 0
Logic Input Switching Threshold
vs. Supply Voltage (V+)
GND = 0 V T
= 25_C
A
8
10 12 14 16 18
V+ – Positive Supply (V) V+ – Positive Supply (V)
I
vs. Temperature Leakage Current vs. Temperature
D(on)
V+ = +15 V GND = 0 V
= VS = 3 V
V
D
I+ ( A)
1 A
100 nA
10 nA
1 nA
– Leakage I
, I
SD
100 pA
14
12
10
8
6
4
2
0
Supply Current vs.
Supply Voltage and Temperature
GND = 0 V
10 11
12 13 14 15 16 17 18
V+ = +15 V GND = 0 V
125_C
I
D(off)
–55_C
I
S(off)
25_C
10 pA
1 pA
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
–120
–100
(dB)
TALK(AI)
X
Document Number: 70070 S-02315—Rev. D, 05-Oct-00
Adjacent Input Crosstalk vs. Frequency –3 dB Bandwidth Insertion Loss vs. Frequency
–80
–60
–40
–20
Test Circuit
See Figure 10
0
0.1 1 10 100
10 pA
1 pA
Temperature (_C) Temperature (_C)
0
DG536 R
= 10
IN
DG536 R
= 75
IN
DG535 R
= 10
IN
f – Frequency (MHz) f – Frequency (MHz)
–4
–8
–12
Insertion Loss (dB)
–16
–20
1 10 100 1000
Test Circuit
See Figure 6
R
= 50
L
DG536
–3 dB Points
DG535
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5-5
DG535/536
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
–160 –140
–120
–100
(dB)
–80
TALK(CD)
–60
X
–40
–20
160 140
120
100
80
Test Circuit
See Figure 8
DG536 R
= 75
L
DG535 R
= 75
L
0
0.1 1 10 100 f – Frequency (MHz) f – Frequency (MHz)
tON, t
and Break-Before-Make vs. Temperature Single Channel Crosstalk vs. Frequency
OFF
Test Circuit
See Figures 2, 3, 4
t
BBM
Chip Disable Crosstalk vs. Frequency All Hostile Crosstalk vs. Frequency
DG536 R
= 50
L
t
ON
–160 –140
–120
–100
(dB)
–80
TALK(AH)
–60
X
–40
–20
–160 –140
–120
–100
(dB)
–80
Test Circuit
See Figure 7
DG535
= 10
R
IN
R
= 10 k
L
0
0.1 1 10 100
Test Circuit
See Figure 9
R
= 75
IN
= 75
R
L
DG536
= 10
R
IN
R
= 10 k
L
DG536 R
= 75
IN
R
= 75
L
DG536
60
Switching Time (ns)
40
20
0
–55 –35 5–15 25 45 65 85 105 125
Temperature (_C)
t
OFF
INPUT TIMING REQUIREMENTS
15 V
ST
0 V
15 V
CS, A0, A1, A2, A CS, EN
3
0 V
7.5 V
10.5 V
4.5 V
–60
TALK(SC) X
–40
–20
0
0.1 1 10 100 f – Frequency (MHz)
t
SW
t
DW
t
WD
10.5 V
4.5 V
DG535
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5-6
FIGURE 1.
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
TEST CIRCUITS
DG535/536
Vishay Siliconix
Logic Input
Address
Input
Logic
Input
+15 V
+15 V
+15 V
ST A
0
A
1
A
2
A
3
EN or CS CS
EN, CS A1, A2, A
A
0
ST
GND
V+
GND
+15 V
V+
3
S1 – S
S2 – S
CS
Address
Logic Input
<20 ns
t
r
<20 ns
t
f
S
16
15
+3 V
15 V
50%
0 V
CS
EN or CS
90%
35 pF
V
O
Signal Output
t
ON
t
OFF
D
1 k
FIGURE 2. EN, CS, CS, Turn On/Off Time
Address
Logic Input
<20 ns
t
r
<20 ns
t
f
S
15
+3 V
1
35 pF
V
O
D
1 k
V
15 V
0 V
15 V
0 V
OUT
0 V
50%
t
ON(ST)
90%
+15 V
EN CS ST A
0
A
1
A
2
A
3
GND
Document Number: 70070 S-02315—Rev. D, 05-Oct-00
V+
S2 thru S
CS
FIGURE 3. Strobe ST Turn On Time
+3 V+15 V
Address
Logic Input
<20 ns
t
r
<20 ns
t
35 pF
f
V
O
S
1
S
16
15
D
1 k
15 V
0 V
Switch Output
S
1
Turning Off Turning On
FIGURE 4. Transition Time and Break-Before-Make Interval
50%
90%
t
TRANS
t
BBM
S
16
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5-7
DG535/536
Vishay Siliconix
TEST CIRCUITS
+15 V +15 V
+15 V
V+
A0, A1, A2, A
3
ST
EN
+3 V
Logic
Input
S
CS
16
GND
D
CS
CS
V
OUT
V
is the measured voltage error due to charge injection.
OUT
The charge injection in Coulombs is Q = C
x V
L
FIGURE 5. Charge Injection FIGURE 6. Bandwidth
V
OUT
OUT
V
O
C
L
1000 pF
Signal
Generator
(75 )
+15 V
EN CS ST
S
1
GND
+15 V
V+
S2 thru S
CS
15
D
A
0
to
A
3
R
L
50 W
V
O
S
Channel 1 On
1
S
2
R
IN
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
V
X
TALK(AH)
+ 20 log
O
10
V
V
O
R
L
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
VV
All Channels Off
TALK(CD)
+ 20 log
X
V
O
R
L
V
O
10
V
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5-8
FIGURE 7. All Hostile Crosstalk
FIGURE 8. Chip Disabled Crosstalk
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
TEST CIRCUITS
R
IN
V
Notes:
1. Any individual channel between S V
O
2. X
TALK(SC)
+ 20 log
is scanned sequentially from S
10
V
Channel 1 On
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
and S16 can be selected
2
DG535/536
Vishay Siliconix
R
IN
10
V
Sn–1
S
n–1
V
Sn
S
V
Sn – 1
V
Sn
n
S
n+1
or 20 log
R
L
10 k
V
Sn ) 1
10
V
Sn
V
O
V
Sn+1
R
L
X
TALK(AI)
to S
2
16
+ 20 log
R
IN
10
10
FIGURE 9. Single Channel Crosstalk FIGURE 10. Adjacent
Input Crosstalk
PIN DESCRIPTION
Symbol Description
S1 thru S
D Multiplexer output/demultiplexer input
DIS Open drain low impedance to analog ground when any channel is selected
CS, CS, EN Logic inputs to selected desired multiplexer(s) when using several multiplexers in a system
A
thru A
0
ST Strobe input that latches A0, A1, A2, A3, CS, CS, EN V+ Positive supply voltage input
GND Analog signal ground and most negative potential
Analog inputs/outputs
16
Binary address inputs to determine which channel is selected
3
All ground pins should be connected externally to ensure dynamic performance
Document Number: 70070 S-02315—Rev. D, 05-Oct-00
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5-9
DG535/536
Vishay Siliconix
DETAILED DESCRIPTION
The DG535/536 are 16-channel single-ended multiplexers with on-chip address logic and control latches.
The multiplexer connects one of sixteen inputs (S
, S2 through
1
S16) to a common output (D) under the control of a 4-bit binary address (A0 to A3). The specific input channel selected for each address is given in the Truth Table.
All four address inputs have on-chip data latches which are controlled by the Strobe (ST) input. These latches are transparent when Strobe is high but they maintain the chosen address when Strobe goes low. To facilitate easy microprocessor control in large matrices a choice of three independent logic inputs (EN, CS and CS
) are provided on chip. These inputs are gated together (see Figure 1 1) and only when EN = CS = 1 and CS = 0 can an output switch be selected. This necessary logic condition is then latched-in when Strobe (ST) goes low.
CS
CS
Latch
A
Latch
A
Latch
0
1
Signal
IN
SW1 SW3
SW2
Signal
GND
FIGURE 12. “T” Switch
Arrangement
Signal
OUT
The two second level series switches further improve crosstalk and help to minimize output capacitance.
The DIS output can be used to signal external circuitry. DIS is a high impedance to GND when no channel is selected and a low impedance to GND when any one channel is selected.
The DG535/536 have extensive applications where any high frequency video or digital signals are switched or routed. Exceptional crosstalk and bandwidth performance is achieved by using n-channel DMOS FETs for the “T” and series switches.
EN
ST
A
2
Latch
A
3
Latch
FIGURE 11.CS, CS, EN, ST Control Logic
Decode Logic
Break-before-make switching prevents momentary shorting when changing from one input to another.
The devices feature a two-level switch arrangement whereby two banks of eight switches (first level) are connected via two series switches (second level) to a common DRAIN output.
In order to improve crosstalk all sixteen first level switches are configured as “T” switches (see Figure 12).
With this method SW2 operates out of phase with SW1 and SW3. In the on condition SW1 and SW3 are closed with SW open whereas in the off condition SW1 and SW3 are open and SW2 closed. In the off condition the input to SW3 is ef fectively the isolation leakage of SW1 working into the on-resistance of SW
(typically 200 ).
2
p
Gate
p–
Substrate
GND
Source
n+
FIGURE 13. Cross-Section of a Single
DMOS Switch
Drain
n+
It can clearly be seen from Figure 13 that there exists a PN junction between the substrate and the drain/source terminals.
Should a signal which is negative with respect to the substrate (GND pin) be connected to a source or drain terminal, then the PN junction will become forward biased and current will flow
2
between the signal source and GND. This effective shorting of the signal source to GND will not necessarily cause any damage to the device, provided that the total current flowing is less than the maximum rating, (i.e., 20 mA).
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5-10
Document Number: 70070
S-02315—Rev. D, 05-Oct-00
DETAILED DESCRIPTION
DG535/536
Vishay Siliconix
Since no PN junctions exist between the signal path and V+, positive overvoltages are not a problem, unless the breakdown voltage of the DMOS drain terminal (see Figure
13) (+18 V) is exceeded. Positive overvoltage conditions must not exceed +18 V with respect to the GND pin. If this condition is possible (e.g. transients in the signal), then a diode or Zener clamp may be used to prevent breakdown.
The overvoltage conditions described may exist if the supplies are collapsed while a signal is present on the inputs. If this condition is unavoidable, then the necessary steps outlined above should be taken to protect the device
DC Biasing
To avoid negative overvoltage conditions and subsequent distortion of ac analog signals, dc biasing may be necessary. Biasing is not required, however, in applications where signals are always positive with respect to the GND or substrate connection, or in applications involving multiplexing of low level (up to "200 mV) signals, where forward biasing of the PN substrate-source/drain terminals would not occur.
Biasing can be accomplished in a number of ways, the simplest of which is a resistive potential divider and a few dc blocking capacitors as shown in Figure 14.
being coupled back to the analog signal source and C2 blocks the dc bias from the output signal. Both C1 and C2 should be tantalum or ceramic disc type capacitors in order to operate efficiently at high frequencies. Active bias circuits are recommended if rapid switching time between channels is required.
An alternative method is to offset the supply voltages (see Figure 15).
Decoupling would have to be applied to the negative supply to ensure that the substrate is well referenced to signal ground. Again the capacitors should be of a type offering good high frequency characteristics.
Level shifting of the logic signals may be necessary using this offset supply arrangement.
+12 V
Analog
Signal
IN
S
V+
DG536
GND
Analog
D
Signal
OUT
+15 V
Analog
Signal
IN
R
and R2 are chosen to suit the appropriate biasing
1
C
100 F/16 V
Tantalum
R
1
FIGURE 14. Simp
1
+
R
2
V+
S
DG536
GND
le Bias Circuit
+
D
C
2
Analog
100 F/16 V
Tantalum
Signal
OUT
requirements. For video applications, approximately 3 V of bias is required for optimal differential gain and phase performance. Capacitor C
Document Number: 70070 S-02315—Rev. D, 05-Oct-00
blocks the dc bias voltage from
1
Decoupling
Capacitors
+
FIGURE 15. DG536 with
Offset Supply
–3 V
TTL to CMOS level shifting is easily obtained by using a MC14504B.
Circuit Layout
Good circuit board layout and extensive shielding is essential for optimizing the high frequency performance of the DG536. Stray capacitances on the PC board and/or connecting leads will considerably degrade the ac performance. Hence, signal paths must be kept as short as practically possible, with extensive ground planes separating signal tracks.
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