VIS VG26V17400FJ-5, VG26V17400FJ-6, VG26S17400FJ-6, VG26S17400FJ-5 Datasheet

VG26(V)(S)17400FJ

10

±

4,194,304 x 4 - Bit

VIS

Description

The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. A new refresh feature called “ self-refresh “ is supported and very slow CBR cycles are being performed. It is packaged in JEDEC standard 26/24 - pin plastic SOJ or TSOP (II).

Features

• Single 5V (%) or 3.3V (+10%,-5%) only power supply

• High speed t

• Low power dissipation

- Active mode : 5V version 605/550 mW (Max.)

3.3V version 396/360 mW (Max.)

- Standby mode : 5V version 1.375 mW (Max.)

3.3V version 0.54 mW (Max.)

• Fast Page Mode access

• I/O level : TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V)

• 2048 refresh cycles in 32 ms (Std) or 128ms (S - version)

• 4 refresh mode :

- RAS only refresh

- CAS-before-RAS refresh

- Hidden refresh

- Self - refresh (S - version)

access time : 50/60 ns

RAC

CMOS Dynamic RAM

Document : Rev. Page 1

VG26(V)(S)17400FJ

VIS

Pin configuration

26/24 - PIN 300mil Plastic SOJ

4,194,304 x 4 - Bit

CMOS Dynamic RAM

V DQ1 DQ2

WE

RAS

NC

A

V

CC

A A A A

CC

1

2

3

4

5 6

10

8

9

0

10

1

11

2

12

3

13

VG26(V) (S)17400EJ

26

25

23

22 21

19

18

16

15 14

V

SS

DQ4 DQ3

24

CAS OE

A

9

A

8

A

7

A

17

6

A

5

A

4

V

SS

Pin Description

Pin Name Function A0 - A10 Address inputs

- Row address A0 - A10

- Column address A0 - A10

- Refresh address A0 - A10 DQ1 ~ DQ4 Data - in/data - out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable V

cc

V

ss

Power (+ 5V or + 3.3V) Ground

Document : Rev. Page 2

VIS

DQ1

DQ4

Block Diagram

VG26(V)(S)17400FJ

4,194,304 x 4 - Bit

CMOS Dynamic RAM

WE

A0 A1 A2

A3 A4 A5

A6 A7 A8

A9

A10

CAS

NO. 2 CLOCK

GENERATOR

COLUMN-

ADDRESS

BUFFERS (11)

REFRESH

CONTROLLER

REFRESH COUNTER

ROW

ADDRESS

BUFFERS (11)

CONTROL

LOGIC

DATA - IN BUFFER

DATA - OUT

BUFFER

COLUMN

DECODER

2048

SENSE AMPLIFIERS

I/O GATING 2048 x 4

2048 x 2048 x 4

MEMORY

ROW

DECODER

2048

ARRAY

RAS

NO. 1 CLOCK

GENERATOR

Vcc

Vss

Document : Rev. Page 3

VG26(V)(S)17400FJ

HX

→

HL

→

LH→

HL→

HL

→

HL

→

LH

→

HL

→

HL

→

LH

→

LHL→→

HL

→

4,194,304 x 4 - Bit

VIS

Truth Table

ADDRESSES

FUNCTION RAS CAS WE OE

STANDBY H X X X X High - Z READ L L H L ROW COL Data - Out

WRITE : (EARLY WRITE)

READ WRITE L L ROW COL Data - Out, Data - In

L L L X ROW COL Data - In

ROW COL

CMOS Dynamic RAM

DQ

S

Notes

PAGE - MODE READ

PAGE - MODE WRITE

PAGE - MODE READ - WRITE

HIDDEN REFRESH

RAS - ONLY REFRESH L H X X ROW n/a High - Z CBR REFRESH L H X X X High - Z Notes : 1. EARLY WRITE only.

1st Cycle L H L ROW COL Data - Out

2st

Cycle

1st Cycle L L X ROW COL Data - In

2st

Cycle

1st Cycle L ROW COL Data - Out, Data - In

2st

Cycle

READ L H L ROW COL Data - Out WRITE L L X ROW COL Data - In 1

L H L n/a COL Data - Out

L L X n/a COL Data - In

L n/a COL Data - Out, Data - In

Document : Rev. Page 4

VG26(V)(S)17400FJ

±

VIS

Absolute Maximum Rating

Parameter Symbol Value Unit

Voltage on any pin relative to Vss 5V

3.3V

Supply voltage relative to Vss 5V

3.3V

Short circuit output current I Power dissipation P Operating temperature T Storage temperature T

Recommended DC Operating Conditions

Parameter/Condition Symbol 5 Volt Version 3.3 Volt Version Unit

Min Typ Max Min Typ Max

Supply Voltage V Input High Voltage, all inputs V Input Low Voltage, all inputs V

cc IH

IL

4.5 5.0 5.5 3.15 3.3 3.6 V

2.4 - V

-1.0 - 0.8 -0.3 - 0.8 V

4,194,304 x 4 - Bit

CMOS Dynamic RAM

V

T

V

cc

OUT

D OPT STG

+ 1.0 2.0 - V

CC

-1.0 to + 7.0

-0.5 to + 4.6

-1.0 to + 7.0

-0.5 to + 4.6 50 mA

1.0 W

0 to + 70 °C

-55 to + 125 °C

+ 0.3 V

CC

V

Capacitance

Ta = 25°C, V

Input capacitance (Address) C Input capacitance

(RAS, CAS, OE, WE) Output capacitance

(Data - in, Data - out) Note : 1. Capacitance measured with effective capacitance measuring method.

2. CAS = VIH to disable Dout.

= % or 3.3V(+10%,-5%), f = 1MHz

CC

Parameter Symbol Typ Max Unit Note

l1

C

l2

C

I/O

- 5 pF 1

- 7 pF 1

- 7 pF 1,2

Document : Rev. Page 5

VG26(V)(S)17400FJ

±

CC

≥

CC

≥

t

RASS

100µS≥µA

0.2V

≤

0VVIL0.2V

≤≤

0.2VV

IHVIH

≤≤

t

RAS

300ns

≤

µA

VIS

DC Characteristics; 5 - Volt verion

(Ta= 0 to 70°C, VCC = + 5V10%, V

Parameter Symbol Test Conditions

Operating current I

CC1

= 0V)

ss

RAS cycling CAS cycling tRC = min.

4,194,304 x 4 - Bit

CMOS Dynamic RAM

VG26 (V) (S) 17400E

-5 -6

Min Max Min Max

- 145 - 135 mA 1, 2

Unit Notes

Low power S - version

Standby Current

RAS - only refresh current

Fast page mode current

CAS - before - RAS refresh current

Self - refresh currant (S - Version)

CAS - before - RAS long refresh current (S - Version)

Standard power version

TTL interface RAS, CAS = V

Dout = high - Z CMOS interface

RASCAS,V

Dout = high - Z

I

CC2

TTL interface RAS, CAS = V

Dout = high - Z CMOS interface

RASCAS,V

Dout = high - Z

I

RAS cycling, CAS = V

CC3

t

CC4

t

CC5tRC

RAS, CAS cycling

CC8

CC9

Standby : VCC CAS before RAS refresh :

2048 cycles/128ms RAS, RAS :

VCC - (Max) Dout = high - Z,

RC

PC

= min.

- 2 - 2

IH

- 0.25 - 0.25

- 0.2V

- 2 - 2

IH

- 1 - 1

- 0.2V

IH

RAS

- 145 - 135

- 100 - 90

- 145 - 135

- 350 - 350

- 500 - 500

mA

1, 2

mA

1,3

mA

1, 2

mA

Document : Rev. Page 6

VG26(V)(S)17400FJ

±

0VVinV

≤≤

µA

0VVoutV

≤≤

µA

VIS

DC Characteristics ; 5 - Volt Version (cont.)

(Ta = 0 to 70°C, V

Parameter Symbol Test Conditions

lnput leakage current

Output leakage current

Output high voltage

Output low voltage

Notes :

1. lCC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. lCC max is specified at the output open condition.

2. Address can be changed once or less while RAS = VIL.

3. For l

= + 5V10%, V

CC

I

V

, address can be changed once or less within one Fast page mode cycle time.

CC4

= 0V)

ss

LI

LO

Dout = Disable

OH lOH

OL lOL

4,194,304 x 4 - Bit

CMOS Dynamic RAM

VG26 (V) (S) 17400E

-5 -6

Min Max Min Max

+ 0.5V

CC

+ 0.5V

CC

= -5mA 2.4 - 2.4 - V

= + 4.2mA - 0.4 - 0.4 V

-5 5 -5 5

Unit Notes

Document : Rev. Page 7

VG26(V)(S)17400FJ

CC

≥

CC

≥

t

100µS≥µA

0.2V

≤

0VV

0.2V

≤≤

0.2VV

IHVIH

≤≤

t

300ns

≤

µA

VIS

DC Characteristics ; 3.3 - Volt Verion

(Ta = 0 to 70°C, V

Parameter Symbol Test Conditions

Operating current I

= + 3.3V(+10%,-5%), V

CC

CC1

RAS cycling CAS cycling tRC = min.

ss

= 0V)

4,194,304 x 4 - Bit

CMOS Dynamic RAM

VG26 (V) (S) 17400E

-5 -6

Min Max Min Max

- 145 - 135 mA 1, 2

Unit Notes

Low power S - version

Standby Current

RAS - only refresh current

Fast page mode current

CAS - before - RAS refresh current

Self - refresh currant (S - Version)

CAS - before - RAS long refresh current (S - Version)

Standard power version

LVTTL interface RAS, CAS = V

Dout = high - Z

CMOS interface

RASCAS,V

Dout = high - Z

I

LVTTL interface

CC2

RAS, CAS = V Dout = high - Z

CMOS interface

RASCAS,V

Dout = high - Z

CC3

CC4

CC5 tRC

CC8

CC9

RAS cycling, CAS = V t

t

RAS, CAS cycling

Standby : VCC CAS before RAS refresh :

2048 cycles/128ms RAS, RAS : VCC - (Max)

Dout = high - Z,

= min.

RC

= min.

PC

= min.

RASS

IH

- 0.2V

IL

RAS

IH

RAS

- 0.5 - 0.5

- 0.15 - 0.15

- 2 - 2

- 0.5 - 0.5

- 145 - 135

- 100 - 90

- 145 - 135

- 250 - 250

- 300 - 300

mA

1, 2

mA

1,3

mA

1, 2

mA

Document : Rev. Page 8

VIS VG26V17400FJ-5, VG26V17400FJ-6, VG26S17400FJ-6, VG26S17400FJ-5 Datasheet

Specifications and Main Features

Frequently Asked Questions

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