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VIP
HB140 | CPU | 314-6CF03 | GB | 16-43
A System 300S
CPU | 314-6CF03 | Manual
SPEED7 CPU 314ST
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VIPA GmbH
Ohmstr
91074 Herzogenaurach
Telephone: +49 9132 744-0
Fax: +49 9132 744-1864
Email: [email protected]
Internet: www.vipa.com
314-6CF03_000_CPU 314ST,3,GB - © 2016
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VIPA System 300S Table of contents
Table of contents
1 General...................................................................................... 6
1.1 Copyright © VIP
1.2 About this manual.............................................................. 7
1.3 Safety information.............................................................. 8
2 Basics..................................................................................... 10
2.1 Safety information for users............................................. 10
2.2 Operating structure of a CPU........................................... 11
2.2.1 General.......................................................................... 11
2.2.2 Applications .................................................................. 11
2.2.3 Operands...................................................................... 12
2.3 CPU 314-6CF03............................................................... 13
2.4 General data.................................................................... 16
3 Assembly and installation guidelines.................................. 18
3.1 Overview.......................................................................... 18
3.2 Installation dimensions..................................................... 18
3.3 Assembly SPEED-Bus..................................................... 20
3.4 Assembly standard bus.................................................... 23
3.5 Cabling............................................................................. 25
3.6 Installation guidelines....................................................... 27
A GmbH ................................................... 6
4 Hardware description............................................................ 31
4.1 Properties......................................................................... 31
4.2 Structure........................................................................... 32
4.2.1 General......................................................................... 32
4.2.2 Interfaces...................................................................... 32
4.2.3 Memory management................................................... 34
4.2.4 Storage media slot ....................................................... 34
4.2.5 Battery backup for clock and RAM................................ 35
4.2.6 Operating mode switch................................................. 36
4.2.7 LEDs............................................................................. 36
4.2.8 In-/Output range CPU 314-6CF03................................ 39
4.3 Technical data.................................................................. 41
5 Deployment CPU 314-6CF03................................................. 54
5.1 Assembly.......................................................................... 54
5.2 Start-up behavior.............................................................. 54
5.3 Addressing....................................................................... 55
5.3.1 Overview....................................................................... 55
5.3.2 Addressing.................................................................... 55
5.3.3 Address assignment I/O part......................................... 58
5.4 Hardware configuration - CPU......................................... 59
5.5 Hardware configuration - I/O modules............................. 60
5.6 Hardware configuration - Ethernet PG/OP channel......... 61
5.7 Hardware configuration - SPEED-Bus............................. 63
5.7.1 Preconditions................................................................ 63
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VIPA System 300STable of contents
5.7.2 Proceeding.................................................................... 64
5.8 Setting standard CPU parameters................................... 64
5.8.1 Parameterization via Siemens CPU.............................. 64
5.8.2 Parameters CPU........................................................... 65
5.8.3 Parameters for DP........................................................ 67
5.8.4 Parameters for MPI/DP ................................................ 68
5.9 Setting VIPA specific CPU parameters............................ 69
5.9.1 Proceeding.................................................................... 69
5.9.2 VIPA specific parameters.............................................. 71
5.10 Project transfer............................................................... 74
5.10.1 Transfer via MPI/PROFIBUS....................................... 74
5.10.2 Transfer via Ethernet................................................... 76
5.10.3 Transfer via MMC........................................................ 77
5.11 Access to the internal Web page.................................... 78
5.12 Operating modes............................................................ 81
5.12.1 Overview..................................................................... 81
5.12.2 Function security......................................................... 83
5.13 Overall reset................................................................... 84
5.14 Firmware update............................................................ 85
5.15 Reset to factory settings................................................. 88
5.16 Slot for storage media.................................................... 89
5.17 Memory extension with MCC......................................... 90
5.18 Extended know-how protection...................................... 91
5.19 CMD - auto commands.................................................. 92
5.20 Diagnostic entries........................................................... 94
5.21 Control and monitoring of variables with test functions 127
6 Deployment I/O periphery................................................... 129
6.1 Overview........................................................................ 129
6.2 In-/Output range CPU 314-6CF03................................. 130
6.3 Address assignment I/O part.......................................... 132
6.4 Analog part..................................................................... 134
6.5 Analog part - Parametrization........................................ 138
6.6 Analog part - Diagnostic functions................................. 142
6.7 Digital part...................................................................... 145
6.8 Counter - Fast introduction............................................. 147
6.9 Counter - In-/output area................................................ 149
6.10 Counter - Parametrization............................................ 152
6.11 Counter - Functions...................................................... 159
6.12 Counter - Additional functions...................................... 164
6.13 Counter - Diagnostic and interrupt............................... 171
6.13.1 Process interrupt....................................................... 171
6.13.2 Diagnostic interrupt................................................... 172
7 Deployment PtP communication........................................ 178
7.1 Fast introduction............................................................. 178
7.2 Principle of the data transfer.......................................... 179
7.3 Deployment of RS485 interface for PtP ........................ 179
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VIPA System 300S Table of contents
7.4 Parametrization.............................................................. 182
7.4.1 FC/SFC 216 - SER_CFG - Parametrization PtP......... 182
7.5 Communication.............................................................. 183
7.5.1 FC/SFC 217 - SER_SND - Send to PtP...................... 183
7.5.2 FC/SFC 218 - SER_RCV - Receive from PtP............. 183
7.6 Protocols and procedures ............................................. 183
7.7 Modbus - Function codes .............................................. 187
7.8 Modbus - Example communication................................ 192
8 Deployment PROFIBUS communication........................... 194
8.1 Overview........................................................................ 194
8.2 Fast introduction............................................................. 195
8.3 Hardware configuration - CPU....................................... 195
8.4 Deployment as PROFIBUS DP master.......................... 196
8.5 Deployment as PROFIBUS DP slave............................ 197
8.6 PROFIBUS installation guidelines.................................. 200
8.7 Commissioning and Start-up behavior........................... 203
9 WinPLC7............................................................................... 205
9.1 System conception......................................................... 205
9.2 Installation...................................................................... 205
9.3 Example project engineering.......................................... 207
9.3.1 Job definition............................................................... 207
9.3.2 Project engineering..................................................... 207
9.3.3 Test the PLC program in the Simulator.......................
213
9.3.4 Transfer PLC program to CPU and its execution........ 214
10 Configuration with TIA Portal............................................. 216
10.1 TIA Portal - Work environment .................................... 216
10.1.1 General..................................................................... 216
10.1.2 Work environment of the TIA Portal.......................... 216
10.2 TIA Portal - Hardware configuration - CPU ................. 217
10.3 TIA Portal - Hardware configuration - I/O modules...... 218
10.4 TIA Portal - Hardware configuration - Ethernet PG/OP
channel......................................................................... 219
10.5 TIA Portal - Setting VIPA specific CPU parameters..... 222
10.6 TIA Portal - VIPA-Include library................................... 225
10.7 TIA Portal - Project transfer.......................................... 226
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VIPA System 300SGeneral
Copyright © VIP
A GmbH
1 General
1.1 Copyright © VIPA GmbH
All Rights Reserved
This document contains proprietary information of VIPA and is not to
be disclosed or used except in accordance with applicable agreements.
This material is protected by the copyright laws. It may not be reproduced, distributed, or altered in any fashion by any entity (either
internal or external to VIPA), except in accordance with applicable
agreements, contracts or licensing, without the express written consent of VIPA and the business management owner of the material.
For permission to reproduce or distribute, please contact: VIPA,
Gesellschaft für Visualisierung und Prozessautomatisierung mbH
Ohmstraße 4, D-91074 Herzogenaurach, Germany
Tel.: +49 9132 744 -0
Fax.: +49 9132 744-1864
EMail: [email protected]
http://www.vipa.com
CE Conformity Declaration
Conformity Information
Every effort has been made to ensure that the information contained in this document was complete and
accurate at the time of publishing. Nevertheless, the
authors retain the right to modify the information.
This customer document describes all the hardware
units and functions known at the present time. Descriptions may be included for units which are not present at
the customer site. The exact scope of delivery is
described in the respective purchase contract.
Hereby, VIPA GmbH declares that the products and systems are in
compliance with the essential requirements and other relevant provisions. Conformity is indicated by the CE marking af
product.
For more information regarding CE marking and Declaration of Conformity (DoC), please contact your local VIPA customer service
organization.
fixed to the
6
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VIPA System 300S General
About this manual
Trademarks
Information product
support
VIPA, SLIO, System 100V, System 200V, System 300V, System
300S, System 400V
registered trademarks of VIPA Gesellschaft für Visualisierung und
Prozessautomatisierung mbH.
SPEED7 is a registered trademark of profichip GmbH.
SIMATIC, STEP, SINEC, TIA Portal, S7-300 and S7-400 are registered trademarks of Siemens AG.
Microsoft and Windows are registered trademarks of Microsoft Inc.,
USA.
Portable Document Format (PDF) and Postscript are registered trademarks of Adobe Systems, Inc.
All other trademarks, logos and service or product marks specified
herein are owned by their respective companies.
Contact your local VIPA Customer Service Organization representative if you wish to report errors or questions regarding the contents of
this document. If you are unable to locate a customer service centre,
contact VIPA as follows:
VIPA GmbH, Ohmstraße 4, 91074 Herzogenaurach, Germany
Telefax: +49 9132 744-1204
, System 500S and Commander Compact are
EMail: [email protected]
Technical support
Contact your local VIPA Customer Service Organization representative if you encounter problems with the product or have questions
regarding the product. If you are unable to locate a customer service
centre, contact VIPA as follows:
VIPA GmbH, Ohmstraße 4, 91074 Herzogenaurach, Germany
Tel.: +49 9132 744-1150 (Hotline)
EMail: [email protected]
1.2 About this manual
Objective and contents
Product Order no. as of state:
CPU-HW CPU-FW DPM-FW
This manual describes the SPEED7 CPU 314-6CF03 of the CPU
from VIPA. It contains a description of the construction, project implementation and usage.
CPU 314ST 314-6CF03 1 V3.6.0 V3.1.2
Target audience
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The manual is targeted at users who have a background in automation technology
.
Page 8
Safety information
VIPA System 300SGeneral
Structure of the manual
Guide to the document
Availability
Icons Headings
The manual consists of chapters. Every chapter provides a self-contained description of a specific topic.
The following guides are available in the manual:
n An overall table of contents at the beginning of the manual
n References with page numbers
The manual is available in:
n printed form, on paper
n in electronic form as PDF-file (Adobe Acrobat Reader)
Important passages in the text are highlighted by following icons and
headings:
DANGER!
Immediate or likely danger
. Personal injury is possible.
1.3 Safety information
Applications conforming with specifications
CAUTION!
Damages to property is likely if these warnings are not
heeded.
Supplementary information and useful tips.
The system is constructed and produced for:
n communication and process control
n general control and automation tasks
n industrial applications
n operation within the environmental conditions specified in the
technical data
n installation into a cubicle
DANGER!
This device is not certified for applications in
in explosive environments (EX-zone)
–
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VIPA System 300S General
Safety information
Documentation
Disposal
The manual must be available to all personnel in the
n project design department
n installation department
n commissioning
n operation
CAUTION!
The following conditions must be met before using
or commissioning the components described in
this manual:
– Hardware modifications to the process control
system should only be carried out when the system
has been disconnected from power!
Installation and hardware modifications only by
–
properly trained personnel.
– The national rules and regulations of the respective
country must be satisfied (installation, safety,
EMC ...)
National rules and regulations apply to the disposal of the unit!
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Safety information for users
2 Basics
2.1 Safety information for users
VIPA System 300SBasics
Handling of electrostatic sensitive modules
VIPA modules make use of highly integrated components in MOSTechnology. These components are extremely sensitive to over-voltages that can occur during electrostatic discharges. The following
symbol is attached to modules that can be destroyed by electrostatic
discharges.
The Symbol is located on the module, the module rack or on packing
material and it indicates the presence of electrostatic sensitive equipment. It is possible that electrostatic sensitive equipment is destroyed
by energies and voltages that are far less than the human threshold
of perception. These voltages can occur where persons do not discharge themselves before handling electrostatic sensitive modules
and they can damage components thereby
become inoperable or unusable. Modules that have been damaged
by electrostatic discharges can fail after a temperature change,
mechanical shock or changes in the electrical load. Only the consequent implementation of protection devices and meticulous attention
to the applicable rules and regulations for handling the respective
equipment can prevent failures of electrostatic sensitive modules.
, causing the module to
Shipping of modules
Measurements and
alterations on electrostatic sensitive modules
Modules must be shipped in the original packing material.
When you are conducting measurements on electrostatic sensitive
modules you should take the following precautions:
n Floating instruments must be discharged before use.
n Instruments must be grounded.
Modifying electrostatic sensitive modules you should only use soldering irons with grounded tips.
CAUTION!
Personnel and instruments should be grounded when
working on electrostatic sensitive modules.
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VIPA System 300S Basics
Operating structure of a CPU > Applications
2.2 Operating structure of a CPU
2.2.1
Cyclic processing
Timer processing
Alarm controlled processing
General
The CPU contains a standard processor with internal program
memory
unit provides a powerful solution for process automation applications
within the System 300S family. A CPU supports the following modes
of operation:
n cyclic operation
n timer processing
n alarm controlled operation
n priority based processing
Cyclicprocessing represents the major portion of all the processes
that are executed in the CPU. Identical sequences of operations are
repeated in a never-ending cycle.
Where a process requires control signals at constant intervals you
can initiate certain operations based upon a timer, e.g. not critical
monitoring functions at one-second intervals.
If a process signal requires a quick response you would allocate this
signal to an alarm controlled procedure. An alarm can activate a
procedure in your program.
. In combination with the integrated SPEED7 technology the
Priority based processing
2.2.2 Applications
System routine
User application
The above processes are handled by the CPU in accordance with
their priority. Since a timer or an alarm event requires a quick reaction, the CPU will interrupt the cyclic processing when these high-priority events occur to react to the event. Cyclic processing will resume,
once the reaction has been processed. This means that cyclic processing has the lowest priority
The program that is present in every CPU is divided as follows:
n System routine
n User application
The system routine organizes all those functions and procedures of
the CPU that are not related to a specific control application.
This consists of all the functions that are required for the processing
of a specific control application. The operating modules provide the
interfaces to the system routines.
.
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Operating structure of a CPU > Operands
2.2.3 Operands
The following series of operands is available for programming the
CPU:
n Process image and periphery
n Bit memory
n T
n Data blocks
VIPA System 300SBasics
imers and counters
Process image and
periphery
Bit Memory
The user application can quickly access the process image of the
inputs and outputs PIO/PII. Y
ou may manipulate the following types of
data:
n individual Bits
n Bytes
n Words
n Double words
You may also gain direct access to peripheral modules via the bus
from user application. The following types of data are available:
n Bytes
ords
n W
n Blocks
The bit memory is an area of memory that is accessible by means of
certain operations. Bit memory is intended to store frequently used
working data.
You may access the following types of data:
n individual Bits
n Bytes
ords
n W
n Double words
Timers and counters
Data Blocks
In your program you may load cells of the timer with a value between
10ms and 9990s. As soon as the user application executes a startoperation, the value of this timer is decremented by the interval that
you have specified until it reaches zero.
You may load counter cells with an initial value (max. 999) and increment or decrement these when required.
A data block contains constants or variables in the form of bytes,
words or double words. You may always access the current data
block by means of operands.
You may access the following types of data:
n individual Bits
n Bytes
ords
n W
n Double words
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VIPA System 300S Basics
CPU 314-6CF03
2.3 CPU 314-6CF03
Overview
The CPU 314-6CF03 bases upon the SPEED7 technology. This supports the CPU at programming and communication by means of coprocessors that causes a power improvement for highest needs.
n The CPU is programmed in STEPÒ7 from Siemens. For this you
may use the SIMA
the instruction set of the S7-400 from Siemens is used.
n The CPU has a parallel SPEED-Bus that enables the additional
connection of up to 10 modules from the SPEED-Bus periphery.
While the standard peripheral modules are plugged at the right
side of the CPU, the SPEED-Bus peripheral modules are connected via a SPEED-Bus bus connector at the left side of the
CPU.
n The CPU has digital and analog input output components. If there
is no hardware configuration available, the in- and output areas
starting with address 1024 are mapped to the address range of
the CPU.
The following components are integrated:
– Analog input: 4x12Bit, 1xPt100
– Analog output: 2x12Bit
– Digital input: 8xDC 24V with interrupt capability, 4 counter
– Digital input/output: 8xDC 24V, 0.5A
n Modules and CPUs of the System 300S from VIPA and Siemens
may be used at the bus as a mixed configuration.
n The user application is stored in the battery buffered RAM or on
an additionally pluggable MMC storage module.
n The CPU is configured as CPU 317-2DP (6ES7 317-2AJ10-0AB0/
V2.6) from Siemens.
TIC Manager or TIA Portal from Siemens. Here
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CPU 314-6CF03
Access
VIPA System 300SBasics
Memory
SPEED-Bus
Please always use the CPU 317-2DP (6ES7
317-2AJ10-0AB0/V2.6) from Siemens of the hardware
catalog to configure this CPU from VIP
A. For the
project engineering, a thorough knowledge of the Siemens SIMATIC Manager and the hardware configurator from Siemens is required!
The CPU has an integrated memory. Information about the capacity
of the memory may be found at the front of the CPU. The memory is
divided into the following parts:
n Load memory 2Mbyte
n Code memory (50% of the work memory)
n Data memory (50% of the work memory)
ork memory 512kbyte
n W
– There is the possibility to extend the work memory to its max-
imum printed capacity 2Mbyte by means of a MCC memory
extension card.
n The SPEED-Bus is a 32bit parallel bus developed from VIP
A.
n Via the SPEED-Bus you may connect up to 10 SPEED-Bus
modules to your CPU.
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VIPA System 300S Basics
CPU 314-6CF03
n In opposite to the "standard" backplane bus where the modules
are plugged-in at the right side of the CPU by means of single bus
connectors, the modules at the SPEED-Bus are plugged-in at the
left side of the CPU via a special SPEED-Bus rail.
n VIP
A delivers profile rails with integrated SPEED-Bus for 2, 6, or
10 SPEED-Bus peripheral modules with different lengths.
Each SPEED-Bus rail has a slot for an external power
supply
. The deployment of this external power supply
at the CPU 314-6CF03 is not permitted.
Integrated PROFIBUS
DP master/slave respectively PtP functionality
Integrated Ethernet
PG/OP
channel
Operation Security
The CPU has a PROFIBUS/PtP interface with a fix pinout. After an
overall reset the interface is deactivated. By appropriate configuration, the following functions for this interface may be enabled:
n PROFIBUS DP master operation: Configuration via PROFIBUS
sub module with ‘Operation mode’ master in the hardware configuration.
n PROFIBUS DP slave operation: Configuration via PROFIBUS sub
module with ‘Operation mode’ slave in the hardware configuration.
n PtP functionality: Configuration as virtual PROFIBUS master
system by including the VIP
A SPEEDBUS.GSD.
The CPU has an Ethernet interface for PG/OP communication. After
assigning IP address parameters with your configuration tool, via the
"PLC" functions you may directly access the Ethernet PG/OP channel
and program res. remote control your CPU. Y
ou may also access the
CPU with a visualization software via these connections.
n Wiring by means of spring pressure connections (CageClamps) at
the front connector
n Core cross-section 0.08...2.5mm
n T
otal isolation of the wiring at module change
2
n Potential separation of all modules to the backplane bus
Dimensions/ Weight
Dimensions of the basic enclosure:
n 2tier width: (WxHxD) in mm: 80x125x120
Integrated power supply
The CPU comes with an integrated power supply. The power supply
is to be supplied with DC 24V
. By means of the supply voltage, the
internal electronic is supplied as well as the connected modules via
backplane bus. The power supply is protected against inverse polarity
and overcurrent.
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VIPA System 300SBasics
General data
2.4 General data
Conformity and approval
Conformity
CE 2014/35/EU Low-voltage directive
2014/30/EU EMC directive
Approval
UL Refer to Technical data
others
RoHS 2011/65/EU Product is lead-free; Restriction of the use of
certain hazardous substances in electrical and
electronic equipment
Protection of persons and device protection
Type of protection - IP20
Electrical isolation
to the field bus - electrically isolated
to the process level - electrically isolated
Insulation resistance -
Insulation voltage to reference earth
Inputs / outputs - AC / DC 50V, test voltage AC 500V
Protective measures - against short circuit
Environmental conditions to EN 61131-2
Climatic
Storage / transport EN 60068-2-14 -25…+70°C
Operation
Horizontal installation hanging EN 61131-2 0…+60°C
Horizontal installation lying EN 61131-2 0…+55°C
Vertical installation EN 61131-2 0…+50°C
Air humidity EN 60068-2-30 RH1 (without condensation, rel. humidity 10…
95%)
Pollution EN 61131-2 Degree of pollution 2
Installation altitude max. - 2000m
Mechanical
Oscillation EN 60068-2-6 1g, 9Hz ... 150Hz
Shock EN 60068-2-27 15g, 11ms
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VIPA System 300S Basics
General data
Mounting conditions
Mounting place - In the control cabinet
Mounting position - Horizontal and vertical
EMC Standard Comment
Emitted interfer-
EN 61000-6-4 Class A (Industrial area)
ence
Noise immunity
zone B
EN 61000-6-2 Industrial area
EN 61000-4-2
ESD
8kV at air discharge (degree of severity 3),
4kV at contact discharge (degree of severity
2)
EN 61000-4-3 HF field immunity (casing)
80MHz … 1000MHz, 10V/m, 80% AM (1kHz)
1.4GHz ... 2.0GHz, 3V/m, 80% AM (1kHz)
2GHz ... 2.7GHz, 1V/m, 80% AM (1kHz)
EN 61000-4-6 HF conducted
150kHz … 80MHz, 10V
, 80% AM (1kHz)
EN 61000-4-4 Burst, degree of severity 3
EN 61000-4-5 Surge, installation class 3 *
*) Due to the high-energetic single pulses with Surge an appropriate external protective circuit with lightning protection elements like conductors
for lightning and overvoltage is necessary
.
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Installation dimensions
3 Assembly and installation guidelines
3.1 Overview
VIPA System 300SAssembly and installation guidelines
General
Serial Standard bus
This CPU is provided with a parallel SPEED-Bus that enables the
additional connection of up to 10 modules from the SPEED-Bus
periphery. While the standard peripheral modules are plugged-in at
the right side of the CPU, the SPEED-Bus peripheral modules are
connected via a SPEED-Bus bus connector at the left side of the
CPU.
VIPA delivers profile rails with integrated SPEED-Bus for 2, 6 or 10
SPEED-Bus peripheral modules with different lengths.
The single modules are directly installed on a profile rail and connected via the backplane bus coupler
you have to clip the backplane bus coupler to the module from the
backside. The backplane bus couplers are included in the delivery of
the peripheral modules.
. Before installing the modules
Parallel SPEED-Bus
Assembly possibilities
With SPEED-Bus the bus connection happens via a SPEED-Bus rail
integrated in the profile rail at the left side of the CPU. Due to the parallel SPEED-Bus not all slots must be occupied in sequence.
You may assemble the System 300 horizontally, vertically or lying.
Please regard the allowed environment temperatures:
1 horizontal assembly: from 0 to 60°C
2 vertical assembly: from 0 to 50°C
3 lying assembly: from 0 to 55°C
3.2 Installation dimensions
Dimensions Basic
enclosure
2tier width (WxHxD) in mm: 80 x 125 x 120
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VIPA System 300S Assembly and installation guidelines
Installation dimensions
Dimensions
Installation dimensions
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Page 20
Assembly SPEED-Bus
3.3 Assembly SPEED-Bus
VIPA System 300SAssembly and installation guidelines
Pre-manufactured
SPEED-Bus profile rail
Dimensions
For the deployment of SPEED-Bus modules, a pre-manufactured
SPEED-Bus rail is required. This is available mounted on a profile rail
with 2, 6 or 10 extension slots.
Order
number
391-1AF10 2/6 530 100 268 510 10
391-1AF30 6/2 530 100 105 510 10
391-1AF50 10/0 530 20 20 510 10
391-1AJ10 2/15 830 22 645 800 15
391-1AJ30 6/11 830 22 480 800 15
Number of modules
SPEED-Bus/Standard
bus
A B C D E
391-1AJ50 10/7 830 22 320 800 15
Measures in mm
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VIPA System 300S Assembly and installation guidelines
Assembly SPEED-Bus
Installation of the profile rail
1. Bolt the profile rail with the background (screw size: M6), so that
you still have minimum 65mm space above and 40mm below
the profile rail. Please look for a low-impedance connection
between profile rail and background.
2. Connect the profile rail with the protected earth conductor
. The
minimum cross-section of the cable to the protected earth conductor has to be 10mm2.
Installation SPEED-Bus
module
1. Dismantle the according protection flaps of the SPEED-Bus slot
with a screw driver (open and pull down).
For the SPEED-Bus is a parallel bus, not every SPEED-Bus slot
must be used in series. Leave the protection flap installed at an
unused SPEED-Bus slot.
2. At deployment of a DC 24V power supply
, install it at the shown
position at the profile rail at the left side of the SPEED-Bus and
push it to the left to the isolation bolt of the profile rail.
3. Fix the power supply by screwing.
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Page 22
Assembly SPEED-Bus
VIPA System 300SAssembly and installation guidelines
Installation CPU without
Standard-Bus-Modules
4. T
o connect the SPEED-Bus modules, plug it between the triangular positioning helps to a slot marked with "SLOT ..." and pull
it down.
5. Fix the CPU by screwing.
1. T
o deploy the SPEED7-CPU exclusively at the SPEED-Bus,
plug it between the triangular positioning helps to the slot
marked with "CPU SPEED7" and pull it down.
2. Fix the CPU by screwing.
Installation CPU with
Standard-Bus-Modules
Installation StandardBus-Modules
1. If also standard modules shall be plugged, take a bus coupler
and click it at the CPU from behind like shown in the picture.
Plug the CPU between the triangular positioning helps to the slot
marked with "CPU SPEED7" and pull it down.
2. Fix the CPU by screwing.
Repeat this procedure with the peripheral modules, by clicking a
backplane bus coupler
, stick the module right from the modules
you've already fixed, click it downwards and connect it with the
backplane bus coupler of the last module and bolt it.
HB140 | CPU | 314-6CF03 | GB | 16-43 22
Page 23
VIPA System 300S Assembly and installation guidelines
Assembly standard bus
CAUTION!
– The power supplies must be released before instal-
lation and repair tasks, i.e. before handling with the
power supply or with the cabling you must disconnect current/voltage (pull plug, at fixed connection
switch of
f the concerning fuse)!
– Installation and modifications only by properly
trained personnel!
3.4 Assembly standard bus
General
Profile rail
The single modules are directly installed on a profile rail and connected via the backplane bus connector
. Before installing the
modules you have to clip the backplane bus connector to the module
from the backside. The backplane bus connector is delivered together
with the peripheral modules.
Order number A B C
390-1AB60 160 140 10
390-1AE80 482 466 8.3
390-1AF30 530 500 15
390-1AJ30 830 800 15
390-9BC00* 2000 Drillings only left 15
*) Unit pack: 10 pieces
Measures in mm
HB140 | CPU | 314-6CF03 | GB | 16-43 23
Page 24
Assembly standard bus
Bus connector
VIPA System 300SAssembly and installation guidelines
For the communication between the modules the System 300S uses
a backplane bus connector
. Backplane bus connectors are included
in the delivering of the peripheral modules and are clipped at the
module from the backside before installing it to the profile rail.
Assembly possibilities
Approach
Please regard the allowed environment temperatures:
n horizontal assembly: from 0 to 60°C
n vertical assembly: from 0 to 40°C
n lying assembly: from 0 to 40°C
1. Bolt the profile rail with the background (screw size: M6), so that
you still have minimum 65mm space above and 40mm below
the profile rail.
2. If the background is a grounded metal or device plate, please
look for a low-impedance connection between profile rail and
background.
3. Connect the profile rail with the protected earth conductor
. For
this purpose there is a bolt with M6-thread.
4. The minimum cross-section of the cable to the protected earth
conductor has to be 10mm2.
5. Stick the power supply to the profile rail and pull it to the left side
to the grounding bolt of the profile rail.
6. Fix the power supply by screwing.
7. T
ake a backplane bus connector and click it at the CPU from the
backside like shown in the picture.
8. Stick the CPU to the profile rail right from the power supply and
pull it to the power supply
.
HB140 | CPU | 314-6CF03 | GB | 16-43 24
Page 25
VIPA System 300S Assembly and installation guidelines
Cabling
9. Click the CPU downwards and bolt it like shown.
10. Repeat this procedure with the peripheral modules, by clicking a
backplane bus connector
modules you've already fixed, click it downwards and connect it
with the backplane bus connector of the last module and bolt it.
, stick the module right from the
3.5 Cabling
CAUTION!
– The power supplies must be released before instal-
lation and repair tasks, i.e. before handling with the
power supply or with the cabling you must disconnect current/voltage (pull plug, at fixed connection
switch off the concerning fuse)!
– Installation and modifications only by properly
trained personnel!
HB140 | CPU | 314-6CF03 | GB | 16-43 25
Page 26
Cabling
VIPA System 300SAssembly and installation guidelines
CageClamp technology
(green)
For the cabling of power supply of a CPU, a green plug with CageClamp technology is deployed. The connection clamp is realized as
plug that may be clipped of
f carefully if it is still cabled.
Here wires with a cross-section of 0.08mm2 to 2.5mm2 may be connected. You can use flexible wires without end case as well as stiff
wires.
1 Test point for 2mm test tip
2 Locking (orange) for screwdriver
3 Round opening for wires
The picture on the left side shows the cabling step by step from top
.
view
1. For cabling you push the locking vertical to the inside with a
suiting screwdriver and hold the screwdriver in this position.
2. Insert the de-isolated wire into the round opening. Y
wires with a cross-section from 0.08mm2 to 2.5mm
ou may use
2
3. By removing the screwdriver the wire is connected safely with
the plug connector via a spring.
HB140 | CPU | 314-6CF03 | GB | 16-43 26
Page 27
VIPA System 300S Assembly and installation guidelines
Installation guidelines
Front connector I/O
periphery
40 pole front connector order number 392-1AM00
1. Open the front flap of your I/O module.
2. Bring the front connector in cabling position.
For this you plug the front connector on the module until it locks.
In this position the front connector juts out of the module and
has no contact yet.
3. De-isolate your wires. If needed, use core end cases.
4. If you want to lead out your cables from the bottom of the
module, start with the cabling from bottom to top, res. from top
to bottom, if the cables should be led out at the top.
5. Bolt also the connection screws of not cabled screw clamps.
6. Put the included cable binder around the cable bundle and the
front connector
.
3.6
Installation guidelines
7. Fix the cable binder for the cable bundle.
8. Bolt the fixing screw of the front connector
9. Now the front connector is electrically connected with your
module.
10. Close the front flap.
11. Fill out the labeling strip to mark the single channels and push
the strip into the front flap.
.
General
HB140 | CPU | 314-6CF03 | GB | 16-43 27
The installation guidelines contain information about the interference
free deployment of a PLC system. There is the description of the
ways, interference may occur in your PLC, how you can make sure
the electromagnetic compatibility (EMC), and how you manage the
isolation.
Page 28
Installation guidelines
VIPA System 300SAssembly and installation guidelines
What does EMC mean?
Possible interference
causes
Electromagnetic compatibility (EMC) means the ability of an electrical
device, to function error free in an electromagnetic environment
without being interfered respectively without interfering the environment.
The components of VIP
A are developed for the deployment in industrial environments and meets high demands on the EMC. Nevertheless you should project an EMC planning before installing the components and take conceivable interference causes into account.
Electromagnetic interferences may interfere your control via different
ways:
n Electromagnetic fields (RF coupling)
n Magnetic fields with power frequency
n Bus system
n Power supply
n Protected earth conductor
Depending on the spreading medium (lead bound or lead free) and
the distance to the interference cause, interferences to your control
occur by means of dif
ferent coupling mechanisms.
There are:
Basic rules for EMC
n galvanic coupling
n capacitive coupling
n inductive coupling
n radiant coupling
In the most times it is enough to take care of some elementary rules
to guarantee the EMC. Please regard the following basic rules when
installing your PLC.
ake care of a correct area-wide grounding of the inactive metal
n T
parts when installing your components.
– Install a central connection between the ground and the pro-
tected earth conductor system.
– Connect all inactive metal extensive and impedance-low.
– Please try not to use aluminium parts. Aluminium is easily oxi-
dizing and is therefore less suitable for grounding.
n When cabling, take care of the correct line routing.
– Organize your cabling in line groups (high voltage, current
supply, signal and data lines).
– Always lay your high voltage lines and signal respectively data
lines in separate channels or bundles.
– Route the signal and data lines as near as possible beside
ground areas (e.g. suspension bars, metal rails, tin cabinet).
HB140 | CPU | 314-6CF03 | GB | 16-43 28
Page 29
VIPA System 300S Assembly and installation guidelines
Installation guidelines
n Proof the correct fixing of the lead isolation.
–
Data lines must be laid isolated.
– Analog lines must be laid isolated. When transmitting signals
with small amplitudes the one sided laying of the isolation may
be favourable.
– Lay the line isolation extensively on an isolation/protected
earth conductor rail directly after the cabinet entry and fix the
isolation with cable clamps.
– Make sure that the isolation/protected earth conductor rail is
connected impedance-low with the cabinet.
– Use metallic or metallised plug cases for isolated data lines.
n In special use cases you should appoint special EMC actions.
– Consider to wire all inductivities with erase links.
– Please consider luminescent lamps can influence signal lines.
n Create a homogeneous reference potential and ground all elec-
trical operating supplies when possible.
– Please take care for the targeted employment of the grounding
actions. The grounding of the PLC serves for protection and
functionality activity.
– Connect installation parts and cabinets with your PLC in star
topology with the isolation/protected earth conductor system.
So you avoid ground loops.
– If there are potential differences between installation parts and
cabinets, lay sufficiently dimensioned potential compensation
lines.
Isolation of conductors
Electrical, magnetically and electromagnetic interference fields are
weakened by means of an isolation, one talks of absorption. Via the
isolation rail, that is connected conductive with the rack, interference
currents are shunt via cable isolation to the ground. Here you have to
make sure, that the connection to the protected earth conductor is
impedance-low, because otherwise the interference currents may
appear as interference cause.
When isolating cables you have to regard the following:
n If possible, use only cables with isolation tangle.
n The hiding power of the isolation should be higher than 80%.
n Normally you should always lay the isolation of cables on both
sides. Only by means of the both-sided connection of the isolation
you achieve high quality interference suppression in the higher
frequency area. Only as exception you may also lay the isolation
one-sided. Then you only achieve the absorption of the lower frequencies. A one-sided isolation connection may be convenient, if:
the conduction of a potential compensating line is not possible.
–
– analog signals (some mV respectively µA) are transferred.
– foil isolations (static isolations) are used.
n With data lines always use metallic or metallised plugs for serial
couplings. Fix the isolation of the data line at the plug rack. Do not
lay the isolation on the PIN 1 of the plug bar!
n At stationary operation it is convenient to strip the insulated cable
interruption free and lay it on the isolation/protected earth conductor line.
HB140 | CPU | 314-6CF03 | GB | 16-43 29
Page 30
Installation guidelines
VIPA System 300SAssembly and installation guidelines
n T
o fix the isolation tangles use cable clamps out of metal. The
clamps must clasp the isolation extensively and have well contact.
n Lay the isolation on an isolation rail directly after the entry of the
cable in the cabinet. Lead the isolation further on to your PLC and
don't lay it on there again!
CAUTION!
Please regard at installation!
At potential dif
ferences between the grounding points,
there may be a compensation current via the isolation
connected at both sides.
Remedy: Potential compensation line
HB140 | CPU | 314-6CF03 | GB | 16-43 30
Page 31
VIPA System 300S Hardware description
Properties
4 Hardware description
4.1 Properties
CPU 314-6CF03
n SPEED7 technology and SPEED-Bus integrated
n 512kbyte work memory integrated (256kbyte code, 256kbyte data)
ork memory expandable to max. 2Mbyte (1Mbyte code, 1Mbyte
n W
data)
n 2Mbyte load memory
n PROFIBUS DP master integrated (DP-V0, DP-V1)
n RS485 interface configurable for PROFIBUS DP master respec-
tively PtP communication
n Ethernet PG/OP interface integrated
n MPI interface
n MCC slot for external memory cards (lockable)
n Status LEDs for operating state and diagnostics
n Real-time clock battery buffered
n Fast digital I/Os: DI 8xDC24V / DIO 8xDC 24V, 0.5A
n Analog I/Os: AI 4x12Bit / AO 2x12Bit / AI 1xPt100
n 4 counter (100kHz)
n I/O address range digital/analog 8191byte
n 512 timer
n 512 counter
n 8192 flag byte
Ordering data
Type Order number Description
CPU 314ST 314-6CF03 SPEED-Bus, MPI interface, card slot, real time
clock, Ethernet interface for PG/OP
master, DI 8xDC24V / DIO 8xDC24V, 0.5A, AI
4x12Bit / AO 2x12Bit / AI 1xPt100, 4 Counter
HB140 | CPU | 314-6CF03 | GB | 16-43 31
, PROFIBUS DP
Page 32
Structure > Interfaces
4.2 Structure
VIPA System 300SHardware description
4.2.1
CPU 314-6CF03
4.2.2
General
Interfaces
1 LEDs of the integrated PROFIBUS DP master
2 Storage media slot (lockable)
3 LEDs of the CPU part
4 LEDs of the I/O part
5 Operating mode switch CPU
6 Slot for DC 24V power supply
7 Twisted pair interface for Ethernet PG/OP channel
8 MPI interface
9 PROFIBUS DP/PtP interface
The components 6 - 9 are under the front flap!
Power supply X1
The CPU has an integrated power supply.
n The power supply has to be provided with DC 24V
the double DC 24V slot, that is underneath the flap.
n Via the power supply not only the internal electronic is provided
with voltage, but by means of the backplane bus also the connected modules.
HB140 | CPU | 314-6CF03 | GB | 16-43 32
. For this serves
Page 33
VIPA System 300S Hardware description
Structure > Interfaces
n The power supply is protected against polarity inversion and over-
current.
n The internal electronic is galvanically connected with the supply
voltage.
Each SPEED-Bus rail has a slot for an external power
supply
. This allows you to raise the maximum current
at the back plane bus. The deployment of this external
power supply at the CPU 314-6CF03 is not permitted!
X2: MPI interface
X5: Ethernet PG/OP
channel
9pin SubD jack:
n The MPI interface serves for the connection between program-
ming unit and CPU.
n By means of this the project engineering and programming hap-
pens.
n MPI serves for communication between several CPUs or between
HMIs and CPU.
n Standard setting is MPI Address 2.
8pin RJ45 jack:
n The RJ45 jack serves the interface to the Ethernet PG/OP
channel.
n This interface allows you to program res. remote control your
CPU, to access the internal web site or to connect a visualization.
n Configurable connections are not possible.
n For online access to the CPU via Ethernet PG/OP channel valid
IP address parameters have to be assigned to this.
HB140 | CPU | 314-6CF03 | GB | 16-43 33
Page 34
Structure > Storage media slot
VIPA System 300SHardware description
X3: PROFIBUS/PtP
interface with configurable functionality
9pin SubD jack:
The CPU has a PROFIBUS/PtP interface with a fix pinout. After an
overall reset the interface is deactivated. By appropriate configuration, the following functions for this interface may be enabled:
n PROFIBUS DP master operation
Configuration via PROFIBUS sub module X1 (MPI/DP) with
–
‘Operation mode’ master in the hardware configuration.
n PROFIBUS DP slave operation
– Configuration via PROFIBUS sub module X1 (MPI/DP) with
‘Operation mode’ slave in the hardware configuration.
n PtP functionality
– Using the PtP functionality the RS485 interface is allowed to
connect via serial point-to-point connection to different source
res. target systems.
– Here the following protocols are supported: ASCII, STX/ETX,
3964R, USS and Modbus-Master (ASCII, RTU).
– The activation of the PtP functionality happens by embedding
the SPEEDBUS.GSD from VIPA in the hardware catalog. After
the installation the CPU may be configured in a PROFIBUS
master system and here the interface may be switched to PtP
communication.
4.2.3 Memory management
Memory
The CPU has an integrated memory. Information about the capacity
of the memory may be found at the front of the CPU. The memory is
divided into the following parts:
n Load memory 2Mbyte
n Code memory (50% of the work memory)
n Data memory (50% of the work memory)
n W
4.2.4 Storage media slot
n As external storage medium for applications and firmware you
n The VIP
n After PowerON respectively an overall reset the CPU checks, if
n Push the memory card into the slot until it snaps in leaded by a
n By sliding down the sliding mechanism, a just installed memory
n To remove, slide the sliding mechanism up again and push the
ork memory 512kbyte
– There is the possibility to extend the work memory to its max-
imum printed capacity 2Mbyte by means of a MCC memory
extension card.
may use a MMC storage module (Multimedia card).
A storage media are pre-formatted with the PC format
FAT16 and can be accessed via a card reader.
there is a storage medium with data valid for the CPU.
spring mechanism. This ensures contacting.
card can be protected against drop out.
storage media against the spring pressure until it is unlocked with
a click.
HB140 | CPU | 314-6CF03 | GB | 16-43 34
Page 35
VIPA System 300S Hardware description
Structure > Battery backup for clock and RAM
CAUTION!
If the media was already unlocked by the spring mechanism, with shifting the sliding mechanism, a just
installed memory card can jump out of the slot!
4.2.5 Battery backup for clock and RAM
A rechargeable battery is installed on every CPU to safeguard the
contents of the RAM when power is removed. This battery is also
used to buf
tained by a charging circuit that receives its power from the internal
power supply and that maintain the clock and RAM for a max. period
of 30 days.
fer the internal clock. The rechargeable battery is main-
– Please connect the CPU at least for 24 hours to the
power supply
, so that the internal accumulator/
battery is loaded accordingly.
– Please note that in case of repeated discharge
cycles (charging/buffering) can reduce the buffer
time continuously. Only after a charging time of 24
hours there is a buffer for max. 30 days.
CAUTION!
– After a power reset and with an empty battery the
CPU starts with a BA
T error and executes an
overall reset. The loading procedure is not influenced by the BAT error.
– The BAT error can be deleted again, if once during
power cycle the time between switching on and off
the power supply is at least 30sec. and the battery
is fully loaded. Otherwise with a short power cycle
the BAT error still exists and an overall reset is executed.
HB140 | CPU | 314-6CF03 | GB | 16-43 35
Page 36
Structure > LEDs
4.2.6 Operating mode switch
n With the operating mode switch you may switch the CPU between
ST
n During the transition from STOP to RUN the operating mode
START-UP is driven by the CPU.
n Placing the switch to MRES (Memory Reset), you request an
overall reset with following load from MMC, if a project there
exists.
4.2.7 LEDs
VIPA System 300SHardware description
OP and RUN.
LEDs CPU
As soon as the CPU is supplied with 5V
, the green PW-LED (Power)
is on.
RN
(RUN)ST(ST
green
Boot-up after PowerON
● BB* ● ● ● * Blinking with 10Hz: Firmware is loaded.
● ● ● ● ● Initialization: Phase 1
● ● ● ● ○ Initialization: Phase 2
● ● ● ○ ○ Initialization: Phase 3
○ ● ● ○ ○ Initialization: Phase 4
Operation
○ ● X X X CPU is in STOP state.
BB ● X X X CPU is in start-up state, the RUN LED blinks during
OP)SF(SFAIL)FC(FRCE)MC(MMC)
yellow red yellow yellow
Meaning
operating OB100 at least for 3s.
● ○ ○ X X CPU is in state RUN without error.
X X ● X X There is a system fault. More information may be
found in the diagnostics buf
X X X ● X Variables are forced.
X X X X ● Access to the memory card.
X BB* ○ ○ ○ * Blinking with 10Hz: Configuration is loaded.
Overall reset
○ BB X X X Overall reset is requested.
○ BB* X X X * Blinking with 10Hz: Overall reset is executed.
Factory reset
● ● ○ ○ ○ Factory reset is executed.
○ ● ● ● ● Factory reset finished without error.
fer of the CPU.
HB140 | CPU | 314-6CF03 | GB | 16-43 36
Page 37
VIPA System 300S Hardware description
Structure > LEDs
RN
(RUN)ST(ST
Firmware update
○ ● BB BB ● The alternate blinking indicates that there is new
○ ○ BB BB ● The alternate blinking indicates that a firmware
○ ● ● ● ● Firmware update finished without error.
○ BB* BB* BB* BB* * Blinking with 10Hz: Error during Firmware update.
on: ● | off: ○ | blinking (2Hz): BB | not relevant: X
LEDs Ethernet PG/OP channel L/A, S
The green L/A-LED (Link/Activity) indicates the physical connection of the Ethernet PG/OP channel to
Ethernet. Irregular flashing of the L/A-LED indicates communication of the Ethernet PG/OP channel via
Ethernet.
If the green S-LED (Speed) is on, the Ethernet PG/OP has a communication speed of 100MBit/s otherwise
10MBit/s.
LEDs PROFIBUS/PtP
interface X3
OP)SF(SFAIL)FC(FRCE)MC(MMC)
Dependent on the mode of operation the LEDs show information
about the state of operation of the PROFIBUS part according to the
Meaning
firmware on the memory card.
update is executed.
following pattern:
Master operation
RN
(RUN)
ER
(ERR)
DE IF Meaning
green red green red
○ ○ ○ ○ Master has no project, this means the interface is
deactivated respectively PtP is active.
● ○ ○ ○ Master has bus parameters and is in RUN without
slaves.
● ○ BB ○ Master is in "clear" state (safety state). The inputs of
the slaves may be read. The outputs are disabled.
● ○ ● ○ Master is in "operate" state, this means data exchange
between master and slaves. The outputs may be
accessed.
● ● ● ○ CPU is in RUN, at least 1 slave is missing.
● ● BB ○ CPU is in STOP, at least 1 slave is missing.
○ ○ ○ ● Initialization error at faulty parametrization.
○ ● ○ ● Waiting state for start command from CPU.
on: ● | off: ○ | blinking (2Hz): BB
HB140 | CPU | 314-6CF03 | GB | 16-43 37
Page 38
Structure > LEDs
Slave operation
VIPA System 300SHardware description
RN
(RUN)
green
ER
DE IF Meaning
(ERR)
red green red
○ ○ ○ ○ Slave has no project respectively PtP is active.
BB ○ ○ ○ Slave is without master.
BB* ○ BB* ○ * Alternate flashing at configuration faults.
● ○ ● ○ Slave exchanges data between master.
on: ● | off: ○ | blinking (2Hz): BB
HB140 | CPU | 314-6CF03 | GB | 16-43 38
Page 39
VIPA System 300S Hardware description
Structure > In-/Output range CPU 314-6CF03
4.2.8 In-/Output range CPU 314-6CF03
Overview CPU
314-6CF03
The CPU 314-6CF03 has the following analog and digital in- and
output ranges integrated in one casing:
n Analog input: 4x12Bit, 1xPt100
n Analog output: 2x12Bit
n Digital input: 8xDC 24V
, interrupt capable, 4 counter
n Digital in-/output: 8xDC 24V, 0.5A
CAUTION!
Please regard that the voltage at an output channel is
always £ the supply voltage connected to L+. Please
regard also that due to the parallel connection of inand output channel for each group one set output can
be supplied via a connected input signal. A thus connected output remains active even with shut down
supply voltage. Non-observance may cause damages
of the module.
HB140 | CPU | 314-6CF03 | GB | 16-43 39
Page 40
Structure > In-/Output range CPU 314-6CF03
CPU 314-6CF03: Analog part pin assignment and status indicator
Pin Assignment LEDs Description
1 Power supply DC 24V AIO 1L+
2 Voltage measurement channel 0
3 Current measurement channel 0
4 Ground channel 0
5 Voltage measurement channel 1
6 Current measurement channel 1
7 Ground channel 1
8 Voltage measurement channel 2
9 Current measurement channel 2
10 Ground channel 2
11 Voltage measurement channel 3
VIPA System 300SHardware description
LED (green)
Supply voltage
available
F
LED (red)
Sum error
12 Current measurement channel 3
13 Ground channel 3
14 Pt 100 channel 4
15 Pt 100 channel 4
16 Output + channel 5
17 Ground output channel 5
18 Output + channel 6
19 Ground output channel 6
20 Ground power supply AIO
HB140 | CPU | 314-6CF03 | GB | 16-43 40
Page 41
VIPA System 300S Hardware description
Technical data
CPU 314-6CF03: Digital part pin assignment and status indicator
Pin Assignment LEDs Description
21 Power supply +DC 24 V DI DI:
22 I+0.0 / Counter 0(A)
23 I+0.1 / Counter 0(B)
24 I+0.2 / Gate0/Latch0/Reset0
25 I+0.3 / Counter 1(A)
26 I+0.4 / Counter 1(B)
27 I+0.5 / Gate1/Latch1/Reset1
28 I+0.6 / Counter 2(A)
29 I+0.7 / Counter 2(B)
30 Ground DI
31 Power supply +DC 24 V DIO
32 I/Q+1.0 / Gate2/Latch2/Reset2
33 I/Q+1.1 / Counter 3(A)
34 I/Q+1.2 / Counter 3(B)
35 I/Q+1.3 / Gate3/Latch3/Reset3
36 I/Q+1.4 / OUT0/Latch0/Reset0
37 I/Q+1.5 / OUT1/Latch1/Reset1
38 I/Q+1.6 / OUT2/Latch2/Reset2
39 I/Q+1.7 / OUT3/Latch3/Reset3
40 Ground DIO
.0 ... .7
LED (green)
I+0.0 ... I+0.7
starting with ca.
15V the signal
"1" at the input is
recognized and
the according
LED is activated
DIO:
2L+
LED (green)
Supply voltage
available for DIO
.0 ... .7
LED (green)
I/Q+1.0 ... I/Q
+1.7
on at active
output/input
F
LED (red)
Overload or
short circuit error
4.3 Technical data
Order no. 314-6CF03
Type CPU 314ST/DPM
SPEED-Bus
Technical data power supply
Power supply (rated value) DC 24 V
Power supply (permitted range) DC 20.4...28.8 V
Reverse polarity protection
Current consumption (no-load operation) 300 mA
Current consumption (rated value) 1 A
Inrush current 5 A
I²t 0.5 A²s
Max. current drain at backplane bus 2.5 A
Max. current drain load supply -
ü
ü
HB140 | CPU | 314-6CF03 | GB | 16-43 41
Page 42
Technical data
Order no. 314-6CF03
Power loss 14 W
Technical data digital inputs
Number of inputs 8
Cable length, shielded 1000 m
Cable length, unshielded 600 m
Rated load voltage DC 24 V
VIPA System 300SHardware description
Reverse polarity protection of rated load
ü
voltage
Current consumption from load voltage L+
70 mA
(without load)
Rated value DC 24 V
Input voltage for signal "0" DC 0...5 V
Input voltage for signal "1" DC 15...28.8 V
Input voltage hysteresis -
Frequency range -
Input resistance -
Input current for signal "1" 6 mA
Connection of Two-Wire-BEROs possible
ü
Max. permissible BERO quiescent current 1.5 mA
Input delay of "0" to "1" parameterizable 2.56µs - 40ms
Input delay of "1" to "0" parameterizable 2.56µs - 40ms
Number of simultaneously utilizable inputs hori-
8
zontal configuration
Number of simultaneously utilizable inputs ver-
8
tical configuration
Input characteristic curve IEC 61131-2, type 1
Initial data size 34 Byte
Technical data digital outputs
Number of outputs 8
Cable length, shielded 1000 m
Cable length, unshielded 600 m
Rated load voltage DC 24 V
Reverse polarity protection of rated load
-
voltage
Current consumption from load voltage L+
30 mA
(without load)
HB140 | CPU | 314-6CF03 | GB | 16-43 42
Page 43
VIPA System 300S Hardware description
Technical data
Order no. 314-6CF03
Total current per group, horizontal configura-
4 A
tion, 40°C
Total current per group, horizontal configura-
3 A
tion, 60°C
Total current per group, vertical configuration 3 A
Output voltage signal "1" at min. current L+ (-0.8 V)
Output voltage signal "1" at max. current L+ (-0.8 V)
Output current at signal "1", rated value 0.5 A
Output current, permitted range to 40°C 5 mA to 0.6 A
Output current, permitted range to 60°C 5 mA to 0.6 A
Output current at signal "0" max. (residual cur-
100 µA
rent)
Output delay of "0" to "1" 100 µs
Output delay of "1" to "0" 100 µs
Minimum load current -
Lamp load 5 W
Parallel switching of outputs for redundant con-
possible
trol of a load
Parallel switching of outputs for increased
not possible
power
Actuation of digital input
ü
Switching frequency with resistive load max. 2.5 kHz
Switching frequency with inductive load max. 0.5 Hz
Switching frequency on lamp load max. 2.5 kHz
Internal limitation of inductive shut-off voltage L+ (-52 V)
Short-circuit protection of output yes, electronic
Trigger level 1 A
Number of operating cycle of relay outputs -
Switching capacity of contacts -
Output data size 18 Byte
Technical data analog inputs
Number of inputs 5
Cable length, shielded 200 m
Rated load voltage DC 24 V
Reverse polarity protection of rated load
ü
voltage
HB140 | CPU | 314-6CF03 | GB | 16-43 43
Page 44
Technical data
Order no. 314-6CF03
VIPA System 300SHardware description
Current consumption from load voltage L+
85 mA
(without load)
Voltage inputs
ü
Min. input resistance (voltage range) 120 kΩ
Input voltage ranges -10 V ... +10 V
0 V ... +10 V
Operational limit of voltage ranges +/-0.3%
Operational limit of voltage ranges with SFU -
Basic error limit voltage ranges +/-0.3%
Basic error limit voltage ranges with SFU -
Destruction limit voltage max. 15V
Current inputs
ü
Max. input resistance (current range) 85 Ω
Input current ranges -20 mA ... +20 mA
0 mA ... +20 mA
+4 mA ... +20 mA
Operational limit of current ranges +/-0.3%
Operational limit of current ranges with SFU -
Basic error limit current ranges +/-0.2%
Radical error limit current ranges with SFU -
Destruction limit current inputs (electrical cur-
max. 50mA
rent)
Destruction limit current inputs (voltage) max. 15V
Resistance inputs
ü
Resistance ranges 0 ... 600 Ohm
Operational limit of resistor ranges +/-0.4%
Operational limit of resistor ranges with SFU -
Basic error limit +/-0.2%
Basic error limit with SFU -
Destruction limit resistance inputs max. 15V
Resistance thermometer inputs
ü
Resistance thermometer ranges Pt100
Pt1000
Ni100
Ni1000
HB140 | CPU | 314-6CF03 | GB | 16-43 44
Page 45
VIPA System 300S Hardware description
Technical data
Order no. 314-6CF03
Operational limit of resistance thermometer
+/-0.6%
ranges
Operational limit of resistance thermometer
-
ranges with SFU
Basic error limit thermoresistor ranges +/-0.4%
Basic error limit thermoresistor ranges with
-
SFU
Destruction limit resistance thermometer inputs max. 15V
Thermocouple inputs -
Thermocouple ranges -
Operational limit of thermocouple ranges -
Operational limit of thermocouple ranges with
-
SFU
Basic error limit thermoelement ranges -
Basic error limit thermoelement ranges with
-
SFU
Destruction limit thermocouple inputs -
Programmable temperature compensation -
External temperature compensation -
Internal temperature compensation -
Technical unit of temperature measurement °C
Resolution in bit 12
Measurement principle Sigma-Delta
Basic conversion time 6 ms
Noise suppression for frequency 80 dB
Initial data size 10 Byte
Technical data analog outputs
Number of outputs 2
Cable length, shielded 200 m
Rated load voltage DC 24 V
Reverse polarity protection of rated load
ü
voltage
Current consumption from load voltage L+
-
(without load)
Voltage output short-circuit protection -
Voltage outputs
ü
Min. load resistance (voltage range) 1 kΩ
HB140 | CPU | 314-6CF03 | GB | 16-43 45
Page 46
Technical data
Order no. 314-6CF03
Max. capacitive load (current range) 1 µF
Max. inductive load (current range) 30 mA
Output voltage ranges -10 V ... +10 V
0 V ... +10 V
Operational limit of voltage ranges +/-0.4%
Basic error limit voltage ranges with SFU +/-0.3%
VIPA System 300SHardware description
Destruction limit against external applied
max. 15V
voltage
Current outputs
ü
Max. in load resistance (current range) 500 Ω
Max. inductive load (current range) 10 mH
Typ. open circuit voltage current output 16 V
Output current ranges -20 mA ... +20 mA
0 mA ... +20 mA
+4 mA ... +20 mA
Operational limit of current ranges +/-0.4%
Radical error limit current ranges with SFU +/-0.3%
Destruction limit against external applied
max. 15V
voltage
Settling time for ohmic load 0.2 ms
Settling time for capacitive load 0.5 ms
Settling time for inductive load 0.75 ms
Resolution in bit 12
Conversion time 1 ms
Substitute value can be applied yes
Output data size 4 Byte
Technical data counters
Number of counters 4
Counter width 32 Bit
Maximum input frequency 100 kHz
Maximum count frequency 100 kHz
Mode incremental encoder
Mode pulse / direction
Mode pulse
ü
ü
ü
Mode frequency counter -
HB140 | CPU | 314-6CF03 | GB | 16-43 46
Page 47
VIPA System 300S Hardware description
Technical data
Order no. 314-6CF03
Mode period measurement -
Gate input available
Latch input available
Reset input available
Counter output available
ü
ü
ü
ü
Load and working memory
Load memory, integrated 2 MB
Load memory, maximum 2 MB
Work memory, integrated 512 KB
Work memory, maximal 2 MB
Memory divided in 50% program / 50% data
ü
Memory card slot MMC-Card with max. 1 GB
Hardware configuration
Racks, max. 4
Modules per rack, max. 8 in multiple-, 32 in a single-rack configuration
Number of integrated DP master 1
Number of DP master via CP 4
Operable function modules 8
Operable communication modules PtP 8
Operable communication modules LAN 8
Status information, alarms, diagnostics
Status display yes
Interrupts yes
Process alarm yes, parameterizable
Diagnostic interrupt yes, parameterizable
Diagnostic functions yes
Diagnostics information read-out possible
Supply voltage display green LED
Group error display red SF LED
Channel error display red LED per group
Isolation
Between channels
ü
Between channels of groups to 8
Between channels and backplane bus
ü
HB140 | CPU | 314-6CF03 | GB | 16-43 47
Page 48
Technical data
Order no. 314-6CF03
Between channels and power supply -
Max. potential difference between circuits DC 75 V/ AC 50 V
Max. potential difference between inputs (Ucm) -
VIPA System 300SHardware description
Max. potential difference between Mana and
-
Mintern (Uiso)
Max. potential difference between inputs and
-
Mana (Ucm)
Max. potential difference between inputs and
-
Mintern (Uiso)
Max. potential difference between Mintern and
-
outputs
Insulation tested with DC 500 V
Command processing times
Bit instructions, min. 0.01 µs
Word instruction, min. 0.01 µs
Double integer arithmetic, min. 0.01 µs
Floating-point arithmetic, min. 0.06 µs
Timers/Counters and their retentive characteristics
Number of S7 counters 512
S7 counter remanence 0 .. 512
S7 counter remanence adjustable C0 .. C7
Number of S7 times 512
S7 times remanence 0 .. 512
S7 times remanence adjustable not retentive
Data range and retentive characteristic
Number of flags 8192 Byte
Bit memories retentive characteristic adjustable 0 .. 8192
Bit memories retentive characteristic preset MB0 .. MB15
Number of data blocks 4095
Max. data blocks size 64 KB
Max. local data size per execution level 1024 Byte
Blocks
Number of OBs 23
Number of FBs 2048
Number of FCs 2048
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Page 49
VIPA System 300S Hardware description
Technical data
Order no. 314-6CF03
Maximum nesting depth per priority class 8
Maximum nesting depth additional within an
4
error OB
Time
Real-time clock buffered
ü
Clock buffered period (min.) 6 w
Accuracy (max. deviation per day) 10 s
Number of operating hours counter 8
Clock synchronization
ü
Synchronization via MPI Master/Slave
Synchronization via Ethernet (NTP) no
Address areas (I/O)
Input I/O address area 8192 Byte
Output I/O address area 8192 Byte
Input process image maximal 2048 Byte
Output process image maximal 2048 Byte
Digital inputs 65536
Digital outputs 65536
Digital inputs central 1032
Digital outputs central 1032
Integrated digital inputs 8
Integrated digital outputs 8
Analog inputs 1024
Analog outputs 1024
Analog inputs, central 261
Analog outputs, central 258
Integrated analog inputs 5
Integrated analog outputs 2
Communication functions
PG/OP channel
Global data communication
ü
ü
Number of GD circuits, max. 4
Size of GD packets, max. 22 Byte
S7 basic communication
ü
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Page 50
Technical data
Order no. 314-6CF03
S7 basic communication, user data per job 76 Byte
VIPA System 300SHardware description
S7 communication
S7 communication as server
ü
ü
S7 communication as client -
S7 communication, user data per job 160 Byte
Number of connections, max. 32
PWM data
PWM channels -
PWM time basis -
Period length -
Minimum pulse width -
Type of output -
Functionality Sub-D interfaces
Type X2
Type of interface RS485
Connector Sub-D, 9-pin, female
Electrically isolated
MPI
ü
ü
MP²I (MPI/RS232) -
DP master -
DP slave -
Point-to-point interface -
5V DC Power supply max. 90mA, isolated
24V DC Power supply max. 100mA, non-isolated
Type X3
Type of interface RS485
Connector Sub-D, 9-pin, female
Electrically isolated
ü
MPI -
MP²I (MPI/RS232) -
DP master yes
DP slave yes
Point-to-point interface
ü
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Page 51
VIPA System 300S Hardware description
Technical data
Order no. 314-6CF03
5V DC Power supply max. 90mA, isolated
24V DC Power supply max. 100mA, non-isolated
Functionality MPI
Number of connections, max. 32
PG/OP channel
Routing
Global data communication
S7 basic communication
S7 communication
S7 communication as server
ü
ü
ü
ü
ü
ü
S7 communication as client -
Transmission speed, min. 19.2 kbit/s
Transmission speed, max. 12 Mbit/s
Functionality PROFIBUS master
PG/OP channel
Routing
S7 basic communication
S7 communication
S7 communication as server
ü
ü
ü
ü
ü
S7 communication as client -
Activation/deactivation of DP slaves
Direct data exchange (slave-to-slave communi-
ü
-
cation)
DPV1
ü
Transmission speed, min. 9.6 kbit/s
Transmission speed, max. 12 Mbit/s
Number of DP slaves, max. 124
Address range inputs, max. 1 KB
Address range outputs, max. 1 KB
User data inputs per slave, max. 244 Byte
User data outputs per slave, max. 244 Byte
Functionality PROFIBUS slave
PG/OP channel
Routing
ü
ü
HB140 | CPU | 314-6CF03 | GB | 16-43 51
Page 52
Technical data
Order no. 314-6CF03
VIPA System 300SHardware description
S7 communication
S7 communication as server
ü
ü
S7 communication as client -
Direct data exchange (slave-to-slave communi-
-
cation)
DPV1
ü
Transmission speed, min. 9.6 kbit/s
Transmission speed, max. 12 Mbit/s
Automatic detection of transmission speed -
Transfer memory inputs, max. 244 Byte
Transfer memory outputs, max. 244 Byte
Address areas, max. 32
User data per address area, max. 32 Byte
Point-to-point communication
PtP communication
Interface isolated
ü
ü
RS232 interface -
RS422 interface -
RS485 interface
ü
Connector Sub-D, 9-pin, female
Transmission speed, min. 150 bit/s
Transmission speed, max. 115.5 kbit/s
Cable length, max. 500 m
Point-to-point protocol
ASCII protocol
STX/ETX protocol
3964(R) protocol
ü
ü
ü
RK512 protocol -
USS master protocol
Modbus master protocol
ü
ü
Modbus slave protocol -
Special protocols -
Functionality RJ45 interfaces
Type X5
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Page 53
VIPA System 300S Hardware description
Technical data
Order no. 314-6CF03
Type of interface Ethernet 10/100 MBit
Connector RJ45
Electrically isolated
PG/OP channel
ü
ü
Number of connections, max. 4
Productive connections -
Housing
Material PPE
Mounting Rail System 300
Mechanical data
Dimensions (WxHxD) 80 mm x 125 mm x 120 mm
Weight 480 g
Environmental conditions
Operating temperature 0 °C to 60 °C
Storage temperature -25 °C to 70 °C
Certifications
UL certification yes
KC certification yes
HB140 | CPU | 314-6CF03 | GB | 16-43 53
Page 54
Start-up behavior
5 Deployment CPU 314-6CF03
5.1 Assembly
Information about assembly and cabling:
‘Assembly and installation guidelines’ on page 18
5.2 Start-up behavior
VIPA System 300SDeployment CPU 314-6CF03
Ä
Chapter 3
Turn on power supply
Default boot procedure,
as delivered
Boot procedure with
valid configuration in
the CPU
Boot procedure with
empty battery
After the power supply has been switched on, the CPU changes to
the operating mode the operating mode lever shows.
When the CPU is delivered it has been reset. After a ST
transition the CPU switches to RUN without program.
The CPU switches to RUN with the program stored in the battery buffered RAM.
n The accumulator/battery is automatically loaded via the integrated
power supply and guarantees a buf
time is exceeded, the battery may be totally discharged. This
means that the battery buffered RAM is deleted.
n In this state, the CPU executes an overall reset. If a MMC is
plugged, program code and data blocks are transferred from the
MMC into the work memory of the CPU. If no MMC is plugged, the
CPU transfers permanent stored "protected" blocks into the work
memory if available.
n Depending on the position of the operating mode switch, the CPU
switches to RUN, if OB81 exists, res. remains in STOP. This event
is stored in the diagnostic buffer as: "Start overall reset automatically (unbuffered PowerON)".
fer for max. 30 days. If this
OP®RUN
CAUTION!
After a power reset and with an empty battery the CPU
starts with a BA
The BAT error can be deleted again, if once during
power cycle the time between switching on and off the
power supply is at least 30sec. and the battery is fully
loaded. Otherwise with a short power cycle the BAT
error still exists and an overall reset is executed.
T error and executes an overall reset.
HB140 | CPU | 314-6CF03 | GB | 16-43 54
Page 55
VIPA System 300S Deployment CPU 314-6CF03
Addressing > Addressing
5.3 Addressing
5.3.1
Overview
5.3.2 Addressing
Backplane bus
periphery
To provide specific addressing of the installed peripheral modules,
certain addresses must be allocated in the CPU. At the start-up of the
CPU, this assigns automatically peripheral addresses for digital in-/
output modules starting with 0 and ascending depending on the slot
location. If no hardware project engineering is available, the CPU
stores at the addressing analog modules to even addresses starting
with 256. Modules at the SPEED-Bus are also taken into account at
the automatic address allocation. Here the digital I/Os are stored
beginning with address 128 and analog I/Os, FMs and CPs beginning
with address 2048.
The CPU 314-6CF03 provides an I/O area (address 0 ... 8191) and a
process image of the in- and outputs (each address 0 ... 255). The
process image stores the signal states of the lower address (0 ... 255)
additionally in a separate memory area.
The process image this divided into two parts:
n process image to the inputs (PII)
n process image to the outputs (PIQ)
Max. number of pluggable modules
The process image is updated automatically when a cycle has been
completed.
Maximally 8 modules per row may be configured by the CPU
314-6CF03.
For the project engineering of more than 8 modules you may use line
interface connections. For this you set in the hardware configurator
the module IM 360 from the hardware catalog to slot 3 of your 1. profile rail. Now you may extend your system with up to 3 profile rails by
starting each with an IM 361 from Siemens at slot 3. Considering the
max total current with the CPU 314-6CF03 from VIP
modules may be arranged in a row. Here the installation of the line
connections IM 360/361 from Siemens is not required.
Further 10 modules at the SPEED-Bus may be connected. CPs and
DP masters that are additionally virtual configured at the standard bus
are taken into the count of 32 modules at the standard bus.
A up to 32
HB140 | CPU | 314-6CF03 | GB | 16-43 55
Page 56
Addressing > Addressing
VIPA System 300SDeployment CPU 314-6CF03
Define addresses by
hardware configuration
Automatic addressing
You may access the modules with read res. write accesses to the
peripheral bytes or the process image.
o define addresses a hardware configuration may be used. For this,
T
click on the properties of the according module and set the wanted
address.
CAUTION!
Please take care not to configure a double address
assignment at connection via external PROFIBUS DP
masters - required for project engineering of a SPEEDBus system! At external DP master systems, the Siemens hardware configurator does not execute an
address check!
If you do not like to use a hardware configuration, an automatic
addressing comes into force. At the automatic address allocation
DIOs occupy depending on the slot location always 4byte and AIOs,
FMs, CPs always 16byte at the standard bus and 256byte at the
SPEED-Bus. Depending on the slot location the start address from
where on the according module is stored in the address range is calculated with the following formulas:
Standard-Bus
n DIOs: Start address = 4×(slot-1)
n AIOs, FMs, CPs: Start address = 16×(slot-1)+256
SPEED-Bus
n DIOs: Start address = 4×(slot-101)+128
n AIOs, FMs, CPs: Start address = 256×(slot-101)+2048
HB140 | CPU | 314-6CF03 | GB | 16-43 56
Page 57
VIPA System 300S Deployment CPU 314-6CF03
Addressing > Addressing
Example for automatic
address allocation
The following sample shows the functionality of the automatic
address allocation separated for standard bus and SPEED-Bus:
HB140 | CPU | 314-6CF03 | GB | 16-43 57
Page 58
Addressing > Address assignment I/O part
5.3.3 Address assignment I/O part
VIPA System 300SDeployment CPU 314-6CF03
Overview
n By including the SPEEDBUS.GSD in your hardware configurator
the module is at your disposal in the hardware catalog. After the
installation of the GSD you will find the CPU 314-6CF03 at
‘Additional field devices è I/O è VIPA_SpeedBus’.
n In case there is no hardware configuration available, the in- and
output areas starting at address 1024 are shown in the address
range of the CPU.
n For the data input a range of 48byte and for the data output a
range of 24byte is available
Input area
Addr. Name Byte Function
+0 DI_0 1 Digital input I+0.0 ... I+0.7
+1 DI_1 1 Digital input I+1.0 ... I+1.7
+2 - 2 reserved
+4 AI_CH0 2 Analog input CH0
+6 AI_CH1 2 Analog input CH1
+8 AI_CH2 2 Analog input CH2
,
+10 AI_CH3 2 Analog input CH3
+12 AI_CH4 2 Analog input CH4
+14 - 2 reserved
+16 CVCL_0 4 Counter/Latch value 0
+20 - 2 reserved
+22 ISTS_0 2 Input status counter 0
+24 CVCL_1 4 Counter/Latch value 1
+28 - 2 reserved
+30 ISTS_1 2 Input status counter 1
+32 CVCL_2 4 Counter/Latch value 2
+36 - 2 reserved
+38 ISTS_2 2 Input status counter 2
+40 CVCL_3 4 Counter/Latch value 3
+44 - 2 reserved
+46 ISTS_3 2 Input status counter 3
HB140 | CPU | 314-6CF03 | GB | 16-43 58
Page 59
VIPA System 300S Deployment CPU 314-6CF03
Hardware configuration - CPU
Output area
Addr. Name Byte Function
+0 - 1 reserved
+1 DO_1 1 Digital output Q+1.0 ... Q+1.7
+2 - 2 reserved
+4 AO_CH0 2 Analog output CH0
+6 AO_CH1 2 Analog output CH1
+8 - 2 reserved
+10 OSTS_0 2 Output status counter 0
+12 - 2 reserved
+14 OSTS_1 2 Output status counter 1
+16 - 2 reserved
+18 OSTS_2 2 Output status counter 2
+20 - 2 reserved
+22 OSTS_3 2 Output status counter 3
5.4 Hardware configuration - CPU
Precondition
The configuration of the CPU takes place at the Siemens ‘hardware
configurator
SIMATIC Manager. It serves for project engineering. The modules,
which may be configured here are listed in the hardware catalog. If
necessary you have to update the hardware catalog with ‘Options
è Update Catalog’.
For project engineering a thorough knowledge of the Siemens
SIMATIC Manager and the Siemens hardware configurator is
required.
’ . The hardware configurator is part of the Siemens
Please consider that this SPEED7-CPU has 4 ACCUs.
After an arithmetic operation (+I, -I, *I, /I, +D, -D,
*D, /D, MOD, +R, -R, *R, /R) the content of ACCU 3
and ACCU 4 is loaded into ACCU 3 and 2. This may
cause conflicts in applications that presume an
unmodified ACCU 2.
For more information may be found in the manual
"VIP
A Operation list SPEED7" at "Differences between
SPEED7 and 300V programming".
HB140 | CPU | 314-6CF03 | GB | 16-43 59
Page 60
Hardware configuration - I/O modules
Proceeding
To be compatible with the Siemens SIMATIC Manager the following
steps should be executed:
1. Start the Siemens hardware configurator with a new project.
2. Insert a profile rail from the hardware catalog.
3. Place at ‘Slot’ -Number 2 the CPU 317-2DP (6ES7
317-2AJ10-0AB0/V2.6).
4. The integrated PROFIBUS DP master (X3) is to be configured
and connected via the sub module X2 (DP).
Hardware configuration - I/O modules
5.5
VIPA System 300SDeployment CPU 314-6CF03
Hardware configuration
of the modules
Parametrization
After the hardware configuration place the System 300 modules in the
plugged sequence starting with slot 4.
For parametrization double-click during the project engineering at the
slot overview on the module you want to parameterize. In the
appearing dialog window you may set the wanted parameters. By
using the SFCs 55, 56 and 57 you may alter and transfer parameters
for wanted modules during runtime. For this you have to store the
module specific parameters in so called "record sets". More detailed
information about the structure of the record sets is to find in the
according module description.
Bus extension with IM
360 and IM 361
For the project engineering of more than 8 modules you may use line
interface connections. For this you set in the hardware configurator
the module IM 360 from the hardware catalog to slot 3 of your 1. profile rail. Now you may extend your system with up to 3 profile rails by
starting each with an IM 361 from Siemens at slot 3. Considering the
max. total current with the VIP
may be arranged in a row. Here the installation of the line connections
IM 360/361 from Siemens is not required.
A SPEED7 CPUs up to 32 modules
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Page 61
VIPA System 300S Deployment CPU 314-6CF03
Hardware configuration - Ethernet PG/OP channel
5.6 Hardware configuration - Ethernet PG/OP channel
Overview
Assembly and commissioning
The CPU 314-6CF03 has an integrated Ethernet PG/OP channel.
This channel allows you to program and remote control your CPU.
The PG/OP channel also gives you access to the internal web page
that contains information about firmware version, connected I/O
devices, current cycle times etc. With the first start-up respectively
after an overall reset the Ethernet PG/OP channel does not have any
IP address. For online access to the CPU via Ethernet PG/OP
channel valid IP address parameters have to be assigned to this by
means of the Siemens SIMA
tion".
1. Install your System 300S with your CPU.
2. Wire the system by connecting cables for voltage supply and
signals.
3. Connect the Ethernet jack of the Ethernet PG/OP channel to
Ethernet
4. Switch on the power supply
After a short boot time the CP is ready for communication.
ð
He possibly has no IP address data and requires an initialization.
TIC Manager. This is called "initializa-
.
"Initialization" via PLC
functions
Assign IP address
parameters
The initialization via PLC functions takes place with the following proceeding:
Determine the current Ethernet (MAC) address of your Ethernet
PG/OP channel. This always may be found as 1. address under
the front flap of the CPU on a sticker on the left side.
You get valid IP address parameters from your system administrator.
The assignment of the IP address data happens online in the Siemens SIMATIC Manager starting with version V 5.3 & SP3 with the
following proceeding:
1. Start the Siemens SIMA
è Set PG/PC interface’ the access path to ‘TCP/IP -> Network
card ....’ .
2.
Open with ‘PLC è Edit Ethernet Node n
the same name.
HB140 | CPU | 314-6CF03 | GB | 16-43 61
TIC Manager and set via ‘Options
’ the dialog window with
Page 62
Hardware configuration - Ethernet PG/OP channel
VIPA System 300SDeployment CPU 314-6CF03
Take IP address parameters in project
3. T
o get the stations and their MAC address, use the [Browse]
button or type in the MAC Address. The Mac address may be
found at the 1. label beneath the front flap of the CPU.
4. Choose if necessary the known MAC address of the list of found
stations.
5. Either type in the IP configuration like IP address, subnet mask
and gateway
.
6. Confirm with [Assign IP configuration].
Direct after the assignment the Ethernet PG/OP channel
ð
may be reached online by these address data. The value
remains as long as it is reassigned, it is overwritten by a
hardware configuration or an factory reset is executed.
1. Open the Siemens hardware configurator und configure the Siemens CPU 317-2DP (6ES7 317-2AJ10-0AB0/V2.6).
2. Configure the modules at the standard bus.
3. For the Ethernet PG/OP channel you have to configure a Sie-
mens CP 343-1 (SIMA
343-1 \ 6GK7 343-1EX11 0XE0)
TIC 300 \ CP 300 \ Industrial Ethernet \CP
always below the really
plugged modules.
4. Open the property window via double-click on the CP
343-1EX1
1 and enter for the CP at ‘Properties’ the IP address
data, which you have assigned before.
5. Assign the CP to a ‘Subnet’ . Without assignment the IP address
data are not used!
6. T
ransfer your project.
HB140 | CPU | 314-6CF03 | GB | 16-43 62
Page 63
VIPA System 300S Deployment CPU 314-6CF03
Hardware configuration - SPEED-Bus > Preconditions
5.7 Hardware configuration - SPEED-Bus
5.7.1
Installation of the
SPEEDBUS.GSD
Preconditions
Since the VIPA specific CPU parameters may be set and the modules
at the SPEED-Bus may be configured, the installation of the
SPEEDBUS.GSD from VIPA in the hardware catalog is necessary.
The CPU and its SPEED-Bus modules may be configured in a
PROFIBUS master after installation.
The GSD (Geräte-Stamm-Datei) is online available in the following
language versions. Further language versions are available on
inquires:
Name Language
SPEEDBUS.GSD German (default)
SPEEDBUS.GSG German
SPEEDBUS.GSE English
The GSD files may be found at www.vipa.com at the "Service" part.
The integration of the SPEEDBUS.GSD takes place with the following
proceeding:
1. Browse to www
2.
Click to ‘Service è Download è GSD- and EDS-Files
è Profibus’
3. Download the file Cx000023_Vxxx.
4. Extract the file to your work directory. The SPEEDBUS.GSD is
stored in the directory VIPA_System_300S.
5. Start the hardware configurator from Siemens.
6. Close every project.
7.
Select ‘Options è Install new GSD-file’.
8. Navigate to the directory VIP
SPEEDBUS.GSD an.
The SPEED7 CPUs and modules of the System 300S from
ð
VIPA may now be found in the hardware catalog at
PROFIBUS-DP / Additional field devices / I/O /
VIPA_SPEEDBUS.
.vipa.com
A_System_300S and select
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Setting standard CPU parameters > Parameterization via Siemens CPU
5.7.2 Proceeding
The embedding of the CPU 314-6CF03 and its modules at the
SPEED-Bus happens by means of a virtual PROFIBUS master
system with the following approach:
VIPA System 300SDeployment CPU 314-6CF03
1.
Perform a hardware configuration for the CPU.
‘Hardware configuration - CPU’ on page 59
2. Since the SPEED-Bus modules are to be linked as a virtual
PROFIBUS system, configure always as last module a Siemens
DP master CP 342-5 (342-5DA02 V5.0). Link the DP master to a
new PROFIBUS net and switch it to DP master operating mode.
3. T
o this master system you assign every SPEED-Bus module as
"VIPA_SPEEDBUS" slave starting with the CPU. Here the
PROFIBUS address corresponds to the slot no. Beginning with
100 for the CPU. Place at slot 0 of every slave the assigned
module
Due to the fact that some SPEED-Bus CPs from VIPA
are similar in project engineering and parametrization
to the corresponding CP from Siemens, for each
SPEED-Bus CP a corresponding Siemens CP is to be
placed and linked at the standard bus.
More information about the configuration of the
according SPEED-Bus module may be found in the
according manual.
Ä
Chapter 5.4
5.8 Setting standard CPU parameters
5.8.1
Parameterization via
Siemens CPU
317-2AJ10
Parameterization via Siemens CPU
Since the CPU is to be configured as Siemens CPU 317-2DP (CPU
317-2AJ10 V2.6) in the Siemens hardware configurator, the standard
parameters of the VIPA CPU may be set with "Object properties" of
the CPU 317-2DP during hardware configuration. Via a double-click
on the CPU 317-2DP the parameter window of the CPU may be
accessed. Using the registers you get access to every standard
parameter of the CPU.
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VIPA System 300S Deployment CPU 314-6CF03
Setting standard CPU parameters > Parameters CPU
5.8.2 Parameters CPU
Supported parameters
General
Startup
The CPU does not evaluate each parameter
, which may be set at the
hardware configuration. The following parameters are supported by
the CPU at this time:
n Short description: The short description of the Siemens CPU is
CPU 317-2DP (6ES7 317-2AJ10-0AB0/V2.6).
n Order No. / Firmware: Order number and firmware are identical to
the details in the "hardware catalog" window
.
n Name: The Name field provides the short description of the CPU.
If you change the name the new name appears in the Siemens
SIMATIC Manager.
n Plant designation: Here is the possibility to specify a plant desig-
nation for the CPU. This plant designation identifies parts of the
plant according to their function. Its structure is hierarchic
according to IEC 1346-1.
n Comment: In this field information about the module may be
entered.
n Startup when expected/actual configuration dif
fers: If the
checkbox for ‘Startup when expected/actual configuration differ’ is
deselected and at least one module is not located at its configured
slot or if another type of module is inserted there instead, then the
CPU does not switch to RUN mode and remains in STOP mode. If
the checkbox for ‘Startup when expected/actual configuration
differ’ is selected, then the CPU starts even if there are modules
not located in their configured slots of if another type of module is
inserted there instead, such as during an initial system start-up.
n Monitoring time for ready message by modules [100ms]: This
operation specifies the maximum time for the ready message of
every configured module after PowerON. Here connected
PROFIBUS DP slaves are also considered until they are parameterized. If the modules do not send a ready message to the CPU
by the time the monitoring time has expired, the actual configuration becomes unequal to the preset configuration. Monitoring time
for ready message by modules [100ms]
n Transfer of parameters to modules [100ms]: The maximum time
for the transfer of parameters to parametrizable modules. If not
every module has been assigned parameters by the time this
monitoring time has expired; the actual configuration becomes
unequal to the preset configuration.
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Setting standard CPU parameters > Parameters CPU
VIPA System 300SDeployment CPU 314-6CF03
Cycle/Clock memory
n Update OB1 process image cyclically: This parameter is not rele-
vant.
n Scan cycle monitoring time: Here the scan cycle monitoring time
in milliseconds may be set. If the scan cycle time exceeds the
scan cycle monitoring time, the CPU enters the ST
OP mode.
Possible reasons for exceeding the time are:
– Communication processes
– a series of interrupt events
– an error in the CPU program
n Minimum scan cycle time: This parameter is not relevant.
n Scan cycle load from Communication: This parameter is not rele-
vant.
n Size of the process image input/output area: Here the size of the
process image max. 2048 for the input/output periphery may be
fixed.
n OB85 call up at I/O access error: The preset reaction of the CPU
may be changed to an I/O access error that occurs during the
update of the process image by the system. The VIPA CPU is
preset such that OB 85 is not called if an I/O access error occurs
and no entry is made in the diagnostic buffer either.
n Clock memory: Activate the check box if you want to use clock
memory and enter the number of the memory byte.
Retentive Memory
Interrupts
Time-of-day interrupts
The selected memory byte cannot be used for temporary data storage.
n Number of Memory bytes from MB0: Enter the number of retentive
memory bytes from memory byte 0 onwards.
n Number of S7 T
imers from T0: Enter the number of retentive S7
timers from T0 onwards. Each S7 timer occupies 2bytes.
n Number of S7 Counters from C0: Enter the number of retentive S7
counter from C0 onwards.
n Areas: This parameter is not supported.
n Priority: Here the priorities are displayed, according to which the
hardware interrupt OBs are processed (hardware interrupt, timedelay interrupt, async. error interrupts).
n Priority: Here the priorities may be specified according to which
the time-of-day interrupt is processed. With priority "0" the corresponding OB is deactivated.
n Active: Activate the check box of the time-of-day interrupt OBs if
these are to be automatically started on complete restart.
n Execution: Select how often the interrupts are to be triggered.
Intervals ranging from every minute to yearly are available. The
intervals apply to the settings made for start date and time.
n Start date/time: Enter date and time of the first execution of the
time-of-day interrupt.
n Process image partition: This parameter is not supported.
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VIPA System 300S Deployment CPU 314-6CF03
Setting standard CPU parameters > Parameters for DP
Cyclic interrupts
Diagnostics/Clock
n Priority: Here the priorities may be specified according to which
the corresponding cyclic interrupt is processed. With priority "0"
the corresponding interrupt is deactivated.
n Execution: Enter the time intervals in ms, in which the watchdog
interrupt OBs should be processed. The start time for the clock is
when the operating mode switch is moved from ST
OP to RUN.
n Phase offset: Enter the delay time in ms for current execution for
the watch dog interrupt. This should be performed if several
watchdog interrupts are enabled. Phase offset allows to distribute
processing time for watchdog interrupts across the cycle.
n Process image partition: This parameter is not supported.
n Report cause of ST
OP: Activate this parameter, if the CPU should
report the cause of STOP to PG respectively OP on transition to
STOP.
n Number of messages in the diagnostics buffer: Here the number
of diagnostics are displayed, which may be stored in the diagnostics buffer (circular buffer).
n Synchronization type: Here you specify whether clock should syn-
chronize other clocks or not.
– as slave: The clock is synchronized by another clock.
– as master: The clock synchronizes other clocks as master.
– none: There is no synchronization
n Time interval: Time intervals within which the synchronization is to
be carried out.
n Correction factor: Lose or gain in the clock time may be compen-
sated within a 24 hour period by means of the correction factor in
ms. If the clock is 1s slow after 24 hours, you have to specify a
correction factor of "+1000" ms.
Protection
5.8.3 Parameters for DP
General
n Level of protection: Here 1 of 3 protection levels may be set to
protect the CPU from unauthorized access.
– Protection level 1 (default setting):
No password adjustable, no restrictions
– Protection level 2 with password:
Authorized users: read and write access
Unauthorized user: read access only
– Protection level 3:
Authorized users: read and write access
Unauthorized user: no read and write access
The properties dialog of the PROFIBUS part is opened via a double
click to the sub module DP
.
n Short description: Here the short description "DP" for PROFIBUS
DP is specified.
n Order no.: Nothing is shown here.
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Setting standard CPU parameters > Parameters for MPI/DP
n Name: Here "DP" is shown. If you change the name, the new
name appears in the Siemens SIMA
n Interface: The PROFIBUS address is shown here.
n Properties: With this button the properties of the PROFIBUS DP
interface may be preset.
n Comment: You can enter the purpose of the PROFIBUS interface.
VIPA System 300SDeployment CPU 314-6CF03
TIC Manager.
Address
n Diagnostics: A diagnostics address for PROFIBUS DP is to be
n Operating mode: Here the operating mode of the PROFIBUS part
n Configuration: Within the operating mode "DP-Slave" you may
n Clock: These parameters are not supported.
5.8.4 Parameters for MPI/DP
The properties dialog of the MPI interface is opened via a double click
to the sub module MPI/DP
General
n Short description: Here the short description "MPI/DP" for the MPI
n Order no.: Nothing is shown here.
n Name: At Name "MPI/DP" for the MPI interface is shown. If you
n Type: Please regard only the type "MPI" is supported by the VIPA
n Interface: Here the MPI address is shown.
n Properties: With this button the properties of the MPI interface
n Comment: You can enter the purpose of the MPI interface.
preset here. In the case of an error the CPU is informed via this
address.
may be preset. More may be found at chapter "Deployment
PROFIBUS Communication".
configure your slave system. More may be found at chapter
"Deployment PROFIBUS communication".
.
interface is specified.
change the name, the new name appears in the Siemens
TIC Manager.
SIMA
CPU.
may be preset.
Address
n Diagnostics: A diagnostics address for the MPI interface is to be
preset here. In the case of an error the CPU is informed via this
address.
n Operating mode, Configuration, Clock: These parameters are not
supported.
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Page 69
VIPA System 300S Deployment CPU 314-6CF03
Setting VIPA specific CPU parameters > Proceeding
5.9 Setting VIPA specific CPU parameters
5.9.1
Overview
Requirements
Proceeding
Except of the VIPA specific CPU parameters the CPU parameterization takes place in the parameter dialog of the CPU from Siemens.
With installing of the SPEEDBUS.GSD the VIPA specific parameters
may be set during hardware configuration. Here the following parameters may be accessed:
n Function RS485 X3 (PtP
and CPU)
n Token Watch
n Number remanence flag, timer, counter
n Priority OB 28, OB 29, OB 33, OB 34
n Execution OB 33, OB 34
n Phase offset OB 33, OB 34
Since the VIPA specific CPU parameters may be set, the installation
of the SPEEDBUS.GSD from VIP
sary. The CPU may be configured in a PROFIBUS master system
and the appropriate parameters may be set after installation.
, Synchronization between DP master
A in the hardware catalog is neces-
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Setting VIPA specific CPU parameters > Proceeding
VIPA System 300SDeployment CPU 314-6CF03
Installation of the
SPEEDBUS.GSD
The GSD (Geräte-Stamm-Datei) is online available in the following
language versions. Further language versions are available on
inquires:
Name Language
SPEEDBUS.GSD German (default)
SPEEDBUS.GSG German
SPEEDBUS.GSE English
The GSD files may be found at www.vipa.com at the "Service" part.
The integration of the SPEEDBUS.GSD takes place with the following
proceeding:
1. Browse to www
2.
Click to ‘Service è Download è GSD- and EDS-Files
.vipa.com
è Profibus’
3. Download the file Cx000023_Vxxx.
4. Extract the file to your work directory
. The SPEEDBUS.GSD is
stored in the directory VIPA_System_300S.
Hardware configuration
5. Start the hardware configurator from Siemens.
6. Close every project.
7.
Select ‘Options è Install new GSD-file
8. Navigate to the directory VIP
A_System_300S and select
’.
SPEEDBUS.GSD an.
The SPEED7 CPUs and modules of the System 300S from
ð
VIPA may now be found in the hardware catalog at
PROFIBUS-DP / Additional field devices / I/O /
VIPA_SPEEDBUS.
The embedding of the CPU 314-6CF03 happens by means of a virtual PROFIBUS master system with the following approach:
HB140 | CPU | 314-6CF03 | GB | 16-43 70
Page 71
VIPA System 300S Deployment CPU 314-6CF03
Setting VIPA specific CPU parameters > VIPA specific parameters
1.
Perform a hardware configuration for the CPU.
Ä
Chapter 5.4
‘Hardware configuration - CPU’ on page 59
2. Configure always as last module a Siemens DP master CP
342-5 (342-5DA02 V5.0). Connect and parameterize it at operation mode "DP-Master".
3. Connect the slave system "VIP
A_SPEEDbus". After installing
the SPEEDBUS.GSD this may be found in the hardware catalog
at Profibus-DP / Additional field devices / I/O / VIPA /
VIPA_SPEEDBUS.
4. For the slave system set the PROFIBUS address 100.
5. Configure at slot 0 the VIP
A CPU 314-6CF03 of the hardware
catalog from VIPA_SPEEDbus.
6. By double clicking the placed CPU 314-6CF03 the properties
dialog of the CPU may be opened.
The hardware configuration, which is shown here, is
only required, if you want to customize the VIP
A spe-
cific parameters.
5.9.2 VIPA specific parameters
The following parameters may be accessed by means of the properties dialog of the VIP
5.9.2.1 Function RS485 X3
Using this parameter the RS485 interface may be switched to PtP
communication (point to point) respectively the synchronization
between DP master system and CPU may be set:
Deactivated Deactivates the RS485 interface.
PtP With this operating mode the
PROFIBUS DP async PROFIBUS DP master operation
A CPU.
PROFIBUS DP master is deactivated and the RS485 interface
acts as an interface for serial
point-to-point communication.
Here data may be exchanged
between two stations by means
of protocols.
asynchronous to CPU cycle The
RS485 interface is preset at
default to PROFIBUS DP async.
Here CPU cycle and cycles of
every VIP
A PROFIBUS DP
master run independently.
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Setting VIPA specific CPU parameters > VIPA specific parameters
PROFIBUS DP syncIn The CPU is waiting for DP
PROFIBUS DP syncOut The DP master system is waiting
PROFIBUS DP syncInOut CPU and DP master system are
Default: PROFIBUS DP async
5.9.2.1.1 Synchronization between master system and CPU
VIPA System 300SDeployment CPU 314-6CF03
master input data.
for CPU output data.
waiting on each other and form
thereby a cycle.
Overview
PROFIBUS DP
SyncInOut
Normally the cycles of CPU and DP master run independently
. The
cycle time of the CPU is the time needed for one OB1 cycle and for
reading respectively writing the inputs respectively outputs. The cycle
time of a DP master depends among others on the number of connected slaves and the baud rate, thus every plugged DP master has
its own cycle time. Due to the asynchronism of CPU and DP master
the whole system gets relatively high response times. The synchronization behavior between every VIPA PROFIBUS DP master and the
CPU may be configured by means of a hardware configuration as
shown above. The different modes for the synchronization are in the
following described.
In PROFIBUS DP SyncInOut mode CPU and DP master system are
waiting on each other and form thereby a cycle. Here the whole cycle
is the sum of the longest DP master cycle and CPU cycle. By this
synchronization mode you receive global consistent in-/ output data,
since within the total cycle the same input and output data are handled successively by CPU and DP master system. If necessary the
time of the Watchdog of the bus parameters should be increased at
this mode.
PROFIBUS DP SyncOut
In this operating mode the cycle time of the VIPA DP master system
depends on the CPU cycle time. After CPU start-up the DP master
gets synchronized. As soon as their cycle is passed they wait for the
next synchronization impulse with output data of the CPU. So the
response time of your system can be improved because output data
were directly transmitted to the DP master system. If necessary the
time of the W
atchdog of the bus parameters should be increased at
this mode.
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VIPA System 300S Deployment CPU 314-6CF03
Setting VIPA specific CPU parameters > VIPA specific parameters
PROFIBUS-DP SyncIn
5.9.2.2 Token Watch
In the operating mode PROFIBUS DP SyncIn the CPU cycle is
synchronized to the cycle of the VIP
A PROFIBUS DP master system.
Here the CPU cycle depends on the VIPA DP master with the longest
cycle time. If the CPU gets into RUN it is synchronized with each
PROFIBUS DP master. As soon as the CPU cycle is passed, it waits
for the next synchronization impulse with input data of the DP master
system. If necessary the Scan Cycle Monitoring Time of the CPU
should be increased.
By presetting the PROFIBUS bus parameters within the hardware
configuration a token time for the PROFIBUS results. The token time
defines the duration until the token reaches the DP master again. Per
default this time is supervised. Due to this monitoring disturbances on
the bus can af
fect a reboot of the DP master. Here with the parameter
Token Watch the monitoring of the token time can be switched off
respectively on.
Default: On
5.9.2.3 Number remanence flag
Here the number of flag bytes may be set. With 0 the value Retentive
memory > Number of memory bytes starting with MB0 set at the
parameters of the Siemens CPU is used. Otherwise the adjusted
value (1 ... 8192) is used. Default: 0
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Project transfer > Transfer via MPI/PROFIBUS
5.9.2.4 Phase offset and execution of OB 33 and OB 34
The CPU offers additional cyclic interrupts, which interrupt the cyclic
processing in certain distances. Point of start of the time interval is
the change of operating mode from ST
cyclic interrupts of different cyclic interrupt OBs receive a start
request at the same time and so a time out may occur, there is the
possibility to set a phase offset respectively a time of execution.
n The phase offset (0 ... 60000ms) serves for distribution processing
times for cyclic interrupts across the cycle. Default: 0
n The time intervals, in which the cyclic interrupt OB should be pro-
cessed may be entered with execution (1 ... 60000ms). Default:
OB 33: 500ms, OB 34: 200ms
5.9.2.5 Priority of OB 28, OB 29, OB 33 and OB 34
The priority fixes the order of interrupts of the corresponding interrupt
OB. Here the following priorities are supported: 0 (Interrupt-OB is
deactivated), 2, 3, 4, 9, 12, 16, 17, 24. Default: 24
VIPA System 300SDeployment CPU 314-6CF03
OP to RUN. To avoid that the
5.9.2.6
Call OB 80 on cyclic interrupt error
5.10 Project transfer
Overview
Once during a cyclic interrupt OB (OB 28, 29, 32 ... 35) the same
cyclic interrupt is requested, the interrupt requests are collected and
processed sequentially
you can set here for the corresponding cyclic interrupt group that on a
cyclic interrupt instead of the sequential processing the OB 80 is to be
called. With this parameter you have the following settings:
n Deactivated (default)
– At a cyclic interrupt error the interrupt requests are collected
and processed sequentially.
n for OB...
– At a cyclic interrupt error of the corresponding cyclic interrupt
OB, the OB 80 is called.
There are the following possibilities for project transfer into the CPU:
ransfer via MPI/PROFIBUS
n T
n Transfer via Ethernet
n Transfer via MMC
. Via the parameter ‘OB 80 for cyclic interrupt’
5.10.1 Transfer via MPI/PROFIBUS
General
For transfer via MPI/PROFIBUS there is the following interface:
n X2: MPI interface
n X3: PROFIBUS interface
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VIPA System 300S Deployment CPU 314-6CF03
Project transfer > Transfer via MPI/PROFIBUS
Net structure
MPI programming cable
Terminating resistor
The structure of a MPI net is electrically identical with the structure of
a PROFIBUS net. This means the same rules are valid and you use
the same components for the build-up. The single participants are
connected with each other via bus interface plugs and PROFIBUS
cables. Please consider with the CPU 314-6CF03 that the total extension of the MPI net does not exceed 50m. Per default the MPI net
runs with 187.5kbaud. VIP
A CPUs are delivered with MPI address 2.
The MPI programming cables are available at VIPA in different variants. The cables provide a RS232 res. USB plug for the PC and a
bus enabled RS485 plug for the CPU. Due to the RS485 connection
you may plug the MPI programming cables directly to an already
plugged plug on the RS485 jack. Every bus participant identifies itself
at the bus with an unique address, in the course of the address 0 is
reserved for programming devices.
A cable has to be terminated with its surge impedance. For this you
switch on the terminating resistor at the first and the last participant of
a network or a segment. Please make sure that the participants with
the activated terminating resistors are always power supplied. Otherwise it may cause interferences on the bus.
Approach transfer via
MPI interface
1. Connect your PC to the MPI jack of your CPU via a MPI pro-
gramming cable.
2. Load your project in the SIMA
3.
Choose in the menu ‘Options è Set PG/PC interface’.
TIC Manager from Siemens.
4. Select in the according list the "PC Adapter (MPI)"; if appropriate
you have to add it first, then click on [Properties].
5. Set in the register MPI the transfer parameters of your MPI net
and type a valid address.
6. Switch to the register Local connection.
7. Set the COM port of the PCs and the transfer rate 38400Baud
for the MPI programming cable from VIP
8.
ia ‘PLC è Load to module’ via MPI to the CPU and save it on
V
A.
a MMC via ‘PLC è Copy RAM to ROM’ if one is plugged.
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Project transfer > Transfer via Ethernet
VIPA System 300SDeployment CPU 314-6CF03
Proceeding Transfer via
PROFIBUS interface
1. Connect your PC to the PB-DP jack X3 of your CPU via a MPI
programming cable.
2. Load your project in the Siemens SIMA
3.
Choose in the menu ‘Options è Set PG/PC interface’.
TIC Manager.
4. Select in the according list the "PC Adapter (PROFIBUS)"; if
appropriate you have to add it first, then click at [Properties].
5. Set in the register PROFIBUS the transfer parameters of your
PROFIBUS net and enter a valid PROFIBUS address. The
PROFIBUS address
must be assigned to the DP master by a
project before.
6. Switch to the register Local connection.
7. Set the COM port of the PCs and the transfer rate 38400baud
for the MPI programming cable from VIP
8.
T
ransfer your project via ‘PLC è Load to module’ via
A.
PROFIBUS to the CPU and save it with ‘PLC
è Copy RAM to ROM’ on a memory card if one is plugged.
Transfer via PROFIBUS is available by DP master, if
projected as master and assigned with a PROFIBUS
address before.
5.10.2 Transfer via Ethernet
For transfer via Ethernet the CPU has the following interface:
n X5: Ethernet PG/OP channel
Initialization
Transfer
So that you may access the Ethernet PG/OP channel you have to
assign IP address parameters by means of the "initialization".
Ä
Chapter 5.6 ‘Hardware configuration - Ethernet PG/OP channel’
on page 61
1. For the transfer
2. Open your project with the Siemens SIMA
3.
W
ithin selecting the slave mode you have additionally
to select the option "Test, commissioning, routing".
, connect, if not already done, the appropriate
Ethernet port to your Ethernet.
TIC Manager.
Set via ‘Options è Set PG/PC Interface
’ the access path to
"TCP/IP ® Network card .... ".
4.
Click to ‘PLC è Download’ Download ® the dialog "Select
target module" is opened. Select your target module and enter
the IP address parameters of the Ethernet PG/OP channel for
connection. Provided that no new hardware configuration is
transferred to the CPU, the entered Ethernet connection is permanently stored in the project as transfer channel.
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VIPA System 300S Deployment CPU 314-6CF03
Project transfer > Transfer via MMC
5. With [OK] the transfer is started.
System dependent you get a message that the projected system differs from target system. This message
may be accepted by [OK].
®
Your project is transferred and may be executed in
the CPU after transfer.
5.10.3 Transfer via MMC
The MMC (Memory Card) serves as external transfer and storage
medium. There may be stored several projects and sub-directories on
a MMC storage module. Please regard that your current project is
stored in the root directory and has one of the following file names:
n S7PROG.WLD
n AUT
OLOAD.WLD
Transfer MMC ® CPU
Transfer CPU ® MMC
With ‘File è Memory Card File è New
Manager a new wld file may be created. After the creation copy the
blocks from the project blocks folder and the System data into the wld
file.
The transfer of the application program from the MMC into the CPU
takes place depending on the file name after an overall reset or PowerON.
n S7PROG.WLDis read from the MMC after overall reset.
n AUT
The blinking of the MC LED of the CPU marks the active transfer.
Please regard that your user memory serves for enough space, otherwise your user program is not completely loaded and the SF LED
gets on.
When the MMC has been installed, the write command stores the
content of the battery buf
The write command is controlled by means of the block area of the
Siemens SIMATIC Manager ‘PLC è Copy RAM to ROM’. During the
write process the MC LED of the CPU is blinking. When the LED
expires the write process is finished.
OLOAD.WLD is read after PowerON from the MMC.
fered RAM as S7PROG.WLD on the MMC.
’ in the Siemens SIMATIC
If this project is to be loaded automatically from the MMC with PowerON, you have to rename this on the MMC to AUTOLOAD.WLD.
Transfer control
HB140 | CPU | 314-6CF03 | GB | 16-43 77
After a MMC access, an ID is written into the diagnostic buffer of the
CPU. To monitor the diagnosis entries, you select ‘PLC
è Module Information’ in the Siemens SIMATIC Manager. Via the
register "Diagnostic Buffer" you reach the diagnosis window.
Ä
Chapter 5.20 ‘Diagnostic entries’ on page 94.
Page 78
Access to the internal Web page
5.11 Access to the internal Web page
VIPA System 300SDeployment CPU 314-6CF03
Access to the web page
Requirements
Web page
CPU with Ethernet-PG/OP
The Ethernet PG/OP channel provides a web page that you may
access via an Internet browser by its IP address. The web page contains information about firmware versions, current cycle times etc.
The current content of the web page is stored on MMC by means of
Ä
the MMC-Cmd WEBP
on page 92
A PG/OP channel connection should be established between PC with
Internet browser and CPU 314-6CF03. This may be tested by Ping to
the IP address of the PG/OP channel.
The access takes place via the IP address of the Ethernet PG/OP
channel. The web page only serves for information output. The monitored values are not alterable.
AGE.
Chapter 5.19 ‘CMD - auto commands’
Slot 100
VIPA 314-6CF03 V.... Px000164.pkg,
SERIALNUMBER 05439
SUPPORTDATA :
PRODUCT V3420, HARDW
HX000027.110 , Bx000227 V6420, Ax000086 V1200,
Ax000056 V0220, fx000007.wld V1140, FlashFileSystem :
V102
Memorysizes(Bytes):LoadMem:LoadMem : 2113536,
W
orkMemCode : 1048576, WorkMemData : 1048576
OnBoardEthernet : MacAddress : 0020D50144C1, IPAddress : 172.20.120.62, SubnetMask : 255.255.255.0,
Gateway : 172.20.120.62
Cpu state : Run CPU state
FunctionRS485 X2/COM1: MPI
FunctionRS485 X3/COM2: DPM-async
ARE V0114, 5679H-V20 ,
Order no., firmware vers.,
package, serial no.
Information for support
Information about memory configuration, load memory, work
memory (code/data)
Ethernet PG/OP: Addresses
Operating mode RS485
n MPI: MPI operation
n DPM: DP master operation
or
PtP: point to point operation
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VIPA System 300S Deployment CPU 314-6CF03
Access to the internal Web page
Slot 100
Cycletime [microseconds] : min=0 cur=770 ave=750
max=878
CPU cycle time:
min = minimal
cur = current
max = maximal
MCC-Trial-Time: 70:23 Remaining time in hh:mm for
deactivation of the expansion
memory if MCC is removed.
ArmLoad [percent] : cur=67, max=70 Information for support
PowerCycleHxRetries : 29, 0, 0, 0, 0
AutoCompress activated
Slot 201 CPU component:
DP master
VIPA 342-1DA70 V3.3.0 Px000062.pkg Name, firmware-version,
package
SUPPORTDATA :
Information for support
PRODUCT V3300, BB000218 V5300, AB000068 V4170,
ModuleT
ype CB2C0010
Cycletime [microseconds] : min=65535000 cur=0 ave=0
max=0 cnt=0
CPU cycle time:
min = minimal
cur = current
max = maximal
Slot 206 CPU component: I/O part
HS_DI8_DIO8_AI5_AO2, V2.0.6 Px000025.pkg, Name, firmware-version,
package
SUPPORTDATA :
Information for support
BB000156 V2060, AB000073 V2020, AB000074 V2000
PRODUCT V2060, Hx000012 V1000
ModuleT
ype 8400000
Address Input 1024...1071
Address Output 1024...1071
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VIPA System 300SDeployment CPU 314-6CF03
Access to the internal Web page
SPEED-BUS
Slot 101 Module at the SPEED-Bus
VIPA 321-1BH70 V1.0.1 Px000029.pkg Name, firmware-version,
package
SUPPORTDATA :
Information for support
BB000189 V1010, AB000076 V1010
PRODUCT V1010, Hx000013 V1000
ModuleT
ype 1FC20001
Address Input 128...131
Slot 102 Module at the SPEED-Bus
VIPA 322-1BH70 V1.0.1 Px000030.pkg Name, firmware-version,
package
SUPPORTDATA :
Information for support
BB000190 V1010, AB000077 V1000
PRODUCT V1010, Hx000014 V1000
ModuleT
ype AFD00001
Address Input 132...135
...
Standard Bus
Standard Bus Modules at the standard bus
BaudRate Read Mode1, BaudRate Write Mode1 Information for support
Line 1: ModuleType 94F9: IM36x IM interface if exists
Rack 0 /Slot 4 Rack no. / slot
ModuleType: 9FC3: Digital Input 32
Baseaddress Input 0
Type of module
Configured base address
if exists firmware no. and
package
Rack 0 /Slot 5 ... Rack no. / slot
...
Line 2: ModuleType A4FE: IM36x IM interface if exists
Rack 1 /Slot 4
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VIPA System 300S Deployment CPU 314-6CF03
Operating modes > Overview
Standard Bus Modules at the standard bus
ModuleType: 9FC3: Digital Input 32
Baseaddress Input 0
Rack 1 /Slot 5 ... Rack no. / slot
Type of module
Configured base address
if exists firmware no. and
package
5.12 Operating modes
5.12.1
Overview
The CPU can be in one of 4 operating modes:
n Operating mode ST
n Operating mode START-UP
n Operating mode RUN
n Operating mode HOLD
Certain conditions in the operating modes START-UP and RUN
require a specific reaction from the system program. In this case the
application interface is often provided by a call to an organization
block that was included specifically for this event.
OP
Operating mode STOP
Operating mode STARTUP
n The application program is not processed.
n If there has been a processing before, the values of counters,
timers, flags and the process image are retained during the transition to the ST
n Outputs are inhibited, i.e. all digital outputs are disabled.
n RUN-LED off
n STOP-LED on
n During the transition from ST
start-up organization block OB 100. The processing time for this
OB is not monitored. The START-UP OB may issue calls to other
blocks.
n All digital outputs are disabled during the START-UP, i.e. outputs
are inhibited.
n RUN-LED
blinks as soon as the OB 100 is operated and for at least 3s, even
if the start-up time is shorter or the CPU gets to STOP due to an
error. This indicates the start-up.
n STOP-LED off
When the CPU has completed the START-UP OB, it assumes the
operating mode RUN.
OP mode.
OP to RUN a call is issued to the
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Operating modes > Overview
VIPA System 300SDeployment CPU 314-6CF03
Operating mode RUN
Operating mode HOLD
Precondition
n The application program in OB 1 is processed in a cycle. Under
the control of alarms other program sections can be included in
the cycle.
n All timers and counters being started by the program are active
and the process image is updated with every cycle.
n The BASP-signal (outputs inhibited) is deactivated, i.e. all digital
outputs are enabled.
n RUN-LED on
n ST
OP-LED off
The CPU offers up to 3 breakpoints to be defined for program diagnosis. Setting and deletion of breakpoints happens in your programming environment. As soon as a breakpoint is reached, you may
process your program step by step.
For the usage of breakpoints, the following preconditions have to be
fulfilled:
esting in single step mode is possible with STL. If necessary
n T
switch the view via ‘View è STL’ to STL.
n The block must be opened online and must not be protected.
Approach for working
with breakpoints
Behavior in operating
state HOLD
1.
Activate ‘V
iew è Breakpoint Bar’.
2. Set the cursor to the command line where you want to insert a
breakpoint.
3.
Set the breakpoint with ‘Debug è Set Breakpoint
The according command line is marked with a circle.
ð
4. T
o activate the breakpoint click on ‘Debug
’.
è Breakpoints Active’.
The circle is changed to a filled circle.
ð
5. Bring your CPU into RUN.
When the program reaches the breakpoint, your CPU
ð
switches to the state HOLD, the breakpoint is marked with
an arrow and the register contents are monitored.
6. Now you may execute the program code step by step via
‘Debug è Execute Next Statement’
or run the program until the
next breakpoint via ‘Debug è Resume’.
7. Delete (all) breakpoints with the option ‘Debug
è Delete All Breakpoints
n The RUN-LED blinks and the ST
’.
OP-LED is on.
n The execution of the code is stopped. No level is further executed.
n All times are frozen.
n The real-time clock runs is just running.
n The outputs were disabled (BASP is activated).
n Configured CP connections remain exist.
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Page 83
VIPA System 300S Deployment CPU 314-6CF03
Operating modes > Function security
The usage of breakpoints is always possible. Switching
to the operating mode test operation is not necessary
.
With more than 2 breakpoints, a single step execution
is not possible.
5.12.2 Function security
The CPUs include security mechanisms like a W
atchdog (100ms) and
a parameterizable cycle time surveillance (parameterizable min. 1ms)
that stop res. execute a RESET at the CPU in case of an error and
set it into a defined STOP state. The VIPA CPUs are developed function secure and have the following system properties:
Event concerns Effect
RUN ® ST
OP general BASP (Befehls-Ausgabe-Sperre, i.e. com-
mand output lock) is set.
central digital outputs The outputs are disabled.
central analog outputs The outputs are disabled.
n V
oltage outputs issue 0V
n Current outputs 0...20mA issue 0mA
n Current outputs 4...20mA issue 4mA
If configured also substitute values may be
issued.
decentral outputs Same behavior as the central digital/analog
outputs.
decentral inputs The inputs are cyclically be read by the
decentralized station and the recent values
are put at disposal.
STOP ® RUN res.
PowerON
general First the PII is deleted, then OB 100 is
called. After the execution of the OB, the
BASP is reset and the cycle starts with:
Delete PIO ® Read PII ® OB 1.
decentral inputs The inputs are once be read by the decen-
tralized station and the recent values are
put at disposal.
RUN general The program execution happens cyclically
and can therefore be foreseen: Read PII ®
OB 1 ® W
PII: Process image inputs, PIO: Process image outputs
rite PIO.
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Page 84
Overall reset
5.13 Overall reset
VIPA System 300SDeployment CPU 314-6CF03
Overview
Overall reset by means
of the operating mode
switch
During the overall reset the entire user memory is erased. Data
located in the memory card is not af
tiate an overall reset:
n initiate the overall reset by means of the operating mode switch
n initiate the overall reset by means of the Siemens SIMATIC Man-
ager
You should always issue an overall reset to your CPU
before loading an application program into your CPU to
ensure that all blocks have been cleared from the
CPU.
Precondition
The operating mode of the CPU is to be switched to STOP. For
this switch the operating mode switch of the CPU to "ST
The ST-LED is on.
ð
Overall reset
1. Switch the operating mode switch to MRES position for about 3
seconds.
fected. You have 2 options to ini-
OP".
The ST
ð
2. Place the operating mode switch in the position ST
switch it to MRES and quickly back to STOP within a period of
less than 3 seconds.
The ST-LED blinks (overall reset procedure).
ð
3. The overall reset has been completed when the ST
on permanently.
The ST-LED is on. The following figure illustrates the above
ð
procedure:
-LED is blinking.
OP and
OP-LED is
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Page 85
VIPA System 300S Deployment CPU 314-6CF03
Firmware update
Overall reset by means
of the Siemens SIMA
Manager
Automatic reload
Reset to factory setting
TIC
n Precondition The operating mode of the CPU is to be switched to
ST
OP. You may place the CPU in STOP by the menu command
‘PLC è Operating mode’.
n Overall reset: You may request the overall reset by means of the
menu command ‘PLC è Clean/Reset’. In the dialog window you
may place your CPU in STOP state and start the overall reset if
this has not been done as yet. The ST-LED blinks during the
overall reset procedure. When the ST-LED is on permanently the
overall reset procedure has been completed.
If there is a project S7PROG.WLD on the MMC, the CPU attempts to
reload this project from MMC.
® The MC LED is on. When the reload has been completed the LED
expires. The operating mode of the CPU will be STOP respectively
RUN, depending on the position of the operating mode switch.
The Reset to factory setting deletes completely the internal RAM of
the CPU and resets this to delivery state. Please regard that the MPI
Ä
address is also set back to default 2!
settings’ on page 88
Chapter 5.15 ‘Reset to factory
5.14 Firmware update
Overview
n There is the opportunity to execute a firmware update for the CPU
and its components via MMC. For this an accordingly prepared
MMC must be in the CPU during the startup.
n So a firmware files can be recognized and assigned with startup,
a pkg file name is reserved for each updateable component an
hardware release, which begins with "px" and dif
with six digits. The pkg file name of every updateable component
may be found at a label right down the front flap of the module.
n After PowerON and CPU STOP the CPU checks if there is a *.pkg
file on the MMC. If this firmware version is different to the existing
firmware version, this is indicated by blinking of the LEDs and the
firmware may be installed by an update request.
fers in a number
HB140 | CPU | 314-6CF03 | GB | 16-43 85
Page 86
Firmware update
VIPA System 300SDeployment CPU 314-6CF03
Latest firmware at
www
.vipa.com
Display the Firmware
version of the SPEED7
system via W
eb Site
The latest firmware versions are to be found in the service area at
.vipa.com. For example the following files are necessary for the
www
firmware update of the CPU 314-6CF03 and its components with
hardware release 1:
n 314-6CF03, Hardware release 1: Px000164.pkg
n PROFIBUS-DP master: Px000062.pkg
n DI/DO/AIO: Px000025.pkg
CAUTION!
When installing a new firmware you have to be
extremely careful. Under certain circumstances you
may destroy the CPU, for example if the voltage supply
is interrupted during transfer or if the firmware file is
defective. In this case, please call the VIP
A-Hotline!
Please regard that the version of the update firmware
has to be different from the existing firmware otherwise
no update is executed.
The CPU has an integrated website that monitors information about
firmware version of the SPEED7 components. The Ethernet PG/OP
channel provides the access to this web site. The CPU has an integrated website that monitors information about firmware version of
the SPEED7 components. The Ethernet PG/OP channel provides the
access to this web site. ‘PLC è Assign Ethernet Address’. After that
you may access the PG/OP channel with a web browser via the IP
Ä
address of the project engineering.
Chapter 5.11 ‘Access to the
internal Web page’ on page 78
Load firmware and
transfer it to MMC
n Go to www
.vipa.com
n Click on ‘Service è Download è Firmware’.
n Navigate via ‘System 300S è CPU’ to your CPU and download
the zip file to your PC.
n Extract the zip file and copy the extracted pkg files to your MMC.
CAUTION!
With a firmware update an overall reset is automatically executed. If your program is only available in the
load memory of the CPU it is deleted! Save your program before executing a firmware update! After the
firmware update you should execute a "Set back to fac-
Ä
tory settings".
Chapter 5.15 ‘Reset to factory set-
tings’ on page 88
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Page 87
VIPA System 300S Deployment CPU 314-6CF03
Firmware update
Transfer firmware from
MMC into CPU
1. Switch the operating mode switch of your CPU in position ST
OP.
Turn off the voltage supply. Plug the MMC with the firmware files
into the CPU. Please take care of the correct plug-in direction of
the MMC. Turn on the voltage supply.
2. After a short boot-up time, the alternate blinking of the LEDs SF
and FC shows that at least a more current firmware file was
found on the MMC.
3. Y
ou start the transfer of the firmware as soon as you tip the
operating mode switch downwards to MRES within 10s.
4. During the update process, the LEDs SF and FC are alternately
blinking and MC LED is on. This may last several minutes.
5. The update is successful finished when the LEDs PW
, ST, SF,
FC and MC are on. If they are blinking fast, an error occurred.
6. T
urn Power OFF and ON. Now it is checked by the CPU,
whether further current firmware versions are available at the
MMC. If so, again the LEDs SF and FC flash after a short startup period. Continue with point 3.
If the LEDs do not flash, the firmware update is ready. Now a
ð
factory reset should be executed (see next page). After that
the CPU is ready for duty.
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Page 88
Reset to factory settings
5.15 Reset to factory settings
VIPA System 300SDeployment CPU 314-6CF03
Proceeding
With the following proceeding the internal RAM of the CPU is completely deleted and the CPU is reset to delivery state.
Please note that here also the IP address of the Ethernet PG/OP
channel is set to 0.0.0.0 and the MPI address is reset to the address
2!
A reset to factory setting may also be executed by the MMC-Cmd
Ä
ACTORY_RESET.
F
on page 92
1. Switch the CPU to ST
2. Push the operating mode switch down to position MRES for 30s.
Here the ST
changes to static light. Now the STOP LED changes between
static light and flashing. Starting here count the static light
states.
3. After the 6. static light release the operating mode switch and tip
it downwards to MRES. Now the RUN LED lights up once. This
means that the RAM was deleted completely
4. For the confirmation of the resetting procedure the LEDs PW
ST, SF, FC and MC get ON. If not, the factory reset has failed
and only an overall reset was executed. In this case you can
repeat the procedure. A factory reset can only be executed if the
stop LED has static light for exactly 6 times.
Chapter 5.19 ‘CMD - auto commands’
OP.
OP-LED flashes. After a few seconds the stop LED
.
,
5. The end of factory reset is shown by static light of the LEDs PW
ST, SF, FC and MC. Switch the power supply off and on.
The proceeding is shown in the following Illustration:
After the firmware update you always should execute a
Reset to factory setting.
,
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Page 89
VIPA System 300S Deployment CPU 314-6CF03
Slot for storage media
5.16 Slot for storage media
Overview
Accessing the storage
medium
At the front of the CPU there is a slot for storage media. V
as external storage medium for applications and firmware you may
use a memory card (MMC respectively SD). You can cause the CPU
to load a project automatically respectively to execute a command file
by means of pre-defined file names.
Please note that the write protection function of SD
cards is not evaluated!
To the following times an access takes place on a storage medium:
n After overall reset
The CPU checks if there is a project S7PROG.WLD. If exists
–
the project is automatically loaded.
– The CPU checks if there is a project PROTECT.WLD with pro-
tected blocks. If exists the project is automatically loaded.
These blocks are stored in the CPU until the CPU is reset to
factory setting or an empty PROTECT.WLD is loaded
– The CPU checks if a MCC memory extension card is put. If
exists the memory extension is enabled, otherwise a memory
expansion, which was activated before, is de-activated.
n After PowerON
– The CPU checks if there is a project AUTOLOAD.WLD. If
exists an overall reset is established and the project is automatically loaded.
– The CPU checks if there is a command file with
VIPA_CMD.MMC. If exists the command file is loaded and the
containing instructions are executed.
– After PowerON and CPU STOP the CPU checks if there is a
*.pkg file (firmware file). If exists this is indicated by blinking of
the LEDs and the firmware may be installed by an update
request.
n Once in STOP
– If a storage medium is put, which contains a command file
VIPA_CMD.MMC, the command file is loaded and the containing instructions are executed.
ia this slot
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Page 90
Memory extension with MCC
5.17 Memory extension with MCC
Overview
There is the possibility to extend the work memory of the CPU. For
this, a MCC memory extension card is available from VIP
is a specially prepared MMC (Multimedia Card). By plugging the MCC
into the MCC slot and then an overall reset the according memory
expansion is released. There may only one memory expansion be
activated at one time. On the MCC there is the file memory.key. This
file may not be altered or deleted. You may use the MCC also as
"normal" MMC for storing your project.
VIPA System 300SDeployment CPU 314-6CF03
A. The MCC
Proceeding
To extend the memory, plug the MCC into the card slot at the CPU
labelled with "MCC" and execute an overall reset.
If the memory expansion on the MCC exceeds the maximum extendible memory range of the CPU, the maximum possible memory of the
CPU is automatically used. Y
extension via the integrated web page or with the Siemens SIMATIC
Manager at Module Information - "Memory".
CAUTION!
Please regard that the MCC must remain plugged
when you’ve executed the memory expansion at the
CPU. Otherwise the CPU switches to ST
hours. The MCC
the same memory configuration.
ou may determine the recent memory
OP after 72
cannot be exchanged with a MCC of
Behavior
When the MCC memory configuration has been taken over you may
find the diagnostic entry 0xE400 in the diagnostic buf
After pulling the MCC the entry 0xE401 appears in the diagnostic
buffer, the SF LED is on and after 72 hours the CPU switches to
STOP. A reboot is only possible after plugging-in the MCC again or
after an overall reset.
The remaining time after pulling the MCC is always been shown with
the parameter MCC-Trial-Time on the web page.
After re-plugging the MCC, the SF LED extinguishes and 0xE400 is
entered into the diagnostic buffer. You may reset the memory configuration of your CPU to the initial status at any time by executing an
overall reset without MCC.
HB140 | CPU | 314-6CF03 | GB | 16-43 90
fer of the CPU.
Page 91
VIPA System 300S Deployment CPU 314-6CF03
Extended know-how protection
5.18 Extended know-how protection
Overview
Standard protection
Extended protection
Besides the "standard" Know-how protection the SPEED7-CPUs from
A provide an "extended" know-how protection that serves a
VIP
secure block protection for accesses of 3. persons.
The standard protection from Siemens transfers also protected blocks
to the PG but their content is not displayed. But with according manipulation the Know-how protection is not guaranteed.
The "extended" know-how protection developed by VIPA offers the
opportunity to store blocks permanently in the CPU. At the "extended"
protection you transfer the protected blocks into a WLD-file named
protect.wld. By plugging the MMC and following overall reset, the
blocks in the protect.wld are permanently stored in the CPU. You may
protect OBs, FBs and FCs. When back-reading the protected blocks
into the PG, exclusively the block header are loaded. The block code
that is to be protected remains in the CPU and cannot be read.
Protect blocks with protect.wld
Transfer protect.wld to
CPU with overall reset
Create a new wld-file in your project engineering tool with ‘File
è Memory Card file è New
the according blocks into the file by dragging them with the mouse
from the project to the file window of protect.wld.
Transfer the file protect.wld to a MMC storage module, plug the MMC
into the CPU and execute an overall reset with the following
approach:
’ and rename it to "protect.wld". Transfer
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Page 92
CMD - auto commands
VIPA System 300SDeployment CPU 314-6CF03
The overall reset stores the blocks in protect.wld permanently in the
CPU protected from accesses of 3. persons.
Protection behavior
Change respectively
delete protected blocks
Usage of protected
blocks
Protected blocks are overwritten by a new protect.wld. Using a PG 3.
persons may access protected blocks but only the block header is
transferred to the PG. The block code that is to be protected remains
in the CPU and cannot be read.
Protected blocks in the RAM of the CPU may be substituted at any
time by blocks with the same name. This change remains up to next
overall reset. Protected blocks may permanently be overwritten only if
these are deleted at the protect.wld before. By transferring an empty
protect.wld from the MMC you may delete all protected blocks in the
CPU.
Due to the fact that reading of a "protected" block from the CPU monitors no symbol labels it is convenient to provide the "block covers" for
the end user
Delete all networks in the blocks so that these only contain the variable definitions in the according symbolism.
5.19 CMD - auto commands
Overview
A command file at a MMC is automatically executed under the following conditions:
. For this, create a project out of all protected blocks.
n CPU is in ST
n After each PowerON
Command file
Commands
Command Description Diagnostics entry
CMD_START In the first line CMD_ST
The command
sequence to be stored as vipa_cmd.mmc in the root directory of the
MMC. The file has to be started by CMD_START as 1. command, fol-
lowed by the desired commands (no other text) and must be finished
by CMD_END as last command.
Text after the last command CMD_END e.g. comments is permissible, because this is ignored. As soon as the command file is recognized and executed each action is stored at the MMC in the log file
logfile.txt. In addition for each executed command a diagnostics entry
may be found in the diagnostics buffer.
Please regard the command sequence is to be started with
CMD_START and ended with CMD_END.
OP and MMC is stuck
file is a text file, which consists of a command
ART is to be located. 0xE801
There is a diagnostic entry if CMD_ST
missing
HB140 | CPU | 314-6CF03 | GB | 16-43 92
ART is
0xE8FE
Page 93
VIPA System 300S Deployment CPU 314-6CF03
CMD - auto commands
Command Description Diagnostics entry
WAIT1SECOND Waits about 1 second. 0xE803
WEBPAGE The current web page of the CPU is stored at
0xE804
the MMC as" webpage.htm".
LOAD_PROJECT The function "Overall reset and reload from
0xE805
MMC" is executed. The wld file located after the
command is loaded else "s7prog.wld" is loaded.
SAVE_PROJECT The recent project (blocks and hardware config-
0xE806
uration) is stored as "s7prog.wld" at the MMC. If
the file just exists it is renamed to "s7prog.old".
If your CPU is password protected so you have
to add this as parameter
. Otherwise there is no
project written. Example: SAVE_PROJECT
password
FACTORY_RESET Executes "factory reset". 0xE807
DIAGBUF The current diagnostics buffer of the CPU is
stored as "diagbuf
f.txt" at the MMC.
SET_NETWORK IP parameters for Ethernet PG/OP channel may
0xE80B
0xE80E
be set by means of this command. The IP
parameters are to be given in the order IP
address, subnet mask and gateway in the
format x.x.x.x each separated by a comma.
Enter the IP address if there is no gateway
used.
CMD_END In the last line CMD_END is to be located. 0xE802
Examples
The structure of a command file is shown in the following. The corresponding diagnostics entry is put in parenthesizes.
Example 1
CMD_START
LOAD_PROJECT proj.wld
WAIT1SECOND
WEBPAGE
DIAGBUF
Marks the start of the command sequence (0xE801)
Execute an overall reset and load "proj.wld" (0xE805)
Wait ca. 1s (0xE803)
Store web page as "webpage.htm" (0xE804)
Store diagnostics buffer of the CPU as "diagbuff.txt"
(0xE80B)
CMD_END
... arbitrary text ...
Marks the end of the command sequence (0xE802)
Text after the command CMD_END is not evaluated.
Example 2
CMD_START
LOAD_PROJECT proj2.wld
WAIT1SECOND
Marks the start of the command sequence (0xE801)
Execute an overall reset and load "proj2.wld" (0xE805)
Wait ca. 1s (0xE803)
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Page 94
Diagnostic entries
VIPA System 300SDeployment CPU 314-6CF03
WAIT1SECOND
Wait ca. 1s (0xE803)
IP parameter (0xE80E)
SET_NETWORK 172.16.129.210,255.255.224.0,172.16.129.210
WAIT1SECOND
WAIT1SECOND
WEBPAGE
DIAGBUF
Wait ca. 1s (0xE803)
Wait ca. 1s (0xE803)
Store web page as "webpage.htm" (0xE804)
Store diagnostics buffer of the CPU as "diagbuff.txt"
(0xE80B)
CMD_END
... arbitrary text ...
Marks the end of the command sequence (0xE802)
Text after the command CMD_END is not evaluated.
The parameters IP address, subnet mask and gateway
may be received from the system administrator
Enter the IP address if there is no gateway used.
.
5.20 Diagnostic entries
Accessing diagnostic
data
Overview of the system
specific event IDs
Event ID Description
0x115C Vendor-specific interrupt (OB 57) at EtherCAT
OB: OB number
ZInfo1: Logical address of the slave that triggered the interrupt
ou may read the diagnostics buffer of the CPU via the Siemens
n Y
SIMATIC Manager. Besides of the standard entries in the diagnostics buffer, the VIPA CPUs support some additional specific entries
as Event-IDs.
n To monitor the diagnostics entries you choose in the Siemens
SIMATIC manager ‘PLC è Module information’. Via the register
"Diagnostics Buffer" you reach the diagnostics window.
n The current content of the diagnostic buffer is stored at the
memory card by means of the CMD DIAGBUF.
‘CMD - auto commands’ on page 92
n The diagnostic is independent from the operating mode of the
CPU. You may store a max. of 100 diagnostic entries in the CPU.
Ä
Chapter 5.19
ZInfo2: Interrupt type
0x00: Reserved
0x01: Diagnostic interrupt (incoming)
0x02: Hardware interrupt
0x03: Pull interrupt
0x04: Plug interrupt
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Page 95
VIPA System 300S Deployment CPU 314-6CF03
Diagnostic entries
Event ID Description
0x05: Status interrupt
0x06: Update interrupt
0x07: Redundancy interrupt
0x08: Controlled by the supervisor
0x09: Enabled
0x0A: Wrong sub module plugged
0x0B: Restoration of the sub module
0x0C: Diagnostic interrupt (outgoing)
0x0D: Cross traffic connection message
0x0E: Neighbourhood change message
0x0F: Synchronisation message (bus)
0x10: Synchronisation message (device)
0x11: Network component message
0x12: Clock synchronisation message (bus)
0x1F: Pull interrupt module
ZInfo3: CoE error code
0xE003 Error on accessing the periphery
ZInfo1 : Transfer type
ZInfo2 : Periphery address
ZInfo3 : Slot
0xE004 Multiple configuration of a periphery address
ZInfo1 : Periphery address
ZInfo2 : Slot
0xE005 Internal error - Please contact the hotline!
0xE007 Configured in-/output bytes do not fit into periphery area
0xE008 Internal error - Please contact the hotline!
0xE009 Error on accessing the standard backplane bus
0xE010 There is a undefined module at the backplane bus
ZInfo2 : Slot
ZInfo3 : Type ID
0xE011 Master project engineering at slave CPU not possible or wrong slave configuration
0xE012 Error at parametrization
0xE013 Error at shift register access to standard bus digital modules
0xE014 Error at Check_Sys
0xE015 Error at access to the master
ZInfo2 : Slot of the master
ZInfo2 : Page frame master
0xE016 Maximum block size at master transfer exceeded
HB140 | CPU | 314-6CF03 | GB | 16-43 95
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Diagnostic entries
Event ID Description
ZInfo1 : Periphery address
ZInfo2 : Slot
0xE017 Error at access to integrated slave
0xE018 Error at mapping of the master periphery
0xE019 Error at standard back plane bus system recognition
0xE01A Error at recognition of the operating mode (8 / 9 bit)
0xE01B Error - maximum number of plug-in modules exceeded
0xE020 Error - Interrupt information undefined
ZInfo2 : Slot
ZInfo3 : Not relevant to the user
DatID : Interrupt type
0xE030 Error of the standard bus
0xE033 Internal error - Please contact the hotline!
VIPA System 300SDeployment CPU 314-6CF03
0xE0B0 SPEED7 is not stoppable (e.g. undefined BCD value at timer)
ZInfo1 : Not relevant to the user
ZInfo2 : Not relevant to the user
ZInfo3 : Not relevant to the user
DatID : Not relevant to the user
0xE0C0 Not enough space in work memory for storing code block (block size exceeded)
0xE0CB Error at SSL access
ZInfo1 : Error
4: SSL wrong
5: Sub-SSL wrong
6: Index wrong
ZInfo2 : SSL ID
ZInfo3 : Index
0xE0CC Communication errors
ZInfo1 : Error code
1: Wrong priority
2: Buffer overflow
3: Telegram format error
4: Wrong SSL request (SSL ID not valid)
5: Wrong SSL request (SSL sub ID invalid)
6: Wrong SSL request (SSL-Index not valid)
7: Wrong value
8: Wrong return value
9: Wrong SAP
10: Wrong connection type
HB140 | CPU | 314-6CF03 | GB | 16-43 96
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VIPA System 300S Deployment CPU 314-6CF03
Diagnostic entries
Event ID Description
11: Wrong sequence number
12: Faulty block number in the telegram
13: Faulty block type in the telegram
14: Inactive function
15: Wrong size in the telegram
20: Error in writing on MMC
90: Faulty buffer size
98: Unknown error
99: Internal error
0xE0CD Error at DP-V1 job management
ZInfo1 : Not relevant to the user
ZInfo2 : Not relevant to the user
ZInfo3 : Not relevant to the user
DatID : Not relevant to the user
0xE0CE Error: Timeout at sending of the i-slave diagnostics
0xE100 Memory card access error
0xE101 Memory card error file system
0xE102 Memory card error FAT
0xE104 Memory card error at saving
ZInfo3 : Not relevant to the user
0xE200 Memory card writing finished (Copy Ram2Rom)
PK : Not relevant to the user
OB : Not relevant to the user
0xE210 Memory card reading finished (reload after overall reset)
ZInfo1 : Not relevant to the user
PK : Not relevant to the user
OB : Not relevant to the user
0xE21E Memory card reading: Error at reload (after overall reset), error in block header
ZInfo1 : Block type
0x38: OB
0x41: DB
0x42: SDB
0x43: FC
0x44: SFC
0x45: FB
0x46: SFB
0x6F: VOB
0x65: VFB
HB140 | CPU | 314-6CF03 | GB | 16-43 97
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VIPA System 300SDeployment CPU 314-6CF03
Diagnostic entries
Event ID Description
0x63: VFC
0x61: VDB
0x62: VSDB
0x64: VSFC
0x66: VSFB
ZInfo2 : Block number
ZInfo3 : Block length
0xE21E Memory card reading: Error at reload (after overall reset), file "Protect.wld" too big
OB : Not relevant to the user
0xE21F Memory card reading: Error at reload (after overall reset), checksum error at reading
PK : Not relevant to the user
OB : Not relevant to the user
ZInfo1 : Not relevant to the user
ZInfo2 : BstTyp
0x38: OB
0x41: DB
0x42: SDB
0x43: FC
0x44: SFC
0x45: FB
0x46: SFB
0x6F: VOB
0x65: VFB
0x63: VFC
0x61: VDB
0x62: VSDB
0x64: VSFC
0x66: VSFB
ZInfo3 : BstNr
0xE300 Internal flash writing finished (Copy Ram2Rom)
0xE310 Internal flash writing finished (reload after battery failure)
0xE400 FSC card was plugged
DatID : FeatureSet Trialtime in minutes
ZInfo1 : Memory extension in kB
ZInfo2 : FeatureSet PROFIBUS
ZInfo2 : FeatureSet field bus
ZInfo2 : FeatureSet motion
ZInfo2 : Reserved
HB140 | CPU | 314-6CF03 | GB | 16-43 98
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VIPA System 300S Deployment CPU 314-6CF03
Diagnostic entries
Event ID Description
0xE401 FSC card was removed
DatID : FeatureSet Trialtime in minutes
ZInfo1 : Memory extension in kB
ZInfo2 : FeatureSet PROFIBUS
ZInfo2 : FeatureSet field bus
ZInfo2 : FeatureSet motion
ZInfo2 : Reserved
ZInfo3 : Source of the FSC
0: CPU
1: Card
0xE402 A configured functionality is not activated
ZInfo1 : FCS ErrorCode
1: The PROFIBUS functionality is disabled The interface acts further as MPI interface
2: The EtherCAT functionality is not enabled
3: The number of configured axis is not enabled
0xE403 FSC can not be activated in this CPU
ZInfo1 : Memory extension in kB
ZInfo2 : FeatureSet PROFIBUS
ZInfo2 : FeatureSet field bus
ZInfo2 : FeatureSet motion
ZInfo2 : Reserved
0xE404 FeatureSet deleted due to CRC error
DatID : Not relevant to the user
0xE405 The trial time of a feature set or MMC has expired
DatID : Not relevant to the user
0xE410 A CPU feature set was activated
DatID : Not relevant to the user
0xE500 Memory management: Deleted block without corresponding entry in BstList
ZInfo2 : Block type
0x38: OB
0x41: DB
0x42: SDB
0x43: FC
0x44: SFC
0x45: FB
0x46: SFB
0x6F: VOB
0x65: VFB
HB140 | CPU | 314-6CF03 | GB | 16-43 99
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Diagnostic entries
Event ID Description
0x63: VFC
0x61: VDB
0x62: VSDB
0x64: VSFC
0x66: VSFB
ZInfo3 : Block no.
0xE501 Parser error
ZInfo3 : SDB number
ZInfo1 : ErrorCode
1: Parser error: SDB structure
2: Parser error: SDB is not a valid SDB type.
ZInfo2 : SDB type
0xE502 Invalid block type in protect.wld
VIPA System 300SDeployment CPU 314-6CF03
ZInfo2 : Block type
0x38: OB
0x41: DB
0x42: SDB
0x43: FC
0x44: SFC
0x45: FB
0x46: SFB
0x6F: VOB
0x65: VFB
0x63: VFC
0x61: VDB
0x62: VSDB
0x64: VSFC
0x66: VSFB
ZInfo3 : Block number
0xE503 Inconsistency of code size and block size in work memory
ZInfo1 : Code size
ZInfo2 : Block size (high word)
ZInfo3 : Block size (low word)
0xE504 Additional information for CRC error in work memory
ZInfo2 : Block address (high word)
ZInfo3 : Block address (low word)
0xE505 Internal error - Please contact the hotline!
0xE604 Multiple parametrization of a periphery address for Ethernet PG/OP channel
HB140 | CPU | 314-6CF03 | GB | 16-43 100
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