ViewSonic makes no representations or warranties, either expressed or implied, with respect to the contents
hereof and specifically disclaims any warranty of merchantability or fitness for any particular purpose. Further,
ViewSonic reserves the right to revise this publication and to make changes from time to time in the contents
hereof without obligation of ViewSonic to notify any person of such revision or changes.
Trademarks
Optiquest is a registered trademark of ViewSonic Corporation.
ViewSonic is a registered trademark of ViewSonic Corporation.
All other trademarks used within this document are the property of their respective owners.
Revision History
Revision SM Editing Date ECR Number Description of Changes Editor
1a 03/26/10 Initial Release Sophia Kao
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TABLE OF CONTENTS
2
1. Precautions and Safety Notices................................................................. 3
10. Exploded View And Exploded Parts List.................................................. 81
11. Recommend Spare Parts List................................................................... 84
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1. Precautions and Safety Notices
3
1. Appropriate Operation
(1) Turn off the product before cleaning.
(2) Use only a dry soft cloth when cleaning the LCD panel surface.
(3) Use a soft cloth soaked with mild detergent to clean the display housing.
(4) Disconnect the power plug from AC outlet if the product is not used for a long period of time.
(5) If smoke, abnormal noise, or strange odor is present, immediately switch the LCD display off.
(6) Do not touch the LCD panel surface with sharp or hard objects.
(7) Do not place heavy objects on the LCD display, video cable, or power cord.
(8) Do not use abrasive cleaners, waxes or solvents for your cleaning.
(9) Do not operate the product under the following conditions:
- Extremely hot, cold or humid environment.
- Areas susceptible to excessive dust and dirt.
- Near any appliance generating a strong magnetic field.
- Place in direct sunlight.
2. Caution
No modification of any circuit should be attempted. Service work should only be performed after you are
thoroughly familiar with all of the following safety checks and servicing guidelines.
3. Safety Check
Care should be taken while servicing this LCD display. Because of the high voltage used in the inverter
circuit, the voltage is exposed in such areas as the associated transformer circuits.
4. Power Supply Requirements
The external AC power operating range shall be from 90 to 264Vac
5. LCD Module Handling Precautions
5.1. Handling Precautions
(1) Since front polarizer is easily damaged, pay attention not to scratch it.
(2) Be sure to turn off power supply when inserting or disconnecting from input connector.
(3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
(4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
(5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.
(6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth
when handling.
(7) Do not open nor modify the Module Assembly.
(8) Do not press the reflector sheet at the back of the module to any directions.
(9) In case if a Module has to be put back into the packing container slot after once it was taken out
from the container, do not press the center of the CCFL Reflector edge. Instead, press at the far
ends of the CFL Reflector edge softly. Otherwise the TFT Module may be damaged.
(10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the
Interface Connector of the TFT Module.
(11) After installation of the TFT Module into an enclosure (LCD monitor housing, for example), do
not twist nor bend the TFT Module even momentary. At designing the enclosure, it should be
taken into consideration that no bending/twisting forces are applied to the TFT Module from
outside. Otherwise the TFT Module may be damaged.
(12) Cold cathode fluorescent lamp in LCD contains a small amount of mercury. Please follow local
ordinances or regulations for disposal.
(13) Small amount of materials having no flammability grade is used in the LCD module. The LCD
module should be supplied by power complied with requirements of Limited Power Source
(IEC60950 or UL1950), or be applied exemption.
(14) The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit
(IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.
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5.2. Handling and Placing Methods
4
Correct Methods: Incorrect Methods:
Only touch the metal frame of the LCD panel or the
front cover of the monitor. Do not touch the surface
of the polarizer.
Surface of the LCD panel is pressed by fingers and
that may cause “Mura”
Take out the monitor with cushions Taking out the monitor by grasping the LCD panel.
That may cause “Mura”
Place the monitor on a clean and soft foam pad.Placing the monitor on foreign objects. That could
scratch the surface of the panel or cause “Mura”
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2. Specification
5
LCD panel of this product shall be provided by “CMO” with a model number of M270H1-L01.The
following table defines this panel specification. Any changes in panel must be pre-approved by
ViewSonic in written.
ParameterSpecification
LCD Type
LCD Interface 2-Channel LVDS
Resolution (Native) 1920 x 1080
Display Area 27” diagonal; 597.89 (H) x 336.31 (V) mm
Pixel Pitch
Viewing Angle H = 170, V = 160 with CR10 (Typical)
Contrast Ratio 1200:1 (Typical)
Brightness 300 nits (Typical)
Response Time 3.4 ms, (Typical), g-g
Brightness Uniformity 1.33 (Max), measured per panel spec.
Chromaticity(CIE1931) White-x:0.313,White-y:0.329 (Standard Mode Only)
Colors 16.7M (8-bits)
Surface Treatment Hard coating (3H)
Backlight 4 CCFLs (Cold cathode Fluorescent Lamp)
Preset Color Panel Default
Gray Scale 0-255
Rated Life (Backlight) > 50KHrs*(ILO at 3.0mA)
Front Screen Artifacts
Panel Acceptance Spec
Note: Also refer to the panel defect acceptance specification.
Panel performance characteristics “ MUST BE” met in all display modes/inputs at standard test
conditions.
a-Si TFT Active Matrix Wide Color, Transmissive Mode,
Normally Black
0.3114 (H) x 0.3114(V) mm
VS Standard:
a.) No Visible Streaking, Sag or Smearing artifacts when
driven by the specified video cards (see 7.1 General Test
Equipment) in the primary mode (VGA & 60 Hz) and after
user adjustment
b.) No image drift or lose fine-tune settings due to panel
temperature change.
Refer to the panel acceptance criteria specification.
Note: Intermittent and/or Display Pattern defects which result
in further bright or dark dots will be counted individually
against the above specification.
1. RF Tuner
RF tuner of this product shall be provided by “Samsung DTVA50FVH10109B” for NTSC/ATSC. The
following table defines this tuner specification.
ParameterSpecification
RF Tuning Range
RF Tuner Sensitivity (S/N
Ratio at un-weight)
Channel Bandwidth NTSC/ATSC/Digital Cable: 6 MHz Maximum
CVBS Characteristics:
Video Amplitude Signal
Audio Characteristics:
SIF out level
Compatible system TUNER NTSC/ATSC/QAM
Compatible system AV NTSC M
NTSC/ATSC: 55.25 to 803 MHz, 2-69 Channels for Off-Air and
1-125 Channels for CATV
44 dB (min.)// 48 dB (max.)
0.8(min.)–1.2(max.) V
500mV (typ.)
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2. Video
N
6
Built-in A/D converter shall provide analog to digital converter for this product.
Input Parameter Specification
CVBS Characteristics:
Video Amplitude Signal
DC Level Sync Pulse
S-Video Characteristics:
Video Amplitude Signal
Y, Pb, Pr Characteristics:
Video Amplitude Signal
Video Bandwidth
HDMI Characteristics Panel Link T.M.D.S HDMI-1.3
RGB Characteristics:
Signal Type
Sync Type
Input Signal Rating
Sync Level:
Frequency Range
Pixel Color
DDC Compliance
EDID Data Table
0.7(min.) – 1.1(max.) V
Typical. 0.3 V
Y : 1.0Vp-p W / Neg. Sync (IN 75 ȍ )
C : 0.285Vp-p (IN 75 ȍ )
Y:1.0Vp-p (IN 75 ȍ)
Pb:0.7 Vp-p(IN 75 ȍ),Pr:0.7 Vp-p (IN 75 ȍ)
TSC: 6 MHz Maximum
Analog VGA
TTL, Separate Sync, with 2.2K: pull-down resistors
1250mV Max without damage to the product, 0-700 mV Full Range
2.5-5.25 V
Horizontal: 30-82K Hz, Vertical: 55-76 Hz
16.7 M
DDC2B Compliant, Rev 1.3
Refer to Appendix
3. Audio
Audio amp of this product shall be provided by “TI” with a Model Number of TPA3113D2 .
“MST” MSD3003 for VT2730-1M shall be used as sound processor. In addition, a pair of speakers shall
be integrated within this product. The audio signals of this product shall comply with the specification
listed in the following table.
ParameterSpecification
Tuner Input Base band Input
Power Output Max Rating 5W at 10 % T.H.D Distortion 5W at 10% T.H.D Distortion
Speaker Impedance main speaker :6ȍmain speaker :6 ȍ
Line In
Line Out earphone jack
Flatness of Amplitude
Response
Total Harmonic Distortion
(Po=0.1 to 1 W, f=1KHz)
Signal to Noise:
NTSC: BTSC Mono / Stereo(standard)
PAL: FM Mono / Stereo(standard)
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4.
7
Electrical
The following table defines the electrical specification of this product.
ELECTRICAL SPECIFICATION
1 Power Input Voltage Range 100-240VAC +/- 10% Wide Range
2 Input Frequency Range 47-63 Hz
3 Input Current 1.0A @ 115VAC // 0.5A @ 230VAC
Max in < 80A (with fully loaded power supply) at 230Vac
4 Power Supply Inrush
5 Power Consumption: 70 W (Normal), 75W (Max) // Stand by: < 1W
6 Interference with RF and Video
7 Electromagnetic Compatibility
Power Supply Transient Immunity
8
(Supply Transients and Outage)
9 Surge Immunity Test
Power Supply Missing Cycle
10
Immunity
11 Power Supply Acoustics
12 Efficiency >= 80% @ full load, nominal line
13 Leakage Current <0.5mA @ 240VAC
14 Power Saving(DPMS) N/A
15 Recovery Time < 3 sec.
16 Power Factor Correction Compliant with EN61000-3-2
Shall not result in permanent failure of power supply
(including blown fuse)
There shall be no visible interference between power supply,
RF and video signals. This applies to all available RF
channels and video modes.
This product shall adhere to the compatibility and immunity
specifications in FCC.
Able to withstand an ANSI / IEEE C62.41 – 1980 2000V
ring wave with no damage.
Able to withstand 1.25X nominal Line Voltage for one cycle
with no damage.
Function properly without reset or visible screen artifact
when 1/3 cycle of AC Power is randomly missing.
The Power Supply shall not produce audible noise that would
be detectable by the user (Excluding Power Supply Fan).
“Audible” shall be defined in accordance with ISO 7779
(DIN EN27779:1991).
Power Switch noise shall be Excluded.
5. Firmware & OSD
The product firmware of VS13154-1M shall have a firmware version of V2.00EB0. Any
changes/revisions afterward shall also be pre-approved by ViewSonic in written. For VS13154-1M, its
firmware shall have a built-in frequency table for NTSC/ATSC off-air TV/CATV, and with MTS
implementation.
All audio/video and other output adjustments shall be performed by using an On Screen Display (OSD)
via a Remote Control Unit (RCU) in conjunction with the front panel adjustments.The following tables
list the OSD functions supported by VS13154-1M.
OSD Table for VS13154-1M
PICTURE
Picture Mode Standard, Dynamic, Soft ,Personal
Contrast 0~50~100
Brightness 0~50~100
Sharpness 0~50~100
Tint 0~50~100
Color 0~50~100
Color Mode Cool, Normal, Warm, Personal
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AUDIO
8
TIME
Zoom Mode Movie Scale, Zoom In,4:3, Normal
NR Middle, Strong, Off, Weak,
Sound Mode Standard, Music, Movie, Sports, Personal
Treble/Bass Bass, Treble, Balance
Audio Language(ATSC) English, French, Spanish
Surround Sound SRS TruSurround HD, Off
Audio Only On, Off
Sleep Timer OFF, 5,10,15,30,45,60,90,120,180,240 Min
Random, None, Right Drag Left Drag, Down Drag, Up
Drag, S-Play, N-Play, Fade In/Out, Fly In/Out
None, Sort by Name, Sort by Name Z->A, Sort by
Size, Sort by Date, Sort by Date New->Old
Scan all channels, Digital channel only, Analog channel
only
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6. Remote Control Unit (RCU)
9
An IR remote control unit shall accompany this product along with battery. In addition, this remote
control unit shall have an operational distance of 5 meters and an operational angle of 15 degrees for both
horizontal and vertical. Besides the key-code and protocol has fully conformed to VS standard.
ParameterSpecification
Type IR; Made by Sighter Electronics Co., Ltd.
Range
Life Testing
(Buttons)
Color
Protocol VS key-code & protocol.
Off axis r 15qt 5M
On axis: t 7M
100,000 cycle operations at a rate of 20~30 cycle / minute without load (with
battery)
Painting Color - PANTONE 427C (Black for front & back cover)
Power Key - PANTONE 032C (RED)
Key Pads – PANTONE 10C & PANTONE 7C(Cool Gray)
Texts Printed on Front Cover and Key Pads - PANTONE 427C
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7. Mechanical
10
The following table defines the mechanical specifications of this product for both chassis and cabinet.
ParameterSpecification
Dimension
W/O stand
Net Weight 6.97 kg
Gross Weight 8.85 kg
Net weight *without*
stand
Chassis Plastic Material ABS (ABS HB / PC)
External Plastic Chassis
Components
Exterior Chassis
Color/Texture/Details
Chassis Color Drift Due
to UV-Light
Molded Plastic Workmanship shall be inspected according to ViewSonic Molded Plastic
Screen Printed Parts,
Bird Logo Recess
Rear Label A label identifying the product name, model/serial number and FCC
Wall Mount 100 mm x 200 mm VESA high hole (n=4), M4 X 10mm , pitch =0.7mm
Sample Sample of textured color chips, plastic material specification, and Material
646.3 x 465.7 x 227.8 mm
646.3x 409.7x 74.8 mm
5.58 kg
Plastic Chassis, Cover, Stand (Metal + Plastic),Lens and Button
Refer to – Product ID Guide
The color drift due to UL-Light shall be less than 10 “Delta E” in the 1976
CIE L*a*b color space. Testing shall be performed according to the
requirements of ASTM Test Method D4459-93.
Parts Specification, VSCMPPSPEC001V1.2.
Artwork shall be provided and confirmed by ViewSonic.
ID/Logo shall be placed into the rear label recess located on the rear panel
of the chassis.
screw mounting kit not included.
Safety Data Sheets shall be submitted to ViewSonic prior to Mass
Production Release.
In addition, all exterior surfaces shall have uniform texture/color. The maximum acceptable gap between the
buckets to bezel plastic pieces shall be within 1 mm. The maximum acceptable gap between LCD panel and
bezel shall be within 1.5 mm.
8. Environmental
The following table defines the operational/storage conditions of the product.
Operating Temperature
Humidity 10% ~ 65% non-condensing
Altitude 0 meter to +2000 meters above sea level
Storage Temperature
Humidity 0 ~ 90% non-condensing
Altitude 0 meter to 12,000 meters above sea level
0qC to +40qC
-20qC to +60qC
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3. Front Panel Function Control Description
11
)URQW9LHZRIWKH3URGXFW
ItemDescription
Power LED Indicator
1
Remote Control Receiver
2
Volume Up
3
Volume Down
4
MENU
5
CH Up
6
CH Down
7
INPUT
8
Power ON/OFF button
9
Lights up in blue when the TV is turned on. Lights up in orange
when the TV is in standby mode.
Receives IR signals from the remote control.
Increase sound volume or adjust a highlighted control while in
OSD menu.
Decrease sound volume or adjust a highlighted control while in
OSD menu.
Turn OSD menu ON/OFF.
Channel up when source is TV, or select a control while in OSD
menu.
Channel down when source is TV, or select a control while in
OSD menu.
Select input source.
Turn the power on from standby mode or turn the power off to
return to the standby mode.
EL
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5HDU9LHZRIWKH3URGXFW
12
ItemDescription
1Power (AC input)
USB
2
HDMI 1 Input Terminal
3
HDMI 2 Input Terminal
4
PC Audio input
5
VGA signal input
6
YPbPr signal input
7
YPbPr signal Audio
8
input (left/ right)
Audio output
9
Plug-in the supplied AC Power cord and connect to the AC input
power source.
Basic Selection: To set basic analog closed caption
options. (CC1~CC4, TEXT1~TEXT4, Off)
Advanced Selection: To select closed caption signal
formats and set up caption modes for digital TV
channels. (Service1~6, Off)
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C (children)
C8+ (children eight years and older)
G (general programming, suitable for all audiences)
PG (parental guidance)
14+ (viewers and older)
18+ (adult programming)
EXEMPT (exempt)
3. Press MENU to exit.
*The picture here only shows an example of the content
of RRT Setting. However, the selections and sub selections of RRT Setting may be different in your OSD
menu according to the local broadcasting system.
be displayed on the screen and the TV will automatically
turn into power-saving mode after a few seconds’ idleness.
Press INPUT or POWER button on the remote control
and the TV will return to VGA mode.
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Using USB Function
27
1. When input source is selected to USB, insert the USB
device into the USB jack. USB only supports JPEG,
To select the auto-play effects of the slide show.
!!
File List Sorting:
To select the pictures arrange.
!!
SlideShow Repeat:
To select the slide show repeat to On or Off.
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Annotations for OSD Menu Items
28
See below for meanings of the control items in each menu.
Picture menu
Picture Mode: To select picture mode.
Contrast: To adjust contrast of video.
Brightness: To adjust luminance of video.
Sharpness: To adjust picture sharpness.
Tint: To adjust tint level.(Except PC source)
Color: To adjust color.(Except PC source)
Color Mode: To select and adjust color mode.
Zoom Mode: To select image size between Normal,
Movie Scale, Zoom in and 4:3.(Except PC source)
Noise Reduction: To reduce the noise level of connected
Bass: To adjust bass.
Treble: To adjust the treble.
Balance: To adjust left and right audio balance.
Audio Language: To select available audio language.
(Only
Surround Sound:7RVHOHFW³6567UX6XUURXQG+'´
available in DTV)
effect or not.
Audio Only: To turn off the screen picture but keep the
sound on.
MTS: To select audio mode.(EX: Mono, Stereo, SAP)
(Only
available in ATV)
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Time menu
29
Sleep Timer: To set the off timer.
Time Zone: To select the time zone appropriate to
your location.
DST: To turn on/off daylight saving.
Time Format: To select 12-hour or 24-hour.
Auto Sync: To turn on/off Auto Sync.
Clock: To set the clock.
Option menu
Menu Language: To select OSD language.
Transparent: To select OSD (On Screen Display)
transparent level.
OSD Time Out: To select OSD show time.
Closed Caption: To set close caption options.
(Only available in TV, AV, S-Video source)
Restore Default: To restore the factory default settings.
Input Label: To Change the input source name.
DCR: To turn on/off the DCR (Dynamic Contrast Ratio)
function.(Except USB source)
Over Scan: To select this function to On or Off in
HDMI1, HDMI2 and HDMI3.(Only available when
input signal is in video timing. Ex:480i, 480p, 720p,
1080i, 1080p)
Media: To set the picture slide show setting.(Only
available in USB source)
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Lock menu
30
Change Password: To Change the current Password.
System Lock: To select On or Off to Lock parent
control.
Unrated Lock: To block unrated movie or TV
programs.
Input Block: To block by input source.
US: Select TV and MPAA to set the parent control.
Canada: Select Canadian English and Canadian French
to set the parent control.
RRT Setting: To set Rating Region Table.
Reset RRT: To reset Rating Region Table.
Favorite: To set your favorite channel into memory .
Show/Hide: To set the cannel show or hide.
Channel No.: To select the cannel you want to edit the
name.
Channel Label: To edit a name for the current cannel.
DTV Signal: To display the detected signal strength of
the current DTV channel.
Notes:Initial password:0000
If you forget your initial password,you can press"3660"to resume.
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4. Circuit Description
31
z A/D converter
This brick convert is the 110-220AC input voltage to 24V output for inverter use and 5V for panel ,
system and audio use and 3.3V,1.8V for controller use.
z INVERTER
In order to drive the CCFLs embedded in the panel module, there is a half bridge inverter to convert by
the controller.
The input 24V up to hundreds of AC voltage output.
The inverter is formed by symmetric in order to drive the separate lamp modules.
The input stage consists of a PWM controller, half bridge inverter, and switching MOSFET to convert
DC input into AC output.
The output stage consists of a tuning capacitor, coupling capacitor, transformer, push-pull MOSFET
pair to boost AC output up to hundreds of voltage.
And one resister is serial to lamp for output voltage feedback.
There are two signal to control the inverter which come from system.
Logic “high” level which send to I901 is turn on the inverter.
BRI signal control brightness by DC level which was integral from PWM signal.
z
I113 Scaler MSD3003EG
The MSD3003EG is a highly integrated controller IC for LCD/PDP DTV applications with resolutions
up to full-HD (1920 x 1080). It is configured with an integrated triple-ADC/PLL, a multi-standard TV
video and audio decoder, a motion adaptive video de-interlacer, a scaling engine, the MStarACE-3
color engine, an advanced 2D graphics engine, a transport processor, a high-definition (HD) MPEG
video decoder, a 24-bit DSP for MPEG audio decoding, a DVI/HDCP/HDMI receiver, and a peripheral
control unit providing a variety of HDTV control functions.
For digital TV application, the MSD3003EG comprises an MPEG-2 transport processor with advanced
section filtering capability, an MPEG-2 (MP@HL profile) video decoder, Dolby Digital (AC-3)/MPEG
layer I and II digital audio decoder with analog audio outputs that are designed to support ATSC
HD/SDTV programs while handling ATSC CC and EPG. With additional software support, the
MSD3003EG can be used in DVB-T standard areas such as part of Asia, Africa, and Australia.
Furthermore, it is also possible to decode JPEG, MP3 formats from external sources such as USB
interfaces.
For analog TV the MSD3003EG includes NTSC/PAL/SECAM multi-standard video decoder
comprising a 3D motion adaptive comb filter and time-based correction, and a BTSC/A2/EIA-J audio
decoder to support worldwide television standards. In addition, the MStar advanced LCD TV
processor enhances video quality, motion adaptive
de-interlacer, picture quality adjustment units, and MStarACE-3 color engine.
For multimedia applications, the MSD3003EG includes an build-in MStarϗs proprietary M-link
interface, making it possible for the MSD3003EGto decode media (such as H.264 or MPEG-4) files via
the companion chip.
By integrating peripherals including USB 2.0 host controller, UART, IR, SPI, I2C, and PWM, the
MSD3003EG fulfills
all requirements in advanced DTV sets. To further reduce system costs, the MSD3003EG also
integrates intelligent power management control capability for green-mode requirements and
spread-spectrum support for EMI management.
PIN DESCRIPTION
VCLAMP CVBS/YC Mode Clamp Voltage Bypass H3
REFP Internal ADC Top De-coupling Pin H4
REFM Internal ADC Bottom De-coupling Pin H5
REXT Analog Input External Resister 390 ohm to AVDD_33 F4
HSYNC0 Schmitt Trigger Input w/
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5V-tolerant
32
HSYNC / Composite Sync for VGA Input from channel 0 K6
VSYNC0 Schmitt Trigger Input
VSYNC for VGA Input from channel 0 J6
HSYNC1 Schmitt Trigger Input
HSYNC / Composite Sync for VGA Input from channel 1 G6
VSYNC1 Schmitt Trigger Input
VSYNC for VGA Input from channel 1 G5
VSYNC2 Schmitt Trigger Input
VSYNC for VGA Input from channel 2 T3
BINM Analog Input Reference Ground for Analog Blue Input N3
BIN0P Analog Input Analog Blue Input from Channel 0 N2
BIN1P Analog Input Analog Blue Input from Channel 1 J1
BIN2P Analog Input Analog Blue Input from Channel 2 R3
GINM Analog Input Reference Ground for Analog Green Input N1
GIN0P Analog Input Analog Green Input from Channel 0 M3
GIN1P Analog Input Analog Green Input from Channel 1 J3
GIN2P Analog Input Analog Green Input from Channel 2 T2
SOGIN0 Analog Input Sync On Green Input from Channel 0 L3
SOGIN1 Analog Input Sync On Green Input from Channel 1 J2
SOGIN2 Analog Input Sync On Green Input from Channel 2 T1
RINM Analog Input Reference Ground for Analog Red Input M2
RIN0P Analog Input Analog Red Input from Channel 0 M1
RIN1P Analog Input Analog Red Input from Channel 0 K1
RIN2P Analog Input Analog Red Input from Channel 0 U1
Analog Video Input/Output Interface
Pin Name Pin Type Function Pin
CVBS7 Analog Input CVBS (Composite) Video Input Channel 7 K3
CVBS6 Analog Input CVBS (Composite) Video Input Channel 6 K2
CVBS5 Analog Input CVBS (Composite) Video Input Channel 5 L2
CVBS4 Analog Input CVBS (Composite) Video Input Channel 4 L1
CVBS3 Analog Input CVBS (Composite) Video Input Channel 3 P3
CVBS2 Analog Input CVBS (Composite) Video Input Channel 2 R2
CVBS1 Analog Input CVBS (Composite) Video Input Channel 1 R1
CVBS0 Analog Input CVBS (Composite) Video Input Channel 0 W3
VCOM1 Analog Input CVBS Input Reference Ground P2
VCOM0 Analog Input CVBS Input Reference Ground Y3
CVBSOUT0 Analog Output CVBS (Composite) Video Output Channel 0 U2
CVBSOUT1 Analog Output CVBS (Composite) Video Output Channel 1 P1
Analog Audio Input/Output Interface
Pin Name Pin Type Function Pin
SIF0P Analog Input SIF Audio Input Channel 0 Y1
SIF0M Analog Input Reference Ground for SIF Audio Input Channel 0 Y2
I2S_OUT_MCK Output Audio Master Clock Output C13
I2S_OUT_WS Output Word Select Output; 4mA driving strength D13
I2S_OUT_BCK Output Audio Bit Clock Output C12
I2S_OUT_SD Output Audio Serial Data Output; 4mA driving strength E12
I2S_OUT_MUTE/UART1_RX Output Audio Output Mute Control /Universal Asynchronous Receiver
1
C10
SPDIFO Output S/PDIF Audio Output; 4mA driving strength B11
I2S_IN_WS I/O Word Select Input C14
I2S_IN_BCK I/O Audio Bit Clock Input D14
I2S_IN_SD Input Audio Serial Data Input A13
SPDIFI Input w/ 5V-tolerant S/PDIF Audio Input B13
AUL0 Analog Input Audio Line Input Left Channel 0 J4
AUR0 Analog Input Audio Line Input Right Channel 0 J5
AUL1 Analog Input Audio Line Input Left Channel 1 K4
AUR1 Analog Input Audio Line Input Right Channel 1 K5
AUL2 Analog Input Audio Line Input Left Channel 2 L6
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AUR2 Analog Input Audio Line Input Right Channel 2 L4
33
Pin Name Pin Type Function Pin
AUL3 Analog Input Audio Line Input Left Channel 3 L5
AUR3 Analog Input Audio Line Input Right Channel 3 M6
AUL4 Analog Input Audio Line Input Left Channel 4 M5
AUR4 Analog Input Audio Line Input Right Channel 4 N6
AUL5 Analog Input Audio Line Input Left Channel 5 N4
AUR5 Analog Input Audio Line Input Right Channel 5 N5
AUCOM Analog Input Reference Ground for Audio Line Input M4
AUVRM Analog Output Negative Reference Voltage for Audio ADC R4
AUVRP Analog Output Positive Reference Voltage for Audio ADC P4
AUVAG Analog Output Reference Voltage for Audio Common Mode P5
AUOUTL2 Analog Output Main Audio Output Left Channel 2 W1
AUOUTR2 Analog Output Main Audio Output Right Channel 2 V1
AUOUTL1 Analog Output Main Audio Output Left Channel 1 W2
AUOUTR1 Analog Output Main Audio Output Right Channel 1 V2
AUOUTL0 Analog Output Main Audio Output Left Channel 0 V3
AUOUTR0 Analog Output Main Audio Output Right Channel 0 U3
TS Input Interface
Pin Name Pin Type Function Pin
TS0CLK Input w/ 5V-tolerant TS Clock T5
TS0DATA[7:0] Input w/ 5V-tolerant TS Data in Parallel; LSB (bit 0) is for serial TS data U5, V5,
W5,Y5, U4, V4,W4, Y4
TS0VALID Input w/ 5V-tolerant TS Data Valid T4
TS0SYNC Input w/ 5V-tolerant TS Sync-Byte Indicator R5
TS1CLK Input w/ 5V-tolerant 2nd TS Clock H16
TS1DATA Input w/ 5V-tolerant 2nd TS Data in Parallel J17
TS1VALID Input w/ 5V-tolerant 2nd TS Data Valid J16
TS1SYNC Input w/ 5V-tolerant 2nd TS Sync-Byte Indicator H17
DVI/HDMI Interface
Pin Name Pin Type Function Pin
RXACKN DVI/HDMI Input Negative DVI/HDMI Input for A Link Clock Channel E1
RXACKP DVI/HDMI Input Positive DVI/HDMI Input for A Link Clock Channel E2
RXA0N DVI/HDMI Input Negative DVI/HDMI Input for A Link Data Channel 0 F1
Pin Name Pin Type Function Pin
RXA0P DVI/HDMI Input Positive DVI/HDMI Input for A Link Data Channel 0 F2
RXA1N DVI/HDMI Input Negative DVI/HDMI Input for A Link Data Channel 1 G1
RXA1P DVI/HDMI Input Positive DVI/HDMI Input for A Link Data Channel 1 G2
RXA2N DVI/HDMI Input Negative DVI/HDMI Input for A Link Data Channel 2 H1
RXA2P DVI/HDMI Input Positive DVI/HDMI Input for A Link Data Channel 2 H2
RXBCKN DVI/HDMI Input Negative DVI/HDMI Input for B Link Clock Channel A1
RXBCKP DVI/HDMI Input Positive DVI/HDMI Input for B Link Clock Channel A2
RXB0N DVI/HDMI Input Negative DVI/HDMI Input for B Link Data Channel 0 B1
RXB0P DVI/HDMI Input Positive DVI/HDMI Input for B Link Data Channel 0 B2
RXB1N DVI/HDMI Input Negative DVI/HDMI Input for B Link Data Channel 1 C1
RXB1P DVI/HDMI Input Positive DVI/HDMI Input for B Link Data Channel 1 C2
RXB2N DVI/HDMI Input Negative DVI/HDMI Input for B Link Data Channel 2 D1
RXB2P DVI/HDMI Input Positive DVI/HDMI Input for B Link Data Channel 2 D2
RXCCKN DVI/HDMI Input Negative DVI/HDMI Input for C Link Clock Channel Y8
RXCCKP DVI/HDMI Input Positive DVI/HDMI Input for C Link Clock Channel W8
RXC0N DVI/HDMI Input Negative DVI/HDMI Input for C Link Data Channel 0 Y9
RXC0P DVI/HDMI Input Positive DVI/HDMI Input for C Link Data Channel 0 W9
RXC1N DVI/HDMI Input Negative DVI/HDMI Input for C Link Data Channel 1 Y10
RXC1P DVI/HDMI Input Positive DVI/HDMI Input for C Link Data Channel 1 W10
RXC2N DVI/HDMI Input Negative DVI/HDMI Input for C Link Data Channel 2 Y11
RXC2P DVI/HDMI Input Positive DVI/HDMI Input for C Link Data Channel 2 W11
LVDS Interface
Pin Name Pin Type Function Pin
LVA0M Output LVDS A-Link Channel 0 Negative Data Output Y17
LVA0P Output LVDS A-Link Channel 0 Positive Data Output W17
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LVA1M Output LVDS A-Link Channel 1 Negative Data Output V17
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LVA1P Output LVDS A-Link Channel 1 Positive Data Output Y16
LVA2M Output LVDS A-Link Channel 2 Negative Data Output W16
LVA2P Output LVDS A-Link Channel 2 Positive Data Output V16
LVA3M Output LVDS A-Link Channel 3 Negative Data Output V15
LVA3P Output LVDS A-Link Channel 3 Positive Data Output Y14
LVA4M Output LVDS A-Link Channel 4 Negative Data Output W14
LVA4P Output LVDS A-Link Channel 4 Positive Data Output V14
LVACKM Output LVDS A-Link Negative Clock Output Y15
Pin Name Pin Type Function Pin
LVACKP Output LVDS A-Link Positive Clock Output W15
LVB0M Output LVDS B-Link Channel 0 Negative Data Output U20
LVB0P Output LVDS B-Link Channel 0 Positive Data Output U19
LVB1M Output LVDS B-Link Channel 1 Negative Data Output U18
LVB1P Output LVDS B-Link Channel 1 Positive Data Output V20
LVB2M Output LVDS B-Link Channel 2 Negative Data Output Y20
LVB2P Output LVDS B-Link Channel 2 Positive Data Output W20
LVB3M Output LVDS B-Link Channel 3 Negative Data Output V19
LVB3P Output LVDS B-Link Channel 3 Positive Data Output Y18
LVB4M Output LVDS B-Link Channel 4 Negative Data Output W18
LVB4P Output LVDS B-Link Channel 4 Positive Data Output V18
LVBCKM Output LVDS B-Link Negative Clock Output Y19
LVBCKP Output LVDS B-Link Positive Clock Output W19
M-Link Interface
Pin Name Pin Type Function Pin
MLINKB_TXP Output M-Link Positive Data Transmitter for B-Link T20
MLINKB_TXN Output M-Link Negative Data Transmitter for B-Link T19
MLINKB_RXP Input M-Link Positive Data Receiver for B-Link R20
MLINKB_RXN Input M-Link Negative Data Receiver for B-Link R19
MLINKA_RX0P Input M-Link Positive Data Receiver 0 for A-Link N20
MLINKA_RX0N Input M-Link Negative Data Receiver 0 for A-Link N19
MLINKA_RX1P Input M-Link Positive Data Receiver 1 for A-Link P20
MLINKA_RX1N Input M-Link Negative Data Receiver 1 for A-Link P19
Serial Flash Interface
Pin Name Pin Type Function Pin
SCK Output SPI Flash Serial Clock V12
SDI Output SPI Flash Serial Data Input Y13
SDO Input w/ 5V-tolerant SPI Flash Serial Data Output W13
SCZ Output SPI Flash Chip select V13
IRIN Input w/ 5V-tolerant IR Receiver Input C4
Parallel Flash Interface
Pin Name Pin Type Function Pin
PF_WEZ Output Parallel Flash Write Enable; active low R12
PF_CE0Z Output Parallel Flash Chip Enable 0; active low T12
PF_CE1Z Output NAND Flash Command Latch Enable
NOR Flash Chip enable 1; active low U14
PF_ALE Output Parallel Flash Address Latch Enable; active high T13
PF_OEZ Output NAND Flash Read Enable; NOR Flash Output
Enable; active low T14
F_RBZ Input NAND Flash Ready/Busy; active low
Not used by NOR Flash U12
PF_AD[15] Output NAND Flash Write Protect; active low
Bit[15] of NOR Flash Address/Data Bus U13
PF_AD[14:0] Output Parallel Flash Address/Data Bus; Bit[14:8] not
used by NAND Flash T7, U10, W7, T6, V9, Y6, V10, V11, U11, T8, R10, P18, P17, N18,N17
PF_D[7:0] Output NOR Flash Address/Data Bus for High Byte in
16-bit Mode V7, U8, V8, U6, V6, M16, M17, N16
GPIO Interface
Pin Name Pin Type Function Pin
GPIO[140:130] I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength E5, E6, D6,
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C6, D7, C7, B7, R15, R16, R17, T18
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GPIO[105:90] I/O General Purpose Input/Output; 4mA driving strength D8, B8, D9, B9,
E10, B14, B10, E11, C11, A11, A14, D15, C15, B15, D12, B12
GPIO[89:88] I/O General Purpose Input/Output; 4mA driving strength A15, A12
UART1_TX/ GPIO87 I/O w/ 5V-tolerant Universal Asynchronous Transmitter 1 General Purpose
Input/Output; 4mA driving strength C8
UART1_RX/ GPIO86 I/O w/ 5V-tolerant Universal Asynchronous Receiver 1 / General Purpose
Input/Output; 4mA driving strength A8
UART2_TX/ GPIO85 I/O w/ 5V-tolerant Universal Asynchronous Transmitter 2 / General Purpose
Input/Output; 4mA driving strength C9
Pin Name Pin Type Function Pin
UART2_RX/ GPIO84 I/O w/ 5V-tolerant Universal Asynchronous Receiver 2 / General Purpose
Input/Output; 4mA driving strength A9
GPIO79/ UART1_TX I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength /
Universal Asynchronous Transmitter 1 D10
I2S_IN_BCK/ GPIO68 I/O Audio Bit Clock Input / General Purpose Input/Output; 4mA driving
strength D14
I2S_IN_WS/ GPIO67 I/O Word Select Input / General Purpose Input/Output; 4mA driving strength
C14
GPIO[62:51] I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength K16, K17, L16,
L17, M16, M17, N16, N17, N18, P16, P17, P18
GPIO[44:20] I/O w/ 5V-tolerant General Purpose Input/Output; 4mA driving strength R11, T10,
T9, R10, R9, T8, U11, V11, W7, Y7, T7, U10, V10. W6, Y6, R7, T6, U9, V9, U7, V7, U8, V8,U6, V6
PWM3 Output Pulse Width Modulation Output; 4mA driving strength T16
PWM2 Output Pulse Width Modulation Output; 4mA driving strength U16
PWM1 Output Pulse Width Modulation Output; 4mA driving strength T15
PWM0 Output Pulse Width Modulation Output; 4mA driving strength U15
SAR3 Analog Input SAR Low Speed ADC Input 3;
General Purpose Input/Output B4
SAR2 Analog Input SAR Low Speed ADC Input 2;
General Purpose Input/Output A4
SAR1 Analog Input SAR Low Speed ADC Input 1; General Purpose Input/Output A5
SAR0 Analog Input SAR Low Speed ADC Input 0;
General Purpose Input/Output B5
DRAM Interface
Pin Name Pin Type Function Pin
MVREF Input Reference Voltage for DDR SDRAM Interface F15
A_MADR[12:0] Output DRAM Memory Address M18, A16, L20, M20,
B16, M19, C16, L18, A17, L19, B17, K19 , C17
A_BADR[1:0] Output DRAM Memory Bank Address J20, K20
A_MCLKE Output DRAM Memory Clock Enable J19
A_ODT I/O On-Die Termination E17
A_WEZ Output Write Enable; active low J18
A_RASZ Output Row Address Strobe; active low D17
A_CASZ Output Column Address Strobe; active low D16
B_MCLK Output DRAM Memory Positive Differential Clock A19
B_MCLKZ Output DRAM Memory Negative Differential Clock A18
B_DDR2_DQM[1:0] Output Data Mask for Low Byte; active high F18, E20
B_DDR2_DQS[1:0] I/O Data Strobe D20, E19
B_DDR2_DQSB[1:0] I/O Data Strobe Inverse D19, E18
B_MDATA[15:0] I/O DRAM Memory Data Bus D18, F19, C18, G18,
G19, C19, F20, C20, B20, G20, A20, H20, H19, B18, H18, B19
USB Interface
Pin Name Pin Type Function Pin
USB_DP Analog I/O USB Non Inverting Data Input/Output B6
USB_DM Analog I/O USB Inverting Data Input/Output A6
UART Interface
Pin Name Pin Type Function Pin
UART1_RX/ GPIO86 Input w/5V-tolerant Universal Asynchronous Receiver 1 /
General Purpose Input/Output; 4mA driving strength A8
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I2S_OUT_MUTE/ UART1_RX Output Audio Output Mute Control /
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Universal Asynchronous Receiver 1 C10
Pin Name Pin Type Function Pin
UART1_TX/ GPIO87 GPIO79/ UART1_TX I/O w/5V-tolerant Universal Asynchronous Transmitter 1 /
General Purpose Input/Output; 4mA driving strength General Purpose Input/Output; 4mA driving
strength / Universal Asynchronous Transmitter 1 C8 , D10
UART2_RX UART2_RX/ GPIO84 Input w/5V-tolerant I/O w/ 5V-tolerant Universal Asynchronous
Receiver 2 Universal Asynchronous Receiver 2 / General Purpose Input/Output; 4mA driving strength
D11, A9
UART2_TX UART2_TX/GPIO85 I/O w/5V-tolerant Universal Asynchronous Transmitter 2
Universal Asynchronous Transmitter 2 / General Purpose Input/Output; 4mA driving strength
A10 ,C9
Misc. Interface
Pin Name Pin Type Function Pin
DDCDA_DA I/O w/ 5V-tolerant HDCP Serial Bus Data / DDC Data of DVI/HDMI Port A G3
DDCDA_CK Input w/ 5V-tolerant HDCP Serial Bus Clock / DDC Clock of DVI/HDMI Port A G4
DDCDB_DA I/O w/ 5V-tolerant HDCP Serial Bus Data / DDC Data of DVI/HDMI Port B D3
DDCDB_CK Input w/ 5V-tolerant HDCP Serial Bus Clock / DDC Clock of DVI/HDMI Port B E3
DDCDC_DA I/O w/ 5V-tolerant HDCP Serial Bus Data / DDC Data of DVI/HDMI Port C R14
DDCDC_CK Input w/ 5V-tolerant HDCP Serial Bus Clock / DDC Clock of DVI/HDMI Port C R13
HOTPLUGA I/O w/ 5V-tolerant Hot-plug control for DVI/HDMI Port A F3
HOTPLUGB I/O w/ 5V-tolerant Hot-plug control for DVI/HDMI Port B C3
HOTPLUGC I/O w/ 5V-tolerant Hot-plug control for DVI/HDMI Port C P14
DDCA_DA I/O w/ 5V-tolerant DDC Data for Analog port F5
DDCA_CK I/O w/ 5V-tolerant DDC Clock for Analog port F6
DDCR_DA I/O w/ 5V-tolerant DDC Data for ROM U17
DDCR_CK I/O w/ 5V-tolerant DDC Clock for ROM T17
DDCR_DA2 I/O w/ 5V-tolerant DDC Data for ROM D11
DDCR_CK2 I/O w/ 5V-tolerant DDC Clock for ROM A10
XIN Crystal Oscillator Input Crystal Oscillator Input B3
XOUT Crystal Oscillator Output Crystal Oscillator Output A3
XTAL_OUT Output Clock Output for MStar Companion Chip R18
CEC I/O Consumer Electronics Control E4
HWRESET Schmitt Trigger Input w/ 5V-tolerant Hardware Reset; active high D5
Pin Name Pin Type Function Pin
AVDD_AU 3.3V Power Audio Power P6, R6
AVDD_LPLL 3.3V Power LPLL Power N15, P15
AVDD_MPLL 3.3V Power MPLL Power E7, E8
AVDD_MEMPLL 3.3V Power PLL Power H14
AVDD_33 3.3V Power ADC Power F7, F8, H6, H8, J8, K8, L8,
M8, N8
AVDD_DM 3.3V Power DM Power L13, M13
AVDD_USB 3.3V Power USB Power F14, G14
VDDP 3.3V Power Digital Input/Output Power F12, F13, F16, F17, J13, K13,
N9, N10
AVDD_MLINK 1.26V Power M-link Power M15
AVDD_PLLA_MLINK 1.26V Power M-link PLLA Power K15
AVDD_PLLB_MLINK 1.26V Power M-link PLLB Power L15
AVDD_DDR 1.8V Power DDR2 Power E15, E16, G15, G16, G17
VDDC 1.26V Power Digital Core Power E9, F9, F10, F11, H9, H10,
H11, H12, H13, N11, N12,
N13, P10, P11
GND Ground Ground A7, C5, D4, E13, E14, H15,
J9, J10, J11, J12, J15, K9,
K10, K11, K12, L9, L10, L11,
L12, M9, M10, M11, M12
No Connects
Pin Name Pin Type Function Pin
NC No connect. K18, R8, T11, W12, Y12
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I118 DDR2
37
The EM68B16C is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous dynamic
random-access memory (SDRAM) containing 512
Mbits in a 16-bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 8Mb
addresses x 16 I/Os The device is designed to comply with DDR2 DRAM key features such as posted
CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance
adjustment, and On Die Termination(ODT). All of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point
of differential clocks (CK rising and CK# falling)
All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous
fashion. The address bus is used to convey row,
column, and bank address information in RAS # , CAS# multiplexing style. Accesses begin with the
registration of a Bank Activate command, and then
it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or
8-bit burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Operating the
four memory banks in an interleaved fashion allows random access operation to occur at a higher rate
than is possible with standard DRAMs. An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data
rate is possible depending on burst length, CAS# latency, and speed grade of the device.
I109 Tuner
The Antenna receive the TV signal and modulate it to the CVBS signal and ATSC signal which can be
recognized By the decoder and MTS audio signal output to the sound multiplexing decoder portion of
IC MSD3003
I130 TPA3113D2 AUDIO AMP
The TPA3113D2 is a 6-W (Per channel) efficient, Class-D audio power amplifier for driving
bridged-tier stereo speakers. Advanced EMI Suppression Technology enables the use of inexpensive
ferrite bead filters at the output while meeting EMC requirements. SpeakerGuaud speaker protection
circuitry includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter
allows the user to set a “ virtual “ voltage rail lower than the chip supply to limit the amount of current
through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal
and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs.
The output are also fully protected against short to GND, VCC, and output to output. The short circuit
protection and thermal protection includes an auto recovery feature.
I131 TPA6113A2
The TPA6113A2 is a stereo audio power amplifier packaged in an 8-pin SOIC package capable of
delivering 40mW of continuous RMS power per channel into 16-Ө loads Amplifier gain is extermally
configured by means of two resistors per input channel and does not require external compensation for
settings of 0 to 20 dB.
I112 MSD809
The MSD1501 is a DTV receiver, which contains a digital receiver compatible with ATSC 8-VSB
mode for terrestrial broadcasting and open cable (SCTE DVS-031) which is in compliant with
64-QAM and 256-QAM modes for digital cable appliances.
It achieves extremely high performance employing direct IF sampling architecture,robust
synchronization, and robust channel equalization. It contains a 12-bit A/D converter and a PWM
generator for automatic gain control. A host interface with an I2C bus is also included to control the
behavior of the MSD1501.
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5. Adjusting Procedure
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5.1. ADJUSTMENT CONDITIONS AND PRECAUTIONS
1. Approximately 30 minutes should be allowed for warm up before proceeding.
2. Adjustments should be undertaken only on those necessary elements since most of them
have been carefully preset at the factory.
3. ESD protection is needed before adjustment.
5.2. MAIN ADJUSTMENTS
NO. FUNCTION DESIGNATION
1. EEPROM Initial Function Key
2. Adjust color temperature Function Key
5.3. ALIGNMENT PROCEDURES
Adjustment Conditions and Precautions:
(A). Power supply voltage:AC 110V± 10% 50 Hz ± 5%.
(B). Warm up time:
The display must be power ON for at least 30 minutes at full white pattern before
starting alignments.
This is especially critical in color temperature and white balance adjustments.
(C). Video : reference the front detail specifications.
1. Eeprom Initial:
Press ”INPUT” ,“Ÿ” KEY,“POWER” key go to factory mode.
2. Adjust color temperature
A. Enter to the factory mode, Source select “ D_Sub” figure 2, Use 19200x1080@60Hz the pattern
is “ 5 block ” figure 1,then move the cursor to the White Balance figure 3. Press “Ź” key. That will
do auto white balance.
B. After auto white balance, switch to the full white pattern then check the color temperature.
C. Enter to the factory mode, Source select “ YPbPr ”, Use NTSC Color Bar (FLUKE 54200 )
Figure 4, Set Color bar to 100 IRE then move the cursor to the White Balance figure 5. Press “Ź”
Key figure 6. That will do auto white balance. Finally change 16 gray scale must be claire in each
grays.
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figure 1 figure 2 figure 3
39
figure 4 figure 5 figure 6
3. Power Consumption Check ( VGA MODE )
A. TIMING: 1920 x 1080@60Hz
B. Pattern: 1010UPRIGHTNESS PATTERN
C. BRIGHTNESS=MAX, CONTRAST=MAX.
D. The power that each MODE consumed is shown in Chart 1.
MODE
NORMAL
Stand-by
4. Check the position of the picture displayed and phase auto adjusting (VGA MODE).
Depend on the TIMING of TIMING TABLE (TABLE 4) to switch MODE in order, stay about 10
seconds each MODE, it can changed and stored automatically each MODE. We can’t switch over
to the next MODE until AUTO ADJUST disappears.
5. HDMI MODE FUNCTION TEST
A.DVI MODE: Depend on the TIMING of TIMING TABLE (TABLE 3 ) to check MODE in
order.
B.HDMI MODE: make sure the 480i, 480p, 720p, 1080i,1080p TIMING is right.
6. OSD FUNCTION TEST
Time:1920*1080@60Hz
Pattern: 16*12 pane
Make sure that Each FUNCTION has one right action.
7. DTV FUNCTION TEST
Both NTSC and ATSC system were mixed together. At this point in tuner to the joints on the need
for 'AIR NTSC and ATSC 2 both systems were mixed with the signal
Both CATV and DIGITAL CABLE two systems are mixed together. At this point in tuner to the
need for a joint 'CATV and DIGITAL CABLE two systems are mixed in a the signal
MAX POWER COMSUMED POWER LED COLOR
75W(max) BLUE
1W (max) ORANGE
Chart 1
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8. YPbPr, S-VIDEO, AV, TV, DTV’S , HDMI, USBFUNCTION TEST
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A. Input YPbPr, S-VIDEO, AV , TV, DTV’S signal and check.
B. Input USA air channel (TABLE 1) and USA CATV channel for TV channel.
Under YPbPr , HDMI MODE, Make sure the 408i, 480P, 720P, 1080i,1080p is right.
Under USB to display “ JPEG, BMP” format.
9. AUDIO FUNCTION TEST
A. Audio input includes PC AUDIO IN, S-VIDEO/AV AUDIO IN and YPbPr/DVI AUDIO IN.
B. Under PC MODE, input PC AUDIO signal, checks whether the action of AUDIO IN is right.
C. Under S-VIDEO/AV MODE, input L/R AUDIO signal, checks whether the action of AUDIO
IN is right.
D. Under YPbPr MODE, input L/R AUDIO signal, checks whether the action of AUDIO IN is
right.Under HDMI MODE, checks whether the action of AUDIO IN is right Under TV MODE,
checks whether the action of AUDIO IN is right.
E. In DTV mode, the input signal ATSC, confirmed AUDIO LANGUAGE and the normal
movements PARENT
10.Under PC MODE, input PC AUDIO signal, determines whether the action of INT SPEAKER
output is right. Meets earphone with the EARPHONE, Determined whether the action of
EARPHONE output is normal.
11.DDC EDID confirm
VGA EDID confirm
By P106 VGA CONNECTOR DOWNLOAD EDID confirm whether normal or not
HDMI EDID confirm
By P109, P110, P111 HDMI CONNECTORS DOWNLOAD EDID confirm whether normal or
not
12.All Modes Reset
After final QC step, we must to erase all saved changes again and restore the factory defaults.
You should do “memory recall ” again.
Turn off the LCD TV by pressing “Power” button
13.BURN IN Mode access methods
Key Pad followed by pressing the "MENU" + "ENTER" 2 KEY, entered BURN IN mode
14.DCR function confirm In all source. (VT2730-M model only)
A. DCR turn ON.
B. Input full white pattern then measure the luminance. For example Value A
C. Input full dark pattern the measure the luminace. For example Value B
D. These two value ratio must be more than 100000. (A/B).
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TTV receiving test:
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TV SIGNAL TEST ITEM
CENTRALISM TRANSMITTING SIGNAL CHECK CONTENT
CHANNEL
ORDER
CHANNEL 2
CHANNEL 6
CHANNEL 7
CHANNEL 13
CHANNEL 14
CHANNEL 36
CHANNEL 69
TV TEST METHOD
A.CHANNEL2 Examines sound by ear, whether the sound does have mechanical resonation and
the electrical unusual sound, and image to sound disturbance.
B.CHANNEL6: Check sound and picture.
C.CHANNEL7: Examines whether the sound does receive the image disturbance, Judgment basis:
Whether there is unusual sound, input signal LEVEL<=36dBu,and STEREO SENSITIVITY is
normal.
D.CHANNEL13: Under main/sub/main-sub mode, check sub function.
E.CHANNEL14: Examines whether the sound does receive the image disturbance, Judgment basis:
Whether there is unusual sound.
F. CHANNEL 36:Check T1 of close-caption. Input signal level<=45dBu.
G.CHANNEL 69: Adjustment attenuator, If the critical point of the change of the image signal to
noise ratio is under LEVEL<=60dBu, regards as normally.
FREQUENCY
(MHz)
55.25 MONO SCOPE SWEEP TONE-10
83.25 COLOR BAR 400Hz -10 SOUND ,PICTURE
175.25 Full White (100
211.25 STAIR DUAL -10
471.25 MULTIBURST MONO -16
603.25 MULTIBURST MONO -10 TEST Close-caption T1
801.25 MONO SCOPE MONO(1KHz)-10 NOISE LIMMITTED
PATTERN SOUNDP/S(dB)
SET CONTENT
IRE)
ELECTRIC
ABNORMITY
SOUND
STEREO -10
STERO FUNCTION
SUB FUNCTION
IMAGE AND
SOUND DISTURB
FUNCTION
SENSITIVITY
CHECK
CONTENT
PRODUCTS OUTPUT CHECK ITEM.
The same as " CENTRALISM TRANSMITTING SIGNAL CHECK CONTENT"
saturation TEST, inputs the TV signal, the input signal LEVEL establishment most greatly is
90dBu,check whether CONTRAST of the image is normal; Whether appears the disturbance
phenomenon.
C.AFT CHECK,
(1) The frequency of the input TV signal is 211.25MHz (CH13), after confirmed the TV set
receives this signal, closure radio station; Then set frequency of the TV signal generator to be
212.25MHz, turn on the TV set and check whether the TV set receives the signal of CH13.
(2). The frequency of the input TV signal is 211.25MHz (CH13), after confirmed the TV set
receives this signal, closure radio station; Then set frequency of the TV signal generator to be
212.00MHz, turn on the TV set and check whether the TV set receives the signal of CH13.
(3). After all of FUNCTION TEST completed, we must erase all saved changes again and restore
the factory defaults.
DTV TEST ITEM
CHANNELFREQUENCYSOUNDdB PETTENCHECK CONTENT
14471.25MHz Y 50
36603.25MHz Y 50Color bar Color
69801.25MHz Y 75
Dynamic
picture
Dynamic
picture
Picture
Sound and Picture
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DTV CHECK METHOD
45
A.CHANNEL14: Check whether there are some pause or the mosaic phenomenon in the picture.
B.CHANNEL36: Check whether the color of the color bar is normal.
C.CHANNEL69: Turn RF attenuator and check the critical point of the change of the image’s S/N
is under LEVEL<45~85> dBu, regards as normally.
TIMING TABLE (FACTORY PRESET MODE) (table 4)
COMPATIBILITY TABLE
ASPECT RATIO
MODE
STANDARD RESOLUTION
DOS 720x400 @ 70Hz 1920x 1080
VESA 640x480 @ 60Hz 1920x 1080
VESA 640x480 @ 75Hz 1920x 1080
VESA 800x600 @ 60Hz 1920x 1080
VESA 800x600 @ 75Hz 1920x 1080
MAC 832x624 @ 75Hz 1920x 1080
VESA 1024x768 @ 60Hz 1920x 1080
VESA 1024x768 @ 75Hz 1920x 1080
VESA 1280x768 @ 60Hz 1920x 1080
VESA 1280x1024@ 60Hz 1920x 1080
VESA 1440x900@ 60Hz 1920x 1080
VESA 1680x1050@60Hz
VESA 1920x1080@60Hz
NTSC 480i(60Hz) 1920x 1080
SD 480p(60Hz) 1920x 1080
HD 720p(60Hz) 1920x 1080
HD 1080i (60Hz) 1920x 1080
Full HD 1080p (60Hz) 1920x 1080
HANDLING
FS*Full-Screen CompositeSVHSYPbPrRGBHDMI
1920x1080
1920x1080
COMPATIBLE INPUTS
No No No Yes Yes
No No No Yes Yes
No No No Yes Yes
No No No Yes Yes
No No No Yes Yes
No No No Yes Yes
No No No Yes Yes
No No No Yes Yes
No No No Yes No
No No No Yes Yes
No No No Yes Yes
NO NO NO Yes Yes
NO NO NO Yes Yes
Yes Ye s Ye s No Ye s
NO NO Yes No Yes
No No Yes No Yes
No No Yes No Yes
No No Yes No Yes
5. 4 Firmware Upgrade Procedure
When you receive the returned LCD TV, please check whether the firmware version is the
latest. If not, please do the following procedures to upgrade it to the latest version.
5.4.1 Equipment Needed
- VT2730-M LCD TV
- Fixture for Firmware Upgrade
- VGA Cable
- PC (Personal Computer)
- Firmware Upgrade Program
- One additional LCD TV for checking the program execution
5.4.2 Connection PC to the Tv set by the tool as the follow picture (pc1~pc3)
Action: The D_SUB cable must be 15 pin, and the TV set must be AC ON
pc.1
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5.4.3 Start the Isp
46
1. Open the “I.exe”
2.
Press the “config” , if the the ISP board have been found ,you will see the picture as
bellow.
pc 2
pc 3
pc.4
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3. Press the “Connect” ,If all the things are ok and ready, it will show the device type as
47
the bellow picture. Than pres “ᒔࡳ”
pc.5
4. Press “read” and choose the right F/W .
pc.6
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5. Press “Auto”, than press “Run”. It will start ISP . When the ISP is ok ,you will see the
48
information as the bellow picture.
pc.7
6. Pull away the AC power Cord and the D-SUB Cable. And start another TV set.
When we start another TV set with AC ON, we only need to press the “RUN”
5.4.4 USB update process
Step 1: Turn off AC power.
Step 2: Plug USB device with correct file name (By each models) F/W into socket.
Step 3: Turn on AC power and wait for a moment to update automatically. During updating,
you can see LED light to flash.
Step 4. When F/W finish updating process, the TV set turn on automatically and turn off AC
power and unplug USB device manually.
5.5 VGA DDC Key In Procedure
Note:
1. Every time after replacing the main board, you have to do the DDC key in.
2. If you find the DDC does not conform to the LCD TV, you have to do the DDC key in.
5.5.1 Equipment Needed
- VT2730-M LCD TV
- DDC Card
- PC
- RS-232 cable
- Barcode Reader
- VGA Cable
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! VT2730-M LCD TV DDC Card PC
49
!!!!!!RS-232 Cable VGA Cable Barcode Reader
5.5.2 Setup Procedure
1. Connect VGA Card and DDC Card with RS-232 cable.
2. Barcode Reader connects with keyboard and PC keyboard port.
3. Connect DDC Card and VT2730-M LCD TV with VGA Cable.
(when key in DVI DDC information, use VGA transform to DVI port )
4. Connect Power Cord to VT2730-M LCD TV.
5. Press ‘MENU’and ‘ENTER’ at the same time, then go into the BURN IN MODE.
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5.5.3 DDC Key In Procedure
50
1. run DDC exe
2. Choose model number the
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3. Press “ENTER” key.
51
4. Press “F4” key and Input bar code
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5. Press “ENTER” key, then the successful picture is as follows. “DDC DOWNLOED OK!
52
6. Exit program.
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5.6 HDMI DDC Key In Procedure
53
There are three EDID files for the different HDMI connectors. So you must be download the
different EDID into each HDMI connector.
5.6.1 Equipment Needed
- VT2730-M LCD TV
- PC
- RS-232 cable
- Barcode Reader
- HDMI Cable
-
VT2730-M LCD TV PC
RS-232 Cable HDMI Cable Barcode Reader
5.6.2 Setup Procedure
1. Connect HDMI Card and DDC Card with RS-232 cable.!
2. Barcode Reader connects with keyboard and PC keyboard port.!
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3. Connect DDC Card and VT2730-M LCD TV with HDMI Cable.
54
4. Connect Power Cord to VT2730-M LCD TV.!
!
5.6.3 DDC Key In Procedure
1. Run DDC.exe
2. Choose model number then
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3. Press “ENTER” key.
55
4. Press “F4” key.
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5. Input bar code
56
6. Press “ENTER” key, then the successful picture is as follows. “DDC DOWNLOED
OK!
7. Exit program
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Packing For Shipping And Disassembly Procedure
57
Packing For Shipping
1. Packing Procedure
1.1 Paste protection film to protect the LCD TV. (Figure 1)
1.2 Put the LCD TV in the PE bag and seal the bag. (Figure 2)
Figure 1 Figure 2
1.3 Put the cushions on the LCD TV. (Figure 3)
1.4 Place the LCD TV into the carton and then Put the other cushions on the LCD TV,put all the
accessories into the carton. At last, close the carton and seal it with tape. (Figure 4)
1.User’s Guide 2.Battery
Remote controlPower Cord
Figure 3
Figure 4
ViewSonic Corporation Confidential - Do Not CopyVT2730-1M
les, supplier can expand the rows to add more necessary item
added items or any change made should be highlighted and correlated with the ECN/ECR approved by ViewSonic Corporation. This is to eliminate repeated cr
27001C15900SET ASS'
27011C15900PCB ASS'
27021C15900PCB-MAI
27041C15900AUTO INSERT-MAI
27061C15900SMT-MAI
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2349900696PCAP,CHIP SPECCHIP C 22u 1206/X5R/10V M T1
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345510396PCAP CHIPCS 0402/Y5V/50V 0.01u Z T1
2345510396PCAP CHIPCS 0402/Y5V/50V 0.01u Z T1
2345522396PCAP CHIPCS 0402/Y5V/50V 0.022u Z T1
2347710696P-01CAP CHIPCS 0805/Y5V/10V 10u Z T DARFO
2347710696P-02CAP CHIPCS 0805/Y5V/10V 10u Z T TD
2347710696P-03CAP CHIPCS 0805/Y5V/10V 10u Z T WALSI
2347710696P-04CAP CHIPCS 0805/Y5V/10V 10u Z T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345110296PCAP CHIPCS 0402/X7R/50V 1000p K T1
2345510396PCAP CHIPCS 0402/Y5V/50V 0.01u Z T1
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345747396PCAP CHIPCS 0402/Y5V/16V 0.047u Z T1
2345747396PCAP CHIPCS 0402/Y5V/16V 0.047u Z T1
2340127096PCAP CHIPCS 0402/NPO/50V 27p J T1
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2347710696P-01CAP CHIPCS 0805/Y5V/10V 10u Z T DARFO
2347710696P-02CAP CHIPCS 0805/Y5V/10V 10u Z T TD
2347710696P-03CAP CHIPCS 0805/Y5V/10V 10u Z T WALSI
2347710696P-04CAP CHIPCS 0805/Y5V/10V 10u Z T MARUW
2340127096PCAP CHIPCS 0402/NPO/50V 27p J T1
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2347710696P-01CAP CHIPCS 0805/Y5V/10V 10u Z T DARFO
2347710696P-02CAP CHIPCS 0805/Y5V/10V 10u Z T TD
2347710696P-03CAP CHIPCS 0805/Y5V/10V 10u Z T WALSI
2347710696P-04CAP CHIPCS 0805/Y5V/10V 10u Z T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2340122096PCAP CHIPCS 0402/NPO/50V 22p J T1
2340122096PCAP CHIPCS 0402/NPO/50V 22p J T1
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
2345310496P-03CAP CHIPCS 0402/X7R/16V 0.1u K T WALSI
2345310496P-04CAP CHIPCS 0402/X7R/16V 0.1u K T MARUW
2345310496P-01CAP CHIPCS 0402/X7R/16V 0.1u K T DARFO
2345310496P-02CAP CHIPCS 0402/X7R/16V 0.1u K T TD
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