The ES66x8 Vibratto II processor is a hig hly integrated single -chip DVD solution that integrates read
channel, ECC, Servo DSP, MCU, and MPEG-2/MPEG-4/DivX decoder that has a state-of-the-art 480p/576p
progressive-scan video feature to provide brilliant and sharp, flicker-free video output to the display, and with
built-in gamma correction and S/PDIF input and output support. The 66x8 performs audio/video stream data
processing, TV encoding, Macrovision copy protection, DVD system navigation, system control, and
housekeeping functions.
The Vibratto II DVD processor is built on the ESS proprietary dual CPU Programmable Multimedia
Processor (PMP) core consisting of 32 -bit RISC and 64-bit DSP processors and offers the best DVD feature set.
These features can be listed as follows:
General Features:
− Single -chip DVD processor incorporating all front-end and back-end functions.
− Unified memory architecture.
− Built-in ADCs and DACs for servo control signals .
− DVD-Video, DVD-VR, VCD 1.1 and 2.0 and SVCD
− Proven ECC, EFM/EFM+ demodulation, and EDC circuit.
− Direct interface of 16-bit DRAM up to 128-Mb capacity.
− Direct interface of 8- or 16-bit SDRAM up to 128-Mb capacity.
− Direct interface for up to 4 banks of 8-bit EPROM or Flash EPROM for up to 4 MB per bank.
− Direct interface to the ES6603 servo AFE chip.
Video Related Features:
− Integrated NTSC/PAL encoder with pixel-adaptive de-interlacer and five 10-bit 54 MHz video DACs .
− DivX and MPEG-4 Advanced Simple Profile at full screen.
− Media playback with CD-ROM, CD-R/RW, DVD-R/RW and DVD+R/RW.
− Simultaneous composite, S-video and YUV outputs.
− CCIR656/601 YUV 4:2:2 output.
− OSD controller supports 256 colors in 8 degrees of transparency.
− JPEG digital photo CD support ( Kodak Picture CD and Fujifilm FujiColor CD ).
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Page 3
Audio Related Features:
− Full DVD-Audio support including MLP and LPCM decode, CPPM decryption, and watermark detection.
− Up to 7.1 channel audio outputs .
− Bass management.
− Dolby Digital ( AC-3 ), Dolby Pro Logic, and Pro Logic II.
− DTS surround ( ES6698 only ).
− S/PDIF digital audio input and output.
− SRS TruSurround.
− Professional karaoke with full scoring scheme.
1.2 MEMORY
1.2.1 System SRAM Interface
The system SRAM interface controls access to optional external SRAM, which can be used for RISC
code, stack, and data. The SRAM bus supports four independent address spaces, each having programmable bus
width and wait states. The interface can support not only SRAM, but also
ROM/EPROM and memory -mapped I/O ports for standalone applications are supported.
1.2.2 DRAM Memory Interface
The Vibratto II provides a glueless 16-bit interface to DRAM memory devices used as video memory
for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous DRAM (SDRAM).
The memory interface is configurable in depth to support 12 8-Mb addressing. The memory interface controls
access to both external SDRAM or EDO memories, which can be the sole unified external read/write memory
acting as program and data memory as well as various decoding and display buffers.
1.3 FRONT PANEL
The front panel is based around an Futaba VFD and a common front panel controller chip, (uPT6311).
The ES66x8 controls the uPT6311 using several control signals, (clock, data, chip select). The infrared remote
control signal is passed directly to the ES66x8 for decoding.
1.4 REAR PANEL
A typical rear panel is included in the reference design. This rear panel supports:
- six channel and two channel audio outputs
- Optical and coax S/PDIF outputs.
- Composite, S-Video, and SCART outputs
The six-video signals used to provide CVBS, S-Video, and RGB are generated by the ES66x8 ’s internal video
DAC. The video signals are buffered by external circuitry.
Six channel audio output by the ES66x8 in the form of three I
stream is also generated by the ES66x8 output by the rear panel. A six channel audio DAC are used for six
channel audio output with ES66x8, and similarly one Audio DAC is used for two channel audio output with
ES66x8.
2
S (or similar) data streams. The S/PDIF serial
3
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2. System Block Diagram and ES66x8 Pin Description
2.1 ES66x8 Pin Description
4
Page 5
5
Page 6
6
Page 7
7
Page 8
8
Page 9
2.1 SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES66x8 Vibratto II DVD player board design is shown in the
following figure:
9
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3. AUDIO OUTPUT
The ES66x8 supports two -channel analog audio output while ES66x8 supports six-channel analog audio output.
In a system configuration with six analog outputs, the front left and right channels can be configured to provide
the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel surround
system.
The ES6008 also provides digital output in S/PDIF format. The board supports both optical and coaxial S/PDIF
outputs.
3. AUDIO DACS
The ES66x8 supports several variations of an I2S type bus, varying the order of the data bits (leading or no
leading zero bit, left or right alignment within frame, and MSB or LSB first) is possible using the ES66x8
internal configuration registers. The I2S format uses four stereo data lines and three clock lines. The I2S data and
clock lines can be connected directly to one or more audio DAC to generate analog audio output.
The two-channel DAC is an CS4392. The DACs support up to 192kHz sampling rate.
The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuits
use National LM833 op-amps to perform the low-pass filtering and the buffering.
5 VIDEO INTERFACE
5.1 Video Display Output
The video output section controls the transfer of video frames stored in memory to the internal TV encoder of the
Vibratto II. The output section consists of a programmable CRT controller capable of operating either in Master
or Slave mode.
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The video output section features internal line buffers which allow the outgoing luminance and chrominance data
to match the internal clock rates with external pixel clock rates, easily facilitating YUV4:2:2 to YUV4:2:0
component and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and interpolation.
Video Bus
The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in CCIR1656 pixel
format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y)
pixels; there are as many chrominance lines as luminance.
Video Post -Processing
The Vibratto II video post-processing circuitry provides support for the color conversion, scaling, and filtering
functions through a combination of special hardware and software. Horizontal up-sampling and filt ering is done
with a programmable, 7-tap polyphase filter bank for accurate
non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in accordance with the
applicable scaling ratio.
Video Timing
The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. The
double clock typically is used for TV displays, the single for computer displays.
6 SDRAM MEMORY
The memory bus interface generates all the control signals to interface with external memory. The Vibratto II
supports different configurations using the memory configuration bits SDCFG[1:0] (bits 12:11), the SD8BIT bit
(bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROL register. Configurations can be
implemented in many ways. The following table lists the typical SDRAM configurations used by the Vibratto II.
Typical SDRAM Configurations:
The memory interface controls access to both external SDRAM or EDO memories, which can be the sole unified
external read/write memory acting as program and data memory as well as various decoding and display buffers.
At high clock speeds, the Vibratto II memory bus interface
11
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has sufficient bandwidth to support the decoding and displaying of CCIR1656/601 resolution images at full
frame rate.
7 FLASH MEMORY
The decoder board supports AMD class Flash memories. Currently 4 configurations are supported:
The Vibratto II permits both 8- and 16-bit common memory I/O accesses with a removable storage card via the
host interface.
8 SERIAL EEPROM MEMORY
An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup,
etc.) and software configuration.. Industry standard EEPROM range in size from 1kbit to 256kbit and share the
same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or
equivalent.
9 AUDIO INTERFACE AUDIO SAMPLING RATE AND PLL COMPONENT
CONFIGURATION
The ES66x8 Vibratto II audio mode configuration is selectable, allowing it to interface directly with
low-cost audio DACs and ADCs. The audio port provides a standard I2S interface input and output and S/PDIF
(IEC958) audio output. Stereo mode is in I2S format while six channels Dolby Digital (5.1 channel) audio output
can be channeled through the S/PDIF. The S/PDIF interface consists of a bi-phase mark encoder, which has low
skew. The transmit I2S interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where
sampling frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the I2S
transmit interface can be 16, 18, 20, 24, and 32-bit samples.
For Linear PCM audio stream format, the Vibratto II supports 48 kHz and 96 kHz. Dolby Digital audio
only supports 48 kHz. The ES6008/18 Vibratto II incorporates a built-in programmable analog PLL in the device
architecture in order to generate a master audio clock. The MCLK pin is for the audio DAC clock and can either
be an output from or an input to the ES66x8 Vibratto II . Audio data out (TSD) and audio frame sync (TWS) are
clocked out of the Vibratto II based on the audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is
used to clock in audio data in (RSD) and audio receive frame sync (RWS).
10 FRONT PANEL
10.1 VFD CONTROLLER
The VFD controller is a PTC PT6311. This controller is not a processor, but does include a simple state
machine which scans the VFD and reads the front panel button matrix. The 6311 also includes RAM so it can
store the current state of all the VFD icons and segments. Therefore, the 6311 need only be accessed when the
VFD status changes and when the button status is read. The E S66x8 can control this chip directly using PIO pins
or can allow the front panel PIC to control the VFD.
11 MISCELLANEOUS FUNCTIONS
11.1 RESET CIRCUITRY
Two different chips are supported to provide the power-on-reset and pushbutton reset function:
AAT3521 or V6300.
12
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12 CONNECTORS
12.1 SCART CONNECTORS
Pinout of the scart connector:
1 ? Audio Right Out
2 ? Audio Right In
3 ? Audio Left / Monu Out
4 ? Audio Gnd
5 ? Blue Gnd
6 ? Audio Left / Mono In
7 ? Blue
8 ? Control Voltage
9 ? Green Gnd
10 ? Comms Data 2
11 ? Green
12 ? Comms Data 1
13 ? Red Gnd
14 ? Comms Data Gnd
15 ? Red
16 ? Fast Blanking
17 ? Video Gnd
18 ? Fast Blanking Gnd
19 ? Composite Video In
20 ? Composite Video Out
21 ? Shield
Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths. For
longer lengths, shielded coax cable become essential.
0.7Vpp ?2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the
S-VHS Chrominance signal, which is 0.3V.
Composite Video / CSync
1Vpp including sync, ?2dB, 75R in put and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV
Video de-emphasis to CCIR 405.1 (625-line TV)
Fast Blanking
75R input and output impedance. This control voltage allows devices to over -ride the composite video input with
RGB inputs, for example when inserting closed caption text. It is called fast because this can be done at the same
speeds as other video signals, which is why it requires the same 75R impedances.
13
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0 to 0.4V: TV is driven by the composite video input signal (pin 19).
Left unconnected, it is pulled to 0V by its 75R termination.
1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the
TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such a s home
computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider
with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V)
negative sync pulse is available, this will be high during the display periods, so this can drive the
blanking signal via a suitable resistor.
Control Voltage
0 to 2V = TV, Normal.
5 to 8V = TV wide screen
9.5 to 12V = AV mode
13. CIRCUIT DESCRIPTION
13.1 POWER SUPPLY:
− Socket PL2 is the 220VAC input.
− Socket PL3 is used for the power button on the front panel.
− 3.15A fuse F1 is used to protect the device against short circuit.
− Voltage is rectified by using diodes D1, D2, D3 and D4. Using capacitor C33 (47?f) a DC voltage is
produced. (310 - 320VDC).
− The current in the primary side of the transformer TR2 comes to the SMPS IC (TNY267P). It has a built-in
oscillator, over current and thermal protection circuitry and runs at 133 kHz. It starts with the current from
the primary side of the transformer and follows the current from the feedback winding.
− Voltages on the secondary side are as follows: 12 Volts at pin11 at C42, 5 Volts at C40,3.3 Volts at C38,
-22Volts at C44, -12 Volts at D22.
− D14 TL431 is a constant current regulator. TL431 watches the 5 volts and supplies the required current to
IC2. There are a LED and a photo transistor in IC2. The LED inside the IC2 transmits the value of the
current from D25 to phototransistor. Depending on the current gain of the phototransistor IC3 keeps the
voltage on the 5-volt-winding constant.
− –22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on the front panel.
14
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Functional Block Diagram of Switcher
13.2 FRONT PANEL:
− All the functions on the front panel are controlled by U1 (ES66x8) on the mainboard.
− U1 sends the commands to IC2 PT6311 via socket J2 (pins 3,4 and 5).
− There are 48 keys scanning function, 5 LED outputs, 1 Stand-by output and VFD drivers on PT6311.
− Vacuum fluorescent display is specially designed for DVD.
− The scanned keys are transmitted via PT6311 to U1 on the mainboard.
− IR remote control receiver module sends the commands from the remote control directly to U1.
13.3 BACK PANEL:
− There are 1 SCART connector (con24), 2 pieces RCA audio jacks for audio output, 1 coaxial digital audio
output and 1 laser digital audio output on the back panel.
− MOFT3C2 is used for laser output.
− Left and right audio outputs are on RCA Conn 6.
− LUMA and CHROMA signals of S-Video are transmitted to P1 via transistors Q39 and Q37 respectively.
15
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CD Update Procedure of 4250D
1. Download the update file from the convenient link according to your default language choice.
2. While there is no CD in the DVD (No Disc Mode) , press “Menu 1 3 5 7” buttons on the remote control
in order to reach the Servi ce Menu of DVD Player:
2.1. Note the software version described as “b.xx “ to be able to compare the sw. Version after update
process.
3. Copy the update file to the desktop and rename it according to the update file name in the hidden menu of
the device.
For example If C2M1AS__ is written then rename it like C2M1AS__.rom
If P6M1AS__ is written then rename it like P6M1AS__.rom
(If you receive the update file already renamed (with addition of .rom) from the customer technical support
department by giving the SAP code of the product then burn the already renamed file with nero program as
it is shown below.)
4. Burn the renamed files by Nero program with below set up.
5. After burning process is completed, place the update CD into the DVD tray and press play button.
6. Wait to see the update process steps as shown below. When the sw. Update is completed unit will switch
itself to standby mode.
7. Finally, press the eject button and take out the update CD while DVD Player remains at stand by Mode.
8. Updating process has been completed. To check whether it is updated correctly or not, repeat the first step
for comparing software version
9. If the previous and letter names are different, CD is update has completed successfully. If the name remains
same than go through the steps from the beginning.
IMPORTANT NOTE: If the AC source breaks down while the updating the unit (main board) will be
totally out of order. This kind of units/boards is out of Warranty.
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Brief Information of Naming the File
Software version differs from each other depending on front models. 23xx and 24xx are called Old VFD and
25xx and 26xx are called Mini VFD. Each character in the file name is an abbreviation of a description as
illustrated below.
C2M1AS__
Progressive Option (with progressive : P, without progressive: _ )
DMR option (with DMR:R, without DMR:_ )
Loader Type (S loader:s W loader:w)
Flash Type ( AMD:A, Intel:I )
Language group
VFD type
DAC channel (2, 6)
DAC Type
17
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Pay attention the left side. Select CD and CD_ROM (ISO) on the upper left side of screen
18
Page 19
Select No Multisession
19
Page 20
Format is Mode 1
20
Page 21
21
Page 22
Leave the dates as it is
22
Page 23
Leave it as it is
23
Page 24
Click the “New” on the upper right corner of the screen
24
Page 25
Select your file from file browser then you will see your file in the “Name” section on the right side and then
copy the files to under “Name” section on the left side.(this is just an example you will see your file name when
you are doing this process)
25
Page 26
Click the “Burns the current compilation”
26
Page 27
Then you will see this screen and click the “Burn” on the right upper side of screen
27
Page 28
You will see this screen and tray will open itself on computer ,then place the CD in CD-ROM
And it will start writing. At the end you will see “burn complited”
.
28
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MOCTL(3)
SVREF21(3)
VCC33
MIRR(3)
ATR_OP(3)
SERIAL EEPROM
1
2
3
45
GND
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
DSCK
DOE#
CS0#
RAS0#
CAS#
DWE#
DQM
RAS1#
RAS2#
XFLAG0
XFLAG1
XFLAG2
XFLAG3
RFO
TESTAD
DA
RFRP
DIP
DIN
TRACK
FOCUS
SLEGP
SLEGN
SPINDLE
MIRR
TEI
FEI
CEI
SPDON
SFGIN
The information has been checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies. Circuit diagrams are provided as a means of illustrating typical applications; consequently complete information for construction purposes is not necessarily given. ESS reserves the right to make changes at any time in order to improve the design.
A
ES66x8
B15
0.1UF
B24
0.1UF
B35
0.1UF
CC126
0.1
B16
0.1UF
B25
0.1UF
B36
0.1UF
CC127
0.1
SDRAM
B17
0.1UF
B28
0.1UF
B37
0.1UF
CC128
0.1
B18
0.1UF
B29
0.1UF
B38
0.1UF
CC129
0.1
GND
GND
B22
0.1UF
B62
10UF
B31
10UF
0.1UF
B60
GND
VCC
GND
GND
B33
10UF
B61
0.1UF
24C01
B45
0.1UF
CC130
100U
VCC
B20
0.1UF
B32
10UF
B43
0.1UF
B19
0.1UF
B30
0.1UF
B40
10UF
+
B
B21
0.1UF
B41
0.1UF
RF50V+5V
CC7
100/10
+
RFGNDRFGND
2
2
2
VCC20
4
OUT
R67
412(1%)
R66
250(1%)
C
D24
IN4148
LL2
FERB
2
CC11
0.1
LL1
FERB
LL5
FERB
LL15
FERB
AMS1117
ADJ
1
0.1UF(OPEN)
GND
1
3.3V REGUALTOR
VCCVCC33
Q2 OPEN
32
INOUT
C23
OPEN
(10UF)
GND
VCC33PLL33V
VCC33RF33V
VCC33VCC33V
U9
32
INOUT
C16
VCC33
MVCC
VCCA
VCC
LL7OPEN
LL3OPEN
MGNDGNDGND
LL14FERB
LL11FERB
LL12FERB
B4
B3
220UF
220UF
GNDAGND
ADJ
1
No need to install
EZ1085 circuitry if
J12 provide +3.3V
2
2
2
(EZ1085)
2
2
R38
OPEN
1%
(412 OHM)
R39
OPEN
1%
(681 OHM)
GND
GNDGNDV
GNDA
+12VVCC33
B1
220UF
GND
B2
OPEN
(100UF)
GND
LL8OPEN
RFGND
LL9OPEN
-12V+5V
S12V
GND
FRONT
EZ1085
ADJ
INP
OUT
2
GND
2
8
7
6
5
4
3
2
1
2.54MM
JS3
VESTEL
Title
MISC
SizeDocument NumberRev
C
VESTEL-4250H-A1
D
Date:Sheet
E
of
45Wednesday, March 03, 2004
A1
Page 32
A
B
C
D
E
UDAC(2)
C236
0.1UF
C173
0.1UF
+5VA
VCCV
C297
100uF/25
VCCV
1
C298
100uF/25
VCCV
C299
100uF/25
1
C128
0.1UF
C174
0.1UF
1
1
R170 1K
R173
OPEN
1
R421
2K2
2
1
R423
1K8
1
R422
2K2
2
1
R425
1K8
1
R429
2K2
2
1
R431
1K8
+12V
IN4148
C227
220uF/25
R176
470
D6
1
1
C191
0.1UF
C193
0.1UF
2
1
GNDVGNDV
GNDVGNDV
GNDVGNDV
Q36
BC848B
13
1
R427
75
Q37
BC848B
13
1
R428
75
Q38
BC848B
13
1
R435
75
1
Q27
2N3904
13
C169
10UF
C175
10UF
R165
6.8K
R171
1K
R426
75
R424
75
1
C170
10UF
C176
10UF
R432
75
1
1
1
IN4148
1
D5
CVBS-OUT
CHROMA-OUT
B-OUT
R167
2.2K
+5VA
2
1
1
13
Q26
8550
D7
IN4148
2
1
P3
RCA CONN 6
13
+5VA
Q25
8550
1
R174
100K
1
QUIET0
C226
470uF
2
FR
1
FL
+12V
U25-1
84
C211
680PF
C172
680PF
5
6
-12V
+12V
-12V
+12V
-12V
+12V
-12V
3
2
C188
680PF
V+
V-
84
V+
V-
84
V+
V-
84
V+
V-
C184
680PF
+12V
-12V
OPA2134UA
1
U25-2
OPA2134UA
7
U24-1
OPA2134UA
1
U24-2
OPA2134UA
7
+12V
84
V+
V-
-12V
U23-2
84
OPA2134UA
V+
7
V-
Rs_OUT
Ls_OUT
LFE_OUT
C_OUT
U23-1
OPA2134UA
1
C213
10UF
C219
10UF
C220
10UF
C214
10UF
C221
10UF
C215
10UF
1
QUIET0
1
QUIET0
1
1
QUIET0
1
QUIET0
1
R159
100K
1
R149
100K
1
R160
100K
QUIET0
1
R150
100K
1
R161
100K
1
R151
100K
QUIET0
R156
1
10 OHM
R29
10 OHM
R157
10 OHM
R30
10 OHM
R158
10 OHM
R148
10 OHM
1
R152
1
470
1
R153
1
1
1
R162
470
R163
470
470
R164
470
R155
470
C216
22PF
C223
22PF
2
C224
22PF
C217
22PF
C225
22PF
C218
22PF
FR
2
2
2
2
2
SUB
CC
13
Q13
2SC3327
13
Q23
2SC3327
13
Q20
2SC3327
13
Q24
2SC3327
13
Q21
2SC3327
13
Q22
2SC3327
RS
LS
FDAC(2)
+12V
-12V
C263
AOUT2R+(4)
44
AOUT2R-(4)
AOUT1R+(4)
AOUT1R-(4)
AOUT1L+(4)
33
AOUT1L-(4)
AOUT2L+(4)
AOUT2L-(4)
22
AOUT0R+(4)
AOUT0R-(4)
AOUT0L+(4)
11
AOUT0L-(4)
10UF
C289
10UF
C292
10UF
C293
10UF
C296
10UF
C262
10UF
C285
10UF
C288
10UF
C261
10UF
C279
10UF
C281
10UF
C284
10UF
R331
R12
1
10K
R338
R175
1
1
1
R409
1
10K
3300PF
R14
1
10K
1
1
10K
C276
3300PF
C278
3300PF
10K
R398
10K
R196
11K
C287
1
1
R417
10K
R24
10K
10K
R414
10K
R20
10K
C189
C235
open
C181
open
open
1
1
1
1
R419
10K
C190
open
R400
10K
C177
open
R416
10K
C185
open
R353
10K
R339
10K
C283
3300PF
R412
10K
R337
680
R25
1
680
R397
680
1
R186
1
680
R399
680
1
R197
1
680
R410
680
1
1
C291
3300PF
1
R415
680
1
1
C295
3300PF
1
R15 680
1
R418680
C286
680PF
1
C275
680PF
R154
1
10K
C277
680PF
R195
1
10K
C282
680PF
R13
1
10K
R16 10K
C290
680PF
R21
680
1
R27
680
3
2
C178
680PF
5
6
3
2
5
6
C180680PF
R22
10K
C294
680PF
R28
10K
YDAC(2)VDAC(2)
CDAC(2)
FB3 FB
SPDIF(2)
3
4
-12V
VCCV
VCCV
2
1
C300
100uF/25
1
C301
100uF/25
VCC
5
697
LSFLRS
GNDV
C232
0.1UF
1
2
1
1
2
1
NN(2)
0.1UF
R430
2K2
R433
1K8
R438
2K2
R437
1K8
R166
10M
C228
R441
75
Q39
BC848B
13
1
R436
75
GNDVGNDV
Q40
BC848B
13
1
R444
75
GNDV
SCART-ON(2)
R408
10K
VCC
1
U27B
34
7404
1
R1721M
8
CC
SUB
1
+12V
G-OUT
1
LUMA-OUT
1
R434
75
P1
6
Q34
U27D
7404
GND
R403
330
1
13
6
5
5
4
4
3
3
CVBS-OUT
R-OUT
G-OUT
B-OUT
1
GND
2
0.1UF
+5VA
12
GND
1
1
C230
R405
100K
L21
47UH
C280
0.1UF
21
21
GNDV
FL
FR
GND
R407
10K
SCART-ON (2)
U27A
12
7404
U27E
1110
7404
U27F
1312
7404
1
R187
68 OHM
J1
1
2
3
4
5
6
7
8
9
10
11
CON24
CVBS-OUT
R-OUT
1
R445
75
10K
R402
1
2
Q31
2N3904
13
GND
+12V
2
GND
13
Q35
2N3904
4
3
13
R406
10K
R411
820
56
P9
RCA CONN
2
GND
LUMA-OUT
CHROMA-OUT
+5VA
R401
10K
1
Q32
8550
1
1
2
R404
10K
D25
IN4148
1
1
R413
1.2K
GNDGND
U27C
7404
1
R179
91 OHM
1
GND
GND
VCC
MOFT3C2
Q30
8550
13
Q33
8550
13
1
R178
1
330 OHM
P2
VIN
2
2
R420
10K
2N3904
98
3
2
1
VESTEL
Title
OUTPUT
SizeDocument NumberRev
C
A
B
C
D
Date:Sheet
VESTEL-4250H-A1
E
of
55Wednesday, March 03, 2004
A1
Page 33
Page 34
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