UTRON UT62W1024LC-55LL, UT62W1024LC-55L, UT62W1024LC-35LL, UT62W1024LC-35L, UT62W1024PC-35LL Datasheet
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UTRON
UT62W1024
Rev. 1.0
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 10µA (typical) L-version
1µA (typical) LL-version
Wide range power supply : 2.7V to 5.5V
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20mm TSOP-1
32-pin 8x13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/ O
COLUMN DECODER
ROW
DECODER
I/O
CONTROL
LOGIC
CONTROL
A15
I/O1
VSS
VCC
WE
OE
1CE
I/O8
.
.
.
.
.
.
. .
.
A13
A
7
A6
A5
A4
A8
A
11
A
2 A1 A0
A
10
.
.
.
.
.
.
MEMORY ARRAY
1024 ROWS × 1024 COLUMNS
A
9
A14
A12
A16
A
3
CE2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
1CE
,CE2
Chip enable 1,2 Inputs
WE
Write Enable Input
OE
Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
GENERAL DESCRIPTION
The UT62W1024 is a 1,048,576-bit low power
CMOS static random access memory organized
as 131,072 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT62W1024 is designed for low power
application. It is particularly well suited for
battery back-up nonvolatile memory application.
The UT62W1024 operates from a wide range of
2.7V~ 5.5V power supply and all inputs and
outputs are fully TTL compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT62W1024
PDIP / SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
1CE
WE
OE
A13
A14
NC
A16
Vcc
A15
29
30
31
32
TSOP-I/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4 A3
UT62W1024
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
1CE
CE2
NC
A15
A16
32
31
30
29
UTRON
UT62W1024
Rev. 1.0
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to Vss V
TERM
-0.5 to +4.6 V
Operating Temperature TA 0 to +70
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 sec) T
solder
260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
1CE
CE2
OE
WE
I/O OPERATION SUPPLY CURRENT
Standby H X X X High - Z
I
SB
,
I
SB1
Standby X L X X High -Z
I
SB
,
I
SB1
Output Disable L H H H High - Z
I
CC
Read L H L H
D
OUT
I
CC
Write L H X L
D
IN
I
CC
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS ( Ⅰ )
(VCC = 2.7V~3.6V, Vss=0V, TA = 0℃ to 70℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage
V
IH
2.0 - V
CC
+0.5 V
Input Low Voltage
V
IL
- 0.5 - 0.6 V
Input Leakage Current
I
IL
VSS ≦VIN ≦VCC
- 1 - 1
µ
A
Output Leakage Current I
OL
VSS ≦V
I/O
≦
V
CC
1CE
=V
IH
or CE2 = VIL or
OE
= V
IH
or
WE
= V
IL
- 1 - 1
µ
A
Output High Voltage
V
OH
IOH = - 1mA 2.2 - - V
Output Low Voltage
V
OL
IOL= 4mA - - 0.4 V
-35 - 40 60 mA
-55 - 35 50 mA
I
CC
Cycle time =Min. 100% Duty,
1CE
=V
IL
, CE2 = VIH,
I
I/O
= 0mA
-70 - 30 40 mA
Average Operating
Power Supply Courrent
I
CC1
Cycle time = 1µs, 100% Duty,
.
1CE
≦
0.2V,CE2≧V
CC
-0.2V,
, C
L
=50PF
- - 5 mA
I
SB
1CE
=V
IH
or CE2 = VIL
- - 1.0 mA
100
- L - 2.5
20*
µ
A
40
Standby Power
Supply Current
I
SB1
1CE
≧
V
CC
-0.2V or
.CE2≦0.2V
-
LL
- 0.5
10*
µ
A
*Those parameters are for reference only under 50℃
UTRON
UT62W1024
Rev. 1.0
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
DC ELECTRICAL CHARACTERISTICS (Ⅱ)
(VCC = 4.5V~5.5V, Vss=0V, TA = 0℃ to 70℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage
V
IH
2.2 - V
CC
+0.5 V
Input Low Voltage
V
IL
- 0.5 - 0.8 V
Input Leakage Current
I
IL
VSS ≦VIN ≦VCC
- 1 - 1
µ
A
Output Leakage Current I
OL
VSS ≦V
I/O
≦
V
CC
1CE
=V
IH
or CE2 = VIL or
OE
= V
IH
or
WE
= V
IL
- 1 - 1
µ
A
Output High Voltage
V
OH
IOH = - 1mA 2.4 - - V
Output Low Voltage
V
OL
IOL= 4mA - - 0.4 V
-35 - 60 100 mA
-55 - 50 85 mA
I
CC
Cycle time =Min. 100% Duty,
1CE
=V
IL
, CE2 = VIH,
, C
L
=100PF
-70 - -40 70 mA
Average Operating
Power Supply Courrent
I
CC1
Cycle time = 1µs, 100% Duty,
.
1CE
≦
0.2V,CE2≧V
CC
-0.2V,
I
I/O
= 0mA
- - 5 mA
I
SB
1CE
=V
IH
or CE2 = VIL
- - 1.0 mA
100
- L - 2.5
20* µ
A
40
Standby Power
Supply Current
I
SB1
1CE
≧
V
CC
-0.2V or
.CE2≦0.2V
-
LL
- 0.5
10*
µ
A
*Those parameters are for reference only under 50℃
UTRON
UT62W1024
Rev. 1.0
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL=100pF, IOH/IOL=-1mA/4mA(VCC=5V)
C
L
=50pF, IOH/IOL=-1mA/2mA(VCC=3.3V)
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V~5.5V, V
SS
=0V , TA = 0℃ to 70℃)
(1) READ CYCLE
PARAMETER
SYMBOL
UT62W1024-35 UT62W1024-55 UT62W1024-70
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time tRC 35 - 55 - 70 - ns
Address Access Time tAA - 35 - 55 - 70 ns
Chip Enable Access Time t
ACE1
, t
ACE2
- 35 - 55 - 70 ns
Output Enable Access Time tOE - 25 - 30 - 35 ns
Chip Enable to Output in Low-Z t
CLZ1
*, t
CLZ2
* 10 - 10 - 10 - ns
Output Enable to Output in Low-Z t
OLZ
* 5 - 5 - 5 - ns
Chip Disable to Output in High-Z t
CHZ1
*, t
CHZ2
* - 25 - 30 - 35 ns
Output Disable to Output in High-Z t
OHZ
* - 25 - 30 - 35 ns
Output Hold from Address Change tOH 5 - 5 - 5 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL
UT62W1024-35
UT62W1024-55
UT62W1024-70
UNIT
MIN.
MAX. MIN.
MAX. MIN. MAX.
Write Cycle Time tWC 35 - 55 - 70 - ns
Address Valid to End of Write tAW 30 - 50 - 60 - ns
Chip Enable to End of Write t
CW1
, t
CW2
30 - 50 - 60 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 25 - 40 - 45 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 20 - 25 - 30 - ns
Data Hold from End of Write-Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High-Z t
WHZ
* - 15 - 20 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT62W1024
Rev. 1.0
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80056
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
t
RC
Address
DOUT Data Valid
t
AA
t
OH
t
OH
READ CYCLE 2 (
1CE
, CE2 and
OE
Controlled)
(1,3,5,6)
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
CHZ1
t
CHZ2
t
OHZ
t
CLZ1
t
CLZ2
t
OH
t
OLZ
HIGH-Z
Data Valid
HIGH-Z
Address
CE1
CE2
OE
Dout
Notes :
1.
WE
is HIGH for a read cycle.
2. Device is continuously selected
OE
,
1CE
=V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with
1CE
low
and CE2 high transition; otherwise tAA is the limiting parameter.
4.
OE
is low.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with CL=5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
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