55ns(max) for Vcc=3.0V~3.6V
70/100ns(max) for Vcc=2.7V~3.6V
CMOS Low operating power
Operating current: 45/35/25mA (Icc max)
Standby current: 20 uA(TYP.) L-version
3 uA(TYP.) LL-version
Single 2.7V~3.6V power supply
Operating temperature:
Commercial : 0℃~70℃
Extended : -20℃~80℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Data byte control :
Package : 44-pin 400mil TSOPⅡ
48-pin 6mm × 8mm TFBGA
LB
UB
(I/O1~I/O8)
(I/O9~I/O16)
FUNCTIONAL BLOCK DIAGRAM
.
MEMORY ARRAY
1024 Rows x 64 Columns x 16 bits
.
. .
COLUMN I/O
12
13
14
15
I/O1
.
.
I/O16
DECODER
. . .
CONTROL
ROW
I/O
.
.
.
.
.
UT62L6416
64K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L6416 is a 1,048,576-bit low power
CMOS static random access memory organized
as 65,536 words by 16 bits.
The UT62L6416 operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
The UT62L6416 is design for upper and low byte
access by data byte control(
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A15 Address Inputs
I/O1 - I/O16 Data Inputs/Outputs
CE
WE
OE
LB
UB
VCC Power Supply
VSS Ground
NC No Connection
VCC
VSS
UB
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
High-Byte Control
LB
).
11
10
COLUMN DECODER
A9
A7 A6
5
CE
WE
OE
LB
UB
LOGIC
CONTROL
UTRON TECHNOLOGY INC. P80073
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
T
UTRON
Preliminary Rev. 0.1
PIN CONFIGURATION
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
2223
UT62L6416
64K X 16 BIT LOW POWER CMOS SRAM
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
A
B
C
D
E
F
G
H
LB
OE
I/O9
UB
I/O11I/O10
I/O12
Vss
I/O13
Vcc
I/O15 I/O14
I/O16
NC
NC
A8
123456
UT62L6416
A0
A3
A5
NC
A14
A12
A9
TFBGA
A1
A4
A6
A7
NC I/O5
A15 I/O6
A13
A10
A2
CE
I/O4NC
WE
A11
NC
I/O1
I/O3I/O2
Vcc
Vss
I/O7
I/O8
NC
TSOP II
TRUTH TABLE
MODE
Output
Disable
Read L
Write L
Note: H = VIH, L=VIL, X = Don't care.
CE
OE
H X X X X High – Z High – Z ISB, I
X X X H H High – Z High – Z I
L
L
H
H
L
L
L
L
L
X
L
L
X
X
WE
LB
UB
H
H
H
H
H
L
L
L
L
X
L
H
L
L
H
L
X L High – Z
H
L
L
H
L
L
I/O OPERATION
I/O1-I/O8 I/O9-I/O16
High – Z
High – Z
D
OUT
High – Z
D
OUT
DIN
High – Z
D
IN
High – Z
High – Z
D
OUT
D
OUT
High – Z
D
IN
DIN
SUPPLY CURREN
Standby
SB1
, I
SB
SB1
ICC,I
CC1,ICC2
I
CC,ICC1,ICC2
I
CC,ICC1,ICC2
UTRON TECHNOLOGY INC. P80073
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
Preliminary Rev. 1.0
ABSOLUTE MAXIMUM RATINGS
64K X 16 BIT LOW POWER CMOS SRAM
*
UT62L6416
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
Operating Temperature
Commercial T
Extended T
Storage Temperature T
-0.5 to 4.6 V
TERM
A
A
-65 to +150
STG
0 to 70
-20 to 80
℃
℃
℃
Power Dissipation PD 1 W
DC Output Current I
Soldering Temperature (under 10 secs) Tsolder 260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
50 mA
OUT
℃
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V~3.6V, TA = 0℃ to 70℃ / -20℃ to 80℃(E))
PARAMETER
SYMBOL
Power Voltage VCC 2.7 3.0 3.6 V
Input High Voltage VIH 2.2 - VCC+0.3 V
Input Low Voltage VIL -0.2 - 0.6 V
Input Leakage Current ILI
Output Leakage Current ILO
Output High Voltage VOH IOH= -1mA 2.2 - - V
Output Low Voltage VOL IOL= 2 mA - - 0.4 V
Operating Power
ICC Cycle time=min, 100%duty,
Supply Current
Icc1
Current
Icc2
Standby Current (TTL) ISB
Standby Current (CMOS) -L - 20 80
I
SB
TEST CONDITION MIN. TYP. MAX. UNIT
V
≦VIN ≦VCC
SS
V
≦V
SS
I/O
≦V
Output Disabled
CC;
- 1 - 1
- 1 - 1
55 - 30 45 mA
I/O=0mA,
CE
=V
;
IL
70 - 25 35 mA
100 - 20 25 mA
Cycle time=1µs,100%duty,I/O=0mA,
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
CE
Cycle time=500ns,100%duty,I/O=0mA,
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
CE
=V
1
1.
2.
1.
CE
UB
CE
other pins =VIL or VIH,
IH,
=
= V
other pins =VIL or VIH,
IH,
-0.2V,
=V
LB
CC
4 5 mA Average Operation
-
8 10 mA
-
- 0.3 0.5 mA
other pins at 0.2V or Vcc-0.2V,
2.
UB
=
=VCC-0.2V,
LB
-LL - 3 25
other pins at 0.2V or Vcc-0.2V,
A
µ
A
µ
A
µ
A
µ
UTRON TECHNOLOGY INC. P80073
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
UTRON
Preliminary Rev. 1.0
CAPACITANCE
(TA=25℃, f=1.0MHz)
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
Input/Output Capacitance C
Note : These parameters are guaranteed by device characterization, but not production tested.
IN
I/O
-
-
6 pF
8 pF
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA / 2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER SYMBOL UT62L6416-55 UT62L6416-70 UT62L6416-100
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
,UB
LB
LB
LB
Access Time
,UB
to High-Z Output
,UB
to Low-Z Output
(2) WRITE CYCLE
PARAMETER SYMBOL UT62L6416-55 UT62L6416-70 UT62L6416-100
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
,UB
LB
*These parameters are guaranteed by device characterization, but not production tested.
*55ns for Vcc=3.0V~3.6V