UTRON UT62L5128SC-100LLI, UT62L5128SC-100LI, UT62L5128LS-70LLI, UT62L5128LS-70LI, UT62L5128LS-55LLI Datasheet

UTRON

UT62L5128(I)

Preliminary Rev. 0.7

512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

1



FEATURES



Access time : 55/70/100 ns



CMOS Low operating power
Operating : 45/35/25mA (max.)
Standby : 20µA (typ.) L-version

3µA (typ.) LL-version



Single 2.7V~3.6V power supply



Industrial Temperature : -40℃~85℃



All inputs and outputs TTL compatible



Fully static operation



Three state outputs



Data retention voltage : 1.5V (min)



Package : 32-pin 450 mil SOP

32-pin 8mm×20mm TSOP-I
32-pin 8mm×13.4mm STSOP

36-pin 6mm×8mm TFBGA

GENERAL DESCRIPTION

The UT62L5128 is a 4,194,304-bit low power
CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

The UT62L5128 operates from a wide range

2.7V~3.6V power supply and all inputs and
outputs are fully TTL compatible.

The UT62L5128 supports industrial operating
temperature range, and supports low data
retention voltage for battery back-up operation
with low data retention current.

FUNCTIONAL BLOCK DIAGRAM

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

512K ×8

MEMORY

ARRAY

COLUMN I/O

OE

WE

A0-A18

Vcc
Vss

I/O1-I/O8

CE

UTRON

UT62L5128(I)

Preliminary Rev. 0.7

512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

2



PIN CONFIGURATION

SOP

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

A17

A8

A9

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

1716

15

20

19

18

22

23

24

25

26

27

21

A13

A14

A18

A16

Vcc

A15

29

30

31

32

OE

CE

WE

I/O4

A11

A9
A8

A13

I/O3

A10

A14
A12

A7
A6
A5

Vcc

I/O8

I/O7
I/O6
I/O5

Vss

I/O2
I/O1

A0
A1

A2

A4 A3

TSOP-1 / STSOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20
19
18

22

23

24

25

26

27

21

WE

OE

CE

A17

A18

A15

32
31
30
29

A16

OE CE

WE

A12A11 A13

NC

A17

A10 A14

A15

I/O6

I/O7

I/O8

A9

Vss

A8

A16

I/O5

Vcc

Vcc

I/O4

A18

Vss

A7

A0

I/O3

I/O2

I/O1

A6A1 A3

A5NC

A4A2

123456

H

G

C

D

E

F

A

B

TFBGA

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A18 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs

CE

Chip Enable Input

WE

Write Enable Input

OE

Output Enable Input

Vcc Power Supply
Vss Ground
NC No Connection

UTRON

UT62L5128(I)

Preliminary Rev. 0.7

512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



ABSOLUTE MAXIMUM RATINGS

*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS V

TERM

-0.5 to 4.6 V

Operating Temperature

Industrial T

A

-40 to 85

℃

Storage Temperature T

STG

-65 to 150

℃

Power Dissipation PD 1 W
DC Output Current I

OUT

50 mA

Soldering Temperature (under 10 secs) Tsolder 260

℃

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

WE

CE

OE

I/O OPERATION SUPPLY CURRENT

Standby X H X High – Z ISB, I

SB1

Output Disable H L H High – Z I

CC , ICC1, ICC2

Read H L L D

OUT

I

CC , ICC1, ICC2

Write L L X DIN I

CC , ICC1, ICC2

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V~3.6V, TA = -40℃ to 85℃)

PARAMETER

SYMBOL

TEST CONDITION MIN. TYP. MAX. UNIT

Power Voltage VCC 2.7 3.0 3.6 V
Input High Voltage VIH 2.0 - VCC+0.3 V
Input Low Voltage VIL -0.2 - 0.6 V
Input Leakage Current

I

LI

V

SS

≦VIN ≦VCC

- 1 - 1

µ

A

Output Leakage Current

I

LO

V

SS

≦V

I/O

≦V

CC;

Output Disabled

- 1 - 1

µ

A
Output High Voltage VOH IOH= -1mA 2.2 - - V
Output Low Voltage VOL IOL= 2.1mA - - 0.4 V

55 - 30 45 mA
70 - 25 35 mA

Operating Power
Supply Current

I

CC

Cycle time=min, 100%duty,
I

I/O

=0mA,

CE

=V

IL

;

100 - 20 25 mA

I

CC1

Cycle time=1µs,100%duty,I

I/O

=0mA,

CE

≦

0.2V,other pins at 0.2V or Vcc-0.2V,

- 4 5 mA

Average Operation
Current

I

CC2

Cycle time=500ns,100%duty,I

I/O

=0mA,

CE

≦

0.2V,other pins at 0.2V or Vcc-0.2V,

- 8 10 mA

Standby Current (TTL) ISB

CE

=V

IH,

other pins = VIH or VIL ;

- 0.3 0.5 mA

-L - 20 80

µ

A

Standby Current (CMOS) I

SB1

CE

=V

CC

-0.2V,

other pins at 0.2V or Vcc-0.2V,

-LL - 3 25

µ

A

UTRON

UT62L5128(I)

Preliminary Rev. 0.7

512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4



CAPACITANCE

(TA=25℃, f=1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C

IN

-

6 pF

Input/Output Capacitance C

I/O

-

8 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF+1TTL , IOH/IOL = -1mA / 2.1mA

AC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V~3.6V , TA = -40℃ to 85℃)

(1) READ CYCLE

UT62L5128-55 UT62L5128-70 UT62L5128-100

PARAMETER SYMBOL

MIN. MAX. MIN. MAX. MIN. MAX.

UNIT

Read Cycle Time

tRC 55 - 70 - 100 - ns

Address Access Time

tAA - 55 - 70 - 100 ns

Chip Enable Access Time

t

ACE

- 55 - 70 - 100 ns

Output Enable Access Time

tOE - 30 - 35 - 50 ns

Chip Enable to Output in Low Z

t

CLZ*

10 - 10 - 10 - ns

Output Enable to Output in Low Z

t

OLZ*

5 - 5 - 5 - ns

Chip Disable to Output in High Z

t

CHZ*

- 20 - 25 - 30 ns

Output Disable to Output in High Z

t

OHZ*

- 20 - 25 - 30 ns

Output Hold from Address Change

tOH 10 - 10 - 10 - ns

(2) WRITE CYCLE

UT62L5128-55 UT62L5128-70 UT62L5128-100

PARAMETER SYMBOL

MIN. MAX. MIN. MAX. MIN. MAX.

UNIT

Write Cycle Time

tWC 55 - 70 - 100 - ns

Address Valid to End of Write

tAW 50 - 60 - 80 - ns

Chip Enable to End of Write

tCW 50 - 60 - 80 - ns

Address Set-up Time

tAS 0 - 0 - 0 - ns

Write Pulse Width

tWP 45 - 55 - 70 - ns

Write Recovery Time

tWR 0 - 0 - 0 - ns

Data to Write Time Overlap

tDW 25 - 30 - 40 - ns

Data Hold from End of Write Time

tDH 0 - 0 - 0 - ns

Output Active from End of Write

t

OW*

5 - 5 - 5 - ns

Write to Output in High Z

t

WHZ*

- 30 - 30 - 40 ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT62L5128(I)

Preliminary Rev. 0.7

512K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

5



TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2,4)

t

RC

Address

DOUT Data Valid

t

AA

t

OH

t

OH

READ CYCLE 2

(CE and

OE

Controlled)

(1,3,5,6)

t

RC

t

AA

t

ACE

t

OE

t

CHZ

t

OHZ

t

CLZ

t

OH

t

OLZ

HIGH-Z

Data Valid

HIGH-Z

Address

CE

OE

Dout

Notes :

1.

WE

is HIGH for read cycle.

2. Device is continuously selected

CE

=V

IL.

3. Address must be valid prior to or coincident with

CE

transition; otherwise t

AA

is the limiting parameter.

4.

OE

is LOW.

5. t

CLZ

, t

OLZ

, t

CHZ

and t

OHZ

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ

is less than t

CLZ

, t

OHZ

is less than t

OLZ.