UTRON UT6264CSC-70LL, UT6264CSC-70L, UT6264CSC-70, UT6264CSC-35LL, UT6264CSC-35L Datasheet
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Rev. 1.1
UTRON
FEATURES
Access time : 35/70ns (max.)
Low power consumption :
Operating : 45/30 mA (typ.)
CMOS Standby : 2mA (typ.) normal
2 µA (typ.) L-version
1 µA (typ.) LL-version
Single 4.5V~5.5V power supply
Operating temperature :
Commercial : 0℃~70℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
A0-A12
I/O1-I/O8
Vcc
Vss
DECODER
I/O DATA
CIRCUIT
8K ×8
MEMORY
ARRAY
COLUMN I/O
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
The UT6264C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input.(
,CE2) ,and supports low
1CE
data retention voltage for battery back-up
operation with low data retention current.
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully
TTL compatible.
PIN CONFIGURATION
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
UT6264C
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
CE2
A8
A9
A11
OE
A10
1CE
I/O8
I/O7
I/O6
I/O5
I/O4
CE1
CE2
WE
OE
CONTROL
CIRCUIT
PDIP/SOP
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A12 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
WE
OE
,CE2
1CE
VCC Power Supply
VSS Ground
NC No connection
GENERAL DESCRIPTION
UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
Rev. 1.1
UTRON
8K X 8 BIT LOW POWER CMOS SRAM
UT6264C
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
Operating Temperature Commercial TA 0 to +70
Storage Temperature T
Power Dissipation PD 1 W
DC Output Current I
Soldering Temperature (under 10 sec) Tsolder 260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
CE
CE2
1
OE
Standby H X X X High - Z ISB, ISB1
Standby X L X X High - Z ISB, ISB1
Output Disable L H H H High - Z Icc,Icc1,Icc2
Read L H L H
Write L H X L
note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V~5.5V, TA = 0℃ to 70℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Power Voltage Vcc 4.5 5.0 5.5 V
Input High Voltage V
Input Low Voltage V
Input Leakage Current
Output Leakage Current I
Output High Voltage V
Output Low Voltage V
2.2 - VCC+0.5 V
IH
- 0.5 - 0.8 V
IL
≦
I
LI
V
SS
V
SS
LO
or
OE
IOH = - 1mA 2.4 - - V
OH
OL
I
CC
I
= 4mA
OL
Cycle time=Min,I
1CE
≦
V
IN
≦
≦
V
I/O
;
= V
IH
= V
CE2= VIH - 70 - 30 45 mA
IL ,
Cycle time=1us; I
Operating Power
Supply Current
Icc1
=0.2V; CE2=Vcc-0.2V;
1CE
other pins at 0.2V or Vcc-0.2V
Cycle time=500ns;I
Icc2
=0.2V; CE2=Vcc-0.2V;
1CE
other pins at 0.2V or Vcc-0.2V
= VIH or CE2= VIL
Standby Current (TTL)
Standby Current (CMOS) I
I
SB
SB1
1CE
1CE
or CE2
≧
VCC-0.2V ;
≦
0.2V;
other pins at 0.2V or Vcc-0.2V
-0.5 to +7.0 V
TERM
℃
-65 to +150
STG
50 mA
OUT
I/O OPERATION SUPPLY CURRENT
WE
VCC
V
CC;
or
WE
=V
1CE
= VIL
IH;
D
OUT
D
IN
or CE2=V
Icc,Icc1,Icc2
Icc,Icc1,Icc2
- 1 - 1
IL;
- 1 - 1
℃
℃
µ
µ
- - 0.4 V
0mA;
;
=
I/O
= 0mA
I/O
- 35 - 45 60 mA
- 20 30 mA
= 0mA;
I/O
- 10 15 mA
Normal - 1 10 mA
- L/- LL - 0.3 3 mA
Normal - 2 5 mA
- L - 2 100
- LL - 1 50
µ
µ
A
A
A
A
UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
Rev. 1.1
CAPACITANCE
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
Input/Output Capacitance C
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 100pF, IOH/IOL = -1mA/4mA
(TA=25℃, f=1.0MHz)
8K X 8 BIT LOW POWER CMOS SRAM
IN
I/O
-
-
10 pF
UT6264C
8 pF
AC ELECTRICAL CHARACTERISTICS
(V
= 4.5V~5.5V, TA = 0℃ to 70℃)
CC
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER SYMBOL
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
*These parameters are guaranteed by device characterization, but not production tested.
SYMBOL
tRC 35 - 70 - ns
tAA - 35 - 70 ns
t
ACE1, tACE2
tOE - 25 - 35 ns
t
CLZ1*, tCLZ2*
t
OLZ*
t
CHZ1*, tCHZ2*
t
OHZ*
tOH 5 - 5 - ns
tWC 35 - 70 - ns
tAW 30 - 60 - ns
t
CW1, tCW2
tAS 0 - 0 - ns
tWP 25 - 50 - ns
tWR 0 - 0 - ns
tDW 20 - 30 - ns
tDH 0 - 0 - ns
t
OW*
t
WHZ*
- 35 - 70 ns
5 - 5 - ns
- 25 - 35 ns
30 - 60 - ns
5 - 5 - ns
- 15 - 25 ns
UT6264C-35 UT6264C-70
MIN. MAX. MIN. MAX.
UNIT
10 - 10 - ns
- 25 - 35 ns
UT6264C-35 UT6264C-70
MIN. MAX. MIN. MAX.
UNIT
UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
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