UTRON UT6264BPC-70L, UT6264BPC-70LL, UT6264BPC-70, UT6264BSC-70LL, UT6264BSC-70L Datasheet
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A
A
A1 A
A
A
UTRON
Rev 1.0
____________________________________________________________________________________________
8K X 8 BIT LOW POWER CMOS SRAM
UT6264B
FEATURES
Access time : 35/70ns (max.)
Low power consumption:
Operating : 60/40 mA (typical)
Standby :0.3 mA (typical) normal
2 µA (typical) L-version
1 µA (typical) LL-version
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
A4
A3
12
A7
A6
A5
A8
A2
I/O1
.
.
.
I/O8
CE
WE
OE
DECODER
.
.
CONTROL
.
CONTROL
ROW
I/O
LOGI C
.
.
256 ROWS × 256 COLUMNS
.
.
.
.
COLUMN DECODER
10
MEMORY ARRAY
.
. .
COLUMN I/ O
11
9
0
The UT6264B is a 65,536-bit low power
CMOS static random access memory
organized as 8,192 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
The UT6264B is designed for high-speed
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.
The UT6264B operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible.
PIN CONFIGURATION
Vcc
28
27
WE
26
NC
25
A8
24
A9
23
A11
22
OE
21
A10
20
CE
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
VCC
VSS
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
UT6264B
5
6
7
8
9
10
11
12
13
14
PDIP / SOP
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 – A12 Address Inputs
I/O1 – I/O8 Data Inputs/Outputs
CE
WE
OE
Chip Enable Input
Write Enable Input
Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
GENERAL DESCRIPTION
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80039
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
L
UTRON
Rev 1.0
____________________________________________________________________________________________
8K X 8 BIT LOW POWER CMOS SRAM
UT6264B
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
Operating Temperature TA 0 to +70
Storage Temperature T
-0.5 to +7.0 V
TERM
-65 to +150
STG
℃
℃
Power Dissipation PD 1 W
DC Output Current I
Soldering Temperature (under 10 sec) Tsolder 260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended
period may affect device reliability.
50 mA
OUT
℃
TRUTH TABLE
MODE
CE
OE
Standby H X X High - Z
Output Disable L H H High - Z
Read L L H
Write L X L
Note: H = VIH, L=VIL, X = Don't care.
I/O OPERATION SUPPLY CURRENT
WE
I
SB, ISB1
D
OUT
D
IN
I
CC
I
CC
I
CC
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V±10%, TA = 0℃ to 70℃)
PARAMETER
Input High Voltage
Input Low Voltage V
Input Leakage Current I
Output Leakage Current I
Output High Voltage V
Output Low Voltage V
Supply Current
Standby Power
Supply Current
SYMBO
V
I
I
TEST CONDITION MIN. TYP. MAX. UNIT
2.2 - VCC+0.5 V
IH
- 0.5 - 0.8 V
IL
LI
LO
OH
OL
CC
SB
SB1
≦
V
SS
≦
V
SS
=V
CE
I
= - 1mA 2.4 - - V
OH
I
= 4mA - - 0.4 V
OL
Cycle time=Min,
= V
CE
= V
CE
CE
≧
IH
V
V
IN
V
I/O
or
IL , II/O
IH
-0.2V
CC
≦
≦
OE
VCC
V
CC
=V
=
IH
0mA,
or
WE
Normal - 1 10 mA I
- L/- LL - - 3 mA
Normal - 0.3 5 mA
- 1 - 1 µA
- 1 - 1 µA
=V
IL
- 35 - 60 100 mA Operating Power
- 70 - 40 70 mA
- L - 2 100
A
µ
- LL - 1 50
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80039
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
A
µ
UTRON
Rev 1.0
_____________________________________________________________________________________________
CAPACITANCE
(T
8K X 8 BIT LOW POWER CMOS SRAM
=25℃, f=1.0MHz)
A
UT6264B
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
C
C
IN
I/O
-
-
8 pF
10 pF
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 100pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER SYMBOL UT6264B-35 UT6264B-70 UNIT
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
*These parameters are guaranteed by device characterization, but not production tested.
SYMBOL UT6264B-35 UT6264B-70 UNIT
tRC 35 - 70 - ns
tAA - 35 - 70 ns
t
ACE
tOE - 25 - 35 ns
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
tOH 5 - 5 - ns
tWC 35 - 70 - ns
tAW 30 - 60 - ns
tCW 30 - 60 - ns
tAS 0 - 0 - ns
tWP 25 - 50 - ns
tWR 0 - 0 - ns
tDW 20 - 30 - ns
tDH 0 - 0 - ns
t
OW*
t
WHZ*
(VCC = 5V±10% , TA = 0℃ to 70℃)
MIN. MAX. MIN. MAX.
- 35 - 70 ns
10 - 10 - ns
5 - 5 - ns
- 25 - 35 ns
- 25 - 35 ns
MIN. MAX. MIN. MAX.
5 - 5 - ns
- 15 - 25 ns
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80039
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
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