UTRON UT62257CPC-70L, UT62257CLS-70LL, UT62257CPC-70, UT62257CLS-70L, UT62257CLS-35LL Datasheet

UTRON

UT62257C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

1



FEATURES



Access time : 35/70ns (max.)



Low power consumption:

Operating : 40 mA (typical.)

Standby : 3mA (typical) normal

2uA (typical) L-version
1uA (typical) LL-version



Single 5V power supply



All inputs and outputs are TTL compatible



Fully static operation



Three state outputs



Data retention voltage : 2V (min.)



Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

COLUMN I/O

COLUMN DECODER

ROW

DECODER

I/O

CONTROL

LOGIC

CONTROL

A4

I/O1

VSS

VCC

WE

CE2

1CE

I/O8

.

.

.

.

.
.

. .

.

A3

A

14

A

13

A

12

A7

A6

A5

A8

A9 A2 A1 A0 A

10

.

.

.

.

.

.

MEMORY ARRAY

512 ROWS × 512 COLUMNS

A

11

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A14 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs

1CE

、

CE2

Chip Enable Inputs

WE

Write Enable Input

VCC Power Supply
VSS Ground

GENERAL DESCRIPTION

The UT62257C is a 262,144-bit low power CMOS
static random access memory organized as
32,768 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

The UT62257C is designed for high-speed and
low power application. With 2 chip controls

(

1CE

、

CE2 ), it is easy to design memory systems
with POWER-DOWN and capacity expansion in
the application circuits. It is particularly well suited

for battery back-up nonvolatile memory
application.

The UT62257C operates from a single 5V
power supply and all inputs and outputs are fully
TTL compatible.

PIN CONFIGURATION

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

Vcc

A8

A9

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT62257C

PDIP/SOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

1CE

WE

A13

A14

CE2

I/O4

A11

A9

A8

A13

I/O3

A10

A14

A12

A7

A6

A5

Vcc

I/O8

I/O7

I/O6

I/O5

Vss

I/O2

I/O1

A0

A1

A2

A4

A3

UT62257C

STSOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

WE

1CE

CE2

UTRON

UT62257C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

2



ABSOLUTE MAXIMUM RATINGS

*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS V

TERM

-0.5 to +7.0 V

Operating Temperature TA 0 to +70

℃

Storage Temperature T

STG

-65 to +150

℃

Power Dissipation PD 1 W
DC Output Current I

OUT

50 mA

Soldering Temperature (under 10 sec) Tsolder 260

℃

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.

TRUTH TABLE

MODE

1

CE

CE2

WE

I/O OPERATION SUPPLY CURRENT

H X X High - Z ISB, I

SB1

Standby

X L X High - Z I

SB

, I

SB1

Read L H H D

OUT

I

CC

, ICC1, ICC2

Write L H L DIN I

CC

, ICC1, ICC2

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

(VCC = 5V±10%, TA = 0℃ to 70℃)

PARAMETER

SYMBOL

TEST CONDITION MIN. TYP. MAX. UNIT

Input High Voltage VIH 2.2 - VCC+0.5 V
Input Low Voltage VIL - 0.5 - 0.8 V
Input Leakage Current ILI

V

SS

≦VIN ≦VCC

- 1 - 1

µ

A

Output Leakage

Current

ILO

V

SS

≦V

I/O

≦V

CC

1CE

=V

IH

or CE2 = VIL

- 1 - 1

µ

A

Output High Voltage VOH IOH= - 1mA 2.4 - - V
Output Low Voltage VOL IOL= 4mA - - 0.4 V

- 35 - 40 50 mA ICC Cycle time=Min., I

I/O

= 0mA ,

1CE

= V

IL

, CE2 = VIH

- 70 - 30 40 mA

ICC1 Cycle time=1µs,100%duty,I

I/O

=0mA,

1CE

= 0.2V ; CE2 = V

CC

-0.2V ,

other pins at 0.2V or V

CC

-0.2V

- - 10 mA

Operating Power

Supply Current

I

CC

2 Cycletime=500ns,100%duty,I

I/O

=0mA,

1CE

= 0.2V ; CE2 = V

CC

-0.2V ,

other pins at 0.2V or V

CC

-0.2V

- - 20 mA

ISB

1CE

=V

IH

or CE2 = VIL

1 10 mA

I

SB1

1CE

≧

V

CC

-0.2V

CE2≧V

CC

-0.2V

normal -

0.3 5 mA

ISB

1CE

=V

IH

or CE2 = V

IL

-L/-LL - - 3 mA

I

SB1

1CE

≧

V

CC

-0.2V

-L - 2 100

µ

A

Standby Power
Supply Current

CE2≧V

CC

-0.2V

-LL - 1 40

µ

A

UTRON

UT62257C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



CAPACITANCE

(TA=25℃, f=1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance CIN - 8 pF
Input/Output Capacitance C

I/O

- 10 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 100pF, IOH/IOL = -1mA/4mA

AC ELECTRICAL CHARACTERISTICS

(VCC = 5V±10% , TA = 0℃ to 70℃)

(1) READ CYCLE
PARAMETER SYMBOL UT62257C-35 UT62257C-70 UNIT

MIN. MAX. MIN. MAX.
Read Cycle Time tRC 35 - 70 - ns
Address Access Time tAA - 35 - 70 ns
Chip Enable Access Time t

ACE

- 35 - 70 ns
Output Enable Access Time tOE - 25 - 35 ns
Chip Enable to Output in Low Z t

CLZ*

10 - 10 - ns

Output Enable to Output in Low Z t

OLZ*

5 - 5 - ns

Chip Disable to Output in High Z t

CHZ*

- 25 - 35 ns

Output Disable to Output in High Z t

OHZ*

- 25 - 35 ns

Output Hold from Address Change tOH 5 - 5 - ns

(2) WRITE CYCLE
PARAMETER SYMBOL UT62257C-35 UT62257C-70 UNIT

MIN. MAX. MIN. MAX.
Write Cycle Time tWC 35 - 70 - ns
Address Valid to End of Write tAW 30 - 60 - ns
Chip Enable to End of Write tCW 30 - 60 - ns
Address Set-up Time tAS 0 - 0 - ns
Write Pulse Width tWP 25 - 50 - ns
Write Recovery Time tWR 0 - 0 - ns
Data to Write Time Overlap tDW 20 - 30 - ns
Data Hold from End of Write Time tDH 0 - 0 - ns
Output Active from End of Write t

OW*

5 - 5 - ns

Write to Output in High Z t

WHZ*

- 15 - 25 ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT62257C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4



TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

t

RC

Address

DOUT Data Valid

t

AA

t

OH

t

OH

READ CYCLE 2 (

1CE

and CE2 Controlled) (1,3,5,6)

t

RC

t

AA

t

ACE1

t

ACE2

t

CHZ1

t

CHZ2

t

CLZ1

t

CLZ2

t

OH

HIGH-Z

Data Valid

HIGH-Z

Address

CE1

CE2

Dout

Notes :

1.

WE

is HIGH for read cycle.

2. Device is continuously selected

1CE

=VIL., CE2= V

IH

3. Address must be valid prior to or coincident with

1CE

,CE2 transition; otherwise tAA is the limiting parameter.

5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.