UTRON UT621024SC-70LL, UT621024SC-70L, UT621024SC-55LL, UT621024SC-55L, UT621024SC-35LL Datasheet



A

Rev. 1.5

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

FEATURES

Access time : 35/55/70ns (max.)



Low power consumption :



Operating : 60/50/40 mA (typical) Standby : 2µA (typical) L-version 1µA (typical) LL-version

Single 5V power supply

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All inputs and outputs TTL compatible

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Fully static operation

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Three state outputs

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Data retention voltage : 2V (min.)

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Package : 32-pin 600 mil PDIP

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32-pin 450 mil SOP 32-pin 8mmx20mm TSOP-1 32-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

A16

A15

A13

A14

A12

7

A6

A5

A4

A8

I/O1

.

I/O8

CE2

WE

OE

1CE

.

DECODER

CONTROL

ROW

I/O

LOGI C

.

MEMORY ARRAY

.

1024 ROWS × 1024 COLUMNS

.

. . .

COLUMN I/ O

COLUMN DECODER

10

11

. .

9

3

VCC

VSS

2 A1 A0

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A16 Address Inputs I/O1 - I/O8 Data Inputs/Outputs

Chip enable 1,2 Inputs

Write Enable Input

Output Enable Input

WE

OE

,CE2

1CE

VCC Power Supply VSS Ground NC No Connection

UT621024

GENERAL DESCRIPTION

The UT621024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT621024 is designed for low power application. It is particularly well suited for battery back-up nonvolatile memory application.

The UT621024 operates from a single 5V power supply and all inputs and outputs are fully TTL compatible.

PIN CONFIGURATION

NC

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

1

2

3

4

UT621024

5

6

7

8

9

10

11

12

13

14

15

PDIP / SOP

A11

A9

A8

A13

WE

CE2

A15

Vcc

NC

A16

A14

A12

A7

A6

A5

A4 A3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

UT621024

TSOP-I/STSOP

Vcc

32

A15

31

CE2

30

29

WE

28

A13

A8

27

A9

26

A11

25

OE

24

A10

23

22

21

20

19

18

1716

1CE

I/O8

I/O7

I/O6

I/O5

I/O4

32

OE

A10

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

1CE

A0

A1

A2

________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

1



t

Rev. 1.5

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT621024

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to Vss V Operating Temperature TA 0 to +70

Storage Temperature T Power Dissipation PD 1 W

DC Output Current I Soldering Temperature (under 10 sec) T

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

1CE

CE2

Standby H X X X High - Z Standby X L X X High -Z Output Disable L H H H High - Z

Read L H L H Write L H X L

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION

Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Curren

Output High Voltage Output Low Voltage Average Operating

I

V

I

V V

V

I

CC

IL

OL

OH

OL

IH

IL

Power Supply Courrent

I

CC1

Standby Power

Supply Current

*Those parameters are for reference only under 50℃

I

SB

I

SB1

*

-0.5 to +7.0 V

TERM

℃

OE

-65 to +150

STG

50 mA

OUT

260

solder

I/O OPERATION SUPPLY CURRENT

WE

D

OUT

D

IN

,

I

SB

SB1

,

I

SB

SB1

I

CC

I

CC

I

CC

℃

(VCC = 5V±10%, TA = 0℃ to 70℃)

MIN. TYP. MAX.

VSS ≦VIN ≦VCC

≦

VSS ≦V

=V

1CE

= V

OE

V

I/O

CC

or CE2 = VIL or

IH

or

WE

IH

= V

2.2 - V

- 0.5 - 0.8 V

- 1 - 1

IL

CC

IOH = - 1mA 2.4 - - V IOL= 4mA - - 0.4 V Cycle time=min, 100% duty,

=V

I

I/O

, CE2 = VIH,

1CE

IL

= 0mA

Cycle time=1µs,100% duty,I

≦

.

0.2V,CE2≧V

1CE

other pins at 0.2V or V

=V

1CE

or CE2 = V

IH

-0.2V,

CC

IL

-0.2V,

=0mA

I/O

-

-35

-55

-70

60

-

50

-

40

100

- - 10 mA

- - 3 mA

other pins at 0.2V or VCC-0.2V,

≧

V

1CE

-0.2V or

CC

.CE2≦0.2V

other pins at 0.2V or V

-0.2V,

CC

- L - 2

-

- 1

LL

100

40* µ

15*

UNIT

+0.5 V

µ

mA 85 70

50

mA

µ

A

________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

2



Rev. 1.5

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT621024

CAPACITANCE

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance Input/Output Capacitance

Note : These parameters are guaranteed by device characterization, but not production tested.

(TA=25℃, f=1.0MHz)

C

IN

I/O

-

8 pF 10 pF

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Load CL=100pF, IOH/IOL=-1mA/4mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE PARAMETER

Read Cycle Time tRC 35 - 55 - 70 - ns Address Access Time tAA - 35 - 55 - 70 ns Chip Enable Access Time t Output Enable Access Time tOE - 25 - 30 - 35 ns Chip Enable to Output in Low-Z t Output Enable to Output in Low-Z t Chip Disable to Output in High-Z t Output Disable to Output in High-Z t Output Hold from Address Change tOH 5 - 5 - 5 - ns

(2) WRITE CYCLE PARAMETER SYMBOL UT621024-

Write Cycle Time tWC 35 - 55 - 70 - ns Address Valid to End of Write tAW 30 - 50 - 60 - ns Chip Enable to End of Write t Address Set-up Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 25 - 40 - 45 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Data to Write Time Overlap tDW 20 - 25 - 30 - ns Data Hold from End of Write-Time tDH 0 - 0 - 0 - ns Output Active from End of Write tOW* 5 - 5 - 5 - ns Write to Output in High-Z t

*These parameters are guaranteed by device characterization, but not production tested.

SYMBOL UT621024-35 UT621024-55 UT621024-70 UNIT

, t

ACE1

*, t

CLZ1

* 5 - 5 - 5 - ns

OLZ

*, t

CHZ1

* - 25 - 30 - 35 ns

OHZ

, t

CW1

* - 15 - 20 - 25 ns

WHZ

(VCC = 5V±10% , TA = 0℃ to 70℃)

MIN. MAX. MIN. MAX. MIN. MAX.

- 35 - 55 - 70 ns

ACE2

* 10 - 10 - 10 - ns

CLZ2

* - 25 - 30 - 35 ns

CHZ2

35 MIN.

30 - 50 - 60 - ns

CW2

MAX. MIN.

UT621024-55

MAX. MIN. MAX.

UT621024-70 UNIT

_________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

3



t

A

Rev. 1.5

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled)

Address

DOUT Data Valid

READ CYCLE 2 (

ddress

1CE

CE2

OE

D

OUT

Notes :

1.

2. Device is continuously selected

3. Address must be valid prior to or coincident with

4.

5. t

6. At any given temperature and voltage condition, t

is HIGH for read cycle.

WE

is low.

OE

, t

CLZ2

, t

OLZ

CLZ1

High

, t

CLZ1

tCLZ2

-Z

CHZ1

1CE

, t

t

AA

t

OH

, CE2 and

t

AA

tACE1

tACE2

tOLZ

CE

and t

CHZ2

OHZ

(1,2,4)

t

RC

Controlled)

OE

t

RC

tOE

(1,3,5,6)

tCHZ1 tCHZ2

CLZ1

, t

CHZ2

is less than t

Data Valid

=V

and CE2=V

IL

1

are specified with CL=5pF. Transition is measured ±500mV from steady state.

IH.

and CE2 transition; otherwise t

1

CE

is less than t

CHZ1

UT621024

t

OH

tOHZ

tOH

is the limiting parameter.

AA

CLZ2

, t

OHZ

High-Z

is less than t

OLZ.

_________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

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