UNIWILL 258SA0 Service Manual

Chapter 1 General System Description

UNIWILL COMPUTER CORP.

No. 24 Pei Yuan Road
Chung Li Industrial Park, Chung Li City
Tao Yuan, Taiwan,
R.O.C.
TEL: [phone]
FAX: [phone]
URL: http:// www.uniwill.com.tw/

755IA5 Rev : A Page 1 - 15

Chapter 1 General System Description

1.1. Hardware / Software Specifications……………………………………….

755IA5 Rev : A Page 2 - 15

Chapter 1 General System Description

HARDWARE &SOFTWARE SPECIFICATION:

1. CPU

A. D/T INTEL P4 PROCESSOR

The Intel Pentium® 4 Processor with 512-KB L2 cache on 0.13 micron process utilizes
Flip Chip Pin Gray Array (FC-PGA2) package technology, and plugs into a 478-pin surface
mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Pentium 4
Processor with 512-KB L2 cache on 0.13 micron process, like its predecessor, the P4 processor
in the 478 pin package, is based on the same Intel 32-bit microarchitecture and maintains the
tradition of compatibility with 1A-32 software.

Hyper-Threading Technology is a new feature in the Intel P4 processor at 800MHz system
bus and 3.06GHz/533 MHz system bus with 512-KB L2 cache on 0.13 micron process. HT
Technology allows a single, physical P4 processor to function as two logical processors. Intel
recommend enabling HT Technology with Microsoft Windows XP Professional or Windows
XP Home, and disabling HT Technology via the BISO for all previous versions of Windows
operating system.

The Intel NetBurst microarchitecture features include hyper pipeline technology, a rapid
execution engine, a 400MHz, 533MHz, or 800MHz system bus, and an execution trace cache.
The Hyper pipeline technology doubles the pipeline depth in the P4 processor to run at twice
the core frequencies. The rapid execution engine allows the two integer ALUs in the processor
to run at twice the core frequency , which allow many integer instructions to execute in 1/2 clock
tick. The 400MHz, 533MHz, or 800MHz system bus is a quad-pumped bus running off a
100MHz or a 133MHz system clock, making 3.2Gbytes/sec, 4.3Gbytes/sec, or 6.4Gbytes/sec
data transfer rates possible.

B. MOBILE INTEL PROCESSOR

Flip-Chip Pin Grid Array (Micro-FCPGA) package with Integrated Heat Spreader, and plugs
into a surface mount, Zero Insertion Force (ZIF) socket. The Mobile Intel Pentium 4 processor
maintains full compatibility with IA-32 software.

The Intel NetBurst micro-architecture features include hyper-pipelined technology, a rapid
execution engine, a 533MHz system bus, and execution trace cache. The hyper piplined
technology doubles the pipeline depth in the Mobile Intel Pentium 4 Processor allowing the
processor to reach much higher core frequency, which allows many integer instructions to
execute in 1/2 clock tick. The 533MHz system bus is a quad-pumped bus running off a
133MHz system clock making 4.3Gbytes/sec data transfer rates possible.

The processor, when used in conjunction with the requisite Intel SpeedStep technology

The Mobile Intel Pentium 4 processor with 533MHz utilizes a 478-pin, Micro

755IA5 Rev : A Page 3 - 15

Chapter 1 General System Description

applet or its equivalent, support Enhanced Intel SpeedStep technology, which enables real-time
dynamic switching of the voltage and frequency between two performance modes. This occurs
by switching the bus ratios, core operating voltage, and core processor speeds without resetting
the system. The processor features the Auto Halt, Stop Grant, Deep Sleep, and Deeper Sleep
low power states. The processor system bus uses a variant of GTL+ signaling technology called
Assisted Gunning Transceiver Logic (AGTL+) signal technology.

2. SIS648FX HMAC

performance host interface for Intel Pentium 4 processor, a high performance memory
controller, an AGP interface, and SIS MuTIOL 1G Technology connecting w/ SIS963L
MuTIOL 1G Media IO.

The SIS648FX Host Interface features the AGTL&AGTL+ compliant bus driv er technology
with integrated on-die termination to support Intel Pentium 4 series processors with PSB 400
MHz/ 533MHz/ 800MHz. It provides a 12-level In-Order-Queue to support maximum
outstanding transactions on host bus up to 12.

The Memory Controller supporting DDR only. It can offer bandwidth up to 3.2GB/s under
DDR333 in order to sustain the bandwidth demand from host processor , as well as the multi I/O
master and AGP masters. The memory Controller mainly comprises the Memory Arbiter, the
M-data/M-Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a
plenty of memory access Host Controller, and I/O bus master based on a default optimized
priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid
to offering privileged server to 1) the isochronous downstream transfer to guarantee the min.
latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the
maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data
queue, any command compliant to the paging mechanism is generated and push into the
M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing
requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utm ost by
scheduling the command requests in the background when the data requests streamlines in the
foreground. The memory controller also supports the Suspend to RAM function by retaining
the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power.

3. ATI M10-P VGA CHIP(NO INTER GRATED MEMORY)

multimedia graphics performance for notebooks. Its architecture introduces the latest
achievements in the graphic industry, which enable the use of the progressive new features in
upcoming applications, but without compromising performance. ATI’s support of DirectXR9

features, highly optimized OpenGLR support, and flexible memory configurations allow

implementations targeted at the gaming enthusiast, consumer, business and workstation platforms.

The SIS648FX Host & Memory & AGP Controller integrates a high

The MOBILITY M10 provides the fastest and most advanced 2D, 3D, and

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Chapter 1 General System Description

4. CLOCK GENERATOR & DDR ZERO DELAY BUFFER
The Main clock ICS952005 is a chip clock solution for desktop design using SIS

648FX style chipsets. When used with a Zero Delay buffer such as the ICS93722 for DDR applications
it provides all the necessary clocks signals for such a system.

 Programmable output frequency, divider ratios, output rise/fall time, output skew.
 Programmable spread percentage for EMI control.
 Watchdog timer technology to reset system if system malfunctions.
 Support I2C index read/write and block read/write operations.
 Selectable asynchronous/synchronous AGP, ZCLK and PCI output.
 Support DDR333 OEM frequencies.

Uses external 14.318MHz crystal.

5. SYSTEM MEMORY

258SA Support PC 2100/2700 128MB/256MB/512MB/1GB DDR 266/333

SDRAM for Extending with 2 un-buffer Double-side DIMM DDR 266/333:

 Sustains DDR SDRAM CAS Latency at option of 2, 2.5, &3 clock.
 Support up to 2 un-buffer Double-sided DIMM DDR 266/333

DIMM1 DIMM2 TOTAL

128MB 0 128MB
256MB 0 256MB
512MB 0 512MB

6. SIS963 MUTIOL 1G MEDIAI/O

The SIS963 MuTIOL Media I/O integrates one Universal Series Bus 2.0 Host

Controller, the Audio Controller with AC97 Interface, the Ethernet MAC Controller w/ standard MII
interface, three Universal Serial Bus 1.1 Host Controller, the IDE Master/Slave controllers, and SiS MuTIOL
technology. The PCI to LPC bridge, I/O Advance Programmable Interrupt Controller and legacy power
management functionalities are integrated as well

A.

Ethernet MAC

B.

Universal Serial Bus 2.0 (USB2.0)

C.

IDE Interface

D.

IEEE 1394 Link Interface

SiS962 support 6 PCI master and complies with PCI2.2 specification. It also

incorporates the legacy system I/O like: two 8237A compatible DMA controllers, three 8254
compatible programmable 16-bit counters. hardwire keyboard controller and PS2 mouse
interface, Real Time clock with 512b CMOS SRAM and two 8259A compatible interrupt
controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB
interrupt delivery modes is supported

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Chapter 1 General System Description

7. MINI PCI(WIRELESS LAN)

Product Name: 11Mbps Wireless LAN Mini-PCI Card

Model Number: WL-350F
Host Interface: Mini PCI type III A
Operating Voltage: 3.3V+-5%
Frequency Band: 2.400~2.4835GHz (subject to regulation)
Standards: IEEE802.11b, Wi-Fi compliant

8. PCMCIA

The OZ711M1 is a single socket PC Card controller that also support Smart
Cards and flash media cards. The OZ711M1 is enhance with O
MultiMediaBay™ technology, enabling a single passive adapter that supports all four flash
media formats - SmartMedia™, Memory Stick™, MultiMediaCard (MMC) and SD Memory
Card.

The OZ711M1 also provides a secondary Optional Dedicated Reader (ODR) interface that
can support a Smart Card socket, a MMC/SD Card socket, or a Memory Stick socket. The
software drivers that support the optional dedicated reader are identical to those required for the
PC Card socket extensions for MultiMediaBay™.

The OZ711M1 provides a SmartMedia™ reader fully compliant with the SmartMedia™
Standard, Millennium Version, released in 2000 by the SSFDC forum. The reader supports the
unique identifier extension for SDMI, 3Vand 5V SmartMedia™ cards in any capacity from
1MB to 128MB including MASK ROM versions. The integrated MMC/SD Memory Card and
Memory Stick reader transfers data at an operating frequency of 16.5MHz and supports all
capacities of these media formats and Memory Stick cards.

9. BIOS

The 258SA using AMI system BIOS, and support PnP, APM 1.2 and ACPI 2.0
function. Both of System and VGA BIOS are flashed in a 4Mbit EEPROM, The Flash ROM in
the 32-pin PLCC package, there are three of suppliers for BIOS:

 EON (EN29LF040-70)
 AMIC (A29040L-70)
 Hyundai (HY29F040A-70)

2Micro’s patent pending

755IA5 Rev : A Page 6 - 15

Chapter 1 General System Description

10. IEEE1394 PHY

a two-port node in a cable based IEEE 1394-1995 and IEEE 1394a-2000 network. Each cable
port incorporates two differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection status, for initialization, and
for packet reception and transmission. The PHY is designed to interface with a link-layer
controller (LLC).

The PHY require an external 24.576MHz crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which generates the required 400MHz reference
signal. The 400MHz reference signal is internally divided to provide the 49.152MHz,

98.304MHz, and 196.608MHz clock signals that control transmission of the outbound encoded
strobe and data information.

When the PHY/link interface is in the disabled state, the FW802B will automatically enter a
low-power mode, if all ports are inactive (disconnected, disabled, or suspended). In this
low-power mode, the FW802B disable its PLL and also disable parts of reference circuitry
depending on the state of the ports (some reference circuitry must remain active in order to
detect incoming TP bias). The lowest power consumption (the microlow-power sleep mode) is
attained when all ports are either disconnected or disabled with the ports interrupt enable bit
cleared.

 Provides two fully compliant cable ports at 100Mbits/s, 200Mbits/s, and 400Mbits/s.

 Fully supports OHCI requirements.

 Support connection debounce.

 Support multispeed packet concatenation.

11. HARD DISK

33/66/100.

Vendor: Toshiba, Fujitsu, IBM
Capacity: Support 20/30 or above HDD
Thickness: 9.5mm/2.5”

Host Interface: Fast IDE Interface

12. OPTICAL DEVICE

Secondary Master:

1. COMBO (DVD/CD-RW)

2. DVD

3. CD-R or CD-R/W

4. CD-ROM

5. Second HDD

FW802B device provides the analog physical layer functions need to implement

The Primary Master HDD supporting PIO Mode 0,1,2,3,4 and Ultra DMA

The Secondary Master also supporting ATAPI CD-ROM Device as follow:

755IA5 Rev : A Page 7 - 15

Chapter 1 General System Description

13. KEYBOARD

Key Board Matrix: 258SA

Travel: 3.0±0.3mm
Contact Resistance: 500 ohm Maximum

Keycap pull off force: Function Key ≧800g; Normal Key ≧800g

Switch Life: 5 Million cycles

14. AUDIO SUBSYSTEM

designed for PC Multimedia systems, include host/soft audio and AMR/CNR based designs.
The ALC650 incorporates proprietary converter technology to achieve a high SNR, greater
than 90dB. The ALC650 AC’97 CODEC supports multiple CODEC extensions with
independent variable sampling rates and built-in 3D effects. The ALC650 CODEC provides
three pairs of outputs with independent volume controls, a mono output, and multiple stereo
and mono inputs, along with flexible mixing, gain and mute functions to provide a complete
integrated audio solution for PCs. The digital interface circuitry of the ALC650 CODEC
operates from a 3.3V power supply with EAPD (External Amplifier Power Down) control for
use in notebook and PC applications. The ALC650 integrates a 50mW/20 ohm headset audio
amplifier in to the CODEC, which can save BOM cost. The ALC 650 also supports an AC’97

2.2 compliant SPDIF out function which allows easy connection from the PC to consumer
electronic products, such as AC3 decoder/speaker and mini disk.

 High performance CODEC with high S/N ratio (>90dB)

 18-bit ADC and 20-bit DAC resolution

 Compliant with AC’97 2.2 specifications

 18-bit stereo full duplex CODEC with independent and variable sampling rate

 One stadard MIC input, and one dedicated Front-MIC input for front panel applications

 Digital SPDIF output

 Digital SPDIF input. (ALC650 Rev. E or later)

15. TOUCH PAD UNITE

button, special firmware that permits the Touch Pad to be initialized into 4-byte wheel Mouse
mode. In this mode the Touch Pad communicates with the PS/2 host as though it were a
Microsoft IntelliMouse. The Touch Pad also includes the standard Synaptics’ enhanced mode
of operation, 6-byte mode.

Scrolling is implemented in the firmware of this Touch Pad. When it is initialize into Wheel
Mouse mode the firmware will decode a finger gesture on the right hand edge of the Touch Pad
as intent to scroll.

The ALC650 is an 18-bit, full duplex AC’97 2.2 compatible stereo audio CODEC

software selectable)

The Synaptics T ouch Pad include two inputs for button switches: Left and Right

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Chapter 1 General System Description

16. LED INDICATOR

1. Two LED indicators on the right case:
SUSPEND LED: Green color for the system active at suspend mode
Power/Charge LED: Green color for system power on, orange color for battery

2. Fore LED indicator beside by power button:

3. HDD/CD-ROM, Num Lock, Caps Lock, Scroll Lock LED

17. MODEM

low-cost, solid-state interface to a telephone line. They eliminate the need for an analog front
end (AFE), and isolation transformer, relays, opto-isolator, and 2- to 4-wire hybrid. The
products dramatically reduce the number of discrete components and cost required to achieve
compliance with FCC Part 68. I800 and M800 comply with AC’97 / MC’97 interface
specification Rev. 2.1.

 Power Consumption: Less than 100mW
 Modem mode speed: 56Kb/p maximum
 Compatibility: Bell 103, Bell 212A, ITU-T V.21, V.32bis, V.34, V.90, V.92
 Transmission Way: Full Duplex
 Fax mode speed: 14.4Kbps

18. IR

provides interface between logic and IR signals for through-air, serial, half-duplex IR data link. The
module is compliant to IrDA Data Physical Layer Specification 1.1 and IEC825-Class 1 Eye Safe.

 Fully Compliant to IrDA 1.1 Physical Layer Specifications – 9.6kb/s to 4Mb/s operation
 Typical Link Distance > 1.5m
 Compatible with ASK, HP SIR, TV Remote
 Low power operation 2.7V to 3.6V
 Low shutdown current 10nA typical

19. HOT KEY DEFINITION.

Fn + F1 (SMI): Standby

Fn + F3 (SMI): Mute battery warning beep
Fn + F4 (SMI): Toggle LCD/CRT display
Fn + F5 (SMI): Volume increase
Fn + F6 (SMI): Volume decrease
Fn + F7 (SMI): Brightness more lightness

Fn + F8 (SMI): Brightness more darkness

There are two portion of LED indicators on 351S1.

charging.

I800 and M800 use Silicon based DAA chip set that provides a digital,

The HSDL-3600/3602 is a low-profile infrared transceiver module that

755IA5 Rev : A Page 9 - 15

Chapter 1 General System Description

20. SYSTEM INDICATOR(LED)

Caps Lock (on/off)

Num Lock (on/off)
Scroll Lock (on/off)
HDD/CDROM (on/off)
Power on (on/off)
Suspend (flash/off)
Power Switch (on/off)
LAN Switch (on/off)

Use Adaptor Power LED Suspend LED Use Battery Power LED Suspend LED

Power On Green Off Power On Green Off

Suspend Off Green Blinking Suspend Off Green Blinking

Power Off Off Off Power Off Off Off

Charging Orange Blinking X Charging X X

Discharging X X Discharging Green X

Low Battery X X Low Battery X

755IA5 Rev : A Page 10 - 15

Chapter 1 General System Description

755IA5 Rev : A Page 11 - 15

Chapter2 Major Components

UNIWILL COMPUTER CORP.

No. 24 Pei Yuan Road
Chung Li Industrial Park, Chung Li City
Tao Yuan, Taiwan,
R.O.C.
TEL: [phone]
FAX: [phone]
URL: http:// www.uniwill.com.tw/

N755IA5 Rev : A Page 1 - 31

Chapter2 Major Components

2.1. System Block Diagram …………………………………………………...

2.2. Major Component Definition.……..……………………………….……

2.3. Connector Definition…….………………………………………………..

N755IA5 Rev : A Page 2 - 31

3

4

35

Chapter2 Major Components

2.1 SYSTEM BLOCK DIAGRAM

DDRCLK0
DDRCLK1
DDRCLK2

AUDIO _CLK

AMPLIFIER

TI

TPA6011A4

L-SPKR R-SPKR

DDR 1

SPDIF
OUT

DDR RAM BUS

DDRCLK0#
DDRCLK1#

DDRCLK4

DDRCLK2#

DDRCLK5

AUDIO CODEC

RELTECK
ALC650

LINE INSPDIF

IN

MIC

DDR 2

MDC

RJ-11

DDRCLK3#DDRCLK3
DDRCLK4#
DDRCLK5#

AC Link

PCI BUS

CPUCLK
CPUCLK#

648CLK
648CLK#

648SDCLK

AGPCLK0
648ZCLK

FWDSDCLK

963ZCLK
963PCICLK
USB_48M

961REF1
961REF3

CPU

Intel

D/T & P4-M

Host BUS

North Bridge

SIS

648FX

HyperZip BUS

South Bridge

SIS

963

AGP BUS

RTC

THERMAL

ADM 1032

VRAM x8

VRAM BUS

ATI

M10P

64/128/256M VRAM

AGPCLK1

LAN(PHY)

REALTEK

RTL8201BL

CRYSTAL

25M HZ

CRYSTAL

32.768K

CRYSTAL

12M HZ

IDE BUS

CRT
S-Video TV

LCD

15.4" WXGA TFT

15.4" WSXGA TFT

RJ-45

HDD

2.5"

PRIMARY
MASTER

CD-ROM
DVD
CD-RW
COMBO

SECONDARY

MASTER

IEEE-1394 PHY

NS

PARALLEL

AGERE
FW802C

1394

BIOS LED

LPC BUS

CRYSTAL

32.768K

INT K/BFIR

USB0 USB1

K/B CONTROLLER

PCICLK_EC

T/P

PC87591L

FAN

USB2

NS

BATTERYCHARGER

DC/DC

CRYSTAL

14.318MHz

PCICLK_M

Mini PCI

SCLK

CARDBUS

O2 MICRE
OZ711M1

MMC/SD/MS

PCMCIA

READER

PCLK_CB

391_48M
LPC_CLK

CRYSTAL

24.576M HZ

LPC

PC87391

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Chapter2 Major Components

2.2 MAJOR COMPONENTS DEFINITION:
CPU1 HOST(U25A)

AC3

IERR

V6

MCERR

B6

FERR

Y4

STPCLK

AA3

BINIT

W5

INIT

AB2

RSP

H5

DBSY

H2

DRDY

J6

TRDY

G1

ADS

G4

LOCK

H6

BRO

G2

BNR

F3

HIT

E3

HITM

D2

BPR

E2

DEFER

D4

TCK

C1

TDI

F7

TMS

E6

TRST

D5

TDO

C3

PROCHOT

B2

IGNNE

B5

SMI

C6

A20M

AB26

SLP

AB23

PWRGOOD

AB25

RESET

AD24

TESTHI0

AA2

TESTHI1

AC21

TESTHI2

AC20

TESTHI3

AC24

TESTHI4

AC23

TESTHI5

AA20

TESTHI6

AB22

TESTHI7

U6

TESTHI8

W4

TESTHI9

Y3

TESTHI10

A6

TESTHI11/GHI#

AD25

TESTHI12/DPSLP#

AC6

BPM0

AB5

BPM1

AC4

BPM2

Y6

BPM3

AA5

BPM4

AB4

BPM5

K26

K25

J26

AC1

AF4

HA34

AB1

HA35

AF3

VCCVID

VCCVIDPRG

F1

G5

F4

K4

K2

RS0

RS1

RS2

HA3

L2

M6

L3

K1

L6

HA8

HA7

HA6

HA5

HA4

N2

M1

N1

M4

M3

HA9

HA13

HA12

HA11

HA10

P3

R2

T1

N5

N4

HA18

HA17

HA16

HA15

HA14

P6

U1

T2

R3

P4

HA23

HA22

HA21

HA20

HA19

W1

R6

V2

T4

U3

HA28

HA27

HA26

HA25

HA24

Y1

W2

V3

U4

T5

HA33

HA32

HA31

HA30

HA29

V5

AC26

ITP_CLK0

AD26

AP0

AP1

ITP_CLK1

DEP0

DEP1

L25

DEP2

DEP3

AE5

AE4

AE3

AE2

VID0

VID1

VID2

COMP0
COMP1

ADSTB0
ADSTB1

DBRESET

THERMDA
THERMDC

THERMTRIP

VCC_SENSE

VSS_SENSE

AE1

VID3

VID4

BCLK0
BCLK1

LINT0
LINT1

STBP0
STBP1
STBP2
STBP3

STBN0
STBN1
STBN2
STBN3

DB#0
DB#1
DB#2
DB#3

REQ0
REQ1
REQ2
REQ3
REQ4

BSEL0
BSEL1

U25A

AF22

AF23

L24

P1

D1

E5

L5

R5

AE25

F21

J23

P23

W23

E22

K22

R22

W22

E21

G25

P26

V21

J1

K5

J4

J3

H3

B3

C4

A2

AD6

AD5

A5

A4

HD0

HD1

HD2

HD3

HD4

HD5

HD6

HD7

HD8

HD9

HD10

HD11

HD12

HD13

HD14

HD15

HD16

HD17

HD18

HD19

HD20

HD21

HD22

HD23

HD24

HD25

HD26

HD27

HD28

HD29

HD30

HD31

HD32

HD33

HD34

HD35

HD36

HD37

HD38

HD39

HD40

HD41

HD42

HD43

HD44

HD45

HD46

HD47

HD48

HD49

HD50

HD51

HD52

HD53

HD54

HD55

HD56

HD57

HD58

HD59

HD60

HD61

HD62

HD63

B21

B22

A23

A25

C21

D22

B24

C23

C24

B25

G22

H21

C26

D23

J21

D25

H22

E24

G23

F23

F24

E25

F26

D26

L21

G26

H24

M21

L22

J24

K23

H25

M23

N22

P21

M24

N23

M26

N26

N25

R21

P24

R25

R24

T26

T25

T22

T23

U26

U24

U23

V25

U21

V22

V24

W26

Y26

W25

Y23

Y24

Y21

AA25

AA22

AA24

SOCKET478

N755IA5 Rev : A Page 4 - 31

Chapter2 Major Components

CPU2 POWER(U25B)

C25

C5

C7

C9

D10

D12

D14

D16

D18

D20

D21

D24

D3

D6

D8

E1

C22

E11

E13

E15

E17

E19

E23

E26

E4

E7

E9

F10

F12

F14

F16

F18

F2

F22

F25

F5

F8

G21

G24

G3

R23

R1

P5

P25

P22

R26

P2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A10

VCC

VSS

A12

VCC

VSS

A14

VCC

VSS

A16

A18

VCC

VCC

VSS

VSS

A20

A8

VCC

VCC

VSS

VSS

AA12

AA10

VCC

VSS

AA14

VCC

VCC

VSS

VSS

AA18

AA16

VCC

VSS

AA8

VCC

VCC

VSS

VSS

AB13

AB11

VCC

VSS

AB15

VCC

VCC

VSS

VSS

AB19

AB17

VCC

VSS

AB7

VCC

VCC

VSS

VSS

AB9

VCC

VSS

AC12

AC10

VCC

VCC

VSS

VSS

AC16

AC14

VCC

VSS

AC8

AC18

VCC

VCC

VSS

VSS

AD11

VCC

VCC

VSS

VSS

AD15

AD13

VCC

VSS

AD19

AD17

VCC

VCC

VSS

VSS

AD7

VCC

VSS

AD9

VCC

VCC

VSS

VSS

AE12

AE10

VCC

VSS

AE14

VCC

VCC

VSS

VSS

AE18

AE16

VCC

VSS

AE20

VCC

VCC

VSS

VSS

AE6

VCC

VSS

AE8

VCC

VSS

AF13

AF11

VCC

VSS

AF15

VCC

VCC

VSS

VSS

AF19

AF17

VCC

VSS

AF2

VCC

VCC

VSS

VSS

AF5

AF21

VCC

VSS

AF7

VCC

VCC

VSS

VSS

AF9

B11

VCC

VCC

VSS

VSS

B13

B15

VCC

VCC

VSS

VSS

B17

VCC

VSS

B19

B7

VCC

VCC

VSS

VSS

B9

C10

VCC

VCC

VSS

VSS

C12

VCC

VSS

C14

VCC

VSS

C16

C8

C20

C18

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS/IMPSEL

D11

VCC

VSS

D13

D15

VCC

VCC

VSS

VSS

D17

VCC

VSS

D19

VCC

VSS

D7

D9

VCC

VCC

VSS

VSS

E10

VCC

VSS

E12

VCC

VSS

E20

E18

E16

E14

VCC

VCC

VCC

VCC

SKTOCC#

VSS

VSS

VSS

E8

F11

VCC

VCC

VSS

VSS

F13

F15

VCC

VCC

VSS

VSS

F17

F19

VCC

VCC

VSS

VSS

F9

VCC

VSS

F6

F20

AA6

AA21

GTLREF0

GTLREF1

GTLREF2

VSS

VSS

VSS

VSS

U25B

VCCIOPLL

VCCA

GTLREF3

VSSA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS

AE23

AD20

AD22

Y5

Y25

Y22

Y2

W6

W3

W24

W21

V4

V26

V23

V1

U5

U25

U22

U2

T6

T3

T24

T21

R4

G6

J2

J22

J25

J5

K21

K24

K3

K6

L1

L23

L26

L4

M2

M22

M25

M5

N21

N24

N3

N6

C17

C15

C13

C11

B8

B4

B26

B23

B20

B18

B16

B14

B12

B10

AF8

AF6

AF26

AF20

AF18

AF16

AF14

AF12

AF10

AF1

AE9

AE7

AE26

AE24

AE22

AE19

AE17

AE15

AE13

AE11

AD8

AD4

AD23

AD21

AD18

AD16

AD14

AD12

AD10

AD1

AC9

AC7

AC5

AC25

AC22

AC2

AC19

AC17

AC15

AC13

AC11

AB8

AB6

AB3

AB24

AB21

AB20

AB18

AB16

AB14

AB12

AB10

AA9

AA7

AA4

AA26

AA23

AA19

AA17

AA15

AA13

AA11

AA1

A9

A3

A26

A24

A21

A19

A17

A15

A13

A11

H26

H23

H4

H1

N755IA5 Rev : A Page 5 - 31

C2

C19

SOCKET478

Chapter2 Major Components

CLOCK GENERATOR(U15)

U15

1

VDDREF

11

VDDZ

13

VDDPCI

19

VDDPCI

28

VDD48

29

VDDAGP

42

VDDCPU

48

VDDSD

5

VSSREF

8

VSSZ

18

VSSPCI

24

VSSPCI

25

VSS48

32

VSSAGP

41

VSSCPU

46

VSSSD

12

PCI_STOP#

45

CPU_STOP#

33

PD#/VTT_PWRGD

38

IREF

36

VDDA

CPUCLK0

CPUCLK#0

CPUCLK1

CPUCLK#1

SDCLK

AGPCLK0
AGPCLK1

ZCLK0
ZCLK1

PCICLK_F0/FS3
PCICLK_F1/FS4

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

REF0/FS0
REF1/FS1
REF2/FS2

24_48M/MULTISEL

48M

40

39

44

43

47

31

30

9

10

14

15

16

17

20

21

22

23

2

3

4

27

26

SCLK

37

ICS952005

VSSA

XIN

6

SDATA

XOUT

7

DDR BUFFER(U28)

U28

3

VDD

12

VDD

23

VDD

10

VDD

7

SCLK

22

SDATA

8

CLKIN

9

CLKIN#

20

FB_IN

21

FB_IN#

GND

GND

GND

FB_OUT

FB_OUT#

GND

CLK0
CLK1
CLK2
CLK3
CLK4
CLK5

CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5

35

34

2

4

13

17

24

26

1

5

14

16

25

27

19

18

6

11

15

ICS93722

28

N755IA5 Rev : A Page 6 - 31

Chapter2 Major Components

SIS648 HOST&AGP(U27A)

AJ31

AJ33

T33

T35

V32

B23

F22

R34

U31

R33

T32

U35

V35

R35

U34

W34

U33

V33

W35

Y33

W31

W33

Y35

AG31

AA33

AH33

AG33

AJ35

AF32

AJ34

AH32

AG35

AE31

AH35

AF35

AE35

AE33

AE34

AF33

AG34

AC33

AD32

AD33

AC35

AD35

AC31

AC34

AB35

AB32

AB33

AA35

AA31

Y32

AA34

U27A

CPUCLK
CPUCLK#

HLOCK#
DEFER#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#

RS#2
RS#1
RS#0

ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#

HREQ4#
HREQ3#
HREQ2#
HREQ1#
HREQ0#

HASTB1#
HASTB0#

HA31#
HA30#
HA29#
HA28#
HA27#
HA26#
HA25#
HA24#
HA23#
HA22#
HA21#
HA20#
HA19#
HA18#
HA17#
HA16#
HA15#
HA14#
HA13#
HA12#
HA11#
HA10#
HA9#
HA8#
HA7#
HA6#
HA5#
HA4#
HA3#

648

C24

HD63#

HD62#

E23

B24

AL36

AK34

C1XAVSS

C1XAVDD

HD61#

HD60#

HD59#

D23

D25

AJ36

AK35

C4XAVSS

HD58#

HD57#

F24

C26

B25

AA26

W26

U26

HVREF0

HVREF1

C4XAVDD

HD56#

HD55#

HD54#

HD53#

B26

D27

D26

E27

R26

L20

HVREF2

HVREF3

HVREF4

HD52#

HD51#

HD50#

B27

D28

C28

D22

C22

B22

HCOMP_P

HCOMP_N

HCOMPVREF_N

HD49#

HD48#

HD47#

HD46#

B28

E29

F28

B29

B6

F7

ST0

ST1

HD45#

HD44#

HD43#

C30

B30

B5

Y5

ST2

AAD0

HD42#

HD41#

B31

C32

W4

V2

AAD1

HD40#

D29

W6

AAD2

AAD3

HD39#

HD38#

C33

B33

V4

U2

AAD4

AAD5

HD37#

HD36#

B35

D32

V5

U4

AAD6

HD35#

B34

E31

R2

T4

AAD7

AAD8

AAD9

HD34#

HD33#

HD32#

D31

D33

R3

T5

AAD10

AAD11

HD31#

HD30#

D35

G31

P2

R4

AAD12

AAD13

HD29#

HD28#

C35

F33

N2

R6

AAD14

AAD15

HD27#

HD26#

E33

D34

L3

L4

AAD16

HD25#

E35

F32

K2

L6

AAD17

AAD18

HD24#

HD23#

J34

G34

J2

J3

AAD19

AAD20

AAD21

HD22#

HD21#

HD20#

H35

F35

K4

J4

AAD22

AAD23

HD19#

HD18#

J33

J31

J6

H4

AAD24

HD17#

G35

G3

H5

AAD25

AAD26

HD16#

HD15#

H33

J35

F2

G4

AAD27

AAD28

HD14#

HD13#

K32

N33

E2

G6

AAD29

AAD30

HD12#

HD11#

K33

L31

E3

AAD31

HD10#

HD9#

L33

K35

F4

SBA7

HD8#

L35

M35

D2

SBA6

SBA5

HD7#

HD6#

M33

F5

P32

E4

SBA4

SBA3

HD5#

HD4#

P33

B2

SBA2

HD3#

L34

E6

SBA1

HD2#

N34

B3

AC/BE3#

SBA0

AC/BE2#
AC/BE1#
AC/BE0#

AFRAME#

ADEVSEL#

AGP8XDET#

ADBIH/PIPE#

SB_STB#

AD_STB0

AD_STB0#

AD_STB1

AD_STB1#

AGPCOMP_P
AGPCOMP_N

A1XAVDD

A1XAVSS

A4XAVDD

A4XAVSS

AGPVREF

AGPVSSREF

HDSTBN3#
HDSTBN2#
HDSTBN1#
HDSTBN0#

HDSTBP3#
HDSTBP2#
HDSTBP1#
HDSTBP0#

HD1#

HD0#

DBI3#

N35

P35

F26

AREQ#
AGNT#

AIRDY#

ATRDY#
ASERR#

ASTOP#

APAR
RBF#

WBF#

ADBIL

SB_STB

AGPCLK

DBI2#

DBI1#

DBI0#

B32

E34

R31

K5

M5

P4

U6

C6

E8

N6

M4

N4

L2

P5

M2

N3

D7

B4

C7

C4

D6

C2

D3

T2

U3

G2

H2

D8

W2

Y2

B8

C8

A7

B7

W3

Y4

D24

F30

G33

N31

E25

D30

H32

M32

N755IA5 Rev : A Page 7 - 31

Chapter2 Major Components

SIS648 MEMORY FOR DDR(U27B)

U27B

AN35

MD0

AP36

MD1

AK33

MD2

AM33

MD3

AN34

MD4

AK32

MD5

AR34

MD6

AN33

MD7

AR35

DQM0

AP34

AM32

AL31

AR31

AL30

AN32

AR33

AN31

AM31

AR32

AP32

AP30

AR30

AM29

AL27

AN30

AN29

AL28

AN28

AL29

AR29

AP26

AN25

AR24

AL24

AL25

AR26

AM25

AN24

AP24

AR25

AN21

AP20

AN20

AL18

AM21

AR21

AL19

AM19

AL20

AR20

AL15

AL14

AN15

AR15

AN16

AM15

AN14

AL13

AP16

AR16

AM13

AL12

AL11

AR12

AP14

AR14

AN13

AP12

AN12

AR13

AL10

AR11

AM9

AR9

AM11

AN11

AP10

AN9

AN10

AR10

DQS0/CSB0#
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1/CSB1#
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2/CSB2#
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
DQS3/CSB3#
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4/CSB4#
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5/CSB5#
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6/CSB6#
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7/CSB7#

FWDSDCLKO

DDRCOMP_P

DDRCOMP_N

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8

MA9
MA10
MA11
MA12
MA13
MA14
MA15

SRAS#
SCAS#

SWE#

CS0#
CS1#
CS2#
CS3#
CS4#
CS5#

CKE0
CKE1
CKE2
CKE3
CKE4
CKE5

S3AUXSW#

SDRCLKI

DLLAVDD

DLLAVSS

DDRAVDD

DDRAVSS

DDRVREFA
DDRVREFB

DRAM_SEL

AR23

AN23

AN22

AM23

AL23

AL26

AN26

AN27

AR27

AR28

AP22

AN18

AR22

AP28

AM27

AL33

AL17

AR19

AN19

AM17

AL16

AN17

AR17

AP18

AR18

AP4

AT3

AR3

AP3

AR2

AN4

AP2

AL21

AL22

AL35

AL34

AM35

AN36

AF16

AF23

AP1

AR8

AP8

648

N755IA5 Rev : A Page 8 - 31

Chapter2 Major Components

SIS648 HYPERZIP (U27C)

U27C

AL6

AL4

AK5

AJ2

AE3

AJ3

AF2

AH5

AK2

AJ4

AJ6

AH2

AH4

AG3

AG6

AF4

AG2

AF5

AG4

AD2

AE6

AE2

AE4

AL3

AK4

AD5

AD4

AN1

AM2

AL2

AL1

ZCLK
ZUREQ

ZDREQ
ZSTB0

ZSTB1
ZSTB0#

ZSTB1#
ZAD0

ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16

ZVREF
ZCOMP_N

ZCOMP_P

Z1XAVDD
Z1XAVSS

Z4XAVDD
Z4XAVSS

648

PCIRST#

PWROK

AN2

AM4

AN3

AUXOK

TRAP1

F9

TRAP0

D10

TESTMODE2

TESTMODE1

TESTMODE0

C9

B9

B10

E10

DLLEN#

ENTEST

D9

NC

NC
NC
NC

NC
NC

NC
NC

NC

NC
NC
NC

NC
NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

B11

B12

B13

B14

B15

B16

C11

C13

C15

D11

D12

D13

D14

D15

D16

E12

E14

E16

F11

F13

F15

A11

A13

N755IA5 Rev : A Page 9 - 31

Chapter2 Major Components

SIS648 POWER(U27D)

L25

L26

M18

M19

M20

M21

M22

M23

M24

M25

M26

N25

P25

R25

T25

U25

V25

W25

Y25

AA25

AL7

AL8

AL9

AM6

AM7

AM8

AN5

AN6

AN7

AN8

AP5

AP6

AP7

AR4

AR5

AR6

AR7

AT4

AT5

AT6

AT7

AB25

AC25

AD12

AD25

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF11

AF12

AF25

AF26

AB24

AC13

AD14

AD16

AD18

AD20

AD22

P14

P15

P16

P17

P18

P19

P20

P21

P22

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

A17

A18

A19

A20

A21

B17

B18

B19

B20

B21

C17

C18

C19

C20

C21

D17

D18

D19

D20

D21

E17

E18

E19

E20

E21

F17

F18

F19

F20

F21

N13

N14

N16

N18

N19

N20

N21

N22

N23

N24

P13

P24

R24

T13

T24

U24

V13

V24

W13

W24

Y13

Y24

AA24

AB13

AC24

AD13

AD15

AD17

AD19

AD21

AD23

AD24

AD3

AE1

AF3

AG1

AH3

AJ1

AK3

AM3

W11

W12

Y11

Y12

AA12

N15

R13

U13

AA13

C10

L17

M17

N17

A9

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ

IVDD
IVDD
IVDD

IVDD
NC

NC
VDD3.3
VDD3.3
VDD3.3

AUX1.8

AB12

VTT

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

VDDM

AUX3.3

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQNCNCNCNCNCNCNCNCNCNCNCVSS

AC12

AA1

AA2

AA3

AA4

AA5

AA6

AB1

AB2

AB3

AB4

AB5

AB6

AC1

AC2

AC3

AC4

AC5

AC6

L11

L12

L13

M11

M12

M13

M14

M15

M16

N11

N12

P12

R12

T12

U12

V12

D4

D5

AM5

AM34

A15

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

C12

C14

C16

E11

E13

E15

A3

A5

C1

C3

C5

E1

E5

E7

E9

F3

G1

G5

H3

J1

J5

K3

L1

VDDM

VDDM

VSS

VSS

L5

M3

VDDM

VSS

N1

N5

VDDM

VDDM

VSS

VSS

P3

R1

VDDM

VDDM

VSS

VSS

R5

T3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

U1

U5

V3

W1

W5

Y3

AE5

AG5

AJ5

P23

VSS

VSS

U27D

AA32

W19

VSS

VSS

AA36

VSS

VSS

W20

AB34

W21

VSS

VSS

W22

VSS

W23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC32

AC36

AD34

AE32

AE36

AF34

AG32

AG36

AH34

AJ32

AM10

AM12

AM14

AM16

AM18

AM20

AM22

AM24

AM26

AM28

AM30

AP9

AP11

AP13

AP15

AP17

AP19

AP21

AP23

AP25

AP27

AP29

AP31

AP33

AP35

AT8

AT10

AT12

AT14

AT16

AT18

AT20

AT22

AT24

AT26

AT28

AT30

AT32

AT34

AL32

648

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

W14

W15

W16

W17

W18

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AL5

A22

A24

A26

A28

A30

A32

A34

C23

C25

C27

C29

C31

C34

C36

E22

E24

E26

E28

E30

E32

E36

F34

G32

G36

H34

J32

J36

K34

L32

L36

M34

N32

N36

P34

R32

R36

T34

U32

U36

V34

W32

W36

Y34

N755IA5 Rev : A Page 10 - 31

Chapter2 Major Components

DDR TERMINATION(U23A)

U23A

H29
H28

J29

J28
K29
K28
L29
L28

N28

P29
P28

R29
R28

T29
T28

U29
N25
R26

P25

R27
R25

T25
T26

U25

V27

W26
W25

Y26

Y25
AA26
AA25
AA27

N29

U28

P26

U26

AG30
AG28
AF28
AD26

M25

N26

V29

V28
W29
W28

AE26
AC26
AE29

M28

V25

AB29
AD28

AD29
AC28
AC29
AA28
AA29

Y28
Y29

AF29
AD27
AE28

AB28

M29

V26

M26
M27

AB26
AB25
AC25

AK21

AJ23
AJ22

AK22

AJ24

AK24
AG23

AG24
AK25

AJ25

AH28

AJ29

AH27

E8
B6

AE25

AG26
AH30
AH29
AG29

N755IA5 Rev : A Page 11 - 31

Part 1 of 5

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE#0
C/BE#1
C/BE#2
C/BE#3

PCICLK
RST#
REQ#
GNT#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
INTA#

WBF#
RBF#

AD_STBF_0
AD_STBF_1
SB_STBF

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

ST0
ST1
ST2

SB_STBS
ADSTBS_0
ADSTBS_1

AGPREF
AGPTEST

DBI_LO
DBI_HI
AGP8X_DET#

R2SET
C_R

Y_G
COMP_B

H2SYNC
V2SYNC

DDC3CLK
DDC3DATA

SSIN
SSOUT
XTALIN
XTALOUT
TESTEN

TEST_YCLK(NC)
TEST_MCLK(NC)
PLLTEST(NC)

SUS_STAT#
STP_AGP#
AGP_BUSY#
RSTB_MSK(NC)

PCI / AGPAGP2X4XDAC2SSCLK

AGP

8X

PWR

ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8

DVO / EXT TMDS / GPIOLVDSTMDSDAC1

ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23

ZV_LCDCNTL0

ZV_LCDCNTL1

ZV_LCDCNTL2

ZV_LCDCNTL3

MAN

DVOMODE

(NC)VREFG
TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN
TXCLK_LP

TXOUT_U0N

TXOUT_U0P

TXOUT_U1N

TXOUT_U1P

TXOUT_U2N

TXOUT_U2P

TXOUT_U3N

TXOUT_U3P

TXCLK_UN

TXCLK_UP

DDC2CLK

DDC2DATA

DDC1DATA

DDC1CLK

AUXWIN

DMINUS

THERM

ATI_M10-P

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

DIGON

BLON

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TXCM

TXCP

HPD1

HSYNC
VSYNC

RSET

DPLUS

AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

AE10
AH6

AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

AG4
AK16

AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19

AE12
AG12

AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13

AE13
AE14

AF12
AK27

R

AJ27

G

AJ26

B

AG25
AH25

AH26
AF25

AF24
AF26

AF11
AE11

Chapter2 Major Components

DDR TERMINATION (U23B)

U23B

L25

L26

K25

K26

J26

H25

H26

G26

G30

D29

D28

E28

E29

G29

G28

F28

G25

F26

E26

F25

E24

F23

E23

D22

B29

C29

C25

C27

B28

B25

C26

B26

F17

E17

D16

F16

E15

F14

E14

F13

C17

B18

B17

B15

C13

B14

C14

C16

A13

A12

C12

B12

C10

C9

B9

B10

E13

E12

E10

F12

F11

E9

F9

F8

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63

ATI_M10-P

Part 2 of 5

MEMORY INTERFACE

A

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11

(MAA13)MAA12
(MAA12)MAA13

(NC)MAA14

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0

QSA1

QSA2

QSA3

QSA4

QSA5

QSA6

QSA7

RASA#

CASA#

WEA#

CSA0#

CSA1#

CKEA
CLKA0

CLKA0#

CLKA1

CLKA1#

MVREFD

MVREFS

DIMA_0
DIMA_1

E22

B22

B23

B24

C23

C22

F22

F21

C21

A24

C24

A25

E21

B20

C19

J25

F29

E25

A27

F15

C15

C11

E11

J27

F30

F24

B27

E16

B16

B11

F10

A19

E18

E19

E20

F20

B19

B21

C20

C18

A18

B7

B8

D30

B13

N755IA5 Rev : A Page 12 - 31

Chapter2 Major Components

DDR TEMINATION(U23C)

U23C

D7

G6

G5

C4

C5

C2

D3

D1

D2

G4

H6

H5

G2

H2

H3

U6

U5

U3

W5

W4

Y6

Y5

U2

W3

Y2

Y3

AA2

AA6

AA5

AB6

AB5

AD6

AD5

AE5

AE4

AB2

AB3

AC2

AC3

AD3

AE1

AE2

AE3

F7

E7

F5

E5

B5

A4

B4

J6

K5

K4

L6

L5

F3

E2

F2

J3

F1

V6

V2

V1

V3

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63

ATI_M10-P

Part 3 of 5

(MAB13)MAB12
(MAB12)MAB13

MEMORY INTERFACE

B

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8

MAB9
MAB10
MAB11

(NC)MAB14

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

CKEB

CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB_0
DIMB_1

ROMCS#

MEMVMODE_0
MEMVMODE_1

MEMTEST

N5

M1

M3

L3

L2

M2

M5

P6

N3

K2

K3

J2

P5

P3

P2

E6

B2

J5

G3

W6

W2

AC6

AD2

F6

B3

K6

G1

V5

W1

AC5

AD1

R2

T5

T6

R5

R6

R3

N1

N2

T2

T3

E3

AA3

AF5

C6

C7

C8

N755IA5 Rev : A Page 13 - 31

Chapter2 Major Components

DDR TEMINATION (U23D)

U23D

T7

VDDR1

R4

VDDR1(CLKBFB)

R1

VDDR1

N8

VDDR1

N7

VDDR1

M4

VDDR1

L27

VDDR1

L8

VDDR1

J24

VDDR1

J23

VDDR1

J8

VDDR1

J7

VDDR1

J4

VDDR1

J1

VDDR1

H10

VDDR1

H13

VDDR1

H15

VDDR1

H17

VDDR1

T8

VDDR1

V4

VDDR1

V7

VDDR1

V8

VDDR1

AA1

VDDR1

AA4

VDDR1

AA7

VDDR1

AA8

VDDR1

A3

VDDR1

A9

VDDR1

A15

VDDR1

A21

VDDR1

A28

VDDR1

B1

VDDR1

B30

VDDR1

D26

VDDR1

D23

VDDR1

D20

VDDR1

D17

VDDR1

D14

VDDR1

D11

VDDR1

D8

VDDR1

D5

VDDR1

E27

VDDR1

F4

VDDR1

G7

VDDR1

G10

VDDR1

G13

VDDR1

G15

VDDR1

G19

VDDR1

G22

VDDR1

G27

VDDR1

H22

VDDR1

H19

VDDR1

AD4

VDDR1

T4

VDDR1

N4

VDDR1

D19

VDDR1(CLKAFB)

D13

VDDR1

AE17

LVDDR_25(LVDDR18_25)

AE20

LVDDR_25(LVDDR18_25)

AE15

LVDDR_18

AF21

LVDDR_18

AJ20

LPVDD

AK12

TPVDD

AF13

TXVDDR

AF14

TXVDDR

F18

VDDRH0

N6

VDDRH1

AG21

A2VDD

AH21

A2VDD

AF22

A2VDDQ

AH24

AVDD

AE24

VDD1DI

AE22

VDD2DI

AK28

PVDD

A7

MPVDD

ATI_M10-P

Part 4 of 5

I/O

VDDC
VDDC
VDDC
VDDC
VDDC

(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15

VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4

VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP

AVSSQ
LVSSR

LVSSR
LVSSR
LVSSR

LPVSS
TPVSS

TXVSSR
TXVSSR
TXVSSR

VSSRH0

POWER

VSSRH1

A2VSSN
A2VSSN
A2VSSQ

AVSSN
VSS1DI
VSS2DI

PVSS

MPVSS

AC13
AD13
AD15
AC15
AC17

P8
Y8
AC11
AC20
Y23
L23
H20
H11

AD7
AD19
AD21
AD22
AC22
AC21
AC19
AC8
AG7
AD9
AC9
AC10
AD10

J30
AF27
AE30
AC27
AC23
AB30
AA24
AA23
Y27
W30
V23
V24
M23
M24
N30
P23
P27
T23
T24
T30
U27

AD24
AF20

AE19
AE16
AF15

AJ19
AJ12

AH12
AG13
AG14

F19
M6
AH22
AJ21
AF23
AH23
AE23
AE21
AJ28
A6

N755IA5 Rev : A Page 14 - 31

Chapter2 Major Components

DDR TERMINATION(U21)

U21

N4

M5

N5

N6

M6

N7

N8

M9

N9

N10

N11

M8

M7

N2

M2

M11

M12

N12

N13

B2

H13

H2

B13

B3

H12

H3

B12

M10

M13

N3

M4

M3

L13

L12

H11

H4

C11

C4

B4

B11

D4

D5

D6

D9

D10

D11

E6

E9

F5

F10

G5

G10

H5

H10

J10

K5

K10

K6

K7

K8

K9

L10

L6

L2

L3

L9

J5

L5

BA0
BA1

A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
A9
A10
A11

CS

RAS

CAS

WE

CLK
CLK#
CKE
VREF
DQS0

DQS1
DQS2
DQS3

DQM0
DQM1
DQM2
DQM3

NC/TH1
NC/TH2
MCL

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS

K4D263238A

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B7

C6

B6

B5

C2

D3

D2

E2

K13

K12

J13

J12

G13

G12

F13

F12

F3

F2

G3

G2

J3

J2

K2

K3

E13

D13

D12

C13

B10

B9

C9

B8

D7

D8

E4

E11

L4

L11

L7

L8

C5

C3

C7

C8

C10

C12

E3

E12

F4

F11

G4

G11

J4

J11

K4

K11

E10

E8

E7

E5

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

N755IA5 Rev : A Page 15 - 31

Chapter2 Major Components

DDR TERMINATION(U20)

U20

N4

M5

N5

N6

M6

N7

N8

M9

N9

N10

N11

M8

L6

M7

N2

M2

L2

L3

M11

M12

N12

N13

B2

H13

H2

B13

B3

H12

H3

B12

L9

M10

M13

N3

M4

M3

L13

L12

H11

H4

C11

C4

B4

B11

D4

D5

D6

D9

D10

D11

E6

E9

F5

F10

G5

G10

H5

H10

J5

J10

K5

K10

K6

K7

K8

K9

L5

L10

BA0
BA1

A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
A9
A10
A11

CS

RAS

CAS

WE

CLK
CLK#
CKE
VREF
DQS0

DQS1
DQS2
DQS3

DQM0
DQM1
DQM2
DQM3

NC/TH1
NC/TH2
MCL

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS

K4D263238A

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B7

C6

B6

B5

C2

D3

D2

E2

K13

K12

J13

J12

G13

G12

F13

F12

F3

F2

G3

G2

J3

J2

K2

K3

E13

D13

D12

C13

B10

B9

C9

B8

D7

D8

E4

E11

L4

L11

L7

L8

C5

C3

C7

C8

C10

C12

E3

E12

F4

F11

G4

G11

J4

J11

K4

K11

E10

E8

E7

E5

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

N755IA5 Rev : A Page 16 - 31

Chapter2 Major Components

DDR TERMINATION(U4)

U4

N4

M5

N5

N6

M6

N7

N8

M9

N9

N10

N11

M8

M7

N2

M2

M11

M12

N12

N13

B2

H13

H2

B13

B3

H12

H3

B12

M10

M13

N3

M4

M3

L13

L12

H11

H4

C11

C4

B4

B11

D4

D5

D6

D9

D10

D11

E6

E9

F5

F10

G5

G10

H5

H10

J10

K5

K10

K6

K7

K8

K9

L10

L6

L2

L3

L9

J5

L5

BA0
BA1

A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
A9
A10
A11

CS

RAS

CAS

WE

CLK
CLK#
CKE
VREF
DQS0

DQS1
DQS2
DQS3

DQM0
DQM1
DQM2
DQM3

NC/TH1
NC/TH2
MCL

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS

K4D263238A

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B7

C6

B6

B5

C2

D3

D2

E2

K13

K12

J13

J12

G13

G12

F13

F12

F3

F2

G3

G2

J3

J2

K2

K3

E13

D13

D12

C13

B10

B9

C9

B8

D7

D8

E4

E11

L4

L11

L7

L8

C5

C3

C7

C8

C10

C12

E3

E12

F4

F11

G4

G11

J4

J11

K4

K11

E10

E8

E7

E5

F6

F7

F8

F9

G6

G7

G8

G9

H6

H7

H8

H9

J6

J7

J8

J9

N755IA5 Rev : A Page 17 - 31