UNIWILL 258SA0 Service Manual

Page 1
Chapter 1 General System Description
UNIWILL COMPUTER CORP.
No. 24 Pei Yuan Road Chung Li Industrial Park, Chung Li City Tao Yuan, Taiwan, R.O.C. TEL: 886-3-461-6000 FAX: 886-3-461-6317 URL: http:// www.uniwill.com.tw/
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Chapter 1 General System Description
1.1. Hardware / Software Specifications……………………………………….
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Chapter 1 General System Description
HARDWARE &SOFTWARE SPECIFICATION:
1. CPU
A. D/T INTEL P4 PROCESSOR
The Intel Pentium® 4 Processor with 512-KB L2 cache on 0.13 micron process utilizes Flip Chip Pin Gray Array (FC-PGA2) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Pentium 4 Processor with 512-KB L2 cache on 0.13 micron process, like its predecessor, the P4 processor in the 478 pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of compatibility with 1A-32 software.
Hyper-Threading Technology is a new feature in the Intel P4 processor at 800MHz system bus and 3.06GHz/533 MHz system bus with 512-KB L2 cache on 0.13 micron process. HT Technology allows a single, physical P4 processor to function as two logical processors. Intel recommend enabling HT Technology with Microsoft Windows XP Professional or Windows XP Home, and disabling HT Technology via the BISO for all previous versions of Windows operating system.
The Intel NetBurst microarchitecture features include hyper pipeline technology, a rapid execution engine, a 400MHz, 533MHz, or 800MHz system bus, and an execution trace cache. The Hyper pipeline technology doubles the pipeline depth in the P4 processor to run at twice the core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency , which allow many integer instructions to execute in 1/2 clock tick. The 400MHz, 533MHz, or 800MHz system bus is a quad-pumped bus running off a 100MHz or a 133MHz system clock, making 3.2Gbytes/sec, 4.3Gbytes/sec, or 6.4Gbytes/sec data transfer rates possible.
B. MOBILE INTEL PROCESSOR
Flip-Chip Pin Grid Array (Micro-FCPGA) package with Integrated Heat Spreader, and plugs into a surface mount, Zero Insertion Force (ZIF) socket. The Mobile Intel Pentium 4 processor maintains full compatibility with IA-32 software.
The Intel NetBurst micro-architecture features include hyper-pipelined technology, a rapid execution engine, a 533MHz system bus, and execution trace cache. The hyper piplined technology doubles the pipeline depth in the Mobile Intel Pentium 4 Processor allowing the processor to reach much higher core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 533MHz system bus is a quad-pumped bus running off a 133MHz system clock making 4.3Gbytes/sec data transfer rates possible.
The processor, when used in conjunction with the requisite Intel SpeedStep technology
The Mobile Intel Pentium 4 processor with 533MHz utilizes a 478-pin, Micro
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Chapter 1 General System Description
applet or its equivalent, support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes. This occurs by switching the bus ratios, core operating voltage, and core processor speeds without resetting the system. The processor features the Auto Halt, Stop Grant, Deep Sleep, and Deeper Sleep low power states. The processor system bus uses a variant of GTL+ signaling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology.
2. SIS648FX HMAC
performance host interface for Intel Pentium 4 processor, a high performance memory controller, an AGP interface, and SIS MuTIOL 1G Technology connecting w/ SIS963L MuTIOL 1G Media IO.
The SIS648FX Host Interface features the AGTL&AGTL+ compliant bus driv er technology with integrated on-die termination to support Intel Pentium 4 series processors with PSB 400 MHz/ 533MHz/ 800MHz. It provides a 12-level In-Order-Queue to support maximum outstanding transactions on host bus up to 12.
The Memory Controller supporting DDR only. It can offer bandwidth up to 3.2GB/s under DDR333 in order to sustain the bandwidth demand from host processor , as well as the multi I/O master and AGP masters. The memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access Host Controller, and I/O bus master based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged server to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and push into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utm ost by scheduling the command requests in the background when the data requests streamlines in the foreground. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power.
3. ATI M10-P VGA CHIP(NO INTER GRATED MEMORY)
multimedia graphics performance for notebooks. Its architecture introduces the latest achievements in the graphic industry, which enable the use of the progressive new features in upcoming applications, but without compromising performance. ATI’s support of DirectXR9
features, highly optimized OpenGLR support, and flexible memory configurations allow
implementations targeted at the gaming enthusiast, consumer, business and workstation platforms.
The SIS648FX Host & Memory & AGP Controller integrates a high
The MOBILITY M10 provides the fastest and most advanced 2D, 3D, and
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Chapter 1 General System Description
4. CLOCK GENERATOR & DDR ZERO DELAY BUFFER The Main clock ICS952005 is a chip clock solution for desktop design using SIS
648FX style chipsets. When used with a Zero Delay buffer such as the ICS93722 for DDR applications it provides all the necessary clocks signals for such a system.
Programmable output frequency, divider ratios, output rise/fall time, output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Support I2C index read/write and block read/write operations. Selectable asynchronous/synchronous AGP, ZCLK and PCI output. Support DDR333 OEM frequencies.
Uses external 14.318MHz crystal.
5. SYSTEM MEMORY
258SA Support PC 2100/2700 128MB/256MB/512MB/1GB DDR 266/333
SDRAM for Extending with 2 un-buffer Double-side DIMM DDR 266/333:
Sustains DDR SDRAM CAS Latency at option of 2, 2.5, &3 clock. Support up to 2 un-buffer Double-sided DIMM DDR 266/333
DIMM1 DIMM2 TOTAL
128MB 0 128MB 256MB 0 256MB 512MB 0 512MB
6. SIS963 MUTIOL 1G MEDIAI/O
The SIS963 MuTIOL Media I/O integrates one Universal Series Bus 2.0 Host
Controller, the Audio Controller with AC97 Interface, the Ethernet MAC Controller w/ standard MII interface, three Universal Serial Bus 1.1 Host Controller, the IDE Master/Slave controllers, and SiS MuTIOL technology. The PCI to LPC bridge, I/O Advance Programmable Interrupt Controller and legacy power management functionalities are integrated as well
A.
Ethernet MAC
B.
Universal Serial Bus 2.0 (USB2.0)
C.
IDE Interface
D.
IEEE 1394 Link Interface
SiS962 support 6 PCI master and complies with PCI2.2 specification. It also
incorporates the legacy system I/O like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters. hardwire keyboard controller and PS2 mouse interface, Real Time clock with 512b CMOS SRAM and two 8259A compatible interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery modes is supported
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Chapter 1 General System Description
7. MINI PCI(WIRELESS LAN)
Product Name: 11Mbps Wireless LAN Mini-PCI Card
Model Number: WL-350F Host Interface: Mini PCI type III A Operating Voltage: 3.3V+-5% Frequency Band: 2.400~2.4835GHz (subject to regulation) Standards: IEEE802.11b, Wi-Fi compliant
8. PCMCIA
The OZ711M1 is a single socket PC Card controller that also support Smart Cards and flash media cards. The OZ711M1 is enhance with O MultiMediaBay™ technology, enabling a single passive adapter that supports all four flash media formats - SmartMedia™, Memory Stick™, MultiMediaCard (MMC) and SD Memory Card.
The OZ711M1 also provides a secondary Optional Dedicated Reader (ODR) interface that can support a Smart Card socket, a MMC/SD Card socket, or a Memory Stick socket. The software drivers that support the optional dedicated reader are identical to those required for the PC Card socket extensions for MultiMediaBay™.
The OZ711M1 provides a SmartMedia™ reader fully compliant with the SmartMedia™ Standard, Millennium Version, released in 2000 by the SSFDC forum. The reader supports the unique identifier extension for SDMI, 3Vand 5V SmartMedia™ cards in any capacity from 1MB to 128MB including MASK ROM versions. The integrated MMC/SD Memory Card and Memory Stick reader transfers data at an operating frequency of 16.5MHz and supports all capacities of these media formats and Memory Stick cards.
9. BIOS
The 258SA using AMI system BIOS, and support PnP, APM 1.2 and ACPI 2.0 function. Both of System and VGA BIOS are flashed in a 4Mbit EEPROM, The Flash ROM in the 32-pin PLCC package, there are three of suppliers for BIOS:
EON (EN29LF040-70)AMIC (A29040L-70) Hyundai (HY29F040A-70)
2Micro’s patent pending
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Chapter 1 General System Description
10. IEEE1394 PHY
a two-port node in a cable based IEEE 1394-1995 and IEEE 1394a-2000 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization, and for packet reception and transmission. The PHY is designed to interface with a link-layer controller (LLC).
The PHY require an external 24.576MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 400MHz reference signal. The 400MHz reference signal is internally divided to provide the 49.152MHz,
98.304MHz, and 196.608MHz clock signals that control transmission of the outbound encoded strobe and data information.
When the PHY/link interface is in the disabled state, the FW802B will automatically enter a low-power mode, if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the FW802B disable its PLL and also disable parts of reference circuitry depending on the state of the ports (some reference circuitry must remain active in order to detect incoming TP bias). The lowest power consumption (the microlow-power sleep mode) is attained when all ports are either disconnected or disabled with the ports interrupt enable bit cleared.
Provides two fully compliant cable ports at 100Mbits/s, 200Mbits/s, and 400Mbits/s.
Fully supports OHCI requirements.
Support connection debounce.
Support multispeed packet concatenation.
11. HARD DISK
33/66/100.
Vendor: Toshiba, Fujitsu, IBM Capacity: Support 20/30 or above HDD Thickness: 9.5mm/2.5”
Host Interface: Fast IDE Interface
12. OPTICAL DEVICE
Secondary Master:
1. COMBO (DVD/CD-RW)
2. DVD
3. CD-R or CD-R/W
4. CD-ROM
5. Second HDD
FW802B device provides the analog physical layer functions need to implement
The Primary Master HDD supporting PIO Mode 0,1,2,3,4 and Ultra DMA
The Secondary Master also supporting ATAPI CD-ROM Device as follow:
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Chapter 1 General System Description
13. KEYBOARD
Key Board Matrix: 258SA
Travel: 3.0±0.3mm Contact Resistance: 500 ohm Maximum
Keycap pull off force: Function Key 800g; Normal Key ≧800g
Switch Life: 5 Million cycles
14. AUDIO SUBSYSTEM
designed for PC Multimedia systems, include host/soft audio and AMR/CNR based designs. The ALC650 incorporates proprietary converter technology to achieve a high SNR, greater than 90dB. The ALC650 AC’97 CODEC supports multiple CODEC extensions with independent variable sampling rates and built-in 3D effects. The ALC650 CODEC provides three pairs of outputs with independent volume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC650 CODEC operates from a 3.3V power supply with EAPD (External Amplifier Power Down) control for use in notebook and PC applications. The ALC650 integrates a 50mW/20 ohm headset audio amplifier in to the CODEC, which can save BOM cost. The ALC 650 also supports an AC’97
2.2 compliant SPDIF out function which allows easy connection from the PC to consumer electronic products, such as AC3 decoder/speaker and mini disk.
High performance CODEC with high S/N ratio (>90dB)
18-bit ADC and 20-bit DAC resolution
Compliant with AC’97 2.2 specifications
18-bit stereo full duplex CODEC with independent and variable sampling rate
One stadard MIC input, and one dedicated Front-MIC input for front panel applications
Digital SPDIF output
Digital SPDIF input. (ALC650 Rev. E or later)
15. TOUCH PAD UNITE
button, special firmware that permits the Touch Pad to be initialized into 4-byte wheel Mouse mode. In this mode the Touch Pad communicates with the PS/2 host as though it were a Microsoft IntelliMouse. The Touch Pad also includes the standard Synaptics’ enhanced mode of operation, 6-byte mode.
Scrolling is implemented in the firmware of this Touch Pad. When it is initialize into Wheel Mouse mode the firmware will decode a finger gesture on the right hand edge of the Touch Pad as intent to scroll.
The ALC650 is an 18-bit, full duplex AC’97 2.2 compatible stereo audio CODEC
software selectable)
The Synaptics T ouch Pad include two inputs for button switches: Left and Right
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Chapter 1 General System Description
16. LED INDICATOR
1. Two LED indicators on the right case: SUSPEND LED: Green color for the system active at suspend mode Power/Charge LED: Green color for system power on, orange color for battery
2. Fore LED indicator beside by power button:
3. HDD/CD-ROM, Num Lock, Caps Lock, Scroll Lock LED
17. MODEM
low-cost, solid-state interface to a telephone line. They eliminate the need for an analog front end (AFE), and isolation transformer, relays, opto-isolator, and 2- to 4-wire hybrid. The products dramatically reduce the number of discrete components and cost required to achieve compliance with FCC Part 68. I800 and M800 comply with AC’97 / MC’97 interface specification Rev. 2.1.
Power Consumption: Less than 100mW Modem mode speed: 56Kb/p maximum Compatibility: Bell 103, Bell 212A, ITU-T V.21, V.32bis, V.34, V.90, V.92 Transmission Way: Full Duplex Fax mode speed: 14.4Kbps
18. IR
provides interface between logic and IR signals for through-air, serial, half-duplex IR data link. The module is compliant to IrDA Data Physical Layer Specification 1.1 and IEC825-Class 1 Eye Safe.
Fully Compliant to IrDA 1.1 Physical Layer Specifications – 9.6kb/s to 4Mb/s operation Typical Link Distance > 1.5m Compatible with ASK, HP SIR, TV Remote Low power operation 2.7V to 3.6V Low shutdown current 10nA typical
19. HOT KEY DEFINITION.
Fn + F1 (SMI): Standby
Fn + F3 (SMI): Mute battery warning beep Fn + F4 (SMI): Toggle LCD/CRT display Fn + F5 (SMI): Volume increase Fn + F6 (SMI): Volume decrease Fn + F7 (SMI): Brightness more lightness
Fn + F8 (SMI): Brightness more darkness
There are two portion of LED indicators on 351S1.
charging.
I800 and M800 use Silicon based DAA chip set that provides a digital,
The HSDL-3600/3602 is a low-profile infrared transceiver module that
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Chapter 1 General System Description
20. SYSTEM INDICATOR(LED)
Caps Lock (on/off)
Num Lock (on/off) Scroll Lock (on/off) HDD/CDROM (on/off) Power on (on/off) Suspend (flash/off) Power Switch (on/off) LAN Switch (on/off)
Use Adaptor Power LED Suspend LED Use Battery Power LED Suspend LED
Power On Green Off Power On Green Off
Suspend Off Green Blinking Suspend Off Green Blinking
Power Off Off Off Power Off Off Off
Charging Orange Blinking X Charging X X
Discharging X X Discharging Green X
Low Battery X X Low Battery X
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Chapter 1 General System Description
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Chapter2 Major Components
UNIWILL COMPUTER CORP.
No. 24 Pei Yuan Road Chung Li Industrial Park, Chung Li City Tao Yuan, Taiwan, R.O.C. TEL: 886-3-461-6000 FAX: 886-3-461-6317 URL: http:// www.uniwill.com.tw/
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Chapter2 Major Components
2.1. System Block Diagram …………………………………………………...
2.2. Major Component Definition.……..……………………………….……
2.3. Connector Definition…….………………………………………………..
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4
35
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Chapter2 Major Components
2.1 SYSTEM BLOCK DIAGRAM
DDRCLK0 DDRCLK1 DDRCLK2
AUDIO _CLK
AMPLIFIER
TI
TPA6011A4
L-SPKR R-SPKR
DDR 1
SPDIF OUT
DDR RAM BUS
DDRCLK0# DDRCLK1#
DDRCLK4
DDRCLK2#
DDRCLK5
AUDIO CODEC
RELTECK ALC650
LINE INSPDIF
IN
MIC
DDR 2
MDC
RJ-11
DDRCLK3#DDRCLK3 DDRCLK4# DDRCLK5#
AC Link
PCI BUS
CPUCLK CPUCLK#
648CLK 648CLK#
648SDCLK
AGPCLK0 648ZCLK
FWDSDCLK
963ZCLK 963PCICLK USB_48M
961REF1 961REF3
CPU
Intel
D/T & P4-M
Host BUS
North Bridge
SIS
648FX
HyperZip BUS
South Bridge
SIS
963
AGP BUS
RTC
THERMAL
ADM 1032
VRAM x8
VRAM BUS
ATI
M10P
64/128/256M VRAM
AGPCLK1
LAN(PHY)
REALTEK
RTL8201BL
CRYSTAL
25M HZ
CRYSTAL
32.768K
CRYSTAL
12M HZ
IDE BUS
CRT S-Video TV
LCD
15.4" WXGA TFT
15.4" WSXGA TFT
RJ-45
HDD
2.5"
PRIMARY MASTER
CD-ROM DVD CD-RW COMBO
SECONDARY
MASTER
IEEE-1394 PHY
NS
PARALLEL
AGERE FW802C
1394
BIOS LED
LPC BUS
CRYSTAL
32.768K
INT K/BFIR
USB0 USB1
K/B CONTROLLER
PCICLK_EC
T/P
PC87591L
FAN
USB2
NS
BATTERYCHARGER
DC/DC
CRYSTAL
14.318MHz
PCICLK_M
Mini PCI
SCLK
CARDBUS
O2 MICRE OZ711M1
MMC/SD/MS
PCMCIA
READER
PCLK_CB
391_48M LPC_CLK
CRYSTAL
24.576M HZ
LPC
PC87391
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Chapter2 Major Components
2.2 MAJOR COMPONENTS DEFINITION: CPU1 HOST(U25A)
AC3
IERR
V6
MCERR
B6
FERR
Y4
STPCLK
AA3
BINIT
W5
INIT
AB2
RSP
H5
DBSY
H2
DRDY
J6
TRDY
G1
ADS
G4
LOCK
H6
BRO
G2
BNR
F3
HIT
E3
HITM
D2
BPR
E2
DEFER
D4
TCK
C1
TDI
F7
TMS
E6
TRST
D5
TDO
C3
PROCHOT
B2
IGNNE
B5
SMI
C6
A20M
AB26
SLP
AB23
PWRGOOD
AB25
RESET
AD24
TESTHI0
AA2
TESTHI1
AC21
TESTHI2
AC20
TESTHI3
AC24
TESTHI4
AC23
TESTHI5
AA20
TESTHI6
AB22
TESTHI7
U6
TESTHI8
W4
TESTHI9
Y3
TESTHI10
A6
TESTHI11/GHI#
AD25
TESTHI12/DPSLP#
AC6
BPM0
AB5
BPM1
AC4
BPM2
Y6
BPM3
AA5
BPM4
AB4
BPM5
K26
K25
J26
AC1
AF4
HA34
AB1
HA35
AF3
VCCVID
VCCVIDPRG
F1
G5
F4
K4
K2
RS0
RS1
RS2
HA3
L2
M6
L3
K1
L6
HA8
HA7
HA6
HA5
HA4
N2
M1
N1
M4
M3
HA9
HA13
HA12
HA11
HA10
P3
R2
T1
N5
N4
HA18
HA17
HA16
HA15
HA14
P6
U1
T2
R3
P4
HA23
HA22
HA21
HA20
HA19
W1
R6
V2
T4
U3
HA28
HA27
HA26
HA25
HA24
Y1
W2
V3
U4
T5
HA33
HA32
HA31
HA30
HA29
V5
AC26
ITP_CLK0
AD26
AP0
AP1
ITP_CLK1
DEP0
DEP1
L25
DEP2
DEP3
AE5
AE4
AE3
AE2
VID0
VID1
VID2
COMP0 COMP1
ADSTB0 ADSTB1
DBRESET
THERMDA THERMDC
THERMTRIP
VCC_SENSE
VSS_SENSE
AE1
VID3
VID4
BCLK0 BCLK1
LINT0 LINT1
STBP0 STBP1 STBP2 STBP3
STBN0 STBN1 STBN2 STBN3
DB#0 DB#1 DB#2 DB#3
REQ0 REQ1 REQ2 REQ3 REQ4
BSEL0 BSEL1
U25A
AF22
AF23
L24
P1
D1
E5
L5
R5
AE25
F21
J23
P23
W23
E22
K22
R22
W22
E21
G25
P26
V21
J1
K5
J4
J3
H3
B3
C4
A2
AD6
AD5
A5
A4
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
SOCKET478
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Chapter2 Major Components
CPU2 POWER(U25B)
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
C22
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
F8
G21
G24
G3
R23
R1
P5
P25
P22
R26
P2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A10
VCC
VSS
A12
VCC
VSS
A14
VCC
VSS
A16
A18
VCC
VCC
VSS
VSS
A20
A8
VCC
VCC
VSS
VSS
AA12
AA10
VCC
VSS
AA14
VCC
VCC
VSS
VSS
AA18
AA16
VCC
VSS
AA8
VCC
VCC
VSS
VSS
AB13
AB11
VCC
VSS
AB15
VCC
VCC
VSS
VSS
AB19
AB17
VCC
VSS
AB7
VCC
VCC
VSS
VSS
AB9
VCC
VSS
AC12
AC10
VCC
VCC
VSS
VSS
AC16
AC14
VCC
VSS
AC8
AC18
VCC
VCC
VSS
VSS
AD11
VCC
VCC
VSS
VSS
AD15
AD13
VCC
VSS
AD19
AD17
VCC
VCC
VSS
VSS
AD7
VCC
VSS
AD9
VCC
VCC
VSS
VSS
AE12
AE10
VCC
VSS
AE14
VCC
VCC
VSS
VSS
AE18
AE16
VCC
VSS
AE20
VCC
VCC
VSS
VSS
AE6
VCC
VSS
AE8
VCC
VSS
AF13
AF11
VCC
VSS
AF15
VCC
VCC
VSS
VSS
AF19
AF17
VCC
VSS
AF2
VCC
VCC
VSS
VSS
AF5
AF21
VCC
VSS
AF7
VCC
VCC
VSS
VSS
AF9
B11
VCC
VCC
VSS
VSS
B13
B15
VCC
VCC
VSS
VSS
B17
VCC
VSS
B19
B7
VCC
VCC
VSS
VSS
B9
C10
VCC
VCC
VSS
VSS
C12
VCC
VSS
C14
VCC
VSS
C16
C8
C20
C18
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS/IMPSEL
D11
VCC
VSS
D13
D15
VCC
VCC
VSS
VSS
D17
VCC
VSS
D19
VCC
VSS
D7
D9
VCC
VCC
VSS
VSS
E10
VCC
VSS
E12
VCC
VSS
E20
E18
E16
E14
VCC
VCC
VCC
VCC
SKTOCC#
VSS
VSS
VSS
E8
F11
VCC
VCC
VSS
VSS
F13
F15
VCC
VCC
VSS
VSS
F17
F19
VCC
VCC
VSS
VSS
F9
VCC
VSS
F6
F20
AA6
AA21
GTLREF0
GTLREF1
GTLREF2
VSS
VSS
VSS
VSS
U25B
VCCIOPLL
VCCA
GTLREF3
VSSA
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS
VSS
VSS
AE23
AD20
AD22
Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
C17
C15
C13
C11
B8
B4
B26
B23
B20
B18
B16
B14
B12
B10
AF8
AF6
AF26
AF20
AF18
AF16
AF14
AF12
AF10
AF1
AE9
AE7
AE26
AE24
AE22
AE19
AE17
AE15
AE13
AE11
AD8
AD4
AD23
AD21
AD18
AD16
AD14
AD12
AD10
AD1
AC9
AC7
AC5
AC25
AC22
AC2
AC19
AC17
AC15
AC13
AC11
AB8
AB6
AB3
AB24
AB21
AB20
AB18
AB16
AB14
AB12
AB10
AA9
AA7
AA4
AA26
AA23
AA19
AA17
AA15
AA13
AA11
AA1
A9
A3
A26
A24
A21
A19
A17
A15
A13
A11
H26
H23
H4
H1
N755IA5 Rev : A Page 5 - 31
C2
C19
SOCKET478
Page 17
Chapter2 Major Components
CLOCK GENERATOR(U15)
U15
1
VDDREF
11
VDDZ
13
VDDPCI
19
VDDPCI
28
VDD48
29
VDDAGP
42
VDDCPU
48
VDDSD
5
VSSREF
8
VSSZ
18
VSSPCI
24
VSSPCI
25
VSS48
32
VSSAGP
41
VSSCPU
46
VSSSD
12
PCI_STOP#
45
CPU_STOP#
33
PD#/VTT_PWRGD
38
IREF
36
VDDA
CPUCLK0
CPUCLK#0
CPUCLK1
CPUCLK#1
SDCLK
AGPCLK0 AGPCLK1
ZCLK0 ZCLK1
PCICLK_F0/FS3 PCICLK_F1/FS4
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5
REF0/FS0 REF1/FS1 REF2/FS2
24_48M/MULTISEL
48M
40
39
44
43
47
31
30
9
10
14
15
16
17
20
21
22
23
2
3
4
27
26
SCLK
37
ICS952005
VSSA
XIN
6
SDATA
XOUT
7
DDR BUFFER(U28)
U28
3
VDD
12
VDD
23
VDD
10
VDD
7
SCLK
22
SDATA
8
CLKIN
9
CLKIN#
20
FB_IN
21
FB_IN#
GND
GND
GND
FB_OUT
FB_OUT#
GND
CLK0 CLK1 CLK2 CLK3 CLK4 CLK5
CLK#0 CLK#1 CLK#2 CLK#3 CLK#4 CLK#5
35
34
2
4
13
17
24
26
1
5
14
16
25
27
19
18
6
11
15
ICS93722
28
N755IA5 Rev : A Page 6 - 31
Page 18
Chapter2 Major Components
SIS648 HOST&AGP(U27A)
AJ31
AJ33
T33
T35
V32
B23
F22
R34
U31
R33
T32
U35
V35
R35
U34
W34
U33
V33
W35
Y33
W31
W33
Y35
AG31
AA33
AH33
AG33
AJ35
AF32
AJ34
AH32
AG35
AE31
AH35
AF35
AE35
AE33
AE34
AF33
AG34
AC33
AD32
AD33
AC35
AD35
AC31
AC34
AB35
AB32
AB33
AA35
AA31
Y32
AA34
U27A
CPUCLK CPUCLK#
HLOCK# DEFER# HTRDY# CPURST# CPUPWRGD BPRI# BREQ0#
RS#2 RS#1 RS#0
ADS# HITM# HIT# DRDY# DBSY# BNR#
HREQ4# HREQ3# HREQ2# HREQ1# HREQ0#
HASTB1# HASTB0#
HA31# HA30# HA29# HA28# HA27# HA26# HA25# HA24# HA23# HA22# HA21# HA20# HA19# HA18# HA17# HA16# HA15# HA14# HA13# HA12# HA11# HA10# HA9# HA8# HA7# HA6# HA5# HA4# HA3#
648
C24
HD63#
HD62#
E23
B24
AL36
AK34
C1XAVSS
C1XAVDD
HD61#
HD60#
HD59#
D23
D25
AJ36
AK35
C4XAVSS
HD58#
HD57#
F24
C26
B25
AA26
W26
U26
HVREF0
HVREF1
C4XAVDD
HD56#
HD55#
HD54#
HD53#
B26
D27
D26
E27
R26
L20
HVREF2
HVREF3
HVREF4
HD52#
HD51#
HD50#
B27
D28
C28
D22
C22
B22
HCOMP_P
HCOMP_N
HCOMPVREF_N
HD49#
HD48#
HD47#
HD46#
B28
E29
F28
B29
B6
F7
ST0
ST1
HD45#
HD44#
HD43#
C30
B30
B5
Y5
ST2
AAD0
HD42#
HD41#
B31
C32
W4
V2
AAD1
HD40#
D29
W6
AAD2
AAD3
HD39#
HD38#
C33
B33
V4
U2
AAD4
AAD5
HD37#
HD36#
B35
D32
V5
U4
AAD6
HD35#
B34
E31
R2
T4
AAD7
AAD8
AAD9
HD34#
HD33#
HD32#
D31
D33
R3
T5
AAD10
AAD11
HD31#
HD30#
D35
G31
P2
R4
AAD12
AAD13
HD29#
HD28#
C35
F33
N2
R6
AAD14
AAD15
HD27#
HD26#
E33
D34
L3
L4
AAD16
HD25#
E35
F32
K2
L6
AAD17
AAD18
HD24#
HD23#
J34
G34
J2
J3
AAD19
AAD20
AAD21
HD22#
HD21#
HD20#
H35
F35
K4
J4
AAD22
AAD23
HD19#
HD18#
J33
J31
J6
H4
AAD24
HD17#
G35
G3
H5
AAD25
AAD26
HD16#
HD15#
H33
J35
F2
G4
AAD27
AAD28
HD14#
HD13#
K32
N33
E2
G6
AAD29
AAD30
HD12#
HD11#
K33
L31
E3
AAD31
HD10#
HD9#
L33
K35
F4
SBA7
HD8#
L35
M35
D2
SBA6
SBA5
HD7#
HD6#
M33
F5
P32
E4
SBA4
SBA3
HD5#
HD4#
P33
B2
SBA2
HD3#
L34
E6
SBA1
HD2#
N34
B3
AC/BE3#
SBA0
AC/BE2# AC/BE1# AC/BE0#
AFRAME#
ADEVSEL#
AGP8XDET#
ADBIH/PIPE#
SB_STB#
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
AGPCOMP_P AGPCOMP_N
A1XAVDD
A1XAVSS
A4XAVDD
A4XAVSS
AGPVREF
AGPVSSREF
HDSTBN3# HDSTBN2# HDSTBN1# HDSTBN0#
HDSTBP3# HDSTBP2# HDSTBP1# HDSTBP0#
HD1#
HD0#
DBI3#
N35
P35
F26
AREQ# AGNT#
AIRDY#
ATRDY# ASERR#
ASTOP#
APAR RBF#
WBF#
ADBIL
SB_STB
AGPCLK
DBI2#
DBI1#
DBI0#
B32
E34
R31
K5
M5
P4
U6
C6
E8
N6
M4
N4
L2
P5
M2
N3
D7
B4
C7
C4
D6
C2
D3
T2
U3
G2
H2
D8
W2
Y2
B8
C8
A7
B7
W3
Y4
D24
F30
G33
N31
E25
D30
H32
M32
N755IA5 Rev : A Page 7 - 31
Page 19
Chapter2 Major Components
SIS648 MEMORY FOR DDR(U27B)
U27B
AN35
MD0
AP36
MD1
AK33
MD2
AM33
MD3
AN34
MD4
AK32
MD5
AR34
MD6
AN33
MD7
AR35
DQM0
AP34
AM32
AL31
AR31
AL30
AN32
AR33
AN31
AM31
AR32
AP32
AP30
AR30
AM29
AL27
AN30
AN29
AL28
AN28
AL29
AR29
AP26
AN25
AR24
AL24
AL25
AR26
AM25
AN24
AP24
AR25
AN21
AP20
AN20
AL18
AM21
AR21
AL19
AM19
AL20
AR20
AL15
AL14
AN15
AR15
AN16
AM15
AN14
AL13
AP16
AR16
AM13
AL12
AL11
AR12
AP14
AR14
AN13
AP12
AN12
AR13
AL10
AR11
AM9
AR9
AM11
AN11
AP10
AN9
AN10
AR10
DQS0/CSB0# MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 DQM1 DQS1/CSB1# MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 DQM2 DQS2/CSB2# MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 DQM3 DQS3/CSB3# MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 DQM4 DQS4/CSB4# MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 DQM5 DQS5/CSB5# MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 DQM6 DQS6/CSB6# MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 DQM7 DQS7/CSB7#
FWDSDCLKO
DDRCOMP_P
DDRCOMP_N
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8
MA9 MA10 MA11 MA12 MA13 MA14 MA15
SRAS# SCAS#
SWE#
CS0# CS1# CS2# CS3# CS4# CS5#
CKE0 CKE1 CKE2 CKE3 CKE4 CKE5
S3AUXSW#
SDRCLKI
DLLAVDD
DLLAVSS
DDRAVDD
DDRAVSS
DDRVREFA DDRVREFB
DRAM_SEL
AR23
AN23
AN22
AM23
AL23
AL26
AN26
AN27
AR27
AR28
AP22
AN18
AR22
AP28
AM27
AL33
AL17
AR19
AN19
AM17
AL16
AN17
AR17
AP18
AR18
AP4
AT3
AR3
AP3
AR2
AN4
AP2
AL21
AL22
AL35
AL34
AM35
AN36
AF16
AF23
AP1
AR8
AP8
648
N755IA5 Rev : A Page 8 - 31
Page 20
Chapter2 Major Components
SIS648 HYPERZIP (U27C)
U27C
AL6
AL4
AK5
AJ2
AE3
AJ3
AF2
AH5
AK2
AJ4
AJ6
AH2
AH4
AG3
AG6
AF4
AG2
AF5
AG4
AD2
AE6
AE2
AE4
AL3
AK4
AD5
AD4
AN1
AM2
AL2
AL1
ZCLK ZUREQ
ZDREQ ZSTB0
ZSTB1 ZSTB0#
ZSTB1# ZAD0
ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZAD16
ZVREF ZCOMP_N
ZCOMP_P
Z1XAVDD Z1XAVSS
Z4XAVDD Z4XAVSS
648
PCIRST#
PWROK
AN2
AM4
AN3
AUXOK
TRAP1
F9
TRAP0
D10
TESTMODE2
TESTMODE1
TESTMODE0
C9
B9
B10
E10
DLLEN#
ENTEST
D9
NC
NC NC NC
NC NC
NC NC
NC
NC NC NC
NC NC NC
NC NC
NC NC
NC NC
NC NC
B11
B12
B13
B14
B15
B16
C11
C13
C15
D11
D12
D13
D14
D15
D16
E12
E14
E16
F11
F13
F15
A11
A13
N755IA5 Rev : A Page 9 - 31
Page 21
Chapter2 Major Components
SIS648 POWER(U27D)
L25
L26
M18
M19
M20
M21
M22
M23
M24
M25
M26
N25
P25
R25
T25
U25
V25
W25
Y25
AA25
AL7
AL8
AL9
AM6
AM7
AM8
AN5
AN6
AN7
AN8
AP5
AP6
AP7
AR4
AR5
AR6
AR7
AT4
AT5
AT6
AT7
AB25
AC25
AD12
AD25
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF11
AF12
AF25
AF26
AB24
AC13
AD14
AD16
AD18
AD20
AD22
P14
P15
P16
P17
P18
P19
P20
P21
P22
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
A17
A18
A19
A20
A21
B17
B18
B19
B20
B21
C17
C18
C19
C20
C21
D17
D18
D19
D20
D21
E17
E18
E19
E20
E21
F17
F18
F19
F20
F21
N13
N14
N16
N18
N19
N20
N21
N22
N23
N24
P13
P24
R24
T13
T24
U24
V13
V24
W13
W24
Y13
Y24
AA24
AB13
AC24
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD3
AE1
AF3
AG1
AH3
AJ1
AK3
AM3
W11
W12
Y11
Y12
AA12
N15
R13
U13
AA13
C10
L17
M17
N17
A9
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD
VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ
IVDD IVDD IVDD
IVDD NC
NC VDD3.3 VDD3.3 VDD3.3
AUX1.8
AB12
VTT
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
AUX3.3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQNCNCNCNCNCNCNCNCNCNCNCVSS
AC12
AA1
AA2
AA3
AA4
AA5
AA6
AB1
AB2
AB3
AB4
AB5
AB6
AC1
AC2
AC3
AC4
AC5
AC6
L11
L12
L13
M11
M12
M13
M14
M15
M16
N11
N12
P12
R12
T12
U12
V12
D4
D5
AM5
AM34
A15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C12
C14
C16
E11
E13
E15
A3
A5
C1
C3
C5
E1
E5
E7
E9
F3
G1
G5
H3
J1
J5
K3
L1
VDDM
VDDM
VSS
VSS
L5
M3
VDDM
VSS
N1
N5
VDDM
VDDM
VSS
VSS
P3
R1
VDDM
VDDM
VSS
VSS
R5
T3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1
U5
V3
W1
W5
Y3
AE5
AG5
AJ5
P23
VSS
VSS
U27D
AA32
W19
VSS
VSS
AA36
VSS
VSS
W20
AB34
W21
VSS
VSS
W22
VSS
W23
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC32
AC36
AD34
AE32
AE36
AF34
AG32
AG36
AH34
AJ32
AM10
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AP9
AP11
AP13
AP15
AP17
AP19
AP21
AP23
AP25
AP27
AP29
AP31
AP33
AP35
AT8
AT10
AT12
AT14
AT16
AT18
AT20
AT22
AT24
AT26
AT28
AT30
AT32
AT34
AL32
648
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
W14
W15
W16
W17
W18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL5
A22
A24
A26
A28
A30
A32
A34
C23
C25
C27
C29
C31
C34
C36
E22
E24
E26
E28
E30
E32
E36
F34
G32
G36
H34
J32
J36
K34
L32
L36
M34
N32
N36
P34
R32
R36
T34
U32
U36
V34
W32
W36
Y34
N755IA5 Rev : A Page 10 - 31
Page 22
Chapter2 Major Components
DDR TERMINATION(U23A)
U23A
H29 H28
J29
J28 K29 K28 L29 L28
N28
P29 P28
R29 R28
T29 T28
U29 N25 R26
P25
R27 R25
T25 T26
U25
V27
W26 W25
Y26
Y25 AA26 AA25 AA27
N29
U28
P26
U26
AG30 AG28 AF28 AD26
M25
N26
V29
V28 W29 W28
AE26 AC26 AE29
M28
V25
AB29 AD28
AD29 AC28 AC29 AA28 AA29
Y28 Y29
AF29 AD27 AE28
AB28
M29
V26
M26 M27
AB26 AB25 AC25
AK21
AJ23 AJ22
AK22
AJ24
AK24 AG23
AG24 AK25
AJ25
AH28
AJ29
AH27
E8 B6
AE25
AG26 AH30 AH29 AG29
N755IA5 Rev : A Page 11 - 31
Part 1 of 5
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BE#0 C/BE#1 C/BE#2 C/BE#3
PCICLK RST# REQ# GNT# PAR STOP# DEVSEL# TRDY# IRDY# FRAME# INTA#
WBF# RBF#
AD_STBF_0 AD_STBF_1 SB_STBF
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7
ST0 ST1 ST2
SB_STBS ADSTBS_0 ADSTBS_1
AGPREF AGPTEST
DBI_LO DBI_HI AGP8X_DET#
R2SET C_R
Y_G COMP_B
H2SYNC V2SYNC
DDC3CLK DDC3DATA
SSIN SSOUT XTALIN XTALOUT TESTEN
TEST_YCLK(NC) TEST_MCLK(NC) PLLTEST(NC)
SUS_STAT# STP_AGP# AGP_BUSY# RSTB_MSK(NC)
PCI / AGPAGP2X4XDAC2SSCLK
AGP
8X
PWR
ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8
DVO / EXT TMDS / GPIOLVDSTMDSDAC1
ZV_LCDDATA9 ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
MAN
DVOMODE
(NC)VREFG TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DDC2CLK
DDC2DATA
DDC1DATA
DDC1CLK
AUXWIN
DMINUS
THERM
ATI_M10-P
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16
DIGON
BLON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
HPD1
HSYNC VSYNC
RSET
DPLUS
AJ5 AH5 AJ4 AK4 AH4 AF4 AJ3 AK3 AH3 AJ2 AH2 AH1 AG3 AG1 AG2 AF3 AF2
AE10 AH6
AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10
AJ10 AK10 AJ11 AH11
AG4 AK16
AH16 AH17 AJ16 AH18 AJ17 AK19 AH19 AK18 AJ18 AG16 AF16 AG17 AF17 AF18 AE18 AH20 AG20 AF19 AG19
AE12 AG12
AJ13 AH14 AJ14 AH15 AJ15 AK15 AH13 AK13
AE13 AE14
AF12 AK27
R
AJ27
G
AJ26
B
AG25 AH25
AH26 AF25
AF24 AF26
AF11 AE11
Page 23
Chapter2 Major Components
DDR TERMINATION (U23B)
U23B
L25
L26
K25
K26
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63
ATI_M10-P
Part 2 of 5
MEMORY INTERFACE
A
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8
MAA9 MAA10 MAA11
(MAA13)MAA12 (MAA12)MAA13
(NC)MAA14
DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA CLKA0
CLKA0#
CLKA1
CLKA1#
MVREFD
MVREFS
DIMA_0 DIMA_1
E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19
J25
F29
E25
A27
F15
C15
C11
E11
J27
F30
F24
B27
E16
B16
B11
F10
A19
E18
E19
E20
F20
B19
B21
C20
C18
A18
B7
B8
D30
B13
N755IA5 Rev : A Page 12 - 31
Page 24
Chapter2 Major Components
DDR TEMINATION(U23C)
U23C
D7
G6
G5
C4
C5
C2
D3
D1
D2
G4
H6
H5
G2
H2
H3
U6
U5
U3
W5
W4
Y6
Y5
U2
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
F7
E7
F5
E5
B5
A4
B4
J6
K5
K4
L6
L5
F3
E2
F2
J3
F1
V6
V2
V1
V3
DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63
ATI_M10-P
Part 3 of 5
(MAB13)MAB12 (MAB12)MAB13
MEMORY INTERFACE
B
MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8
MAB9 MAB10 MAB11
(NC)MAB14
DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7 RASB# CASB#
WEB# CSB0# CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB_0 DIMB_1
ROMCS#
MEMVMODE_0 MEMVMODE_1
MEMTEST
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
E6
B2
J5
G3
W6
W2
AC6
AD2
F6
B3
K6
G1
V5
W1
AC5
AD1
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
E3
AA3
AF5
C6
C7
C8
N755IA5 Rev : A Page 13 - 31
Page 25
Chapter2 Major Components
DDR TEMINATION (U23D)
U23D
T7
VDDR1
R4
VDDR1(CLKBFB)
R1
VDDR1
N8
VDDR1
N7
VDDR1
M4
VDDR1
L27
VDDR1
L8
VDDR1
J24
VDDR1
J23
VDDR1
J8
VDDR1
J7
VDDR1
J4
VDDR1
J1
VDDR1
H10
VDDR1
H13
VDDR1
H15
VDDR1
H17
VDDR1
T8
VDDR1
V4
VDDR1
V7
VDDR1
V8
VDDR1
AA1
VDDR1
AA4
VDDR1
AA7
VDDR1
AA8
VDDR1
A3
VDDR1
A9
VDDR1
A15
VDDR1
A21
VDDR1
A28
VDDR1
B1
VDDR1
B30
VDDR1
D26
VDDR1
D23
VDDR1
D20
VDDR1
D17
VDDR1
D14
VDDR1
D11
VDDR1
D8
VDDR1
D5
VDDR1
E27
VDDR1
F4
VDDR1
G7
VDDR1
G10
VDDR1
G13
VDDR1
G15
VDDR1
G19
VDDR1
G22
VDDR1
G27
VDDR1
H22
VDDR1
H19
VDDR1
AD4
VDDR1
T4
VDDR1
N4
VDDR1
D19
VDDR1(CLKAFB)
D13
VDDR1
AE17
LVDDR_25(LVDDR18_25)
AE20
LVDDR_25(LVDDR18_25)
AE15
LVDDR_18
AF21
LVDDR_18
AJ20
LPVDD
AK12
TPVDD
AF13
TXVDDR
AF14
TXVDDR
F18
VDDRH0
N6
VDDRH1
AG21
A2VDD
AH21
A2VDD
AF22
A2VDDQ
AH24
AVDD
AE24
VDD1DI
AE22
VDD2DI
AK28
PVDD
A7
MPVDD
ATI_M10-P
Part 4 of 5
I/O
VDDC VDDC VDDC VDDC VDDC
(VDDC18)VDD15 (VDDC18)VDD15 (VDDC18)VDD15 (VDDC18)VDD15 (VDDC18)VDD15 (VDDC18)VDD15 (VDDC18)VDD15 (VDDC18)VDD15
VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR4 VDDR4 VDDR4 VDDR4 VDDR4
VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP
AVSSQ LVSSR
LVSSR LVSSR LVSSR
LPVSS TPVSS
TXVSSR TXVSSR TXVSSR
VSSRH0
POWER
VSSRH1
A2VSSN A2VSSN A2VSSQ
AVSSN VSS1DI VSS2DI
PVSS
MPVSS
AC13 AD13 AD15 AC15 AC17
P8 Y8 AC11 AC20 Y23 L23 H20 H11
AD7 AD19 AD21 AD22 AC22 AC21 AC19 AC8 AG7 AD9 AC9 AC10 AD10
J30 AF27 AE30 AC27 AC23 AB30 AA24 AA23 Y27 W30 V23 V24 M23 M24 N30 P23 P27 T23 T24 T30 U27
AD24 AF20
AE19 AE16 AF15
AJ19 AJ12
AH12 AG13 AG14
F19 M6 AH22 AJ21 AF23 AH23 AE23 AE21 AJ28 A6
N755IA5 Rev : A Page 14 - 31
Page 26
Chapter2 Major Components
DDR TERMINATION(U21)
U21
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
M7
N2
M2
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J10
K5
K10
K6
K7
K8
K9
L10
L6
L2
L3
L9
J5
L5
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 15 - 31
Page 27
Chapter2 Major Components
DDR TERMINATION(U20)
U20
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N2
M2
L2
L3
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
L9
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
K6
K7
K8
K9
L5
L10
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 16 - 31
Page 28
Chapter2 Major Components
DDR TERMINATION(U4)
U4
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
M7
N2
M2
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J10
K5
K10
K6
K7
K8
K9
L10
L6
L2
L3
L9
J5
L5
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 17 - 31
Page 29
Chapter2 Major Components
DDR TERMINATION(U5)
U5
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
M7
N2
M2
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J10
K5
K10
K6
K7
K8
K9
L10
L6
L2
L3
L9
J5
L5
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 18 - 31
Page 30
Chapter2 Major Components
DDR TERMINATION(U22)
U22
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
M7
N2
M2
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J10
K5
K10
K6
K7
K8
K9
L10
L6
L2
L3
L9
J5
L5
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 19 - 31
Page 31
Chapter2 Major Components
DDR TERMINATION(U24)
U24
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
M7
N2
M2
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J10
K5
K10
K6
K7
K8
K9
L10
L6
L2
L3
L9
J5
L5
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 20 - 31
Page 32
Chapter2 Major Components
DDR TERMINATION(U6)
U6
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
M7
N2
M2
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J10
K5
K10
K6
K7
K8
K9
L10
L6
L2
L3
L9
J5
L5
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 21 - 31
Page 33
Chapter2 Major Components
DDR TERMINATION(U9)
U9
N4
M5
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N2
M2
L2
L3
M11
M12
N12
N13
B2
H13
H2
B13
B3
H12
H3
B12
L9
M10
M13
N3
M4
M3
L13
L12
H11
H4
C11
C4
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
K6
K7
K8
K9
L5
L10
BA0 BA1
A0 A1 A2 A3 A4 A5 A6 A7 A8(AP) A9 A10 A11
CS
RAS
CAS
WE
CLK CLK# CKE VREF DQS0
DQS1 DQS2 DQS3
DQM0 DQM1 DQM2 DQM3
NC/TH1 NC/TH2 MCL
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS
K4D263238A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
D7
D8
E4
E11
L4
L11
L7
L8
C5
C3
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
E10
E8
E7
E5
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
N755IA5 Rev : A Page 22 - 31
Page 34
Chapter2 Major Components
SIS963 HYPERZIP&PCI&IDE(U32A)
J5
J4
H2
H1
J3
K4
J2
J1
K5
K2
L3
K1
L1
L4
L5
L2
N5
P2
P3
P4
R2
R3
R1
T1
P5
T2
U1
U2
T3
R5
U3
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H5
H3
G1
G2
G3
H4
M4
R4
G4
M3
M1
M2
N4
M5
N3
N1
N2
Y2
C3
V20
M19
J20
N20
K20
N16
N17
R19
N18
R18
P18
U20
U19
T20
T19
R20
P20
F1
F2
E1
F3
K3
P1
E3
F4
E2
PREQ4# PREQ3# PREQ2# PREQ1# PREQ0#
PGNT4# PGNT3# PGNT2# PGNT1# PGNT0#
C/BE3# C/BE2# C/BE1# C/BE0#
INTA# INTB# INTC# INTD#
FRAME# IRDY# TRDY# STOP#
SERR# PAR DEVSEL# PLOCK#
PCICLK PCIRST#
ZCLK ZSTB0
ZSTB1 ZSTB0#
ZSTB1#
ZUREQ ZDREQ
VDDZCMP ZCMP_N
ZCMP_P VSSZCMP
Z1XAVDD Z1XAVSS
Z4XAVDD Z4XAVSS
ZVREF ZAD16
AD31
ZAD0
M18
AD30
ZAD1
N19
M17
AD29
AD28
ZAD2
ZAD3
M16
AD27
ZAD4
M20
AD26
ZAD5
L16
L20
AD25
AD24
ZAD6
ZAD7
L18
K18
AD23
AD22
ZAD8
ZAD9
K19
AD21
ZAD10
K17
AD20
ZAD11
K16
H20
AD19
AD18
ZAD12
ZAD13
J18
AD17
ZAD14
H19
AD16
ZAD15
H18
AD15
AD14
AD13
AD12
AD11
AD10
V1
AD1
AD0
IDEAVDD
IDEAVSS
ICHRDYA
IDREQA
IIRQA
CBLIDA
IIORA#
IIOWA#
IDACKA#
IDSAA2 IDSAA1 IDSAA0
IDECSA1# IDECSA0#
ICHRDYB
IDREQB
IIRQB
CBLIDB
IIORB#
IIOWB#
IDACKB#
IDSAB2 IDSAB1 IDSAB0
IDECSB1# IDECSB0#
IDA0 IDA1 IDA2 IDA3 IDA4 IDA5 IDA6 IDA7 IDA8
IDA9 IDA10 IDA11 IDA12 IDA13 IDA14 IDA15
IDB0
IDB1
IDB2
IDB3
IDB4
IDB5
IDB6
IDB7
IDB8
IDB9 IDB10 IDB11 IDB12 IDB13 IDB14 IDB15
U32A
Y3
Y4
W10
V10
Y11
U12
V11
Y9
Y10
T11
U11
W11
T12
V12
W17
Y17
T16
U17
T14
W16
V16
Y18
T15
V17
U16
W18
U10
V9
W8
T9
Y7
V7
Y6
Y5
W6
U8
W7
V8
U9
Y8
T10
W9
Y16
V15
U14
W14
V13
T13
Y13
Y12
W12
W13
U13
Y14
V14
W15
Y15
U15
963
N755IA5 Rev : A Page 23 - 31
Page 35
Chapter2 Major Components
SIS963(LGPIO&HOST&LPC&APIC&AC97&MII&ACPI)(U32B)
U32B
TXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
RXCLK
RXDV
RXER
RXD0
RXD1
RXD2
RXD3
A8 A9 A6
B6
E8
D7
C6
B4
A7
C7
C8
D8
A5
B5
A4
T18
INIT#
P16
A20M#
R17
SMI#
R16
INTR
Y20
NMI
U18
IGNNE#
T17
FERR#
W20
STPCLK#
V19
CPUSLP#
Y19
APICCK/LDTREQ#
V18
APICD0/THERM2#
W19
APICD1/GPIOFF#
V5
LAD0
T7
LAD1
U6
LAD2
W5
LAD3
W4
LFRAME#
U7
LDRQ#
V6
SIRQ
C2
OSC32KHI
D2
OSC32KHO
D3
BATOK
D1
PWROK
C1
RTCVDD
E4
RTCVSS
OSC25MHI
OSC25MHO
A14 B14 D14
A15
E13
A16
D13
B15
W2
W3
B2 A1
A2 D5
T5
D6 Y1
G5 V3
A3
B1
E5
GPIO20 GPIO19
AC_SDIN0 AC_SDIN1
AC_SDOUT AC_SYNC
AC_RESET# AC_BIT_CLK
OSCI ENTEST SPK
PWRBTN# PME# PSON#
AUXOK ACPILED
GPIO13
GPIO14
GPIO15/KBDAT
GPIO16/KBCLK
GPIO17/PMDAT
GPIO18/PMCLK
COL
CRS
MDC
MDIO
MIIAVDD
MIIAVSS
GPIO0
GPIO1/LDRQ1#
GPIO2/THERM#
GPIO3/EXTSMI#
GPIO4/CLKRUN#
GPIO5/PREQ5#
GPIO6/PGNT5#
GPIO7
GPIO8/RING
GPIO9/AC_SDIN2
GPIO10/AC_SDIN3
GPIO11/OSC25M/STP_PCI#
GPIO12/CPUSTP#
963
B7
E9
C5
E7
B9 B8
V2
T8
T4
T6
W1
U5
U4
C4
C14
E6
B3
F5
D4
N755IA5 Rev : A Page 24 - 31
Page 36
Chapter2 Major Components
SIS963 POWER&USB&USB&1394(U32C)
V4
USBCLK48M
B18
UV0+
C18
UV0-
D18
UV1+
D19
UV1-
E14
UV2+
D15
UV2-
E18
UV3+
F18
UV3-
E16
UV4+
E15
UV4-
G18
UV5+
G19
UV5-
G20
OC0#
G17
OC1#
J16
OC2#
H16
OC3#
H17
OC4#
G16
OC5#
D16
USBVDD
D17
USBVDD
E17
USBVDD
F17
USBVDD
F19
USBVSS
E19
USBVSS
B19
USBVSS
B17
USBVSS
A12
D0
B12
D1
C12
D12
E12
A13
B13
C13
D11
C11
D2
D3
D4
D5
D6
D7 CTL0 CTL1
IPB_OUT0/PLLENN
IPB_OUT1/ZCLKSEL
SCLK
LINKON
LREQ
LPS
GPIO21/EESK
GPIO22/EEDI
GPIO23/EEDO
GPIO24/EECS
OSC12MHI
OSC12MHO
USBREF
USBPVDD
USBPVSS
IVDD_AUX IVDD_AUX
IPBRST#
TDFRAME
RDFRAME
IPB_RDCLK
IPB_TDCLK
IPB_IN0
IPB_IN1
USBREFAVDD
U32C
E11
C19
A19
A20
F20
D20
E20
C20
B16
A17
F16
A18
C15
C16
C17
B11
D10
A11
E10
D9
B10
A10
C10
C9
B20
963
N755IA5 Rev : A Page 25 - 31
Page 37
Chapter2 Major Components
SIS963(U32D)
U32D
G15
J15
J19
L15
L19
N15
P19
K15
G6
H15
M15
R6
R10
R14
P15
R15
H6
M6
R7
R9
R11
R13
N6
R8
R12
F12
F10
F11
F14
F15
F13
L6
K6
P6
J6
F9
F7
F8
VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ VDDZ PVDDZ IVDD IVDD IVDD IVDD IVDD IVDD IVDD
VTT VTT
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
PVDD PVDD PVDD PVDD
IVDD_AUX IVDD_AUX
OVDD_AUX OVDD_AUX OVDD_AUX OVDD_AUX OVDD_AUX
PVDD_AUX PVDD_AUX
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSZ VSSZ VSSZ VSSZ VSSZ VSSZ VSSZ VSSZ VSSZ VSSZ
H8
H9
H10
H11
H12
H13
J8
J9
J10
J11
J12
K8
K9
K10
K11
L8
L9
L10
L11
M8
M9
M10
M11
N8
N9
N10
N11
N12
N13
J13
J17
K12
K13
L12
L13
L17
M12
M13
P17
RTL8201BL(U13)
8
DVDD
DGND
11
14
DVDD
DGND
17
AGND
29
U13
2
TXEN
7
TXC
6
TXD0
5
TXD1
4
TXD2
3
TXD3
25
MDC
26
MDIO
22
RXDV
21
RXD0
20
RXD1
19
RXD2
18
RXD3
16
RXC
1
COL
23
CRS
24
RXER
46
X1
47
X2
42
RESETB
RTL8201BL
32
36
48
AVDD0
AVDD1
LED0/PHYA0 LED1/PHYA1 LED2/PHYA2 LED3/PHYA3 LED4/PHYA4
AGND
AGND
35
45
MII/SNIB
PLLVDD
DUPLEX
SPEED
TPRX+
ISOLATE
RTSET
LDPS
ANE
TPRX-
TPTX-
TPTX+
RTT3
REPT
963
44
41
37
38
39
31
30
33
34
27
40
43
28
9
10
12
13
15
N755IA5 Rev : A Page 26 - 31
Page 38
Chapter2 Major Components
SMART POWER IC(U80
U8
24
SN74CBT3384A
3
4
1A2 1B2
7
8
1A4 1B4
1
4
2A1 2B1
7
8
2A3 2B3
1
2
2A5 2B5
1
1OE#
3
2OE#
2
VCC
GND
2
1B11A1
5
6
1B31A3
9
10
1B51A5
15
16
2B22A2
19
20
2B42A4
23
IEEE1394PHY(U14)
7
17
26
57
62
27
30
31
43
50
51
U14
10
11
12
13
16
24
18
23
63
20
21
22
15
60
59
5
6
8
9
3
4
1
DVDD
D0 D1 D2 D3 D4 D5 D6 D7
CTL0 CTL1
LREQ LPS CPS
C/LKON ISO#
SYSCLK PC0
PC1 PC2 CNA
XO XI
DVSS
2
14
DVDD
DVSS
25
DVDD
DVSS
29
DVDD
DVSS
58
DVDD
DVSS
64
TEST2
DVSS
TEST1
28
AVDD
AVSS
32
AVDD
AVSS
49
AVDD
AVSS
53
AVDD
PDISABLE
RESET#
AVSS
54
52
PLLVDD
TBIAS0
TPA0
TPA0-
TPB0
TPB0-
TBIAS1
TPA1
TPA1-
TPB1
TPB1-
TBIAS2
TPA2
TPA2-
TPB2
TPB2-
BTSET
PLLGND
PLLGND
FW802A
56
37
36
35
34
33
42
41
40
39
38
48
47
46
45
44
19
55
61
N755IA5 Rev : A Page 27 - 31
Page 39
Chapter2 Major Components
OZ MICRO(U17)
14
86
102
122
138
73
71
74
U17 OZ711M1TQFP
63
AUX_VCC
18
PCI_VCC
30
PCI_VCC
50
PCI_VCC
3
AD31
4
AD30
5
AD29
7
AD28
8
AD27
9
AD26
10
AD25
11
AD24
15
AD23
16
AD22
17
AD21
19
AD20
23
AD19
24
AD18
25
AD17
26
AD16
38
AD15
39
AD14
40
AD13
41
AD12
43
AD11
45
AD10
46
AD9
47
AD8
49
AD7
51
AD6
52
AD5
53
AD4
54
AD3
55
AD2
56
AD1
57
AD0
12
C/BE3#
27
C/BE2#
37
C/BE1#
48
C/BE0#
13
IDSEL
21
PCI_CLK
32
DEVSEL#
28
FRAME#
29
IRDY#
31
TRDY#
33
STOP#
36
PAR
34
PERR#
35
SERR#
1
REQ#
2
GNT#
20
PCI_RST#
66
GRST#
62
SPKR_OUT#
59
RI_OUT#/PME#
69
MF6 (CLKRUN#)
67
MF4 (RI_OUT#)
65
MF3 (SIRQ#)
60
MF0 (INTA#)
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
SCLK/VCC3#
SDATA/VCC5#
SLATCH/VPP_PGM
SKT_VCC SKT_VCC
CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10
CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0
CCLK
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR CPERR# CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2 CCD1# CCD2#
CAUDIO
CSTSCHG
CC/BE3# CC/BE2# CC/BE1# CC/BE0#
90
126
144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76
108
111
110
109
107
105
101
104
133
123
106
132
103
136
119
143
84
100
131
117
75
137
134
135
125
112
99
88
GND
GND
GND
GND
GND
GND
GND
GND
DCD#
DFCB/DWP
DSRST#/DCMD/DBS
DSIO/DDATA0/DSDIO
DCLK
ODR_VCC
6
22
42
58
78
94
114
130
44
64
68
61
72
70
N755IA5 Rev : A Page 28 - 31
Page 40
Chapter2 Major Components
AUDIO CODEC(U36
2
3
11
6
10
5
8
12
13
14
15
16
17
18
20
21
22
23
24
XTL-IN XTL-OUT
RESET# BITCLK SYNC SDOUT SDIN
PC-BEEP PHONE AUX-L AUX-R VIDEO-L VIDEO-R CD-L CD-R MIC1 MIC2 LINE-L LINE-R
4
GND
7
GND
1
VDD
CD-GND
19
9
25
38
VDD
AVDD
AVDD
JD/CENTER-OUT
HP-OUT-L/SURR-OUT-L
HP-OUT-R/SURR-OUT-R
AGND
AGND
26
ALC650 / CMI 9738
42
LINEOUT-L LINEOUT-R MONO-OUT
VREF
VREFOUT
AFILT1 AFILT2
VRAD VRDA
NC/LFE-FILT
TEST1/LEF-OUT
ID#1/XTLSEL
EAPD/SPDIFI
NC
ID#0/GPIO0
NC
SPDIFO
U36
35
36
37
27
28
29
30
31
32
33
34
43
44
45
46
47
39
40
41
48
AMP & SPKR(U35)
3
7
SEDIFF
GND
18
VDD
AGND
17
11
ROUT+
VDD
VDD
ROUT-
SE/BTL#
LOUT-
LOUT+
BYPASS
24
2
23
12
14
TPA6011A4
5
RLINEIN
4
RHPIN
6
RIN
8
LIN
10
LHPIN
9
LLINEIN
15
SHUTDOWN#
16
FADE#
22
HP/LINE#
U35
19
20
21
SEMAX
VOLUME
GND
1
13
N755IA5 Rev : A Page 29 - 31
Page 41
Chapter2 Major Components
PC87591VPC(U30)
166
U30
7
SERIRQ
8
LDRQ
9
LFRAME
15
LAD0
14
LAD1
13
LAD2
10
LAD3
18
LCLK
19
LRST1
22
SMI
23
PWUREQ
31
IOPD3/ECSCI
5
GA20/IOPB5
6
KBRST/IOPB6
71
KBSIN0
72
KBSIN1
73
KBSIN2
74
KBSIN3
77
KBSIN4
78
KBSIN5
79
KBSIN6
80
KBSIN7
49
KBSOUT0
50
KBSOUT1
51
KBSOUT2
52
KBSOUT3
53
KBSOUT4
56
KBSOUT5
57
KBSOUT6
58
KBSOUT7
59
KBSOUT8
60
KBSOUT9
61
KBSOUT10
64
KBSOUT11
65
KBSOUT12
66
KBSOUT13
67
KBSOUT14
68
KBSOUT15
105
TINT
106
TCK
107
TDO
108
TDI
109
TMS
110
PSCLK1/IOPF0
111
PSDAT1/IOPF1
114
PSCLK2/IOPF2
115
PSDAT2/IOPF3
116
PSCLK3/IOPF4
117
PSDAT3/IOPF5
118
PSCLK4/IOPF6
119
PSDAT4/IOPF7
158
32KX1/32KCLKIN
160
32KX2
62
IOPJ2/BST0
63
IOPJ3/BST1
69
IOPJ4/BST2
70
IOPJ5/PFS
75
IOPJ6/PLI
76
IOPJ7/BRKL_RSTO
148
IOPM0/D8
149
IOPM1/D9
155
IOPM2/D10
156
IOPM3/D11
3
IOPM4/D12
4
IOPM5/D13
27
IOPM6/D14
28
IOPM7/D15
173
SEL0
174
SEL1
47
CLK
157
136
123
45
34
16
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
95
AVCC
GPI
GPI/O INT-H
GPI/O INT-H
GPI/O
INT-H GPI INT-H
GPI/O INT-H
IOPB7/RING/PFAIL/LRST2
GPO
GPI/O INT-H
GPI
INT-H
GPI/O INT-H
IOPC4/TB1/EXWINT22 IOPC6/TB2/EXWINT23
IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPD2/EXWINT24/LRST2
IOPE6/LPCPD/EXWINT45
IOPE7/CLKRUN/EXWINT46
GPI/O
GPI/O INT-H
GPI/O
GPI/O
GPI/O INT-H
GPI/O
GPI/O GPI/O
GPI/O
161
VBAT
IOPE0AD4 IOPE1/AD5 IOPE2/AD6 IOPE3/AD7
DP/AD8
DN/AD9
IOPA0/PWM0 IOPA1/PWM1 IOPA2/PWM2 IOPA3/PWM3 IOPA4/PWM4 IOPA5/PWM5 IOPA6/PWM6 IOPA7/PWM7
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1 IOPC5/TA2
IOPC7/CLKOUT
IOPE4/SWIN
IOPE5/EXWINT40
IOPH0/A0/ENV0
IOPH1/A1/ENV1 IOPH2/A2/BADDR0 IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6 IOPH7/A7
IOPI0/D0 IOPI1/D1 IOPI2/D2 IOPI3/D3 IOPI4/D4 IOPI5/D5 IOPI6/D6 IOPI7/D7
IOPJ0/RD
IOPJ1/WR0
SELIO
IOPD4 IOPD5 IOPD6 IOPD7
IOPK0/A8
IOPK1/A9 IOPK2/A10 IOPK3/A11 IOPK4/A12
IOPK5/A13/BE0 IOPK6/A14/BE1
IOPK7/A15/CBRD
IOPL0/A16 IOPL1/A17 IOPL2/A18 IOPL3/A19
IOPL4/WR1
AD0 AD1 AD2 AD3
DA0 DA1 DA2 DA3
81
82
83
84
87
88
89
90
93
94
99
100
101
102
32
33
36
37
38
39
40
43
153
154
162
163
164
165
168
169
170
171
172
175
176
1
26
29
30
2
44
24
25
124
125
126
127
128
131
132
133
138
139
140
141
144
145
146
147
150
151
152
41
42
54
55
143
142
135
134
130
129
121
120
113
112
104
103
48
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
PC87591VPC
17
GND1
GND2
35
46
GND3
GND4
122
159
GND6
GND5
167
137
GND7
NC1
AGND
11
96
86
85
21
20
12
NC10
98
97
92
91
N755IA5 Rev : A Page 30 - 31
Page 42
Chapter2 Major Components
011
FLASH ROM(U26)
U26
12
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5
A7
27
A8
26
A9
23
A10
25
A11
4
A12
28
A13
29
A14
3
A15
2
A16
30
A17
1
A18
VCC
O0 O1 O2 O3 O4 O5 O6 O7
WE#
OE
CE
VSS
32
13
14
15
17
18
19
20
21
31
24
22
16
Flash ROM
CHARGER IC TL594 (PU4)
PU4
123
TL594
VCCOUT-CTRL
4
REF
1
1IN+
2
1IN-
3
FB
6
2IN+
5
2IN-
GND
C1
E1
C2
E2
DTC
CT RT
8 9
1 4
5 6
CPU CORE(PU20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PU2
VID1 PLLIN PLLFLTR FCB IN+ IN­DIFFOUT EAIN SGND SENSE1+ SENSE-1 SENSE2+ SENSE2­SENSE3­SENSE3+ RUN/SS Ith VID2
LTC3732CG
VID0
PGOOD
BOOST1
TG1
SW1
BOOSt2
TG2
SW2
Vcc
BG1
PGND
BG2 BG3
SW3
TG3
BOOST3
VID4 VID3
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
N755IA5 Rev : A Page 31 - 31
Page 43
Chapter2 Major Components
PC87391(U1)
15
LAD0
16
LAD1
17
LAD2
18
LAD3
8
LCLK
9
LRESET#
12
LFRAME#
11
LDRQ#
7
LPCPD#
6
CLKRUN#
10
SERIRQ
19
SMI#
20
CLKIN
21
DSKCHG#
22
HDSEL#
23
RDATA#
24
WP#
25
TRK0#
26
WGATE#
27
WDATA#
28
SETP#
29
DIR#
30
DR0#
31
MTR0#
32
INDEX#
33
DENSEL
34
DRATE0/IRSL2
95
NC
94
NC
93
NC
92
NC
91
NC
90
XCNF2
87
NC
86
NC
85
NC
84
MTR1#
83
NC
82
NC
81
RI2#
80
DTR2#_BOUT2
79
CTS2#
78
SOUT2
77
RTS2#
76
SIN2
75
DSR2#
74
DCD2#
14
39
63
88
VDD
VDD
VDD
VDD
PC87391
U1
PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
SLCT/WGATE#
BUSY_WAIT#/MTR1#
SLIN#_ASTRB#/STEP#
AFD#_DSTRB#/DENSEL
ERR#/HDSEL#
STB#_WRITE#
SOUT1/XCNF0
DTR1#_BOUT1/BADDR
IRSL3/PWUREQ#
MTR1#/DRATE0
PNF
PE/WDATA#
ACK#/DR1#
INIT#/DIR#
DCD1#
DSR1#
SIN1
RTS1#/TEST
CTS1#
RI1#
IRTX
IRRX1
IRRX2_IRSL0
IRSL1
NC NC NC NC NC NC NC NC NC
NC
WDO#
IRSL2/DR1#
DR1#
52
50
48
46
45
44
43
42
35
36
37
40
41
47
49
51
53
54
55
56
57
58
59
60
61
62
70
69
68
67
66
65
3
2
1
100
99
98
97
96
4
5
73
71
72
VSS
VSS
VSS
VSS
13
38
64
89
PC87391
N755IA5 Rev : A Page 32 - 31
Page 44
Chapter2 Major Components
1
2
5
2
3
4
0
9
7
6
8
1
MAX1902(PU5)
2
5
BST3
7
DH3
V+
2
VL
12OUT
VDD
BST5
4
5
1
6
4
1
2
3
0
3
7
8
LX3
DL3
CSH3
CSL3
FB3
SKIP#
SHDN#
TIME/ON5
RUN/ON3
MAX1902
1.8 AUX(PU7)
PU5
GND
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RESET#
1
1
1
2
1
1
1
1
9
6
1
PU7
6
VC
2
4
7
8
IRU3037
VCC
GND
Comp
SS
Hdrv
Ldrv
FB
5
3
1
N755IA5 Rev : A Page 33 - 31
Page 45
Chapter2 Major Components
1.8 AUX(PU6)
6
VC
5
Hdrv
3
Ldrv
1
FB
2
4
7
8
PU6
VCC
GND
Comp
SS
IRU3037
2.5V / 1.25 / 1.2V(PU8)
PU8
2
VCC
4
GND
6
VC
5
Hdrv
3
Ldrv
7
Comp
1
8
IRU3037A
SS
FB
2.5V / 1.25 / 1.2V(PU10)
PU10
2
VCC
4
GND
7
Comp
8
SS
6
VC
5
Hdrv
3
Ldrv
1
FB
IRU3037
N755IA5 Rev : A Page 34 - 31
Page 46
Chapter2 Major Components
2.3 CONNECTOR DEFINITION: DDR CONN.(CN30)
143
VDDQ
GND
155
VDDQ
GND
157
VDDQ
GND
179
167
VDDQ
GND
191
10
VDD
VDDQ
GND
GND
22
VDD
GND
34
VDD
GND
36
VDD
GND
46
VDD
VDD
GND
GND
58
70
VDD
GND
VDD
GND
112
111
110
109
108
107
106
105
102
101
115
100
117
116
121
122
134
148
170
184
119
120
118
160
158
133
147
169
183
193
195
194
196
198
199
197
123
124
200
99
97
98
12
26
48
62
78
96
95
35
37
89
91
11
25
47
61
77
1
2
86
85
9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP
A11 A12 DU/A13
BA0 BA1
DU/BA2 CS0
CS1
DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8
WE
CAS
RAS
CKE0 CKE1
CK0 CK0
CK1 CK1
CK2
CK2
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
SDA SCL
SA0 SA1 SA2 VREF VREF VDDID VDDSPD
NC//DU/RESET
NC/DU NC/DU NC/DU NC/DU
VDDQ
GND
21
VDDQ
GND
33
45
VDDQ
GND
57
69
VDDQ
VDDQ
GND
GND
81
93
VDDQ
VDDQ
GND
GND
113
131
VDDQ
VDDQ
GND
GND
VDDQ
GND
82
92
VDD
GND
94
VDD
VDD
GND
GND
114
132
VDD
GND
144
VDD
GND
156
VDD
GND
168
VDD
VDD
GND
GND
180
192
VDD
GND
GND
CN30
VDDQ
D0 D1 D2 D3 D4 D5 D6 D7 D8
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
GND
GND
5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190
71
73
79
83
72
74
80
84
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
138
150
162
3
126
174
186
201
202
DDR CONN
N755IA5 Rev : A Page 35 - 31
Page 47
Chapter2 Major Components
DDR CONN.(CN29)
143
VDDQ
GND
155
157
VDDQ
GND
179
167
VDDQ
VDDQ
GND
GND
191
10
VDD
VDDQ
GND
GND
22
VDD
GND
34
VDD
VDD
GND
GND
36
46
VDD
GND
58
VDD
VDD
GND
GND
70
82
VDD
GND
112
111
110
109
108
107
106
105
102
101
115
100
117
116
121
122
134
148
170
184
119
120
118
160
158
133
147
169
183
193
195
194
196
198
199
197
123
124
200
99
97
98
12
26
48
62
78
96
95
35
37
89
91
11
25
47
61
77
1
2
86
85
9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP
A11 A12 DU/A13
BA0 BA1
DU/BA2 CS0
CS1
DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8
WE
CAS
RAS
CKE0 CKE1
CK0 CK0
CK1 CK1
CK2
CK2
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
SDA SCL
SA0 SA1 SA2 VREF VREF VDDID VDDSPD
NC//DU/RESET
NC/DU NC/DU NC/DU NC/DU
VDDQ
GND
21
33
VDDQ
GND
45
57
VDDQ
VDDQ
GND
GND
69
81
VDDQ
VDDQ
GND
GND
93
113
VDDQ
VDDQ
GND
GND
131
VDDQ
VDDQ
GND
GND
92
VDD
GND
94
VDD
GND
114
VDD
GND
132
VDD
GND
144
VDD
GND
156
VDD
GND
168
VDD
GND
180
VDD
GND
192
VDD
GND
CN29
VDDQ
GND
D0 D1 D2 D3 D4 D5 D6 D7 D8
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
GND
GND
5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190
71
73
79
83
72
74
80
84
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
138
150
162
3
126
174
186
201
202
DDR CONN
N755IA5 Rev : A Page 36 - 31
Page 48
Chapter2 Major Components
S-VIDEO TV(CN14)
D2
C458 270p
NPO
*DA204U
2
3
3
1
D1 *DA204U
C476
33p
NPO
C457 270p
L55
QT1608RL060
C479 100p
NPO
+3V
TVY14
TVC14
R310
R312
75_1%
75_1%
C460
33p
NPO
L52
QT1608RL060
C459 100p
NPO NPO
LVDS CONN.(CN1)
+3V
1
SYout
CN14 S-VIDEO
SCout
2
34
12
5
6
5
6
CN1
12 34 56 78 910 11 12 13 14 15 16 17
18
19
20
21
22
23
24 25 26 27 28 29 30
LVDS
C488
C484
C482
C501
*33p
*33p
*33p
NPO NPO NPO NPO NPONPO NPO
*33p
C502
*33p
C13
*33p
INVERTER CONN.(CN2)
SPKR1-29 SPKR1+29 SPKL1+29
SPKL1-29
L107 QT1608RL060
L108 QT1608RL060
L109 QT1608RL060
L110 QT1608RL060
C483
*33p
CN2
INVERTER
1 2 3 4 5
+
-
­+
6 7 8 9 10
C773
C774
C775
C776
680p
680p
680p
X7R X7R X7R X7R
680p
N755IA5 Rev : A Page 37 - 31
Page 49
Chapter2 Major Components
HDD CONN.(CN33)
V_HDD
HDD/CDROM_RST#23
IDEREQA22
IDEIOW#A22
IDEIOR#A22 ICHRDYA22
IDACK#A22 IDEIRQA22 IDESAA122 IDESAA022
IDECS#A022
IDELED#30
HDD/CDROM_RST# IDEDA7 IDEDA6 IDEDA5 IDEDA4 IDEDA3 IDEDA2 IDEDA1 IDEDA0
A
BAS16
*10K
C
D17
R521
CN33
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
45
46
HDD CONN
V_HDD
IDEDA8 IDEDA9 IDEDA10 IDEDA11 IDEDA12 IDEDA13 IDEDA14 IDEDA15
R516 470
R525 *1K
CBLIDA 22 IDESAA2 22 IDECS#A1 22
CDROM CONN.(CN28)
CN28 CDROM CONN
CD_L29
CDGND29
C288
*1000p
X7R
UV3+24
R167
100K
IDEIOW#B22
ICHRDYB22
IDEIRQB22 IDESAB122 IDESAB022
IDECS#B022
IDELED#30
C205 47p
NPO NPO
R166 1K_1%
R157 0_0603
L29
0_0603
L24 0
HDD/CDROM_RST# IDEDB7 IDEDB6 IDEDB5 IDEDB4 IDEDB3 IDEDB2 IDEDB1 IDEDB0
A
*10K
D7
BAS16
R136
C
R124 470
51 12
34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
46
45
48
47
50
49 525354
55
56
R159
IDEDB8 IDEDB9 IDEDB10 IDEDB11 IDEDB12 IDEDB13 IDEDB14 IDEDB15
1K_1%
R160
100K
IDEREQB 22 IDEIOR#B 22
IDACK#B 22 CBLIDB 22
IDESAB2 22 IDECS#B1 22
R134 *1K
L23 0
C280 *1000p
X7R
CD_R 29
UV3- 24
C200 47p
Secondary Driver(Master)
N755IA5 Rev : A Page 38 - 31
Page 50
Chapter2 Major Components
USB CONN.(CN23,CN24,CN17)
+5V
+5V
S2
POLY SW_1206
S1
POLY SW_1206
220u/6.3V_DIP
+
C577
220u/6.3V_DIP
+
C563
45 mil
C155
0.1u/10V
X7R
C134
0.1u/10V
X7R
45 mil
C156
0.1u/10V
X7R
USBP0­USBP0+
C131
0.1u/10V
X7R
USBP1­USBP1+
CN23
1
1
2
2
3
3
4
4
USB CONN
CN24
1
1
2
2
3
3
4
4
USB CONN
5
5
6
6
5
5
6
6
C486
0.1u/10V
45 mil
1
2
3
4
RID335-2.5TS
L12
Y1
Y8 R2 R3 Y4 Y5
S7 S6
C485
0.1u/10V
X7RX7R
USBP2-
8
7
USBP2+
6
5
CN17
1
1
2
2
3
3
4
4
USB CONN
5
5
6
6
+5V
S3
POLY SW_1206
220u/6.3V_DIP
+
C14
UV2-24
UV2+24
N755IA5 Rev : A Page 39 - 31
Page 51
Chapter2 Major Components
LAN&MODEM CONN.(CN6)(CN25)
CN6
11
RD­RD+
TD­TD+
L120 QTCW-2012-90
1
4
1
4
L121 QTCW-2012-90
2
3
2
3
JC2
JC1
PH2 PH1
GND
8
NC4
7
NC3
6
RO-
5
NC2
4
NC1
3
RO+
2
TD-
1
TD+
10
PH2
9
PH1
12
GND
LAN&MODEN CONN
RV1
DSSA P3100SBRP
PH1
1
12
PH2
2
C180
1000p/2KV_1808
L75
82uH_SMD
L76
82uH_SMD
C194
1000p/2KV_1808
CN25
1 2
MODEM CONN
MDC CONN.(CN8)
+3V
+3V_AUX
MONO_OUT29
SDATO23,29
AC_RESET#23,29
1
MONO_OUT
3
GND
5
AUXR
7
AUXL
9
CDGND
11
CD_R
13
CD_L
15
GND
17
3.3V
19
GND
21
3.3V
23
SDATA_O
25
RESET#
27
GND
29
MCLK BCLK
MONO_PHONE
MDC CONN
CN8
AUDIO_PD
R_D
GND
VCC
R_D R_D
P_DN
VCC
GND
SYNC SDATA_INB SDATA_INA
GND
+5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
R248
4.7K
R252
*4.7K
R251
4.7K
SYNC 23,29 SDATI1 23 SDATI0 23,29
BIT_CLK 23,29
PHONE 29
+5V_AUX
N755IA5 Rev : A Page 40 - 31
Page 52
Chapter2 Major Components
IEEE-1394 CONN.(CN32)
PB0­PB0+ PA0­PA0+ BIAS0
R226 56.2_1%
R227 56.2_1%
C369
0.33u_0603
Y5V
34
10
11
13
12
14
15
20
17
86
73
59
45
61
56
48
72
67
71
29
30
68
64
65
66
25
26
122
121
112
93
43
36
22
21
16
98
100
L86
R230
56.2_1%
C368 220p
X7R
R231
56.2_1%
R229
4.99K_1%
1
Y1
2
R2
3
R3
4
Y4 Y5
*RID335-2.5TS
1
2
3
4
RP54 8P4RX0
Y8 S7 S6
8
7
6
5
8
7
6
5
MINIPCI (CN34)
124
3.3V_AUX
GROUND
GROUND
19
28
31
3.3V
3.3V
GROUND
GROUND
GROUND
40
63
70
3.3V
3.3V
GROUND
GROUND
GROUND 3.3V
88
89
3.3V
GROUND 3.3V
GROUND
3.3V
GROUND
GROUND
GROUND
123
VCC5VA
GROUND
GROUND
CN34
1
TIP
2
RING PME# AD29
4
8PMJ-1
6
8PMJ-2
3
8PMJ-3
8
8PMJ-4 8PMJ-5
5
8PMJ-6
7
8PMJ-7
9
8PMJ-8 LED1_GRNP LED1_GRNN LED2_YELP LED2_YELN CHSGND INTA# INTB# C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR IDSEL DEVSEL# SERR# PERR# REQ# GNT# STOP# FRAME# CLKRUN# TRDY# CLK RST# MPCIACT# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED_WIP RESERVED_WIP
24
3.3V_AUX
18
97
5V
5V
AC_SDATA_IN
AC_SDATA_OUT
AC_BIT_CLK AC_CODEC_ID0# AC_CODEC_ID1#
AC_RESET#
MOD_AUDIO_MON
AUDIO_GND
SYS_AUDIO_OUT
SYS_AUDIO_IN
SYS_AUDIO_OUT_GND
SYS_AUDIO_IN_GND
AUDIO_GND AUDIO_GND
GROUND
GND
GND
GND
GND
TPB0­TPB0+ TPA0­TPA0+
AD31 AD30
AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
AC_SYNC
M66EN
CN32
1
TPB-
2
TPB+
3
TPA-
4
TPA+
IEEE-I1394 CONN
33
38
35
42
39
44
41
46
47
52
51
54
53
58
57
60
76
75
78
79
80
81
84
85
87
90
91
92
95
94
99
96
103
104
105
106
107
108
109
110
111
113
115
116
117
118
119
120
SHLD SHLD
5
6
23
27
32
37
49
50
55
62
69
74
77
82
83
101
102
114
127
128
129
130
MINI PCI CONN
N755IA5 Rev : A Page 41 - 31
Page 53
Chapter2 Major Components
PCMCIA CONN.(CN9)
CN9
51
VCC
17
VCC
52
VPP
18
VPP
19
CCLK (A16)
54
CFRAME# (A23)
20
CIRDY# (A15)
53
CTRDY# (A22)
50
CDEVSEL# (A21)
49
CSTOP# (A20)
13
CPAR (A13)
14
CPERR# (A14)
59
CSERR# (WAIT*)
60
CREQ# (INPACK*)
15
CGNT# (WE*)
16
CINT# (IRQ*)
48
CBLOCK# (A19)
33
CCLKRUN# (IO16*)
58
CRESET# (RESET)
32
RFU (R2_D2)
40
RFU (R2_D14)
47
RFU (R2_A18)
43
CVS1
57
CVS2
36
CCD1# (CD1*)
67
CCD2# (CD2*)
62
CAUDIO (BVD2/SPKR*)
63
CSTSCHG (BVD1/RI*)
61
CC/BE3# (REG*)
21
CC/BE2# (A12)
12
CC/BE1# (A8)
7
CC/BE0# (CE1*)
697071
(D10) CAD31
(D9) CAD30 (D1) CAD29 (D8) CAD28 (D0) CAD27
(A0) CAD26 (A1) CAD25 (A2) CAD24 (A3) CAD23 (A4) CAD22 (A5) CAD21 (A6) CAD20
(A25) CAD19
(A7) CAD18 (A24) CAD17 (A17) CAD16
(IOWR*) CAD15
(A9) CAD14
(IORD*) CAD13
(A11) CAD12
(OE*) CAD11
(CE2*) CAD10
(A10) CAD9
(D15) CAD8
(D7) CAD7
(D13) CAD6
(D6) CAD5
(D12) CAD4
(D5) CAD3
(D11) CAD2
(D4) CAD1 (D3) CAD0
72
GND GND GND GND
66
65
31
64
30
29
28
27
26
25
24
23
56
22
55
46
45
11
44
10
9
42
8
41
6
39
5
38
4
37
3
2
68
35
34
1
PCMCIA CONN
CD# DFCB/DSDWP#
DSIO/DDATA/DSDIO DCLK
DSRST#/DCMD/DBS
R180 47K
SD/MS CONN.(CN31)
R179 47K
R175 47K
INS#
R186 47K
R161 47K
C286
0.1u/10V
X7R
CN31
1
CD1
2
WP1
3
D1
4
D0
5
GND
6
CLK
7
VDD
8
GND
9
CM0
10
D3
11
D2
12
GND
13
BS
14
VCC
15
SDIO
16
REV
17
INS
18
REV
19
SCLK
20
VCC
21
GND
SD/MS CONN
SD CARD
M/S CARD
N755IA5 Rev : A Page 42 - 31
Page 54
Chapter2 Major Components
SPDIF OUT(CN11)
CN11 SPDIF CON
4
4
5
5
3
3
2
2
1
1
Q39 3LP01C
D
S
G
C761 1000p
X7R X7R
AUDGND1
VCC
IN
879
C785 680p
6
10
GND
L100 QT1608RL060
L114 QT1608RL060
6 10
SPDIF
AUDGND1
SPDIF 23
L99 QT1608RL060 L101 QT1608RL060
SE/BTL#
C762 470p
AUDGND1
SPKR1+ 21 SPKR1- 21 SPKL1- 21 SPKL1+ 21
D
Q40
S
2N7002 R562
4.7K
SENSE_PLUG#
R561
4.7K
SENSE_PLUG#
AUDGND1
+5V
C760 470p
X7RX7R
AMPVDD
G
SPDIF IN(CN13)
LINE-R LINE-L
QT1608RL060
L102
L103
QT1608RL060
SENSE_PLUG#1
Footprint must changed
SENSE_PLUG#1
C766 470p
X7R
AUDGND1
AMPVDD
+5V
R565
4.7K
AUDGND1
C765 470p
X7R
S
G
SPDIF IN
CN13 SPDIF CON
4
4
5
5
3
3
2
2
1
1
IN
VCC
8
9
7
Q41 3LP01C
D
C770 1000p
C786 680p
X7RX7R
6
10
GND
Change pin of CON.
L106 QT1608RL060
L117 QT1608RL060
6
10
SPDIF_IN
AUDGND1
AUDGND1
N755IA5 Rev : A Page 43 - 31
Page 55
Chapter2 Major Components
MIC JACK CONN.(CN7,CN12)
L36
QT1608RL060
C772 680p
CN7
1 2
MIC CONN
LFRAME#23,31
CHARGE CSSP33
VADAP33
CN12
MIC JACK
5 4 3 2 1
AUDGND1
INT_MIC
C768 470p
NPOX7R NPO
C767 470p
I/O CONN.(CN20,CN18)
CN20
12 34 56
+3V_AUX
+5V_AUX
+1.8V_AUX
AGPVDD
VINS
VIN
IRRX1 IRSEL
BOUT14 GOUT14 DDC1DATA 14
DDC1CLK14
VBAT32,33
PCIRST#10,14,22,26,27,28,31
AGP_ON31
LPC_CLK7
LID#31
E_MAIL#31
WWW#31
LANLED#31
LANSW#31
LAD0
LID#
78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
IO CONN
CN18
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
IO CONN
IRRX2 IRTX
LAD3 LAD1 LAD2
VINVIN +5V
+3V
393-48M 7
+12V_AUX
LDRQ#0 23,31
SERIRQ 23,28,31 +1.8V_AUX AGPVDD
VIN
HSYNC 14ROUT14 VSYNC 14
+5V_ON 31,32 PWRSW 31 NUMLED# 31 CAPLED# 31 SCROLED# 31 IDELED# 25
L105
QT1608RL060
INT_MIC 23
L104
QT1608RL060
VADAP 33VADAP33 SUS_SKIP 31
ADAP_IN# 31 M_DIS_BAT 31 BATTERY ON 32
BASS
CENTERINT_MIC
R559
4.7K R560
1K_1%
N755IA5 Rev : A Page 44 - 31
Page 56
Chapter2 Major Components
VGA FAN(CN26)
CN26
1 2
AGP FAN
L26
QT1608RL060
+5V
R154
1K_1%
R158
A1797
Q10
E
C
B
R155
VGA_FAN_ON
C206
+
10u/10V_0805
Y5V Y5V
C244
+
10u/10V_0805
0~5V
C245
0.1u/10V
X7R
+5V
R172 100K
100_1%
R89
1K_1%
100_1%
R147 22
Q12
E
R91
100_1%
A1797
C
B
R90
100_1%
R150
5.11K_1%
CPU FAN(CN27)
CPU_FAN_ON
C228
0.1u/10V
X7R
R182
5.11K_1%
C576
+
220u/6.3V_DIP
C207
0.1u/10V
X7R
0~5V
CN27
1 2
CPU FAN
L25
QT1608RL060
T/P CONN.(CN10)
+3V
1
2
3
4
TPDAT TPCK
PAGE_UP# PAGE_DN#
RP102
8P4RX4.7K
5
6
7
8
CN10
6 5 4 3 2 1
T/P CONN
+5V
C738
0.1u/10V
X7R
N755IA5 Rev : A Page 45 - 31
Page 57
Chapter2 Major Components
PCN2
8
7
SMBCLK_EC14,31 SMBDAT_EC14,31
PC157 100p/50V/NPO
PC158 100p/50V/NPO
PB CONN.(CN21)
CN21
VIN_IO
+3V_AUX_IO
+5V_AUX_IO
+1.8V_AUX_IO
AGPVDD_IO
VADAP_IO38,41 VADAP_IO 38,41
VINS_IO
VIN_IO
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PB CONN
IO_393-48M
VIN_IO
+5V_IO +3V_IO
+12V_AUX_IO
+1.8V_AUX_IO
AGPVDD_IO
VIN_IO
6 5 4 3 2 1
9
BATT CON
4
IO_LDRQ#0 IO_SERIRQ
SUS_SKIP_IO 39
PB CONN.(CN19)
IO_IRRX1 IO_IRSEL
IO_LFRAME# IO_PCIRST#
IO_LPCCLK
CN19
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PB CONN
IO_IRRX2 IO_IRTX
IO_LAD3 IO_LAD1 IO_LAD2
+5V_ON_IO 41 PWRSW_IO 38,41 IO_NUMLED# 38 IO_CAPLED# 38 IO_SCROLED# 38 IO_IDELED# 38
N755IA5 Rev : A Page 46 - 31
Page 58
Chapter2 Major Components
COM1 CONN.(CN3)
DCOMDCD1#
QT4532KL080HC_8A_1812
PL2
PC99
0.1u/25V/Y5V
PCN1 DC JACK CONN.
PC92
0.1u/25V/Y5V
CN3
12 34 56 78 910
*COM1 DMY
DCOMRXD1 DCOMDTR1# DCOMDSR1# DCOMCTS1#
6
3
1
5
2
4
8
7
PCN1 DC JACK
9
CRT CONN.(CN15)
LPT CONN.(CN16)
CN16
LPTSLCT LPTPE LPTBUSY LPTACK# LPTD7 LPTD6 LPTD5 LPTD4 LPTD3
LPTSLCTIN# LPTD2 LPTINIT# LPTD1 LPTERR# LPTD0 LPTAFD# LPTSTB#
26 13 25 12 24 11 23 10 22
9
21
8
20
7
19
6
18
5
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PARALLEL CONN
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Chapter2 Major Components
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Chapter3 Explosion Chart
UNIWILL COMPUTER CORP.
No. 24 Pei Yuan Road Chung Li Industrial Park, Chung Li City Tao Yuan, Taiwan, R.O.C. TEL: 886-3-461-6000 FAX: 886-3-461-6317 URL: http:// www.uniwill.com.tw/
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Chapter3 Explosion Chart
3.1. Top Cabinet Assembly …………………………….………………………
3
3.2. Top Housing Assembly………………………………….……..…………...
3.3. Mother Board Assembly…………………………………………………...
3.4. Bottom Assembly ………………………………………………….……….
3.5. HDD Assembly……………………………………………………………..
3.6 CD/DVD/COMBO Assembly……………………………………………...
3.7 LCD Module Assembly…………………………………………………….
4 5 6 7 8
9
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Chapter3 Explosion Chart
3.1 Top Cabinet Assembly.
ITEM PART NO. DESCRIPTION QTY
1 50-UD7052-00 COVER K/B ID1#8139 258SA0 1 2 50-UD7010-00 TOP CAB ID1#8138/8139 258SA0 1 3 50-UD7051-00 COVER HINGE #8139 258SA0 2 4 50-UD7082-00 BUTTTON POWER ID1 258SA0 1 5 50-UD7102-00 LENS STATUS ID1 258SA0 1 6 50-UD7101-00 LENS POWER 258SA0 1 7 50-UD7300-00 FRAME TOUCHPAD 1 8 50-UD7081-00 BUTTON SCROLLID1#8100 258SA0 1
9 50-UD7080-00 BUTTON TOUCHPAD ID1#8100 258SA0 1 10 41-720120-03 SCREW M2.0X3 I #1 NI 4 11 41-720620-06 SCREW M2.0X6 I #1 BNI 1
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Chapter3 Explosion Chart
3.2 Top housing Assembly.
ITEM PART NO. DESCRIPTION QTY
1 29-UD7030-00 FPC TOUCHPAD (SUNFLEX) 258SA0 1 2 40-UD7025-00 BRACKET AUDIO 258SA0 1 3 40-UD7026-00 BRACKET I/O 1 4 41-760120-04 SCREW M2.0X0.4X4L I #1 NI 2 5 73-080041-00 TOUCHPAD TN42DA9307 SYNAPTICS 1 6 41-760120-04 SCREW M2.0X 0.4X4L I #1 NI 4 7 27-300080-00 ADHESIVE TAPE T/ P T-4000 T=0.1mm 258SA0 1 8 40-UD7023-00 BRACKET TOP HOUSING 258SA0 1
9 40-UD7024-00 BRACKET HOUSING SKELETON-L 1 10 40-UD7024-10 BRACKET HOUSING SKELETON-R 1 11 50-UD7212-00 MYLAR TOP HOUSING (K/B) 258SA0 1 12 50-UD7212-10 MYLAR TOP HOUSING (DC/B) 258SA0 1 13 50-UD7212-20 MYLAR TOP HOUSING(T/P BUTTON) 258S0 1 14 50-UD7212-30 MYLAR TOP HOUSING (T/P)258SA0 1 15 41-760120-04 SCREW M2.0X0.4X4L I #1 NI 4 16 51-UD7023-00 SPONGE CR-4305 5X5X4.15 258SA0 2 17 41-720120-06 SCREW M2.0X6 I #1 NI 1 18 41-300002-21 HEX D4.8X10.2L #4-40 4 19 41-720120-04 SCREW M2.0X4 I #1 NI 2
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Chapter3 Explosion Chart
3.3 Main Board Assembly.
ITEM PART NO. DESCRIPTION QTY
1 50-UD7211-20 MYLAR FOR CD R0M 258SA0 1 2 50-UD7211-10 MYLAR FOR PCMCIA 258SA0 1 3 40-UD7710-00 THERMAL MODULE FOR 258SA0 1 4 40-UD7041-00 VGA SINK(ROBIN-SUNON) FOR 258SA0 1 5 40-UD7040-00 SIS SINK FOR 258SA0 1 6 41-670425-06 SCREW M2.5X6 (HEX X 6.5) STEEL-NI 1 7 41-671425-06 SCREW M2.5X6(HEX X 12.7) STEEL -IN 1 8 41-672425-05 SCREW M2.5X5(HEX X 7.1)STEEL -IN 1
9 41-720125-06 SCREW M2.5X6 I#1 NI 3 10 41-720125-06 SCREW M2.5X6 I#1 NI 2 11 41-720125-06 SCREW M2.5X6 I#1 NI 1 12 41-720125-04 SCREW M2.5X4 I #1 NI 1 13 41-721125-04 SCREW M2.5X4 PAN NI ASSY SPR 5 14 41-720102-09 SCREW M2.0X9 D3.5 T0.8 I #1 NI 2 15 41-720102-09 SCREW M2.0X9 D3.5 T0.8 I #1 NI 2 16 41-720120-04 SCREW M2.0X4 I #1 NI 2 17 41-720120-04 SCREW M2.0X4 I #1 NI 2 18 41-720120-06 SCREW M2.0X6 I #1 NI 2
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Chapter3 Explosion Chart
3.4 Botttom Cabinet Assembly.
ITEM PART NO. DESCRIPTION QTY
1 50-UD7020-00 BTM CAB #8086 258SA0 1 2 40-UD7031-00 SHIELDING BOTTOM 259SA0 1 3 40-UD7022-00 BRACKET DOORBTM #8086 258SA0 1 4 52-UD7010-00 RUBBER FOOT (BLACK) 258SA0 5 5 50-UD7072-00 HOOK BATT #8086 258SA0 2 6 50-UD7103-00 LENS IR 258SA0 1 7 50-UD7090-00 LATCH BATT #8086 258SA0 2 8 52-UD7010-00 RUBBER FOOT(BLACK)258SA0 2
9 41-720025-08 SCREW M2.5X8 I #1 BNI AND NYLOK 7 10 41-720620-04 SCREW M2.5X8 I #1 BNI 10 11 41-720620-06 SCREW M2.0X6 I #1 BNI 3 12 41-720625-04 SCREW M2.5X4 I #1 BNI 3 13 41-720625-06 SCREW M2.5X6 I #1 BNI 6 14 41-760120-03 SCREW M2.0X3 H=0.4 I #0 NI 1
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Chapter3 Explosion Chart
3.5 HDD Assembly.
ITEM PART NO. DESCRIPTION QTY
1 41-720130-04 SCREW M3X4mm I NI 4 2 70-822400-10 HDD 40GB MK4021GAS TOSHIBA 1 3 40-UD7027-00 BRACKET HOLDER HDD258SA0 1 4 50-UD7213-00 MYLAR HDD 258SA0 1 5 50-UD7213-10 MYLAR HDD PULL BAR 258SA0 1 6 52-UD7030-00 RUBBER HDD 15X4X12 NR 258SA0 2 7 41-720120-04 SCREW M2.0X4 I #NI 1
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Chapter3 Explosion Chart
3.6 CD/DVD/COMBO Rom Assembly.
ITEM PART NO. DESCRIPTION QTY
1 50-UD7073-00 KNOB COMBO QUA #8086 258SA0 1 2 50-UD7130-00 BEZEL COMBO QUA #8086 258SA0 1 3 41-910217-03 SCREW TP1.7X3 I #0 BLACK H=0.6 1 4 41-720C02-25 SCREW M2X2.5 H=0.4 D=3.5 I#0 NI+NYLOK 4 5 50-UD7160-00 HOLDER CD-ROM #8086 258SA0 1 6 80-UD7020-00B PCB CD ROM TRASFER BD ASSY 1 7 41-720120-06 SCREW M2.0X6 I #1 NI 2 8 70-210030-10 COMBO 24X 24R/24RW/8D SBW-242U 1
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Chapter3 Explosion Chart
3.7 LCD Module Assembly.
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Chapter3 Explosion Chart
ITEM PART NO. DESCRIPTION QTY
1 50-UD7070-00 KNOB FOR LCD #8100 258SA0 1 2 50-UD 7040-00 BACK CAB 15.4” ID1 #8100 258SA0 1 3 50-UD7071-00 HOOK LCD 15.4” #8098 258SA0 1 4 40-U54060-10 SPRING FOR LCD HOOK N34AS1 1 5 40-UD7030-00 SHIELDINGAL FOR LCD 15.4” 258SA0 1 6 76-030003-3A INVERTER SAMPO DIVTN0D03-D11-R3A 1
76-030562-1B INVERTER DELTA DAC-08B031 R0B 1
76-033128-3A INVERTER SUMIDA IVI3I28T/D2 REV3A 1 7 50-UD7211-00 MYLAR FOR LCD INVERTER 258SA0 1 8 29-UD7060-00 CABLE FOR 15.4” LCD INVERTER CNI 258SA0 1
29-UD7060-10 CABLE FOR 15.4” LCD INVERTER HL 258SA0 1 9 29-UD7051-00 CABLE COAXIAL LCD 15.4”XGA HT 258SA0 1
29-UD7051-10 CABLE COAXIAL LCD 15.4”SXGA CMI 258SA0 1
10 22-325140-00 SPEAKER ASSY FG-2514 1.5W 258SA0 1 11 40-UD7021-00 BRACKET –L FOR LCD 15.4’ 258SA0 1 12 40-UD7021-10 BRACKET-R FOR LCD 15.4” 258SA0 1 13 40-UD7050-00 HINGE-L LCD 15.4”(SZS)258SA0 1 14 40-UD7050-10 HINGE-R LCD 15.4”(SZS)258SA0 1 15 50-UD7030-00 FRONT CAB 15.4” #8100258SA0 1 16 22-600061-00 ANTENNA&CABLE WLAN HANNSTAR L895 258SA0 1 17 22-600060-00 ANTENNA&CABLE WLAN HANNSTAR R960 258SA0 1 18 41-720120-03 SCREW M2.0X3 I #1 NI 8 19 41-720520-03 SCREWM2.0X3I NI+NYLOK INSIDE 4 20 41-720525-06 SCREW M2.5X6 I #1 NI +NYLOK 4 21 41-720120-04 SCREW M2.0X4I #1 NI 7 22 41-720525-06 SCREW M2.0X6 I #1 NI+NYLOK 2 23 41-760120-04 SCREW M2.0X0.4X4L I #1 NI 2 24 41-720520-04 SCREW M2.0X4 NI+NYLOK I 4 25 52-U54023-01 RUBBER LCD UP #8079 N34AS1 4 26 50-U54215-00 MYLAR LCD FRONT CAB #B1D0 N34AS1 2 27 29-UD7081-00 CABLE CABLE FOR MIC PHONE 258SA0 1 28 72-115272-00 LCD 15.4”TFT WXGA TX39DB9VC1FAA HITAC 1
72-115261-00 LCD TFT 15.4”WXGA N15I1-L02 CM0 1
72-115273-00 LCD 15.4”TFT LTN154X1-L02 SAMSUNG 1
72-115274-00 LCD 15.4”TFTWXGA CLAA154WA01 CPT 1
72-1152271-00 LCD15.4”TFT WSXGA+TX39D99VC1FAA HITAC 1
72-115277-00 LCD 15.4”TFTWSXGA+LTN154P1-L02 SAM 1
29 40-UD7800-00 MAGNETIC FOR SUCPEND SENSOR 258SA0 1 30 51-UD7020-00 SPONGE CR-4305 65X15X1 258SA0 1 31 50-UD7140-00 FELT 45X20X0.25 FOR LCD FRONT 258SA0 2 32 51-UD7021-00 SPONGE FOR CABLE NIC UP 25BSA0 1 33 51-UD7022-00 SPONGE FOR CABLE NIC UP 25BSA0 1
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Chapter 4 System Disassembly
UNIWILL COMPUTER CORP.
No. 24 Pei Yuan Road Chung Li Industrial Park, Chung Li City Tao Yuan, Taiwan, R.O.C. TEL: 886-3-461-6000 FAX: 886-3-461-6317
URL: http:// www.uniwill.com.tw/
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Chapter 4 System Disassembly
4.1. System Disassembly Procedures……………………………………………
4.2. LCD Display Panel Disassembly Procedure………………….…………...
3
14
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Chapter 4 System Disassembly
4.1. System Disassembly Procedures
1. Please refer to the disassembly procedures of the 258SA0.
2. Unlock the battery knob and pull out the battery pack.
3. Unlock the cd rom knob and pull out the cd rom.
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Chapter 4 System Disassembly
4. Unfasten 11 screws and remove the CPU and VGA cover.
5. Unfasten 6 screws,disconnect the Cpu fan cable and remove the Cpu fan.
6. Lift up the CPU lever arm with an angel of 90 degree and remove the CPU.
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Chapter 4 System Disassembly
7. Disconnect the wireless lan cable And remove wireless lan card and DDR module from their socket.
8. Disconnect the VGA fan cable and Unfasten 6 screws from the VGA fan.
9. Unfasten 2 screws and push backward the HDD drive and remove it from HDD connector.
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Chapter 4 System Disassembly
10. Unlock 3 latches of the keyboard.
11. Disconnect K/B cable and rmove the K/B.
12. Unfasten 14 screws and 2 hexnuts.
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Chapter 4 System Disassembly
13. Remove the led cover assembly and remove the 2 hinge cover (left & right cover)..
14. Unfasten 1 screw and disconnect the 2 LCD cables.
15. Unfasten 4 screws of the hinge (2 left&2 rigth)and remove the LCD gently.
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Chapter 4 System Disassembly
16. Unfasten 3 screws of the top cabinet..
17. Unfasten 1 screw and disconnect touch pad cable..
18. Remove Top housing cabinet gently.
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Chapter 4 System Disassembly
19. Remove the bottom housing cabinet gently.
20. Unfasten 4 hexnuts.
21. Unfasten 3 screw .
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Chapter 4 System Disassembly
22. Unfasten 4 screws.
23. Gently remove the M/B to the m/b bracket.
24. Gently disconnect the power board to the mother board..
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Chapter 4 System Disassembly
25. System Disassembly finished.
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Chapter 4 System Disassembly
4.2 LCD Display panel Disassembly procedure.
1. Remove the 4 rubber stoppers and 2 mylar stoppers.
2. Unfasten 6 screws.
3. Gently disassemble the Lcd front cabinet.
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4. Unfasten the 2 screws in right hinge and 2 screws in left hinge together the the 2 screws in inverter board.
5. Disconnect LCD cable and Inverter cable then remove the inverter.
6. Disconnect the 2 speaker cable.
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Chapter 4 System Disassembly
7. Unfasten 8 screws and remove the lcd panel from the lcd back cabinet.
8. Unfasten 8 screws and remove the right & left lcd bracket.
9. Disconnect the LCD single cable
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Chapter 4 System Disassembly
10.LCD display panel disassembly finished.
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Chapter 5 Installation Guidelines
UNIWILL COMPUTER CORP.
No. 24 Pei Yuan Road Chung Li Industrial Park, Chung Li City Tao Yuan, Taiwan, R.O.C. TEL: 886-3-461-6000 FAX: 886-3-461-6317 URL: http:// www.uniwill.com.tw/
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Chapter 5 Installation Guidelines
5.1. CPU, RAM, HDD Installation……………………………………………
5.2. Upgrade System & Keyboard BIOS…………..…………….…………...
3
8
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Chapter 5 Installation Guidelines
5.1. CPU, RAM, HDD Installation
Warning Notice
For precautionary measures, please disconnect the AC adapter and remove the battery from the
battery compartment while doing the installation procedure of the CPU, Memory & HDD.
Procedure to remove the battery
Unlock the battery knob and pull out the battery pack
A. CPU Installation Guide
Important Notice
The CPU thermal pad of the CPU fan heat sink (black color) is one time use only. Meaning that if you remove the CPU heat sink from the CPU, you must REPLACE the CPU thermal pad with a new thermal pad (black color). Clean any residue on the CPU and the CPU heat sink assembly before putting the new CPU thermal pad. Otherwise, there might be an overheat problem on the CPU.
1.Unfasten 11 screws and remove the CPU cover.
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Chapter 5 Installation Guidelines
2.Unfasten 6 screws,disconnect the Cpu fan cable and remove the Cpu fan.
3. Pull up the lever arm to 90 degree angle sure that the CPU socket is in unlocking position.
4. Align the pin 1 of CPU with pin 1 of CPU socket and gently put the CPU into the CPU socket and press down the lever arm.
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Chapter 5 Installation Guidelines
5. Put back the CPU heat sink assembly, fasten the 6 screws and connect the fan cable to the fan connector.
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Chapter 5 Installation Guidelines
B. HDD Module Installation Guide
1. Fasten 4 screws of HDD module.
2. Push the HDD braket into the HDD socket and fasten the 2 HDD screws.
1. Gently assemble the DDR RAM module
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Chapter 5 Installation Guidelines
5.2. Upgrade the BIOS
Important Notice
The utility only support at real mode (DOS mode), can not run at the protected mode (Window Mode). Do make sure that the system boot from real mode and plug AC power when to update the BIOS or install the utility.
BIOS Update Procedure
The F82741.EXE utility is used to flash the system ROM and upgrade the BIOS.
1. Make sure the AC adapter is connected to your notebook before you run this utility.
2. Please make a clean Boot Disk which has no config.sys and autoexec.bat files.
3. Boot from Floppy disk, enter DOS prompt.
4. Type DIR
5. Please make sure the diskette has the following files : F82741.EXE and xxxx.xxx (Bios Filename)
6. Start to update the system BIOS, AC power must plug into unit A:\F82741 xxxx.xxx
7. Press Enter. After updating the bios, please go to BIOS setup and load DEFAULT setting.
The system reboots automatically after installation is complete.
. Type
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