TRINAMIC TMC2130-EVAL-KIT Instructions

FEATURES AND BENEFITS

2-phase stepper motors up to 2.0A coil current (2.5A peak)
Step/Dir Interface with microstep interpolation microPlyer™
SPI Interface
Voltage Range 4.75… 46V DC
Highest Resolution 256 microsteps per full step

stealthChop™ for extremely quiet operation and smooth
motion

spreadCycle™ highly dynamic motor control chopper
dcStep™ load dependent speed control
stallGuard2™ high precision sensorless motor load detection

coolStep™ current control for energy savings up to 75%
Integrated Current Sense Option
Passive Braking and freewheeling mode
Full Protection & Diagnostics
Small Size 5x6mm2 QFN36 package or TQFP48 package

APPLICATIONS

Textile, Sewing Machines
Factory Automation
Lab Automation
Liquid Handling
Medical
Office Automation
CCTV, Security
ATM, Cash recycler
POS
Pumps and Valves

DESCRIPTION

The TMC2130 is a high performance driver
IC for two phase stepper motors. Standard
SPI and STEP/DIR simplify communication.
TRINAMICs sophisticated stealthChop
chopper ensures noiseless operation
combined with maximum efficiency and
best motor torque. coolStep allows
reducing energy consumption by up to
75%. dcStep drives high loads as fast as
possible without step loss. Integrated
power MOSFETs handle motor currents up
to 1.2A RMS (QFN package) / 1.4A RMS
(TQFP) or 2.5A short time peak current per
coil. Protection and diagnostic features
support robust and reliable operation.

Industries’ most advanced stepper motor

driver enables miniaturized designs with
low external component count for cost­effective and highly competitive solutions.

Universal high voltage driver for two-phase bipolar stepper motor. stealthChop™ for quiet
movement. Integrated MOSFETs for up to 2.0A motor current per coil. With Step/Dir Interface and SPI.

BLOCK DIAGRAM

spreadCycle

stealthChop

DRIVER

TMC2130

Programmable

256 µStep

Sequencer

Protection

& Diagnostics

SPI

stallGuard2 coolStep dcStep

Power
Supply

Motor

Step/Dir

Step Multiplyer

spreadCycle

stealthChop

DAC Reference

IREF optional current scaling

SPI Control,

Config & Diags

CLK

Control

Register

Set

Standstill Current

Reduction

CLK Oscillator /

Selector

Interrupt

INT

Charge

Pump

+5V Regulator

POWER DRIVER FOR STEPPER MOTORS INTEGRATED CIRCUITS

TMC2130-LA DATASHEET

TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 2

CPU

SPI

S/D

High-Level

Interface

N

S

0A+

0A-

0B+

TMC2130

0B-

CPU

SPI

SPI

S/D

TMC4361

Motion

Controller

High-Level

Interface

N

S

0A+

0A-

0B+

TMC2130

0B-

MINIATURIZED DESIGN FOR ONE STEPPER MOTOR

SPI

DESIGN FOR DEMANDING APPLICATIONS WITH S-SHAPED RAMP PROFILES

CPU

SPI

TMC429

Motion

Controller

High-Level

Interface

N

S

0A+

0A-

0B+

TMC2130

0B-

STEP/

DIR

COMPACT DESIGN FOR UP TO THREE STEPPER MOTORS

N

S

0A+

0A-

0B+

TMC2130

0B-

N

S

0A+

0A-

0B+

TMC2130

0B-

SPI

SPI

SPI

STEP/

DIR

STEP/

DIR

Order code

Description

Size [mm2]

TMC2130-LA

1-axis dcStep, coolStep, and stealthChop driver; QFN36

5 x 6

TMC2130-TA

1-axis dcStep, coolStep, and stealthChop driver; TQFP48

9 x 9

TMC2130-EVAL

Evaluation board for TMC2130 two phase stepper motor
controller/driver

85 x 55
TMC4361-EVAL

Motion controller board (part of evaluation board system)

85 x 55

STARTRAMPE

Baseboard for TMC2130-EVAL and further evaluation boards

85 x 55

ESELSBRÜCKE

Connector board for plug-in evaluation board system

61 x 38

In this application, the CPU initializes the
TMC2130 motor driver via SPI interface and
controls motor movement by sending step
and direction signals. A real time software
realizes motion control.

Here, an application with up to three stepper
motors is shown. A single CPU combined
with a TMC429 motion controller manages
the whole stepper motor driver system. This
design is highly economical and space
saving if more than one stepper motor is
needed.

The CPU initializes the TMC4361 motion
controller and the TMC2130. Thereafter, it
sends target positions to the TMC4361. Now,
the TMC4361 takes control over the TMC2130.
Combining the TMC4361 and the TMC2130
offers diverse possibilities for demanding
applications including servo drive features.

APPLICATION EXAMPLES: HIGH VOLTAGE – MULTIPURPOSE USE

The TMC2130 scores with power density, integrated power MOSFETs, and a versatility that covers a
wide spectrum of applications from battery systems up to embedded applications with 2.0A motor
current per coil. Based on stallGuard2, coolStep, dcStep, spreadCycle, and stealthChop, the TMC2130
optimizes drive performance and keeps costs down. It considers velocity vs. motor load, realizes
energy savings, smoothness of the drive and noiselessness. Extensive support at the chip, board, and
software levels enables rapid design cycles and fast time-to-market with competitive products.

ORDER CODES

www.trinamic.com

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 3

Table of Contents

1 PRINCIPLES OF OPERATION ......................... 5

1.1 KEY CONCEPTS ................................................ 7

1.2 SPI CONTROL INTERFACE ............................... 7

1.3 SOFTWARE ...................................................... 7

1.4 MOVING THE MOTOR ...................................... 7

1.5 STEALTHCHOP DRIVER ..................................... 8

1.6 STALLGUARD2 – MECHANICAL LOAD SENSING8

1.7 COOLSTEP – LOAD ADAPTIVE CURRENT

CONTROL ...................................................................... 8

1.8 DCSTEP – LOAD DEPENDENT SPEED CONTROL 9

2 PIN ASSIGNMENTS ......................................... 10

2.1 PACKAGE OUTLINE ........................................ 10

2.2 SIGNAL DESCRIPTIONS ................................. 11

3 SAMPLE CIRCUITS .......................................... 13

3.1 STANDARD APPLICATION CIRCUIT ................ 13

3.2 REDUCED NUMBER OF COMPONENTS ............. 14

3.3 INTERNAL RDSON SENSING .......................... 14

3.4 EXTERNAL 5V POWER SUPPLY ...................... 15

3.5 PRE-REGULATOR FOR REDUCED POWER

DISSIPATION .............................................................. 16

3.6 5V ONLY SUPPLY .......................................... 17

3.7 HIGH MOTOR CURRENT ................................. 18

3.8 DRIVER PROTECTION AND EME CIRCUITRY ... 20

4 SPI INTERFACE ................................................ 21

4.1 SPI DATAGRAM STRUCTURE ......................... 21

4.2 SPI SIGNALS ................................................ 22

4.3 TIMING ......................................................... 23

8 ANALOG CURRENT CONTROL AIN ............. 54

9 SELECTING SENSE RESISTORS .................... 55

10 INTERNAL SENSE RESISTORS ................. 57

11 VELOCITY BASED MODE CONTROL ....... 59

12 DRIVER DIAGNOSTIC FLAGS .................. 61

12.1 TEMPERATURE MEASUREMENT ....................... 61

12.2 SHORT TO GND PROTECTION ....................... 61

12.3 OPEN LOAD DIAGNOSTICS ........................... 61

14 STALLGUARD2 LOAD MEASUREMENT ... 62

14.1 TUNING STALLGUARD2 THRESHOLD SGT ..... 63

14.2 STALLGUARD2 UPDATE RATE AND FILTER .... 65

14.3 DETECTING A MOTOR STALL ......................... 65

14.4 LIMITS OF STALLGUARD2 OPERATION .......... 65

15 COOLSTEP OPERATION ............................. 66

15.1 USER BENEFITS ............................................. 66

15.2 SETTING UP FOR COOLSTEP .......................... 66

15.3 TUNING COOLSTEP ........................................ 68

16 STEP/DIR INTERFACE ................................ 69

16.1 TIMING ......................................................... 69

16.2 CHANGING RESOLUTION ............................... 70

16.3 MICROPLYER STEP INTERPOLATOR AND STAND

STILL DETECTION ....................................................... 71

17 DIAG OUTPUTS ........................................... 72

18 DCSTEP .......................................................... 73

5 REGISTER MAPPING ....................................... 24

5.1 GENERAL CONFIGURATION REGISTERS .......... 25

5.2 VELOCITY DEPENDENT DRIVER FEATURE

CONTROL REGISTER SET ............................................. 27

5.3 SPI MODE REGISTER .................................... 29

5.4 DCSTEP MINIMUM VELOCITY REGISTER ......... 29

5.5 MOTOR DRIVER REGISTERS ........................... 30

6 STEALTHCHOP™ .............................................. 39

6.1 TWO MODES FOR CURRENT REGULATION ...... 39

6.2 AUTOMATIC SCALING .................................... 40

6.3 VELOCITY BASED SCALING ............................ 42

6.4 COMBINING STEALTHCHOP AND SPREADCYCLE

44

6.5 FLAGS IN STEALTHCHOP ................................ 45

6.6 FREEWHEELING AND PASSIVE MOTOR BRAKING

46

7 SPREADCYCLE AND CLASSIC CHOPPER ... 47

7.1 SPREADCYCLE CHOPPER ................................ 48

7.2 CLASSIC CONSTANT OFF TIME CHOPPER ....... 51

7.3 RANDOM OFF TIME ....................................... 52

7.4 CHOPSYNC2 FOR QUIET 2-PHASE MOTOR ..... 53

18.1 USER BENEFITS ............................................. 73

18.2 DESIGNING-IN DCSTEP ................................. 73

18.3 DCSTEP WITH STEP/DIR INTERFACE ........... 74

18.4 STALL DETECTION IN DCSTEP MODE ............ 77

19 SINE-WAVE LOOK-UP TABLE................... 78

19.1 USER BENEFITS ............................................. 78

19.2 MICROSTEP TABLE ........................................ 78

20 EMERGENCY STOP ...................................... 79

21 DC MOTOR OR SOLENOID ....................... 80

21.1 SOLENOID OPERATION.................................. 80

22 QUICK CONFIGURATION GUIDE ............ 81

23 GETTING STARTED ..................................... 84

23.1 INITIALIZATION EXAMPLE ............................. 84

24 STANDALONE OPERATION ...................... 85

25 EXTERNAL RESET ........................................ 88

26 CLOCK OSCILLATOR AND INPUT ........... 88

26.1 CONSIDERATIONS ON THE FREQUENCY .......... 88

27 ABSOLUTE MAXIMUM RATINGS ............ 89

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 4

28 ELECTRICAL CHARACTERISTICS ............. 89

28.1 OPERATIONAL RANGE ................................... 89

28.2 DC AND TIMING CHARACTERISTICS .............. 90

28.3 THERMAL CHARACTERISTICS .......................... 93

29 LAYOUT CONSIDERATIONS ..................... 94

29.1 EXPOSED DIE PAD ........................................ 94

29.2 WIRING GND ............................................... 94

29.3 SUPPLY FILTERING ........................................ 94

29.4 LAYOUT EXAMPLE (QFN36) .......................... 95

30 PACKAGE MECHANICAL DATA ................ 97

30.1 DIMENSIONAL DRAWINGS QFN36 5X6 ....... 97

30.2 DIMENSIONAL DRAWINGS TQFP-EP48 ....... 99

30.3 PACKAGE CODES ......................................... 100

31 DISCLAIMER ............................................... 101

32 ESD SENSITIVE DEVICE.......................... 101

33 TABLE OF FIGURES .................................. 102

34 REVISION HISTORY ................................. 103

35 REFERENCES ............................................... 103

www.trinamic.com

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 5

Half Bridge 1

Half Bridge 2

+V

M

VS

current

comparator

2 phase

stepper

motor

N

S

Stepper driver

Protection

& diagnostics

programmable

sine table

4*256 entry

DAC

stallGuard2™

coolStep™

x

step multiplier

microPlyer

OA1

OA2

BRA

spreadCycle &

stealthChop

Chopper

VCC_IO

TMC2130
Stepper Motor Driver

SPI interface

CSN

SCK

SDO

SDI

STEP

coolStep

&

stealthChop

motor driver

DIR

Half Bridge 1

Half Bridge 2

VS

current

comparator

DAC

OB1

OB2

BRB

Control register

set

CLK oscillator/

selector

DIAG0

CLK_IN

Interface

DIAG1

+V

IO

DIAG out

DRV_ENN

DRV_ENN

GNDP

GNDP

GNDA

F

F = 60ns spike filter

TST_MODE

dcStep™

DIE PAD

RS=0R15 allows for
maximum coil current.
Use low inductance
SMD resistor type.
Tie BRA and BRB to
GND for internal
current sensing

SPI™

opt. ext. clock

10-16MHz

3.3V or 5V

I/O voltage

100n

100n

100n

Diganostics

step & dir input

opt. driver enable

R

S

R

S

DCEN

DCIN

DCO

ISENSE

ISENSE

ISENSE

ISENSE

+V

M

DAC Reference

AIN_IREF

IREF

IREF

IREF

SPI_MODE

PU

PU

PU

PU

PDD

PMD

PU=166K pullup resistor to VCC
PD=166k pull down resistor to GND

PDD=100k pulldown
PMD=50k to VCC/2

PU

PU

PU

PU=166K pullup to VCC

PU

optional current scaling

F

Standstill

current

reduction

leave open

dcStep control
Tie DCEN to GND if
dcStep is not used

R

REF

5VOUT

Optional for internal current
sensing. R

REF

=9K1 allows for

maximum coil current.

5V Voltage

regulator

charge pump

CPO

CPI

VCP

22n

100n

+V

M

5VOUT

VSA

4.7µ

100n

2R2

470n

2R2 and 470n are optional

filtering components for

best chopper precision

VCC

B.Dwersteg, ©

TRINAMIC 2014

1 Principles of Operation

THE TMC2130 OFFERS THREE BASIC MODES OF OPERATION:

In Step/Direction Driver Mode, the TMC2130 is the microstep sequencer and power driver between a
motion controller and a two phase stepper motor. Configuration of the TMC2130 is done via SPI. A
dedicated motion controller IC or the CPU sends step and direction signals to the TMC2130. The
TMC2130 provides the related motor coil currents to operate the motor. In Standalone Mode, the
TMC2130 can be configured using pins. In this mode of operation CPU interaction is not necessary.
The third mode of operation is the SPI Driver Mode, which is used in combination with TRINAMICs
TMC4361 motion controller chip. This mode of operation offers several possibilities for sophisticated
applications.

OPERATION MODE 1: Step/Direction Driver Mode
An external motion controller is used or a central CPU generates step and direction signals. The

motion controller (e.g. TMC429) controls the motor position by sending pulses on the STEP signal
while indicating the direction on the DIR signal. The TMC2130 provides a microstep counter and a sine
table to convert these signals into the coil currents which control the position of the motor. The
TMC2130 automatically takes care of intelligent current and mode control and delivers feedback on the
state of the motor. The microPlyer automatically smoothens motion. To optimize power consumption
and heat dissipation, software may also adjust coolStep and stallGuard2 parameters in real-time, for
example to implement different tradeoffs between speed and power consumption.

Figure 1.1 TMC2130 STEP/DIR application diagram

www.trinamic.com

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 6

Status out

(open drain)

Half Bridge 1

Half Bridge 2

+V

M

VS

current

comparator

2 phase

stepper

motor

N

S

Stepper driver

Protection

& diagnostics

sine table

4*256 entry

DAC

x

step multiplier

microPlyer

OA1

OA2

BRA

spreadCycle &

stealthChop

Chopper

VCC_IO

TMC 2130 Standalone
Stepper Motor Driver

Configuration

interface

with TRISTATE

detection

CFG0

CFG1

CFG3

CFG2

STEP

spreadCycle

&

stealthChop

motor driver

DIR

Half Bridge 1

Half Bridge 2

VS

current

comparator

DAC

OB1

OB2

BRB

CLK oscillator/

selector

DIAG0

CLK_IN

Interface

DIAG1

+V

IO

DRV_ENN

GNDP

GNDP

GNDA

F

F = 60ns spike filter

TST_MODE

DIE PAD

RS=0R15 allows for
maximum coil
current;
Tie BRA and BRB to
GND for internal
current sensing

TRISTATE configuration

(GND, VCC_IO or open)

opt. ext. clock

10-16MHz

3.3V or 5V

I/O voltage

100n

100n

100n

Index pulse

step & dir input

R

S

R

S

ISENSE

ISENSE

ISENSE

ISENSE

+V

M

DAC Reference

AIN_IREF

IREF

IREF

IREF

TG

TG

TG

TG

PDD

PMD

TG= toggle with 166K resistor between VCC
and GND to detect open pin

PDD=100k pulldown
PMD=50k to VCC/2

optional current scaling

F

Standstill

current

reduction

R

REF

5VOUT

Optional for internal current
sensing. R

REF

=9K1 allows for

maximum coil current.

5V Voltage

regulator

charge pump

CPO

CPI

VCP

22n

100n

+V

M

5VOUT

VSA

4.7µ

100n

2R2

470n

2R2 and 470n are optional

filtering components for

best chopper precision

VCC

Driver error

CFG4

TG

CFG5

TG

DRV_ENN_CFG6

TG

CFG6

CFG3

Opt. driver

enable input

CFG0

CFG4

CFG5

CFG1

CFG2

CFG1

CFG2

CFG1

CFG2

B.Dwersteg, ©

TRINAMIC 2014

SPI_MODE

PU

OPERATION MODE 2: Standalone Mode

The TMC2130 positions the motor based on step and direction signals. The microPlyer automatically
smoothens motion. No CPU interaction is required. Configuration is done by hardware pins. Basic
standby current control can be done by the TMC2130. Optional feedback signals allow error detection
and synchronization.

Figure 1.2 TMC2130 standalone driver application diagram

OPERATION MODE 3: SPI Driver Mode

Together with the TMC4361 high-performance S-ramp motion controller the TMC2130 stepper motor
driver offers an SPI control mode, which gives full control over the motor coil currents to the
TMC4361. Combining these two ICs offers several possibilities for demanding applications including
servo features. Please refer to Figure 1.1 for more information about the pinning, which is identical to
step/direction driver mode, except that the STEP & DIR pins are not required for operation.

www.trinamic.com

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 7

1.1 Key Concepts

The TMC2130 implements advanced features which are exclusive to TRINAMIC products. These features
contribute toward greater precision, greater energy efficiency, higher reliability, smoother motion, and
cooler operation in many stepper motor applications.

stealthChop™ No-noise, high-precision chopper algorithm for inaudible motion and inaudible

standstill of the motor.

spreadCycle™ High-precision chopper algorithm for highly dynamic motion and absolutely clean

current wave.

dcStep™ Load dependent speed control. The motor moves as fast as possible and never loses

a step.

stallGuard2™ Sensorless stall detection and mechanical load measurement.
coolStep™ Load-adaptive current control reducing energy consumption by as much as 75%.
microPlyer™ Microstep interpolator for obtaining increased smoothness of microstepping when

using the STEP/DIR interface.

In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect
and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage
conditions for enhancing safety and recovery from equipment malfunctions.

1.2 SPI Control Interface

The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus
master to the bus slave another bit is sent simultaneously from the slave to the master.
Communication between an SPI master and the TMC2130 slave always consists of sending one 40-bit
command word and receiving one 40-bit status word.

The SPI command rate typically is a single initialization after power-on.

1.3 Software

From a software point of view the TMC2130 is a peripheral with a number of control and status
registers. Most of them can either be written only or read only. Some of the registers allow both read
and write access. In case read-modify-write access is desired for a write only register, a shadow
register can be realized in master software.

1.4 Moving the Motor

1.4.1 STEP/DIR Interface

The motor can be controlled by a step and direction input. Active edges on the STEP input can be
rising edges or both rising and falling edges as controlled by a mode bit (dedge). Using both edges
cuts the toggle rate of the STEP signal in half, which is useful for communication over slow interfaces
such as optically isolated interfaces. On each active edge, the state sampled from the DIR input
determines whether to step forward or back. Each step can be a fullstep or a microstep, in which
there are 2, 4, 8, 16, 32, 64, 128, or 256 microsteps per fullstep. A step impulse with a low state on
DIR increases the microstep counter and a high decreases the counter by an amount controlled by the
microstep resolution. An internal table translates the counter value into the sine and cosine values
which control the motor current for microstepping.

1.4.2 SPI Direct Mode

The direct mode allows control of both motor coil currents and polarity via SPI. It mainly is intended
for use with a dedicated external motion controller IC with integrated sequencer. The sequencer

applies sine and cosine waves to the motor coils. This mode also allows control of DC motors, etc.

www.trinamic.com

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 8

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

0 50 100 150 200 250 300 350

Efficiency

Velocity [RPM]

Efficiency with coolStep

Efficiency with 50% torque reserve

1.5 stealthChop Driver

stealthChop is a voltage chopper based principle. It guarantees absolutely quiet motor standstill and
silent slow motion, except for noise generated by ball bearings. stealthChop can be combined with
classic cycle-by-cycle chopper modes for best performance in all velocity ranges. Two additional
chopper modes are available: a traditional constant off-time mode and the spreadCycle mode. The
constant off-time mode provides high torque at highest velocity, while spreadCycle offers smooth
operation and good power efficiency over a wide range of speed and load. spreadCycle automatically
integrates a fast decay cycle and guarantees smooth zero crossing performance. The extremely
smooth motion of stealthChop is beneficial for many applications.

Programmable microstep shapes allow optimizing the motor performance for low cost motors.

Benefits of using stealthChop:

- Significantly improved microstepping with low cost motors

- Motor runs smooth and quiet

- Absolutely no standby noise

- Reduced mechanical resonances yields improved torque

1.6 stallGuard2 – Mechanical Load Sensing

stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall
detection as well as other uses at loads below those which stall the motor, such as coolStep load­adaptive current reduction. This gives more information on the drive allowing functions like
sensorless homing and diagnostics of the drive mechanics.

1.7 coolStep – Load Adaptive Current Control

coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement
information to adjust the motor current to the minimum amount required in the actual load situation.
This saves energy and keeps the components cool.

Benefits are:

- Energy efficiency power consumption decreased up to 75%

- Motor generates less heat improved mechanical precision

- Less or no cooling improved reliability

- Use of smaller motor less torque reserve required → cheaper motor does the job

Figure 1.3 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to
standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example.

Figure 1.3 Energy efficiency with coolStep (example)

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 9

1.8 dcStep – Load Dependent Speed Control

dcStep allows the motor to run near its load limit and at its velocity limit without losing a step. If the
mechanical load on the motor increases to the stalling load, the motor automatically decreases
velocity so that it can still drive the load. With this feature, the motor will never stall. In addition to
the increased torque at a lower velocity, dynamic inertia will allow the motor to overcome mechanical
overloads by decelerating. dcStep feeds back status information to the external motion controller or
to the system CPU, so that the target position will be reached, even if the motor velocity needs to be
decreased due to increased mechanical load. A dynamic range of up to factor 10 or more can be
covered by dcStep without any step loss. By optimizing the motion velocity in high load situations,
this feature further enhances overall system efficiency.

Benefits are:

- Motor does not loose steps in overload conditions

- Application works as fast as possible

- Highest possible acceleration automatically

- Highest energy efficiency at speed limit

- Highest possible motor torque using fullstep drive

- Cheaper motor does the job

www.trinamic.com

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 10

CPI

BRA

OA2

VS

TST_MODE

GNDP

OA1

VCP

STEP

CLK

OB1

GNDP

DCEN_CFG4

BRB

VS

DCO

1

DIR

VCC_IO

SDO_CFG0

SDI_CFG1

SCK_CFG2

CSN_CFG3

DIAG1
DIAG0

AIN_IREF

GNDA

CPO

-

OB2

VSA

-

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

28

27

26

25

24

23

22

21

20

19

36

35

34

33

32

31

30

29

DRV_ENN_CFG6

VCC
5VOUT

SPI_MODE

DCIN_CFG5

PAD = GNDD

TMC2130-LA

QFN-36

5mm x 6mm

25

26

3724

-

-

OA2

OA1

-

VS

-

BRA

-

VCP

STEP

CLK

-

OB1

DCEN_CFG4

BRB

OB2

DCO

1

TST_MODE

DIR

VCC_IO

SDO_CFG0

SDI_CFG1

SCK_CFG2

CSN_CFG3

DIAG1
DIAG0

AIN_IREF

GNDA

CPO

-

-

-

VSA

-

2

3

4

5

6

7

8

9

10

11

14

15

16

17

18

19

20

21

22

23

36

35

34

33

32

31

30

29

28

27

48

47

46

45

44

43

42

41

40

39

DRV_ENN_CFG6

38

GNDP

13

CPI

VCC
5VOUT

PAD = GNDD

12

SPI_MODE

­VS

-

DCIN_CFG5

-

-

GNDP

TMC2130-TA

TQFP-48

9mm x 9mm

2 Pin Assignments

2.1 Package Outline

Figure 2.1 TMC2130-LA package and pinning QFN36 (5x6mm² body)

Figure 2.2 TMC2130-TA package and pinning TQFP-EP 48-EP (7x7mm² body, 9x9mm² with leads)

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 11

Pin

QFN36

TQFP48

Type

Function

CLK 1 2

DI

CLK input. Tie to GND using short wire for internal clock
or supply external clock.

CSN_CFG3

2

3

DI
(tpu)

SPI chip select input (negative active) (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).

SCK_CFG2

3

4

DI
(tpu)

SPI serial clock input (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).

SDI_CFG1

4

5

DI
(tpu)

SPI data input (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).

SDO_CFG0

5

7

DIO
(tpu)

SPI data output (tristate) (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).

STEP

6 8 DI

STEP input

DIR 7 9

DI

DIR input

VCC_IO

8

10 3.3V to 5V IO supply voltage for all digital pins.

DNC

9

11, 14, 16,
18, 20, 22,
28, 41, 43,
45, 47

-

Do not connect. Leave open!

SPI_MODE

10

12

DI
(pu)

Mode selection input with pullup resistor. When tied low,
the chip is in standalone mode and pins have their CFG
functions. When tied high, the SPI interface is available
for control. Integrated pull-up resistor.

N.C.

11

6, 31, 36

Unused pin, connect to GND for compatibility to future
versions.

GNDP

12, 35

13, 48

Power GND. Connect to GND plane near pin.

OB1

13

15 Motor coil B output 1

BRB

14

17

Sense resistor connection for coil B. Place sense resistor
to GND near pin. An additional 100nF capacitor to GND
(GND plane) is recommended for best performance.

OB2

15

19 Motor coil B output 2

VS

16, 31

21, 40

Motor supply voltage. Provide filtering capacity near pin
with short loop to nearest GNDP pin (respectively via GND
plane).

DCO

17

23

DIO

dcStep ready output

DCEN_CFG4

18

24

DI
(tpu)

dcStep enable input (SPI_MODE=1) - tie to GND for normal
operation (no dcStep) or
Configuration input (SPI_MODE=0) (tristate detection).

DCIN_CFG5

19

25

DI
(tpu)

dcStep gating input for axis synchronization (SPI_MODE=1)
or
Configuration input (SPI_MODE=0) (tristate detection).

DIAG0

20

26

DIO

Diagnostics output DIAG0. Use external pull-up resistor
with 47k or less in open drain mode.

DIAG1

21

27

DIO

Diagnostics output DIAG1. Use external pull-up resistor
with 47k or less in open drain mode.

DRV_ENN_
CFG6

22

29

DI
(tpu)

Enable input (SPI_MODE=1) or
configuration / Enable input (SPI_MODE=0) (tristate
detection).
The power stage becomes switched off (all motor outputs
floating) when this pin becomes driven to a high level.

AIN_IREF

23

30

AI

Analog reference voltage for current scaling (optional
mode) or reference current for use of internal sense
resistors

2.2 Signal Descriptions

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 12

Pin

QFN36

TQFP48

Type

Function

GNDA

24

32 Analog GND. Tie to GND plane.

5VOUT

25

33

Output of internal 5V regulator. Attach 2.2µF or larger
ceramic capacitor to GNDA near to pin for best
performance. May be used to supply VCC of chip.

VCC

26

34

5V supply input for digital circuitry within chip and
charge pump. Attach 470nF capacitor to GND (GND plane).
May be supplied by 5VOUT. A 2.2 or 3.3 Ohm resistor is
recommended for decoupling noise from 5VOUT. When
using an external supply, make sure, that VCC comes up
before or in parallel to 5VOUT or VCC_IO, whichever
comes up later!

CPO

27

35 Charge pump capacitor output.

CPI

28

37

Charge pump capacitor input. Tie to CPO using 22nF 50V
capacitor.

VCP

29

38 Charge pump voltage. Tie to VS using 100nF capacitor.

VSA

30

39

Analog supply voltage for 5V regulator. Normally tied to
VS. Provide a 100nF filtering capacitor.

OA2

32

42 Motor coil A output 2

BRA

33

44

Sense resistor connection for coil A. Place sense resistor
to GND near pin. An additional 100nF capacitor to GND
(GND plane) is recommended for best performance.

OA1

34

46 Motor coil A output 1

TST_MODE

36 1 DI

Test mode input. Tie to GND using short wire.

Exposed
die pad

- -

Connect the exposed die pad to a GND plane. Provide as
many as possible vias for heat transfer to GND plane.
Serves as GND pin for digital circuitry.

*(pu) denominates a pin with pullup resistor; (tpu) denominates a pin with pullup resistor or toggle
detection. Toggle detection is active in standalone mode, only (SPI_MODE=0)

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 13

VCC_IO

TMC2130

SPI interface

CSN

SCK

SDO

SDI

Step & Dir input

with microPlyer

STEP

DIR

DIAG / INT out

5V Voltage

regulator

charge pump

22n
63V

100n

16V

DIAG0

CLK_IN

DIAG1

+V

M

5VOUT

VSA

4.7µ

+V

IO

DRV_ENN

GNDP

GNDA

TST_MODE

DIE PAD

VCC

opt. ext. clock

12-16MHz

3.3V or 5V

I/O voltage

100n

100n

Sequencer

Full Bridge A

Full Bridge B

+V

M

VS

stepper
motor

N

S

OA1

OA2

OB1

OB2

Driver

100n

BRB

100µF

CPI

CPO

BRA

R

SA

Use low inductivity SMD

type, e.g. 1206, 0.5W

R

SB

100n

VCP

Optional use lower

voltage down to 6V

2R2

470n

DAC Reference

AIN_IREF

IREF

Use low inductivity SMD

type, e.g. 1206, 0.5W

dcStep Controller

Interface

DC_IN

DC_EN

DCO

opt. driver enable

SPI_MODE

leave open

B.Dwersteg, ©

TRINAMIC 2014

opt. dcStep control

3 Sample Circuits

The sample circuits show the connection of external components in different operation and supply
modes. The connection of the bus interface and further digital signals is left out for clarity.

3.1 Standard Application Circuit

Figure 3.1 Standard application circuit

The standard application circuit uses a minimum set of additional components. Two sense resistors
set the motor coil current. See chapter 9 to choose the right sense resistors. Use low ESR capacitors
for filtering the power supply. The capacitors need to cope with the current ripple cause by chopper
operation. A minimum capacity of 100µF near the driver is recommended for best performance.
Current ripple in the supply capacitors also depends on the power supply internal resistance and
cable length. VCC_IO can be supplied from 5VOUT, or from an external source, e.g. a low drop 3.3V
regulator. In order to minimize linear voltage regulator power dissipation of the internal 5V voltage
regulator in applications where VM is high, a different (lower) supply voltage can be used for VSA, if
available. For example, many applications provide a 12V supply in addition to a higher driver supply
voltage. Using the 12V supply for VSA rather than 24V will reduce the power dissipation of the
internal 5V regulator to about 37% of the dissipation caused by supply with the full motor voltage.

Basic layout hints

Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid
common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor
directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are
recommended for VS filtering.

Attention

In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by
more than one diode drop upon power up or power down.

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 14

5V Voltage

regulator

+V

M

5VOUT

VSA

4.7µ

VCC

100n

Optional use lower

voltage down to 6V

Full Bridge A

Full Bridge B

stepper
motor

N

S

OA1

OA2

OB1

OB2

Driver

BRB

BRA

DAC Reference

AIN_IREF

IREF

AIN_IREF

5VOUT

R

REF

3.2 Reduced Number of Components

Figure 3.2 Reduced number of filtering components

The standard application circuit uses RC filtering to de-couple the output of the internal linear
regulator from high frequency ripple caused by digital circuitry supplied by the VCC input. For cost
sensitive applications, the RC-Filtering on VCC can be eliminated. This leads to more noise on 5VOUT
caused by operation of the charge pump and the internal digital circuitry. There is a slight impact on
microstep vibration and chopper noise performance.

3.3 Internal RDSon Sensing

For cost critical or space limited applications, sense resistors can be omitted. For internal current
sensing, a reference current set by a tiny external resistor programs the output current. For calculation
of the reference resistor, refer chapter 10.

Figure 3.3 RDSon based sensing eliminates high current sense resistors

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 15

5V Voltage

regulator

5VOUT

VSA

4.7µ

VCC

100n

470n

+5V

LL4448

MSS1P3

+V

M

5V Voltage

regulator

5VOUT

VSA

4.7µ

VCC

100n

+5V

+V

M

VCC_IO

470n 100n

3.3V

regulator

3.3V

VCC supplied from external 5V. 5V or 3.3V IO voltage. VCC supplied from external 5V. 3.3V IO voltage generated from same source.

5V Voltage

regulator

5VOUT

VSA

4.7µ

VCC

100n

470n

+5V

BAT54

+V

M

VCC supplied from external 5V using active switch. 5V or 3.3V IO voltage.

4k7

10k

2x BC857 or

1x BC857BS

3.4 External 5V Power Supply

When an external 5V power supply is available, the power dissipation caused by the internal linear
regulator can be eliminated. This especially is beneficial in high voltage applications, and when
thermal conditions are critical. There are two options for using an external 5V source: either the
external 5V source is used to support the digital supply of the driver by supplying the VCC pin, or the
complete internal voltage regulator becomes bridged and is replaced by the external supply voltage.

3.4.1 Support for the VCC Supply

This scheme uses an external supply for all digital circuitry within the driver (Figure 3.4). As the digital
circuitry makes up for most of the power dissipation, this way the internal 5V regulator sees only low
remaining load. The precisely regulated voltage of the internal regulator is still used as the reference
for the motor current regulation as well as for supplying internal analog circuitry.

When cutting VCC from 5VOUT, make sure that the VCC supply comes up before or synchronously
with the 5VOUT supply to ensure a correct power up reset of the internal logic. A simple schematic
uses two diodes forming an OR of the internal and the external power supplies for VCC. In order to
prevent the chip from drawing part of the power from its internal regulator, a low drop 1A Schottky
diode is used for the external 5V supply path, while a silicon diode is used for the 5VOUT path. An
enhanced solution uses a dual PNP transistor as an active switch. It minimizes voltage drop and thus
gives best performance.

In certain setups, switching of VCC voltage can be eliminated. A third variant uses the VCC_IO supply
to ensure power-on reset. This is possible, if VCC_IO comes up synchronously with or delayed to VCC.
Use a linear regulator to generate a 3.3V VCC_IO from the external 5V VCC source. This 3.3V regulator
will cause a certain voltage drop. A voltage drop in the regulator of 0.9V or more (e.g. LD1117-3.3)
ensures that the 5V supply already has exceeded the lower limit of about 3.0V once the reset
conditions ends. The reset condition ends earliest, when VCC_IO exceeds the undervoltage limit of
minimum 2.1V. Make sure that the power-down sequence also is safe. Undefined states can result
when VCC drops well below 4V without safely triggering a reset condition. Triggering a reset upon
power-down can be ensured when VSA goes down synchronously with or before VCC.

Figure 3.4 Using an external 5V supply for digital circuitry of driver (different options)

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 16

5V Voltage

regulator

+5V

5VOUT

VSA

4.7µ

VCC

470n

10R

Well-regulated, stable

supply, better than +-5%

5V Voltage

regulator

5VOUT

VSA

4.7µ

VCC

470n

+V

M

2R2

BCX56 or

similar

22k

4k7

Simple pre-regulator for 24V up to 46V

5V Voltage

regulator

5VOUT

VSA

4.7µ

VCC

470n

+V

M

2R2

BCX56 or

similar

22k

Simple short circuit protected pre-regulator for 24V up to 46V

Z5.6V e.g.

MM5Z5V6

100R

470n

16V

470n

16V

3.4.2 Internal Regulator Bridged

In case a clean external 5V supply is available, it can be used for complete supply of analog and
digital part (Figure 3.5). The circuit will benefit from a well-regulated supply, e.g. when using a +/-1%
regulator. A precise supply guarantees increased motor current precision, because the voltage at
5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current
control. For best performance, the power supply should have low ripple to give a precise and stable
supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher
remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case,
increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low
frequency ripple, this would affect the precision of the motor current regulation as well as add
chopper noise.

Figure 3.5 Using an external 5V supply to bypass internal regulator

3.5 Pre-Regulator for Reduced Power Dissipation

When operating at supply voltages up to 46V for VS and VSA, the internal linear regulator will
contribute with up to 1W to the power dissipation of the driver. This will reduce the capability of the
chip to continuously drive high motor current, especially at high environment temperatures. When no
external power supply in the range 5V to 24V is available, an external pre-regulator can be built with
a few inexpensive components in order to dissipate most of the voltage drop in external components.
Figure 3.6 shows different examples. In case a well-defined supply voltage is available, a single 1W or
higher power Zener diode also does the job.

Figure 3.6 Examples for simple pre-regulators

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 17

VCC_IO

TMC2130

SPI interface

CSN

SCK

SDO

SDI

Step & Dir input

with microPlyer

STEP

DIR

DIAG / INT out

5V Voltage

regulator

charge pump

22n
63V

100n

16V

DIAG0

CLK_IN

DIAG1

+V

IO

DRV_ENN

GNDP

GNDA

TST_MODE

DIE PAD

opt. ext. clock

12-16MHz

3.3V or 5V

I/O voltage

100n

Sequencer

Full Bridge A

Full Bridge B

+5V

VS

stepper
motor

N

S

OA1

OA2

OB1

OB2

Driver

100n

BRB

100µF

CPI

CPO

BRA

R

SA

Use low inductivity SMD

type, e.g. 1206, 0.5W

R

SB

100n

VCP

DAC Reference

AIN_IREF

IREF

Use low inductivity SMD

type, e.g. 1206, 0.5W

dcStep Controller

Interface

A B N

DC_IN

DC_EN

DCO

SPI_MODE

leave open opt. driver enable

+5V

5VOUT

VSA

4.7µ

VCC

470n

opt. dcStep control

3.6 5V Only Supply

Figure 3.7 5V only operation

While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only
application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop
must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the
external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should
have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply.

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 18

Die

Temperature

Peak coil

current

105°C

125°C

2A

Opearation not recommended

for increased periods of time

2.5A1.75A

115°C

135°C

1.5A

Limit by lower limit of
overtemperature threshold

Specified operational
range for max. 125°C

Derating

for >2A

High temperature

range

Current

limitation

2.25A

3.7 High Motor Current

When operating at a high motor current, the driver power dissipation due to MOSFET switch on­resistance significantly heats up the driver. This power dissipation will heat up the PCB cooling
infrastructure also, if operated at an increased duty cycle. This in turn leads to a further increase of
driver temperature. An increase of temperature by about 100°C increases MOSFET resistance by
roughly 50%. This is a typical behavior of MOSFET switches. Therefore, under high duty cycle, high
load conditions, thermal characteristics have to be carefully taken into account, especially when
increased environment temperatures are to be supported. Refer the thermal characteristics and the
layout hints for more information. As a thumb rule, thermal properties of the PCB design become
critical for the QFN-36 at or above about 1000mA RMS motor current for increased periods of time.
Keep in mind that resistive power dissipation raises with the square of the motor current. On the
other hand, this means that a small reduction of motor current significantly saves heat dissipation
and energy.

An effect which might be perceived at medium motor velocities and motor sine wave peak currents
above roughly 1.2A peak is a slight sine distortion of the current wave when using spreadCycle. It
results from an increasing negative impact of parasitic internal diode conduction, which in turn
negatively influences the duration of the fast decay cycle of the spreadCycle chopper. This is, because
the current measurement does not see the full coil current during this phase of the sine wave,
because an increasing part of the current flows directly from the power MOSFETs’ drain to GND and
does not flow through the sense resistor. This effect with most motors does not negatively influence
the smoothness of operation, as it does not impact the critical current zero transition. The effect does
not occur with stealthChop.

3.7.1 Reduce Linear Regulator Power Dissipation

When operating at high supply voltages, as a first step the power dissipation of the integrated 5V
linear regulator can be reduced, e.g. by using an external 5V source for supply. This will reduce overall
heating. It is advised to reduce motor stand still current in order to decrease overall power
dissipation. If applicable, also use coolStep. A decreased clock frequency will reduce power dissipation
of the internal logic. Further a decreased chopper frequency also can reduce power dissipation.

3.7.2 Operation near to / above 2A Peak Current

The driver can deliver up to 2.5A motor peak current. Considering thermal characteristics, this only is
possible in duty cycle limited operation. When a peak current up to 2.5A is to be driven, the driver
chip temperature is to be kept at a maximum of 105°C. Linearly derate the design peak temperature
from 125°C to 105°C in the range 2A to 2.5A output current (see Figure 3.8). Exceeding this may lead
to triggering the short circuit detection.

Figure 3.8 Derating of maximum sine wave peak current at increased die temperature

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 19

Full Bridge A

Full Bridge B

stepper
motor

N

S

OA1

OA2

OB1

OB2

Driver

BRB

BRA

R

SA

R

SB

1A Schottky Diodes like MSS1P6
or MSS1P3 (VM limited to 30V)

3.7.3 Reduction of Resistive Losses by Adding Schottky Diodes

Schottky Diodes can be added to the circuit to reduce driver power dissipation when driving high
motor currents (see Figure 3.9). The Schottky diodes have a conduction voltage of about 0.5V and will
take over more than half of the motor current during the negative half wave of each output in slow
decay and fast decay phases, thus leading to a cooler motor driver. This effect starts from a few
percent at 1.2A and increases with higher motor current rating up to roughly 20%. As a 30V Schottky
diode has a lower forward voltage than a 50V or 60V diode, it makes sense to use a 30V diode when
the supply voltage is below 30V. The diodes will have less effect when working with stealthChop due
to lower times of diode conduction in the chopper cycle. At current levels below 1.2A coil current, the
effect of the diodes is negligible.

Figure 3.9 Schottky diodes reduce power dissipation at high peak currents up to 2A (2.5A)

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 20

Full Bridge A

Full Bridge B

stepper
motor

N

S

OA1

OA2

OB1

OB2

Driver

470pF
100V

470pF
100V

470pF
100V

470pF
100V

Full Bridge A

Full Bridge B

stepper
motor

N

S

OA1

OA2

OB1

OB2

Driver

470pF
100V

470pF
100V

50Ohm @

100MHz

50Ohm @

100MHz

50Ohm @

100MHz

50Ohm @

100MHz

V1

V2

Fit varistors to supply voltage

rating. SMD inductivities

conduct full motor coil

current.

470pF
100V

470pF
100V

Varistors V1 and V2 protect
against inductive motor coil
overvoltage.

V1A, V1B, V2A, V2B:
Optional position for varistors
in case of heavy ESD events.

BRB

R

SA

BRA

100nF
16V

R

SB

100nF
16V

V1A

V1B

V2A

V2B

3.8 Driver Protection and EME Circuitry

Some applications have to cope with ESD events caused by motor operation or external influence.
Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset
or even a destruction of the motor driver, depending on their energy. Especially plastic housings and
belt drive systems tend to cause ESD events of several kV. It is best practice to avoid ESD events by
attaching all conductive parts, especially the motors themselves to PCB ground, or to apply electrically
conductive plastic parts. In addition, the driver can be protected up to a certain degree against ESD
events or live plugging / pulling the motor, which also causes high voltages and high currents into
the motor connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the
dV/dt caused by ESD events. Larger capacitors will bring more benefit concerning ESD suppression,
but cause additional current flow in each chopper cycle, and thus increase driver power dissipation,
especially at high supply voltages. The values shown are example values – they might be varied
between 100pF and 1nF. The capacitors also dampen high frequency noise injected from digital parts
of the application PCB circuitry and thus reduce electromagnetic emission. A more elaborate scheme
uses LC filters to de-couple the driver outputs from the motor connector. Varistors in between of the
coil terminals eliminate coil overvoltage caused by live plugging. Optionally protect all outputs by a
varistor against ESD voltage.

Figure 3.10 Simple ESD enhancement and more elaborate motor output protection

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 21

SPI DATAGRAM STRUCTURE

MSB (transmitted first)

40 bit

LSB (transmitted last)

39 ...

... 0

 8 bit address
 8 bit SPI status

  32 bit data

39 ... 32

31 ... 0

 to TMC2130
RW + 7 bit address
 from TMC2130
8 bit SPI status

8 bit data

8 bit data

8 bit data

8 bit data

39 / 38 ... 32

31 ... 24

23 ... 16

15 ... 8

7 ... 0

W

38...32

31...28

27...24

23...20

19...16

15...12

11...8

7...4

3...0

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1
0

9 8 7 6 5 4 3 2 1

0

4 SPI Interface

4.1 SPI Datagram Structure

The TMC2130 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the device must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.

Each datagram sent to the device is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set. Each register is accessed via 32
data bits even if it uses less than 32 data bits.

For simplification, each register is specified by a one byte address:

- For a read access the most significant bit of the address byte is 0.

- For a write access the most significant bit of the address byte is 1.

Most registers are write only registers, some can be read additionally, and there are also some read
only registers.

4.1.1 Selection of Write / Read (WRITE_notREAD)

The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.

A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.

Whenever data is read from or written to the TMC2130, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 22

SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32

Bit

Name

Comment

7 - unused

6 - unused

5 - unused

4 - unused

3

standstill

DRV_STATUS[31] – 1: Signals motor stand still

2

sg2

DRV_STATUS[24] – 1: Signals stallguard flag active

1

driver_error

GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT)

0

reset_flag

GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT)

Example:

For a read access to the register (DRV_STATUS) with the address 0x6F, the address byte has
to be set to 0x6F in the access preceding the read access. For a write access to the register
(CHOPCONF), the address byte has to be set to 0x80 + 0x6C = 0xEC. For read access, the data
bit might have any value (-). So, one can set them to 0.

action data sent to TMC2130 data received from TMC2130
read DRV_STATUS  0x6F00000000  0xSS & unused data
read DRV_STATUS  0x6F00000000  0xSS & DRV_STATUS
write CHOPCONF:= 0x00ABCDEF  0xEC00ABCDEF  0xSS & DRV_STATUS
write CHOPCONF:= 0x00123456  0xEC00123456  0xSS00ABCDEF

*)S: is a placeholder for the status bits SPI_STATUS

4.1.2 SPI Status Bits Transferred with Each Datagram Read Back

New status information becomes latched at the end of each access and is available with the next SPI
transfer.

4.1.3 Data Alignment

All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.

4.2 SPI Signals

The SPI bus on the TMC2130 has four signals:

- SCK – bus clock input

- SDI – serial data input

- SDO – serial data output

- CSN – chip select input (active low)

The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC2130.

If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.

CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 23

CSN

SCK

SDI

SDO

t

CC

t

CC

t

CL

t

CH

bit39 bit38 bit0

bit39 bit38 bit0

t

DO

t

ZC

t

DU

t

DH

t

CH

SPI interface timing

AC-Characteristics

clock period: t

CLK

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SCK valid before or after change
of CSN

tCC 10

ns

CSN high time

t

CSH

*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only

t

CLK

*)

>2t

CLK

+10

ns

SCK low time

tCL

*) Min time is for
synchronous CLK
only

t

CLK

*)

>t

CLK

+10

ns

SCK high time

tCH

*) Min time is for
synchronous CLK
only

t

CLK

*)

>t

CLK

+10

ns

SCK frequency using internal
clock

f

SCK

assumes minimum
OSC frequency

4

MHz

SCK frequency using external
16MHz clock

f

SCK

assumes
synchronous CLK

8

MHz

SDI setup time before rising
edge of SCK

tDU 10

ns

SDI hold time after rising edge
of SCK

tDH 10

ns

Data out valid time after falling
SCK clock edge

tDO

no capacitive load
on SDO

t

FILT

+5

ns

SDI, SCK and CSN filter delay
time

t

FILT

rising and falling
edge

12

20

30

ns

4.3 Timing

The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.

Figure 4.1 SPI timing

Hint

Usually this SPI timing is referred to as SPI MODE 3

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 24

NOTATION OF HEXADECIMAL AND BINARY NUMBERS

0x

precedes a hexadecimal number, e.g. 0x04

%

precedes a multi-bit binary number, e.g. %100

NOTATION OF R/W FIELD

R

Read only

W

Write only

R/W

Read- and writable register

R+C

Clear upon read

REGISTER

DESCRIPTION

General Configuration Registers

These registers contain

- global configuration

- global status flags

- interface configuration

- and I/O signal configuration

Velocity Dependent Driver Feature Control Register
Set

This register set offers registers for

- driver current control

- setting thresholds for coolStep operation

- setting thresholds for different chopper modes

- setting thresholds for dcStep operation

Motor Driver Register Set

This register set offers registers for

- setting / reading out microstep table and

counter

- chopper and driver configuration

- coolStep and stallGuard2 configuration

- dcStep configuration

- reading out stallGuard2 values and driver error

flags

dcStep Minimum Velocity

Setting for minimum dcStep velocity

5 Register Mapping

This chapter gives an overview of the complete register set. Some of the registers bundling a number
of single bits are detailed in extra tables. The functional practical application of the settings is detailed
in dedicated chapters.

Note

- All registers become reset to 0 upon power up, unless otherwise noted.

- Add 0x80 to the address Addr for write accesses!

OVERVIEW REGISTER MAPPING

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 25

GENERAL CONFIGURATION REGISTERS (0X00…0X0F)

R/W

Addr

n

Register

Description / bit names

RW

0x00

17

GCONF

Bit

GCONF – Global configuration flags

0

I_scale_analog
0: Normal operation, use internal reference voltage
1: Use voltage supplied to AIN as current reference

1

internal_Rsense

0: Normal operation
1: Internal sense resistors. Use current supplied into

AIN as reference for internal sense resistor

2

en_pwm_mode

1: stealthChop voltage PWM mode enabled

(depending on velocity thresholds). Switch from
off to on state while in stand still, only.

3

enc_commutation

1: Enable commutation by full step encoder

(DCIN_CFG5 = ENC_A, DCEN_CFG4 = ENC_B)

4

shaft

1: Inverse motor direction

5

diag0_error

1: Enable DIAG0 active on driver errors:
Over temperature (ot), short to GND (s2g),

undervoltage chargepump (uv_cp)
DIAG0 always shows the reset-status, i.e. is active low
during reset condition.

6

diag0_otpw

1: Enable DIAG0 active on driver over temperature

prewarning (otpw)

7

diag0_stall

1: Enable DIAG0 active on motor stall (set

TCOOLTHRS before using this feature)

8

diag1_stall

1: Enable DIAG1 active on motor stall (set

TCOOLTHRS before using this feature)

9

diag1_index

1: Enable DIAG1 active on index position (microstep

look up table position 0)

10

diag1_onstate

1: Enable DIAG1 active when chopper is on (for the

coil which is in the second half of the fullstep)

11

diag1_steps_skipped
1: Enable output toggle when steps are skipped in

dcStep mode (increment of LOST_STEPS). Do not

enable in conjunction with other DIAG1 options.

12

diag0_int_pushpull

0: DIAG0 is open collector output (active low)
1: Enable DIAG0 push pull output (active high)

13

diag1_pushpull

0: DIAG1 is open collector output (active low)
1: Enable DIAG1 push pull output (active high)

14

small_hysteresis

0: Hysteresis for step frequency comparison is 1/16
1: Hysteresis for step frequency comparison is 1/32

5.1 General Configuration Registers

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 26

GENERAL CONFIGURATION REGISTERS (0X00…0X0F)

R/W

Addr

n

Register

Description / bit names

15

stop_enable

0: Normal operation
1: Emergency stop: DCIN stops the sequencer when

tied high (no steps become executed by the

sequencer, motor goes to standstill state).

16

direct_mode

0: Normal operation
1: Motor coil currents and polarity directly

programmed via serial interface: Register XDIRECT

(0x2D) specifies signed coil A current (bits 8..0)

and coil B current (bits 24..16). In this mode, the

current is scaled by IHOLD setting. Velocity based

current regulation of stealthChop is not available

in this mode. The automatic stealthChop current

regulation will work only for low stepper motor

velocities.

17

test_mode

0: Normal operation
1: Enable analog test output on pin DCO. IHOLD[1..0]

selects the function of DCO:

0…2: T120, DAC, VDDH
Attention: Not for user, set to 0 for normal operation!

R+C

0x01

3

GSTAT

Bit

GSTAT – Global status flags

0

reset

1: Indicates that the IC has been reset since the last

read access to GSTAT. All registers have been

cleared to reset values.

1

drv_err
1: Indicates, that the driver has been shut down

due to overtemperature or short circuit detection

since the last read access. Read DRV_STATUS for

details. The flag can only be reset when all error

conditions are cleared.

2

uv_cp
1: Indicates an undervoltage on the charge pump.

The driver is disabled in this case.

R

0x04

8

+ 8 IOIN

Bit

INPUT

Reads the state of all input pins available

0

STEP

1

DIR

2

DCEN_CFG4

3

DCIN_CFG5

4

DRV_ENN_CFG6

5

DCO

6

This bit always shows 1.

7

Don’t care.

31..
24

VERSION: 0x11=first version of the IC
Identical numbers mean full digital compatibility.

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 27

VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET (0X10…0X1F)

R/W

Addr

n

Register

Description / bit names

W

0x10

5

+

5

+

4

IHOLD_IRUN

Bit

IHOLD_IRUN – Driver current control

4..0

IHOLD
Standstill current (0=1/32…31=32/32)
In combination with stealthChop mode, setting
IHOLD=0 allows to choose freewheeling or coil
short circuit for motor stand still.

12..8

IRUN
Motor run current (0=1/32…31=32/32)

Hint: Choose sense resistors in a way, that normal
IRUN is 16 to 31 for best microstep performance.

19..16

IHOLDDELAY

Controls the number of clock cycles for motor
power down after a motion as soon as standstill is
detected (stst=1) and TPOWERDOWN has expired.
The smooth transition avoids a motor jerk upon
power down.

0: instant power down

1..15: Delay per current reduction step in multiple
of 2^18 clocks

W

0x11

8

TPOWER
DOWN

TPOWERDOWN sets the delay time after stand still (stst) of the

motor to motor current power down. Time range is about 0 to
4 seconds.

0…((2^8)-1) * 2^18 t

CLK

R

0x12

20

TSTEP

Actual measured time between two 1/256 microsteps derived
from the step input frequency in units of 1/fCLK. Measured
value is (2^20)-1 in case of overflow or stand still.

All TSTEP related thresholds use a hysteresis of 1/16 of the
compare value to compensate for jitter in the clock or the step
frequency. The flag small_hysteresis modifies the hysteresis to
a smaller value of 1/32.
(Txxx*15/16)-1 or
(Txxx*31/32)-1 is used as a second compare value for each
comparison value.
This means, that the lower switching velocity equals the
calculated setting, but the upper switching velocity is higher as
defined by the hysteresis setting.

In dcStep mode TSTEP will not show the mean velocity of the
motor, but the velocities for each microstep, which may not be
stable and thus does not represent the real motor velocity in
case it runs slower than the target velocity.

W

0x13

20

TPWMTHRS

This is the upper velocity for stealthChop voltage PWM mode.
TSTEP ≥ TPWMTHRS

- stealthChop PWM mode is enabled, if configured

- dcStep is disabled

5.2 Velocity Dependent Driver Feature Control Register Set

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TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 28

VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET (0X10…0X1F)

R/W

Addr

n

Register

Description / bit names

W

0x14

20

TCOOLTHRS

This is the lower threshold velocity for switching on smart
energy coolStep and stallGuard feature. (unsigned)

Set this parameter to disable coolStep at low speeds, where it
cannot work reliably. The stall detection and stallGuard output
signal becomes enabled when exceeding this velocity. In non­dcStep mode, it becomes disabled again once the velocity falls
below this threshold.

TCOOLTHRS ≥ TSTEP ≥ THIGH:

- coolStep is enabled, if configured

- stealthChop voltage PWM mode is disabled

TCOOLTHRS ≥ TSTEP

- Stop on stall and stall output signal is enabled, if

configured

W

0x15

20

THIGH

This velocity setting allows velocity dependent switching into
a different chopper mode and fullstepping to maximize torque.
(unsigned)
The stall detection feature becomes switched off for 2-3
electrical periods whenever passing THIGH threshold to
compensate for the effect of switching modes.

TSTEP ≤ THIGH:

- coolStep is disabled (motor runs with normal current

scale)

- stealthChop voltage PWM mode is disabled

- If vhighchm is set, the chopper switches to chm=1

with TFD=0 (constant off time with slow decay, only).

- chopSync2 is switched off (SYNC=0)

- If vhighfs is set, the motor operates in fullstep mode

and the stall detection becomes switched over to
dcStep stall detection.

microstep velocity time reference t for velocities: TSTEP = f

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CLK

/ f

STEP

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 29

SPI MODE REGISTER (0X2D)

R/W

Addr

n

Register

Description / bit names

Range [Unit]

RW

0x2D

32

XDIRECT

direct_mode

0: Normal operation
1: Directly SPI driven motor current

Direct mode operation:
XDIRECT specifies Motor coil currents and
polarity directly programmed via the serial
interface. Use signed, two’s complement
numbers.

Coil A current (bits 8..0) (signed)
Coil B current (bits 24..16) (signed)
Range: +-248 for normal operation, up to +-255
with stealthChop

In this mode, the current is scaled by IHOLD
setting. Velocity based current regulation of
voltage PWM is not available in this mode. The
automatic voltage PWM current regulation will
work only for low stepper motor velocities.
dcStep is not available in this mode. coolStep
and stallGuard only can be used, when
additionally supplying a STEP signal. This will
also enable automatic current scaling.

±255
for both coils

DCSTEP MINIMUM VELOCITY REGISTER (0X33)

R/W

Addr

n

Register

Description / bit names

W

0x33

23

VDCMIN

The automatic commutation dcStep becomes enabled by the
external signal DCEN. VDCMIN is used as the minimum step
velocity when the motor is heavily loaded.

Hint: Also set DCCTRL parameters in order to operate dcStep.

5.3 SPI Mode Register

This register cannot be used in STEP/DIR mode.

5.4 dcStep Minimum Velocity Register

time reference t for VDCMIN: t = 2^24 / f

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CLK

TMC2130 DATASHEET (Rev. 1.08 / 2016-SEP-21) 30

MICROSTEPPING CONTROL REGISTER SET (0X60…0X6B)

R/W

Addr

n

Register

Description / bit names

Range [Unit]

W

0x60

32

MSLUT[0]

microstep
table entries
0…31

Each bit gives the difference between entry x
and entry x+1 when combined with the cor­responding MSLUTSEL W bits:
0: W= %00: -1
%01: +0
%10: +1
%11: +2
1: W= %00: +0
%01: +1
%10: +2
%11: +3
This is the differential coding for the first
quarter of a wave. Start values for CUR_A and

CUR_B are stored for MSCNT position 0 in
START_SIN and START_SIN90.

ofs31, ofs30, …, ofs01, ofs00

…

ofs255, ofs254, …, ofs225, ofs224

32x 0 or 1

reset default=
sine wave
table

W

0x61

…

0x67

7

x

32

MSLUT[1...7]

microstep
table entries
32…255

7x
32x 0 or 1

reset default=
sine wave
table

W

0x68

32

MSLUTSEL

This register defines four segments within
each quarter MSLUT wave. Four 2 bit entries
determine the meaning of a 0 and a 1 bit in
the corresponding segment of MSLUT.

See separate table!

0<X1<X2<X3
reset default=
sine wave
table

W

0x69

8

+ 8 MSLUTSTART

bit 7… 0: START_SIN
bit 23… 16: START_SIN90

START_SIN gives the absolute current at
microstep table entry 0.
START_SIN90 gives the absolute current for
microstep table entry at positions 256.
Start values are transferred to the microstep
registers CUR_A and CUR_B, whenever the
reference position MSCNT=0 is passed.

START_SIN
reset default
=0

START_SIN 90
reset default
=247

R

0x6A

10

MSCNT

Microstep counter. Indicates actual position
in the microstep table for CUR_A. CUR_B uses
an offset of 256 (2 phase motor).
Hint: Move to a position where MSCNT is
zero before re-initializing MSLUTSTART or
MSLUT and MSLUTSEL.

0…1023

R

0x6B

9

+ 9 MSCURACT

bit 8… 0: CUR_A (signed):
Actual microstep current for

motor phase A as read from

MSLUT (not scaled by current)
bit 24… 16: CUR_B (signed):
Actual microstep current for

motor phase B as read from

MSLUT (not scaled by current)

+/-0...255

5.5 Motor Driver Registers

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