Transcend Information TS2GSD150 User Manual

Description

2GB 150x Secure Digital Card

Features

TS2GSD150 is a 2GB Secure Digital Card of 150X

ultra-high performance. It is specifically designed to

meet the security, capacity, performance and small

form factor requirements in newly emerging audio

and video consumer electronic devices. Based on

dual channel technology and high quality SLC (Single

Level Cell) NAND flash chip, TS2GSD150 is the ideal

companion to bring out the most from your

high-performance electronic devices.

Placement

• ROHS compliant product

• Operating Voltage: 2.7 ~ 3.6V

• Operating Temperature: -25 ~ 85°C

• Insertion/removal durability: 10,000 cycles

• Fully compatible with SD card spec. v1.1

• Mechanical Write Protection Switch

• Support clock frequencies: 0~50MHz

• Support different Bus width: x1, x4

• Support SD command class 0,2,4,5,7,8

• Supports Copy Protection for Recorded Media(CPRM) for

music and other commercial media

• Form Factor: 24mm x 32mm x 2.1mm

Front Back

Pin Definition

Pin No.

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Name Type Description Name Type Description

CD/DAT3

CMD PP Command/Response

SS1

CLK I Clock

SS2

DAT0 I/O/PP Data Line [Bit0]

DAT1 I/O/PP Data Line [Bit1]

DAT2

I/O/PP

S Supply voltage ground

S Supply voltage

S Supply voltage ground

I/O/PP Data Line [Bit2] RSV

SD Mode SPI Mode

Card Detect/Data Line [Bit3]

CS I

DI I

VSS S

VDD S

SCLK I

VSS2 S

DO O/PP

RSV

Chip Select (neg true)

Data In

Supply voltage ground

Supply voltage

Clock

Supply voltage ground

Data Out

Architecture

2GB 150x Secure Digital Card

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Bus Protocol

SD bus

Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit.

• Command: a command is a token which starts an operation. A command is sent from the host either to a single

card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.

• Response: a response is a token which is sent from an addressed card, or (synchronously) from all connected

cards, to the host as an answer to a previously received command. A response is transferred serially on the CMD line.

• Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.

2GB 150x Secure Digital Card

Figure 4: “no response” and “no data” operations

Card addressing is implemented using a session address, assigned to the card during the initializa-tion phase. The basic transaction on the SD bus is the command/response transaction (refer to Figure 4). This type of bus transactions transfer their information directly within the command or response structure. In addition, some operations have a data token.

Data transfers to/from the SD Memory Card are done in blocks. Data blocks always succeeded by CRC bits. Single and multiple block operations are defined. Note that the Multiple Block operation mode is better for faster write operation. A multiple block transmission is terminated when a stop command follows on the CMD line. Data transfer can be configured by the host to use single or multiple data lines.

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2GB 150x Secure Digital Card

Figure 5: (Multiple) Block read operation

The block write operation uses a simple busy signaling of the write operation duration on the DAT0 data line (see Figure 6) regardless of the number of data lines used for transferring the data.

Figure 6: (Multiple) Block write operation

Command tokens have the following coding scheme:

Figure 7: Command token format

Each command token is preceded by a start bit (‘0’) and succeeded by an end bit (‘1’). The total length is 48 bits. Each token is protected by CRC bits so that transmission errors can be detected and the operation may be repeated.

Response tokens have four coding schemes depending on their content. The token length is either 48 or 136 bits.

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The CRC protection algorithm for block data is a 16 bit CCITT polynomial.

2GB 150x Secure Digital Card

Figure 8: Response token format

In the CMD line the MSB bit is transmitted first the LSB bit is the last.

When the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 10). Start and end bits, as well as the CRC bits, are transmitted for every one of the DAT lines. CRC bits are calculated and checked for every DAT line individually. The CRC status response and Busy indica-tion will be sent by the card to the host on DAT0 only (DAT1-DAT3 during that period are don’t care).

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SPI bus

While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal (i.e. the length is a multiple of 8 clock cycles).

Similar to the SD protocol, the SPI messages consist of command, response and data-block tokens All communication between host and cards is controlled by the host (master). The host starts every bus transaction by asserting the CS signal low.

The response behavior in the SPI mode differs from the SD mode in the following three aspects:

• The selected card always responds to the command.

• Two new (8 & 16 bit) response structure is used

• When the card encounters a data retrieval problem, it will respond with an error response (which replaces the expected data block) rather than by a time-out as in the SD mode.

In addition to the command response, every data block sent to the card during write operations will be responded with a special data response token.

2GB 150x Secure Digital Card

• Data Read

Single and multiple block read commands are supported in SPI mode. However, in order to comply with the SPI industry standard, only two (unidirectional) signal are used. Upon reception of a valid read command the card will respond with a response token followed by a data token of the length defined in a previous SET_BLOCKLEN (CMD16) command. A multiple block read operation is terminated, similar to the SD protocol, with the STOP_TRANSMISSION command.

Figure 11: Read operation

A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial X

In case of a data retrieval error, the card will not transmit any data. Instead, a special data error token will be sent to the host Figure 12 shows a data read operation which terminated with an error token rather than a data block.

+X12 +X5 +1.

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