Transcend Information TS64GSSD25S-S, SSD25S, TS64GSSD25S-M, TS128GSSD25S-M, TS32GSSD25S-M User Manual

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2.5” Solid State Disk

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Description

Due to smaller size (fit the standard dimensions of

2.5” SATA Hard Disk Drives), huge capacity, high

speed, and low power consumption, Solid State Disk

is perfect replacement storage device for PCs,

Laptops, gaming systems, and handheld devices.

Placement

Features

• RoHS compliant

• Fully compatible with devices and OS that support the

SATAⅡ 3.0Gbps standard

• Non-volatile Flash Memory for outstanding data

retention

• Built-in ECC (Error Correction Code) functionality and

wear-leveling algorithm ensures highly reliable of data

transfer

• Shock resistance

Dimensions

Side Millimeters Inches

A

B

C

100.00 ± 0.40 3.937 ± 0.016

69.85 ± 0.20 2.750 ± 0.008

9.50 ± 0.15 0.374 ± 0.004

Transcend Information Inc.

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Specifications

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Physical Specification

Form Factor

Storage Capacities

Dimensions (mm)

Input Voltage

Weight

Connector

Environmental Specifications

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Length

Width

Height

2.5” Solid State Disk

2.5-inch HDD

8 GB to 192 GB

100.0 0 ± 0.40

69.85 ± 0.20

9.50 ± 0.15

5V ± 5%

55g ± 5g

SATA 7+15 pins combo connector

0

Operating Temperature

Storage Temperature

Power Requirements

Input Voltage

Mode Max. (mA) Max. (W)

Power Consumption

(8/16/32/64GB)

Power Consumption

(128GB)

Power Consumption

(192GB)

Write

Read

Idle

Write

Read

Idle

Write

Read

Idle

(peak)

℃ to 70 ℃

℃ to 85 ℃

- 40

5V ± 5%

@25℃

476.1 2.4

426.2 2.1

144.0 0.7

541.6 2.7

461.2 2.3

142.1 0.7

573.3 2.9

483.1 2.4

146.2 0.7

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Performance

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TS8GSSD25S-S 150 MB/s 90 MB/s

TS16GSSD25S-M 150 MB/s 50 MB/s

TS16GSSD25S-S 150 MB/s 100 MB/s

TS32GSSD25S-M 150 MB/s 90 MB/s

TS32GSSD25S-S 150 MB/s 120 MB/s

TS64GSSD25S-M 150 MB/s 90 MB/s

TS64GSSD25S-S 170 MB/s 140 MB/s

TS128GSSD25S-M 150 MB/s 90 MB/s

TS192GSSD25S-M 150 MB/s 90 MB/s

Actual Capacity

TS8GSSD25S-S 15,621,984 15,498 16 63

TS16GSSD25S-M 31,277,056 16,383 16 63

TS16GSSD25S-S 31,277,056 16,383 16 63

TS32GSSD25S-M 62,586,880 16,383 16 63

TS32GSSD25S-S 62,586,880 16,383 16 63

TS64GSSD25S-M 125,206,528 16,383 16 63

TS64GSSD25S-S 125,206,528 16,383 16 63

TS128GSSD25S-M 250,445,824 16,383 16 63

TS192GSSD25S-M 375,685,120 16,383 16 63

Model P/N

Model P/N User Max. LBA Cylinder Head Sector

Sequential Read

Sequential Write

(Max.)

Transcend Information Inc.

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* Note: Reference to the IEC 60068-2-6 Testing procedures; Operating-Sine wave, 5-800Hz/1 oct., 1.5mm, 3g, 0.5 hr./axis, total 1.5 hrs.

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Reliability

Data Reliability

Data Retention

MTBF

Vibration

Operating

Non-Operating

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Supports BCH ECC 8 bits in 512 bytes

10 years

1,000,000 hours

3.0G, 5 - 800Hz

2.5” Solid State Disk

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Shock

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* Note: Reference to the IEC 60068-2-27 Testing procedures; Operating-Half-sine wave, 1500g, 0.5ms, 3 times/dir., total 18 times.

Regulations

Compliance

CE, FCC and BSMI

1500G, 0.5ms

Transcend Information Inc.

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Package Dimensions

Below figure illustrates the Transcend 2.5” SATA Solid State Disk. All dimensions are in mm.

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2.5” Solid State Disk

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Pin Assignments

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Pin No. Pin Name Pin No. Pin Name

01 GND 02 A+

03 A- 04 GND

05 B- 06 B+

07 GND 08 NC

09 NC 10 NC

11 GND 12 GND

13 GND 14 5V

15 5V 16 5V

17 GND 18 GND

19 GND 20 NC

21 NC 22 NC

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2.5” Solid State Disk

Pin Layout

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Block Diagram

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2.5” Solid State Disk

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Transcend Information Inc.

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Wear-Leveling algorithm

The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block

with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase

count is higher than the data blocks', it will activate the static wear leveling, replacing the not so frequently used user

blocks with the high erase count free blocks.

ECC algorithm

The controller use BCH8 ECC algorithm per 512 bytes. BCH8 can correct up to 8 random error bits within 512 data

bytes.

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Bad-block management

When the flash encounters ECC failed, program fail or erase fail, the controller will mark the block as bad block to

prevent the used of this block and caused data lost later on.

Transcend Information Inc.

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SATA Interface

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Out of bank signaling

There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE.

COMINIT, COMRESET and COMWAKE OOB signaling shall be achieved by transmission of either a burst of four Gen1

ALIGN

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P primitives or a burst composed of four Gen1 Dwords with each Dword composed of four D24.3 characters, each

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2.5” Solid State Disk

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burst having a duration of 160 UI

as depicted in Figure 4 and Table 2.

OOB. Each burst is followed by idle periods (at common-mode levels), having durations

Transcend Information Inc.

Figure 4 : OOB signals

Table 2 : OOB signal times

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COMRESET

COMRESET always originates from the host controller, and forces a hardware reset in the device. It is indicated by

transmitting bursts of data separated by an idle bus condition. The OOB COMRESET signal shall consist of no less than

six data bursts, including inter-burst temporal spacing. The COMRESET signal shall be:

1) Sustained/continued uninterrupted as long as the system hard reset is asserted, or

2) Started during the system hardware reset and ended some time after the negation of system hardware reset, or

3) Transmitted immediately following the negation of the system hardware reset signal.

The host controller shall ignore any signal received from the device from the assertion of the hardware reset signal until

the COMRESET signal is transmitted. Each burst shall be 160 Gen1 UI’s long (106.7 ns) and each inter-burst idle state

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2.5” Solid State Disk

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shall be 480 Gen1 UI’s long (320 ns). A COMRESET detector looksfor four consecutive bursts with 320 ns spacing

(nominal). Any spacing less than 175 ns or greater than 525 ns shall invalidate the COMRESET detector output. The

COMRESET interface signal to the Phy layer shall initiate the Reset sequence shown in Figure 5 below. The interface

shall be held inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly.

Transcend Information Inc.

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Description:

1. Host/device are powered and operating normally with some form of active communication.

2. Some condition in the host causes the host to issue COMRESET

3. Host releases COMRESET. Once the condition causing the COMRESET is released, the host releases the

COMRESET signal and puts the bus in a quiescent condition.

4. Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is

also the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT.

5. Host calibrates and issues a COMWAKE.

6. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional).

Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the

ALIGN sequence starting at the device's highest supported speed. After ALIGNP Dwords have been sent

Transcend Information Inc.

Figure 5 : comreset sequence

11

V1.08

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for 54.6us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP

primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional

speeds are available the device tries the next lower supported speed by sending ALIGNP Dwords at that rate for

54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the

lowest speed has been reached without response from the host, the device enters an error state.

7. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate.

Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at

the same speed as received. A host shall be designed such that it acquires lock in 54.6us (2048

nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword

times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with

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multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword

times) the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer.

8. Device locks – the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start

normal operation.

9. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation

may begin.

COMINIT

COMINIT always originates from the drive and requests a communication initialization. It is electrically identical to the

COMRESET signal except that it originates from the device and is sent to the host. It is used by the device to request a

reset from the host in accordance to the sequence shown in Figure 6, below.

Transcend Information Inc.

12

V1.08

Transcend Information TS64GSSD25S-S, SSD25S, TS64GSSD25S-M, TS128GSSD25S-M, TS32GSSD25S-M User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual