1
Symbol
Function
A0–A14
SDRAM address bus
BA0, BA1
SDRAM bank select
BG0, BG1
SDRAM bank group select
RAS_n
SDRAM row address strobe
CAS_n
SDRAM column address strobe
WE_n
SDRAM write enable
CS0_n, CS1_n
DIMM Rank Select Lines
CKE0, CKE1
SDRAM clock enable lines
ODT0, ODT1
SDRAM on-die termination control
lines
ACT_n
SDRAM activate
DQ0–DQ63
DIMM memory data bus
CB0–CB7
DIMM ECC check bits
DM_n/DBI_n/
Input data mask and data bus
inversion
DQS0_t–DQS8_t
SDRAM data strobes
(positive line of differential pair)
DQS0_c–DQS8_c
SDRAM data strobes
(negative line of differential pair)
CK0_t, CK1_t
SDRAM clocks
(positive line of differential pair)
CK0_c, CK1_c
SDRAM clocks
(negative line of differential pair)
PARITY
SDRAM parity input
VDD
SDRAM I/O and core power supply
VREFCA
SDRAM command/address
reference supply
VSS
Power supply return (ground)
VDDSPD
Serial SPD EEPROM positive
power supply
SCL
I2C serial bus clock for EEPROM
SDA
I2C serial bus data line for
EEPROM
SA0–SA2
I2C slave address select for
EEPROM
ALERT_n
SDRAM ALERT_n
VPP
SDRAM Supply
RESET_n
Set DRAMs to a Known State
EVENT_n
SPD signals a thermal event has
occurred
VTT
SDRAM I/O termination supply
RFU
Reserved for future use
NC
No Connection
NF
No function
260Pin DDR4 2133 SO-DIMM
4GB~8GB Based on 512Mx8
TS512MSH64V1H
TS1GSH64V1H
Description
DDR4 SO-DIMMs are high-speed and low power memory
modules that use 512Mx8bits DDR4 SDRAM in FBGA
package and a 4K-bit serial EEPROM on a 260-pin
printed circuit board. DDR4 SO-DIMMs are dual In-Line
memory modules and are intended for mounting into
260-pin edge connector sockets.
The synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges of DQS. The large range of
operation frequencies and programmable latencies allow
the same device to be useful for a variety of high
bandwidth and high performance memory system
Pin Identification
applications.
Features
RoHS compliant
JEDEC standard 1.2V ± 0.06V power supply
VDDQ=1.2V ± 0.06V
Clock Freq: 1067MHZ for 2133Mb/s/Pin.
Programmable CAS Latency: 10,11,12,13,14,15,16
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
Programmable /CAS Write Latency (CWL)
= 11, 14(DDR4-2133)
8 bit pre-fetch
Burst Length: 4, 8
Bi-directional Differential Data-Strobe
On Die Termination with ODT pin
Serial presence detect with EEPROM
On DIMM Thermal Sensor
Asynchronous reset
2
Dimensions (Unit: millimeter)
Note:
1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
3
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
01
VSS
89
VSS
177
DQS4_c
02
VSS
90
VSS
178
DM4_n/
DBI4_n
03
DQ5
91
CB1/NC
179
DQS4_t
04
DQ4
92
CB0/NC
180
VSS
05
VSS
93
VSS
181
VSS
06
VSS
94
VSS
182
DQ39
07
DQ1
95
DQS8_c
183
DQ38
08
DQ0
96
DM8_n/
DBI_n/NC
184
VSS
09
VSS
97
DQS8_t
185
VSS
10
VSS
98
VSS
186
DQ35
11
DQS0_c
99
VSS
187
DQ34
12
DM0_n/
DBI0_n
100
CB6/NC
188
VSS
13
DQS0_t
101
CB2/NC
189
VSS
14
VSS
102
VSS
190
DQ45
15
VSS
103
VSS
191
DQ44
16
DQ6
104
CB7/NC
192
VSS
17
DQ7
105
CB3/NC
193
VSS
18
VSS
106
VSS
194
DQ41
19
VSS
107
VSS
195
DQ40
20
DQ2
108
RESET_n
196
VSS
21
DQ3
109
CKE0
197
VSS
22
VSS
110
CKE1
198
DQS5_c
23
VSS
111
VDD
199
DM5_n/
DBI5_n
24
DQ12
112
VDD
200
DQS5_t
25
DQ13
113
BG1
201
VSS
26
VSS
114
ACT_n
202
VSS
27
VSS
115
BG0
203
DQ46
28
DQ8
116
ALERT_n
204
DQ47
29
DQ9
117
VDD
205
VSS
30
VSS
118
VDD
206
VSS
31
VSS
119
A12
207
DQ42
32
DQS1_c
120
A11
208
DQ43
33
DM1_n/
DBI_n
121
A9
209
VSS
34
DQS1_t
122
A7
210
VSS
35
VSS
123
VDD
211
DQ52
36
VSS
124
VDD
212
DQ53
37
DQ15
125
A8
213
VSS
38
DQ14
126
A5
214
VSS
39
VSS
127
A6
215
DQ49
40
VSS
128
A4
216
DQ48
41
DQ10
129
VDD
217
VSS
42
DQ11
130
VDD
218
VSS
43
VSS
131
A3
219
DQS6_c
44
VSS
132
A2
220
DM6_n/
DBI6_n
45
DQ21
133
A1
221
DQS6_t
46
DQ20
134
EVENT_n,
NF
222
VSS
47
VSS
135
VDD
223
VSS
48
VSS
136
VDD
224
DQ54
49
DQ17
137
CK0_t
225
DQ55
50
DQ16
138
CK1_t/NF
226
VSS
51
VSS
139
CK0_c
227
VSS
52
VSS
140
CK1_c/NF
228
DQ50
53
DQS2_c
141
VDD
229
DQ51
54
DM2_n/
DBI2_n
142
VDD
230
VSS
55
DQS2_t
143
PARITY
231
VSS
56
VSS
144
A0
232
DQ60
57
VSS
145
BA1
233
DQ61
58
DQ22
146
A10/AP
234
VSS
59
DQ23
147
VDD
235
VSS
60
VSS
148
VDD
236
DQ57
61
VSS
149
CS0_n
237
DQ56
62
DQ18
150
BA0
238
VSS
63
DQ19
151
WE_n/
A14
239
VSS
64
VSS
152
RAS_n/
A16
240
DQS7_c
65
VSS
153
VDD
241
DM7_n/
DBI7_n
66
DQ28
154
VDD
242
DQS7_t
67
DQ29
155
ODT0
243
VSS
68
VSS
156
CAS_n/
A15
244
VSS
69
VSS
157
CS1_n
245
DQ62
70
DQ24
158
A13
246
DQ63
71
DQ25
159
VDD
247
VSS
72
VSS
160
VDD
248
VSS
73
VSS
161
ODT1
249
DQ58
74
DQS3_c
162
C0/
CS2_n/NC
250
DQ59
75
DM3_n/
DBI3_n
163
VDD
251
VSS
76
DQS3_t
164
VREFCA
252
VSS
77
VSS
165
C1, CS3_n,
NC
253
SCL
78
VSS
166
SA2
254
SDA
79
DQ30
167
VSS
255
VDDSPD
80
DQ31
168
VSS
256
SA0
81
VSS
169
DQ37
257
VPP
82
VSS
170
DQ36
258
VTT
83
DQ26
171
VSS
259
VPP
84
DQ27
172
VSS
260
SA1
85
VSS
173
DQ33 - -
86
VSS
174
DQ32 - -
87
CB5/NC
175
VSS - -
88
CB4/NC
176
VSS - -
Note:
1. NC for Non ECC SO-DIMM.
Pin Assignments
4
Block Diagram
4GB, 512Mx64 Module (1 Rank x8)
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
5
Block Diagram
8GB, 1Gx64 Module (2 Rank x8)
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
6
Parameter
Symbol
Rating
Unit
Note
Operating Temperature
TOPER
0 to 85
C
1,2
Note:
Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
At 0 - 85C, operation temperature range is the temperature which all DRAM specification will be
supported.
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.3 ~ 1.5
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.3 ~ 1.5
V
1
Voltage on VPP pin relative to Vss
VPP
-0.3 ~ 3.0
V
3
Voltage on any pin relative to Vss
VIN, VOUT
-0.3 ~ 1.5
V
1
Storage temperature
TSTG
-55~+100
C
1,2
Note:
Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
VPP must be equal or greater than VDD/VDDQ at all times.
Parameter
Symbol
Rating
Unit
Note
s
Min
Typ.
Max
Supply voltage
VDD
1.14
1.2
1.26
V
1, 2
Supply voltage for Output
VDDQ
1.14
1.2
1.26
V
1, 2
Wordline supply voltage
VPP
2.375
2.5
2.75
V
3
Note:
Under all conditions VDDQ must be less than or equal to VDD.
VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
DC bandwidth is limited to 20MHz
Parameter
Symbol
DDR4-1600/1866/2133
Unit
Note
Min
Max
I/O Reference Voltage (CMD/ADD)
VREFCA(DC)
0.49*VDDQ
0.51*VDDQ
V
1,2
DC Input Logic High
VIH(DC)
VREF+0.075
VDD
V
DC Input Logic Low
VIL(DC)
VSS
VREF-0.075
V
AC Input Logic High
VIH(AC)
VREF+0.1
Note 1
V
AC Input Logic Low
VIL(AC)
Note 1
VREF-0.1
V
Note:
The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1%
VDD (for reference: approx. ± 12mV)
For reference: approx. VDD/2 ± 12mV
Operating Temperature Condition
Absolute Maximum DC Ratings
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.5)
Single-ended AC & DC input levels for Command and Address
7
Parameter
Symbol
DDR4-1600/1866/2133
Unit
Note
Min
Max
differential input high DC
VIHdiff(DC)
+0.150
NOTE 3
V
1
differential input low DC
VILdiff(DC)
NOTE 3
-0.150
V 1 differential input high AC
VIHdiff(AC)
2 x (VIH(AC) - VREF)
NOTE 3
V 2 differential input low AC
VILdiff(AC)
NOTE 3
2 x (VIL(AC) -VREF)
V
2
Note:
Used to define a differential signal slew-rate.
For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
These values are not defined; however, the differential signals CK_t - CK_c, need to be within the
respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for
overshoot and undershoot.
Parameter
Symbol
DDR4-1600/1866/2133
Unit
Note
DC output high measurement level
VOH(DC)
1.1 x VDDQ
V
DC output mid measurement level
VOM(DC)
0.8 x VDDQ
V
DC output low measurement level
VOL(DC)
0.5 x VDDQ
V
AC output high measurement level
VOH(AC)
(0.7 + 0.15) x VDDQ
V
1
AC output low measurement level
VOL(AC)
(0.7 - 0.15) x VDDQ
V
1
Note:
The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output
peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ.
Parameter
Symbol
DDR4-1600/1866/2133
Unit
Note
AC differential output high
measurement level
VOHdiff(AC)
+0.3 x VDDQ
V
1
AC differential output low
measurement level
VOLdiff(AC)
-0.3 x VDDQ
V
1
Note:
The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak
swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the
differential outputs.
Differential AC and DC Input Levels
Single-ended AC & DC output levels
Differential AC & DC output levels
8
Parameter
Symbol
DDR4 2133 CL15
Unit
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD0
480
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS =
tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD1
520
mA
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2P
240
mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
IDD2Q
312
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD2N
368
mA
Active power - down current; All banks open; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD3P
352
mA
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD3N
504
mA
Operating burst read current; All banks open, Continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD4R
1200
mA
Operating burst write current; All banks open, Continuous burst writes; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R
IDD4W
1280
mA
Burst refresh current; tCK = tCK(IDD); Refresh command at every
tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD5
1520
mA
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
IDD6
160
mA
Operating bank interleave read current; All bank interleaving reads,
IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =
tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE
during DESELECTs; Data pattern is same as IDD4R;
IDD7
1480
mA
Note:
Module IDD was calculated on the specific brand DRAM(3Xnm) component IDD and can be differently
measured according to DQ loading capacitor.
IDD Specification parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
4GB, 512Mx64 Module (1 Rank x8)
9
Parameter
Symbol
DDR4 2133 CL15
Unit
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD0
720
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS =
tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD1
760
mA
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2P
480
mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
IDD2Q
624
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD2N
736
mA
Active power - down current; All banks open; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD3P
704
mA
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD3N
1008
mA
Operating burst read current; All banks open, Continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD4R
1440
mA
Operating burst write current; All banks open, Continuous burst writes; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R
IDD4W
1520
mA
Burst refresh current; tCK = tCK(IDD); Refresh command at every
tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD5
1760
mA
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
IDD6
320
mA
Operating bank interleave read current; All bank interleaving reads,
IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =
tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE
during DESELECTs; Data pattern is same as IDD4R;
IDD7
1720
mA
Note:
Module IDD was calculated on the specific brand DRAM(3Xnm) component IDD and can be differently
measured according to DQ loading capacitor.
8GB, 1Gx64 Module (2 Rank x8)
10
Speed
DDR4 2133
Unit
Parameter
Symbol
Min
Max
Average Clock Period
tCK
0.938
<1.071
ns
CK high-level width
tCH
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
tCK
DQS_t,DQS_c to DQ skew, per group, per
access
tDQSQ - TBD
tCK/2
DQS_t,DQS_c to DQ Skew determin-istic,
per group, per access
tDQSQ - TBD
tCK/2
DQ output hold time from DQS_t,DQS_c
tQH
TBD
-
tCK/2
DQ output hold time deterministic from
DQS_t, DQS_c
tQH
TBD
-
UI
DQS_t,DQS_c to DQ Skew total, per group,
per access; DBI enabled
tDQSQ - TBD
UI
DQ output hold time total from DQS_t,
DQS_c; DBI enabled
tQH
TBD
-
UI
DQ to DQ offset , per group, per ac-cess
referenced to DQS_t, DQS_c
tDQSQ
TBD
TBD
UI
DQS_t, DQS_c differential READ Pre-amble
(2 clock preamble)
tRPRE
0.9
TBD
tCK
DQS_t, DQS_c differential READ Postamble
tRPST
TBD
TBD
tCK
DQS_t, DQS_c differential WRITE Preamble
tWPRE
0.9
-
tCK
DQS_t, DQS_c differential WRITE Postamble
tWPST
TBD
TBD
tCK
DQS_t and DQS_c low-impedance time
(Referenced from RL-1)
tLZ(DQS)
-360
180
ps
DQS_t and DQS_c high-impedance time
(Referenced from RL+BL/2)
tHZ(DQS) - 180
ps
DQS_t, DQS_c differential input low pulse
width
tDQSL
0.46
0.54
tCK
DQS_t, DQS_c differential input high pulse
width
tDQSH
0.46
0.54
tCK
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge (1 clock preamble)
tDQSS
-0.27
0.27
tCK
DQS_t, DQS_c falling edge setup time to
CK_t, CK_c rising edge
tDSS
0.18
-
tCK
DQS_t, DQS_c falling edge hold time from
CK_t, CK_c rising edge
tDSH
0.18
-
tCK
Delay from start of internal write trans-action
to internal read command for different bank
group
tWTR_S
Max(2nCK, 2.5ns)
-
Delay from start of internal write trans-action
to internal read command for same bank
group
tWTR_L
Max(4nCK,7.5ns)
-
WRITE recovery time
tWR
15
-
ns
Mode Register Set command cycle time
tMRD
8
-
nCK
CAS_n to CAS_n command delay for same
bank group
tCCD_L
6
-
nCK
Timing Parameters & Specifications
11
Speed
DDR4 2133
Unit
Parameter
Symbol
Min
Max
CAS_n to CAS_n command delay for
different bank group
tCCD_S
4
-
nCK
Auto precharge write recovery + precharge
time
tDAL
tWR+tRP/tCK
nCK
ACTIVATE to ACTIVATE Command delay to
different bank group for 2KB page size
tRRD_S(2K)
Max(4nCK,5.3ns)
-
nCK
ACTIVATE to ACTIVATE Command delay to
different bank group for 1KB page size
tRRD_S(1K)
Max(4nCK,3.7ns)
-
nCK
ACTIVATE to ACTIVATE Command delay to
different bank group for 1/ 2KB page size
tRRD_S
(1/ 2K)
Max(4nCK,3.7ns)
-
nCK
ACTIVATE to ACTIVATE Command delay to
same bank group for 2KB page size
tRRD_L(2K)
Max(4nCK,6.4ns)
-
nCK
ACTIVATE to ACTIVATE Command delay to
same bank group for 1KB page size
tRRD_L(1K)
Max(4nCK,5.3ns)
-
nCK
ACTIVATE to ACTIVATE Command delay to
same bank group for 1/2KB page size
tRRD_L
(1/ 2K)
Max(4nCK,5.3ns)
-
nCK
Four activate window for 2KB page size
tFAW_2K
Max(28nCK, 30ns)
-
ns
Four activate window for 1KB page size
tFAW_1K
Max(20nCK, 21ns)
-
ns
Four activate window for 1/2KB page size
tFAW_1/2K
Max(16nCK, 15ns)
-
ns
Power-up and RESET calibration time
tZQinit
1024
-
nCK
Normal operation Full calibration time
tZQoper
512
-
nCK
Normal operation short calibration time
tZQCS
128
-
nCK
Exit Self Refresh to commands not re-quiring
a locked DLL
tXS
tRFC(min)+ 10ns
-
Exit Self Refresh to commands requir-ing a
locked DLL
tXSDLL
tDLLK(min)
-
Internal READ Command to PRE-CHARGE
Command delay
tRTP
Max(4nCK,7.5ns)
-
Minimum CKE low width for Self re-fresh
entry to exit timing
tCKESR
tCKE(min)+1nCK
-
Exit Power Down with DLL on to any valid
command;Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
tXP
Max (4nCK,6ns)
-
CKE minimum pulse width
tCKE
Max (3nCK,5ns)
-
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONAS
1.0
9.0
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFAS
1.0
9.0
ns
RTT dynamic change skew
tADC
0.3
0.7
tCK
12
TS512MSH64V1H Serial Presence Detect
Byte No.
Function Described
Standard Specification
Vendor Part
0
Number of Bytes Used / Number of Bytes in SPD
Device / CRC Coverage
CRC:0-255Byte
SPD Byte use: 512Byte
SPD Byte total: 512Byte
23
1
SPD Revision - -
2
Key Byte / DRAM Device Type
DDR4 SDRAM
0C
3
Key Byte / Module Type
SO-DIMM
03
4
SDRAM Density and Banks
4Gb, 16banks
84
5
SDRAM Addressing
ROW:15, Column:10
19
6
SDRAM Package Type
-
-
7
SDRAM Optional Features
-
-
8
SDRAM Thermal and Refresh Options
-
-
9
Other SDRAM Optional Features
-
-
10
Reserved - 00
11
Module Nominal Voltage, VDD
1.2V
03
12
Module Organization
1Rank, 8bits
01
13
Module Memory Bus Width
Non-ECC, 64bits
03
14
Module Thermal Sensor
Support
80
15-16
Reserved - 00
17
Timebases - 00
18
SDRAM Minimum Cycle Time (tCKAVGmin)
0.938ns
08
19
SDRAM Maximum Cycle Time (tCKAVGmax)
1.5ns
0C
20-23
CAS Latencies Supported
10, 11, 12, 13, 14, 15, 16
-
24
Minimum CAS Latency Time (tAAmin)
13.5ns
6C
25
Minimum RAS to CAS Delay Time (tRCDmin)
13.5ns
6C
26
Minimum Row Precharge Delay Time (tRPmin)
13.5ns
6C
27
Upper Nibbles for tRASmin and tRCmin
-
11
28
Minimum Active to Precharge Delay Time (tRASmin),
Least Significant Byte
33ns
08
29
Minimum Active to Active/Refresh Delay Time
(tRCmin), Least Significant Byte
46.5ns
74
30-31
Minimum Refresh Recovery Delay Time (tRFC1min)
260ns
20,08
32-33
Minimum Refresh Recovery Delay Time (tRFC2min)
160ns
00,05
34-35
Minimum Refresh Recovery Delay Time (tRFC4min)
110ns
70,03
36-37
Minimum Four Activate Window Delay Time
(tFAWmin)
21ns
00,A8
38
Minimum Activate to Activate Delay Time
(tRRD_Smin), different bank group
3.7ns
1E
39
Minimum Activate to Activate Delay Time
(tRRD_Lmin), same bank group
5.3ns
2B
40
Minimum CAS to CAS Delay Time (tCCD_Lmin),
same bank group
5.355ns
2B
41-59
Reserved - 00
60-77
Connector to SDRAM Bit Mapping
-
-
SERIAL PRESENCE DETECT SPECIFICATION
13
78-116
Reserved - 00
117
Fine Offset for Minimum CAS to CAS Delay Time
(tCCD_Lmin), same bank group
-
83
118
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Lmin), same bank group
-
B5
119
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Smin), different bank group
-
CE
120
Fine Offset for Minimum Active to Active/Refresh
Delay Time (tRCmin)
-
00
121
Fine Offset for Minimum Row Precharge Delay Time
(tRPmin)
-
00
122
Fine Offset for Minimum RAS to CAS Delay Time
(tRCDmin)
-
00
123
Fine Offset for Minimum CAS Latency Time (tAAmin)
-
00
124
Fine Offset for SDRAM Maximum Cycle Time
(tCKAVGmax)
-
00
125
Fine Offset for SDRAM Minimum Cycle Time
(tCKAVGmin)
-
C2
126-127
Cyclical Redundancy Code
-
-
128
Raw Card Extension, Module Nominal Height
30mm
0F
129
Module Maximum Thickness
Planar Double Sides
11
130
Reference Raw Card Used
Revision 0, Raw card A
00
131
Address Mapping from Edge Connector to DRAM
Standard
00
132-253
Reserved - 00
254-255
Cyclical Redundancy Code (CRC)
-
-
256-319
Reserved - 00
320-321
Module Manufacturer ID Code
Transcend
01,4F
322
Module Manufacturing Location
Taipei
54
323-324
Module Manufacturing Date
-
00
325-328
Module Serial Number
-
00
329-348
Module Part Number
TS512MSH64V1H
54
53
35
31
32
4D
53
48
36
34
56
31
48
20
20
20
20
20
20
20
349
Module Revision Code
-
00
350-351
DRAM Manufacturer ID Code
By Manufacturer
Variable
352
DRAM Stepping
-
00
353-381
Manufacturer Specific Data
By Manufacturer
Variable
382-383
Reserved - 00
384-551
End User Programmable
-
-
14
TS1GSH64V1H Serial Presence Detect
Byte No.
Function Described
Standard Specification
Vendor Part
0
Number of Bytes Used / Number of Bytes in SPD
Device / CRC Coverage
CRC:0-255Byte
SPD Byte use: 512Byte
SPD Byte total: 512Byte
23
1
SPD Revision - -
2
Key Byte / DRAM Device Type
DDR4 SDRAM
0C
3
Key Byte / Module Type
SO-DIMM
03
4
SDRAM Density and Banks
4Gb, 16banks
84
5
SDRAM Addressing
ROW:15, Column:10
19
6
SDRAM Package Type
-
-
7
SDRAM Optional Features
-
-
8
SDRAM Thermal and Refresh Options
-
-
9
Other SDRAM Optional Features
-
-
10
Reserved - 00
11
Module Nominal Voltage, VDD
1.2V
03
12
Module Organization
2Rank, 8bits
09
13
Module Memory Bus Width
Non-ECC, 64bits
03
14
Module Thermal Sensor
Support
80
15-16
Reserved - 00
17
Timebases - 00
18
SDRAM Minimum Cycle Time (tCKAVGmin)
0.938ns
08
19
SDRAM Maximum Cycle Time (tCKAVGmax)
1.5ns
0C
20-23
CAS Latencies Supported
10, 11, 12, 13, 14, 15, 16
-
24
Minimum CAS Latency Time (tAAmin)
13.5ns
6C
25
Minimum RAS to CAS Delay Time (tRCDmin)
13.5ns
6C
26
Minimum Row Precharge Delay Time (tRPmin)
13.5ns
6C
27
Upper Nibbles for tRASmin and tRCmin
-
11
28
Minimum Active to Precharge Delay Time (tRASmin),
Least Significant Byte
33ns
08
29
Minimum Active to Active/Refresh Delay Time
(tRCmin), Least Significant Byte
46.5ns
74
30-31
Minimum Refresh Recovery Delay Time (tRFC1min)
260ns
20,08
32-33
Minimum Refresh Recovery Delay Time (tRFC2min)
160ns
00,05
34-35
Minimum Refresh Recovery Delay Time (tRFC4min)
110ns
70,03
36-37
Minimum Four Activate Window Delay Time
(tFAWmin)
21ns
00,A8
38
Minimum Activate to Activate Delay Time
(tRRD_Smin), different bank group
3.7ns
1E
39
Minimum Activate to Activate Delay Time
(tRRD_Lmin), same bank group
5.3ns
2B
40
Minimum CAS to CAS Delay Time (tCCD_Lmin),
same bank group
5.355ns
2B
41-59
Reserved - 00
60-77
Connector to SDRAM Bit Mapping
-
-
78-116
Reserved - 00
15
117
Fine Offset for Minimum CAS to CAS Delay Time
(tCCD_Lmin), same bank group
-
83
118
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Lmin), same bank group
-
B5
119
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Smin), different bank group
-
CE
120
Fine Offset for Minimum Active to Active/Refresh
Delay Time (tRCmin)
-
00
121
Fine Offset for Minimum Row Precharge Delay Time
(tRPmin)
-
00
122
Fine Offset for Minimum RAS to CAS Delay Time
(tRCDmin)
-
00
123
Fine Offset for Minimum CAS Latency Time (tAAmin)
-
00
124
Fine Offset for SDRAM Maximum Cycle Time
(tCKAVGmax)
-
00
125
Fine Offset for SDRAM Minimum Cycle Time
(tCKAVGmin)
-
C2
126-127
Cyclical Redundancy Code
-
-
128
Raw Card Extension, Module Nominal Height
30mm
0F
129
Module Maximum Thickness
Planar Double Sides
11
130
Reference Raw Card Used
Revision 0, Raw card E
04
131
Address Mapping from Edge Connector to DRAM
Mirrored
01
132-253
Reserved - 00
254-255
Cyclical Redundancy Code (CRC)
-
-
256-319
Reserved - 00
320-321
Module Manufacturer ID Code
Transcend
01,4F
322
Module Manufacturing Location
Taipei
54
323-324
Module Manufacturing Date
-
00
325-328
Module Serial Number
-
00
329-348
Module Part Number
TS1GSH64V1H
54
53
31
47
53
48
36
34
56
31
48
20
20
20
20
20
20
20
20
20
349
Module Revision Code
-
00
350-351
DRAM Manufacturer ID Code
By Manufacturer
Variable
352
DRAM Stepping
-
00
353-381
Manufacturer Specific Data
By Manufacturer
Variable
382-383
Reserved - 00
384-551
End User Programmable
-
-
Loading...