TOSHIBA TMP86FM26UG Technical data

8 Bit Microcontroller

TLCS-870/C Series

TMP86FM26UG

The information contained herein is subject to change without notice. 021023_D

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications.

Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A

The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of

human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B

The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C

The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E

For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

Revision History

Date Revision

2007/3/27 1 First Release

2007/7/27 2 Contents Revised

Table of Contents

TMP86FM26UG

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Operational Description

2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Memory Address Map............................................................................................................................... 9

2.1.2 Program Memory (Flash) .......................................................................................................................... 9

2.1.3 Data Memory (RAM)............................................................................................................................... 10

2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Clock Generator...................................................................................................................................... 10

2.2.2 Timing Generator.................................................................................................................................... 12

2.2.2.1 Configuration of timing generator

2.2.2.2 Machine cycle

2.2.3 Operation Mode Control Circuit .............................................................................................................. 13

2.2.3.1 Single-clock mode

2.2.3.2 Dual-clock mode

2.2.3.3 STOP mode

2.2.4 Operating Mode Control ......................................................................................................................... 18

2.2.4.1 STOP mode

2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode

2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)

2.2.4.4 SLOW mode

2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.3.1 External Reset Input ............................................................................................................................... 33

2.3.2 Address trap reset .................................................................................................................................. 34

2.3.3 Watchdog timer reset.............................................................................................................................. 34

2.3.4 System clock reset.................................................................................................................................. 34

2.3.5 Clock Stop Detection Reset .................................................................................................................... 35

2.3.6 Internal Reset Detection Flags ............................................................................................................... 35

2.4 Clock Stop Detection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.1 Configuration .......................................................................................................................................... 36

2.4.2 Control .................................................................................................................................................... 36

2.4.2.1 Setting the minimum and maximum values for clock stop detection

2.4.2.2 Enabling/Disabling the clock stop detection circuit

2.4.2.3 Generating and releasing a reset

3. Interrupt Control Circuit

3.1 Interrupt latches (IL21 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2.1 Interrupt master enable flag (IMF) .......................................................................................................... 42

3.2.2 Individual interrupt enable flags (EF21 to EF4) ...................................................................................... 43

Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3.1 Interrupt acceptance processing is packaged as follows........................................................................ 45

3.3.2 Saving/restoring general-purpose registers ............................................................................................ 46

3.3.2.1 Using PUSH and POP instructions

3.3.2.2 Using data transfer instructions

3.3.3 Interrupt return ........................................................................................................................................ 47

3.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.4.1 Address error detection .......................................................................................................................... 48

3.4.2 Debugging .............................................................................................................................................. 48

3.5 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.6 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.7 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4. Special Function Register (SFR)

4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5. I/O Ports

5.1 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.2 Port P2 (P24 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3 Port P3 (P33 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.4 Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5 Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.6 Port P7(P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6. Watchdog Timer (WDT)

6.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.2.1 Malfunction Detection Methods Using the Watchdog Timer ................................................................... 72

6.2.2 Watchdog Timer Enable ......................................................................................................................... 73

6.2.3 Watchdog Timer Disable ........................................................................................................................ 74

6.2.4 Watchdog Timer Interrupt (INTWDT)...................................................................................................... 74

6.2.5 Watchdog Timer Reset ........................................................................................................................... 75

6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.3.1 Selection of Address Trap in Internal RAM (ATAS) ................................................................................ 76

6.3.2 Selection of Operation at Address Trap (ATOUT) .................................................................................. 76

6.3.3 Address Trap Interrupt (INTATRAP)....................................................................................................... 76

6.3.4 Address Trap Reset................................................................................................................................ 77

7. Time Base Timer (TBT)

7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.1.1 Configuration .......................................................................................................................................... 79

7.1.2 Control .................................................................................................................................................... 79

7.1.3 Function .................................................................................................................................................. 80

7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

7.2.1 Configuration .......................................................................................................................................... 81

7.2.2 Control .................................................................................................................................................... 81

8. 18-Bit Timer/Counter (TC1)

8.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

8.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.3.1 Timer mode............................................................................................................................................. 87

8.3.2 Event Counter mode............................................................................................................................... 88

8.3.3 Pulse Width Measurement mode............................................................................................................ 89

8.3.4 Frequency Measurement mode .............................................................................................................. 90

9. 8-Bit TimerCounter (TC3, TC4)

9.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.2 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

9.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9.3.1 8-Bit Timer Mode (TC3 and 4) ................................................................................................................ 99

9.3.2 8-Bit Event Counter Mode (TC3, 4) ...................................................................................................... 100

9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)................................................................... 100

9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)................................................................ 103

9.3.5 16-Bit Timer Mode (TC3 and 4) ............................................................................................................ 105

9.3.6 16-Bit Event Counter Mode (TC3 and 4) .............................................................................................. 106

9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)........................................................ 106

9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................. 109

9.3.9 Warm-Up Counter Mode....................................................................................................................... 111

9.3.9.1 Low-Frequency Warm-up Counter Mode

9.3.9.2 High-Frequency Warm-Up Counter Mode

(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)

(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)

10. 8-Bit TimerCounter (TC5, TC6)

10.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

10.2 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

10.3.1 8-Bit Timer Mode (TC5 and 6) ............................................................................................................ 118

10.3.2 8-Bit Event Counter Mode (TC6) ........................................................................................................ 119

10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC6)..................................................................... 119

10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC6).................................................................. 122

10.3.5 16-Bit Timer Mode (TC5 and 6) .......................................................................................................... 124

10.3.6 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)...................................................... 125

10.3.7 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ........................................... 128

10.3.8 Warm-Up Counter Mode..................................................................................................................... 130

10.3.8.1 Low-Frequency Warm-up Counter Mode

10.3.8.2 High-Frequency Warm-Up Counter Mode

(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)

(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)

11. Real-Time Clock (RTC)

11.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

11.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

11.2.1 RTC control registers.......................................................................................................................... 141

11.2.2 Clock counter registers ....................................................................................................................... 141

11.2.3 RTC counters 1 and 2......................................................................................................................... 141

11.2.4 RTC counter monitor registers............................................................................................................ 142

11.2.5 RTC counter 1 compare register ........................................................................................................ 144

iii

11.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

11.3.1 Error measurement mode (RTCCR1<ADJEN1, ADJEN2>) ............................................................... 145

11.3.2 Clock counter lock control (RTCCR1<THOLD>) ................................................................................ 150

11.3.3 RTCOUT pin output ............................................................................................................................ 152

12. Synchronous Serial Interface (SIO)

12.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

12.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

12.3 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

12.3.1 Clock source ....................................................................................................................................... 155

12.3.1.1 Internal clock

12.3.1.2 External clock

12.3.2 Shift edge............................................................................................................................................ 157

12.3.2.1 Leading edge

12.3.2.2 Trailing edge

12.4 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

12.5 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

12.6 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

12.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 158

12.6.2 4-bit and 8-bit receive modes ............................................................................................................. 160

12.6.3 8-bit transfer / receive mode ............................................................................................................... 161

13. Asynchronous Serial interface (UART0 )

13.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

13.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

13.3 Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

13.4 Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

13.5 Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

13.6 STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

13.7 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

13.8 Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

13.8.1 Data Transmit Operation .................................................................................................................... 168

13.8.2 Data Receive Operation ..................................................................................................................... 168

13.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

13.9.1 Parity Error.......................................................................................................................................... 169

13.9.2 Framing Error...................................................................................................................................... 169

13.9.3 Overrun Error ...................................................................................................................................... 169

13.9.4 Receive Data Buffer Full..................................................................................................................... 170

13.9.5 Transmit Data Buffer Empty ............................................................................................................... 170

13.9.6 Transmit End Flag .............................................................................................................................. 171

14. Asynchronous Serial interface (UART1 )

14.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

14.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.3 Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

14.4 Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

14.5 Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

14.6 STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

14.7 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

14.8 Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

14.8.1 Data Transmit Operation .................................................................................................................... 178

14.8.2 Data Receive Operation ..................................................................................................................... 178

14.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

14.9.1 Parity Error.......................................................................................................................................... 179

14.9.2 Framing Error...................................................................................................................................... 179

14.9.3 Overrun Error ...................................................................................................................................... 179

14.9.4 Receive Data Buffer Full..................................................................................................................... 180

14.9.5 Transmit Data Buffer Empty ............................................................................................................... 180

14.9.6 Transmit End Flag .............................................................................................................................. 181

15. Key-on Wakeup (KWU)

15.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

15.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

15.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

16. LCD Driver

16.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

16.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

16.2.1 LCD driving methods .......................................................................................................................... 187

16.2.2 Frame frequency................................................................................................................................. 188

16.2.3 Driving method for LCD driver ............................................................................................................ 189

16.2.3.1 When using the booster circuit (LCDCR<BRES>="1")

16.2.3.2 When using an external resistor divider (LCDCR<BRES>="0")

16.3 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

16.3.1 Display data setting ............................................................................................................................ 191

16.3.2 Blanking .............................................................................................................................................. 192

16.4 Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

16.4.1 Initial setting........................................................................................................................................ 193

16.4.2 Store of display data ........................................................................................................................... 193

16.4.3 Example of LCD drive output .............................................................................................................. 196

17. FLASH Memory

17.1 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

17.2 Conditions for Accessing the FLASH Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

17.3 Differences among Product Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

17.4 FLASH Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

17.4.1 Page Configuration ............................................................................................................................. 202

17.5 Data Memory of FLASH(address 8000H to 81FFH) . . . . . . . . . . . . . . . . . . . . . 204

17.5.1 Configuration ...................................................................................................................................... 204

17.5.2 Control ................................................................................................................................................ 205

17.5.3 FLASH Write Enable Control (EEPCR<EEPMD>) ............................................................................. 207

17.5.4 FLASH Write Forcible Stop (EEPCR<EEPRS>)................................................................................. 207

17.5.5 Power Control for the FLASH Control Circuit...................................................................................... 208

17.5.5.1 Software-based Power Control for the FLASH Control Circuit (EEPCR<MNPWDW>)

17.5.5.2 Automatic Power Control for the FLASH Control Circuit (EEPCR<ATPWDW>)

17.5.6 Accessing the FLASH Data Memory Area.......................................................................................... 211

17.5.6.1 Method of Developing the Control Program in the RAM Area

17.5.6.2 Method of Using Support Programs in the BOOT-ROM

17.6 FLASH Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

17.6.1 Configuration ...................................................................................................................................... 219

17.6.2 Control ................................................................................................................................................ 219

17.6.3 FLASH Write Enable Control (EEPCR<EEPMD>) ............................................................................. 219

17.6.4 FLASH Write Forcible Stop (EEPCR<EEPRS>)................................................................................. 219

17.6.5 Power Control for the FLASH Control Circuit...................................................................................... 219

17.6.6 Accessing the FLASH Program Memory Area.................................................................................... 219

18. Input/Output Circuit

18.1 Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

18.2 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

19. Electrical Characteristics

19.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

19.2 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

19.2.1 MCU mode.......................................................................................................................................... 224

19.2.2 Serial PROM mode............................................................................................................................. 224

19.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

19.4 Timer Counter 1 input (ECIN) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 226

19.5 LCD Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

19.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

19.7 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

19.8 Oscillating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

19.9 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

20. Package Dimensions

This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI).

CMOS 8-Bit Microcontroller

TMP86FM26UG

Note: Of the 32768 bytes of ROM (FLASH), 512 bytes can also be used as flash data memory.

1.1 Features

1. 8-bit single chip microcomputer TLCS-870/C series

- Instruction execution time :

- 132 types & 731 basic instructions

2. 21interrupt sources (External : 6 Internal : 15)

3. Input / Output ports (41 pins)

Large current output: 23pins (Typ. 20mA), LED direct drive

4. Watchdog Timer

5. Prescaler

- Time base timer

- Divider output function

6. 18-bit Timer/Counter : 1ch

- Timer Mode

- Event Counter Mode

- Pulse Width Measurement Mode

- Frequency Measurement Mode

7. 8-bit timer counter : 4 ch

- Timer, Event counter, Programmable divider output (PDO),

Product No.

(FLASH)

0.25 µs (at 16 MHz)

122 µs (at 32.768 kHz)

ROM

32768

bytes

RAM Package Emulation Chip

1024 bytes

LQFP64-P-1010-0.50E TMP86C926XB

• The information contained herein is subject to change without notice. 021023_D

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B

• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C

• The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E

• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

Page 1

1.1 Features TMP86FM26UG

Pulse width modulation (PWM) output,

Programmable pulse generation (PPG) modes

8. Real Time Clock : 1ch

9. 8-bit UART/SIO: 1 ch

10. 8-bit UART : 1 ch

11. Key-on wakeup : 4 ch

12. LCD driver/controller

Built-in voltage booster for LCD driver With display memory LCD direct drive capability (MAX 32 seg × 4 com) 1/4,1/3,1/2duties or static drive are programmably selectable

13. Clock operation

Single clock mode

Dual clock mode

14. Low power consumption operation

STOP mode: Oscillation stops. (Battery/Capacitor back-up.)

SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.)

SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.)

IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.

IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interruputs(CPU restarts).

IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts).

SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.

SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts).

SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruput.

15. Wide operation voltage:

2.7 V to 3.6 V at 16MHz /32.768 kHz

1.8 V to 3.6 V at 8 MHz /32.768 kHz

Page 2

1.2 Pin Assignment

TMP86FM26UG

P74 (SEG11)

P73 (SEG12)

P72 (SEG13)

P71 (SEG14)

P70 (SEG15)

P57 (SEG16)

P56 (SEG17)

SEG3

SEG4

SEG5

SEG6

SEG7

P77 (SEG8)

P76 (SEG9)

P75 (SEG10)

P55 (SEG18)

(TXD1/TC4/ (RXD1/TC6/

SEG2 SEG1

SEG0 COM3 COM2

COM1 COM0

V3 V2

V1 C1 C0

(

DVO) P30

PDO3/PWM3) P31

(TC3/

PDO4/PWM4/PPG4) P32 PDO6/PWM6/PPG6) P33

484746454443424140393837363534

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

123456789

XIN

VSS

TEST

XOUT

VDD

(XTIN) P21

RESET

(XTOUT) P22

(STOP/INT5) P20

10111213141516

INT0) P60

(

SCK) P64

(INT3) P63

(ECIN/INT1) P61

(ECNT/INT2) P62

(INT4/STOP2/

(BOOT/SI/STOP3/RXD0) P65

Figure 1-1 Pin Assignment

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

(SO/STOP4/TXD0) P66

P54(SEG19) P53(SEG20) P52(SEG21) P51(SEG22) P50(SEG23) P17(SEG24) P16(SEG25) P15(SEG26)

P14(SEG27) P13(SEG28) P12(SEG29)

P11(SEG30)

P10(SEG31)

P24(RTCOUT)

P23(RTCIN)

P67(STOP5)

Page 3

1.3 Block Diagram

TMP86FM26UG

Figure 1-2 Block Diagram

Page 4

1.4 Pin Names and Functions

The TMP86FM26UG has MCU mode and serial PROM mode. Table 1-1 shows the pin functions in MCU mode.

The serial PROM mode is explained later in a separate chapter.

Table 1-1 Pin Names and Functions(1/3)

Pin Name Pin Number Input/Output Functions

TMP86FM26UG

P17 SEG24

P16 SEG25

P15 SEG26

P14 SEG27

P13 SEG28

P12 SEG29

P11 SEG30

P10 SEG31

P24 RTCOUT

P23 RTCIN

P22 XTOUT

IOOPORT17

LCD segment output 24

IOOPORT16

LCD segment output 25

IOOPORT15

LCD segment output 26

IOOPORT14

LCD segment output 27

IOIPORT13

LCD segment output 28

IOOPORT12

LCD segment output 29

IOOPORT11

LCD segment output 30

IOOPORT10

LCD segment output 31

IOOPORT24

RTC output

IOIPORT23

RTC input

PORT22

Resonator connecting pins(32.768kHz) for inputting external

clock

P21 XTIN

P20

INT5

STOP

P33

PDO6/PWM6/PPG6

TC6 RXD1

P32

PDO4/PWM4/PPG4

TC4 TXD1

P31

PDO3/PWM3

TC3

P30

DVO

P57 SEG16

PORT21

Resonator connecting pins(32.768kHz) for inputting external

clock

PORT20

External interrupt 5 input

STOP mode release signal input

PORT33

PDO6/PWM6/PPG6 output

TC6 input

UART data input 1

PORT32

PDO4/PWM4/PPG4 output

TC4 input

UART data output 1

PORT31

PDO3/PWM3 output

TC3 input

IOOPORT30

Divider Output

IOOPORT57

LCD segment output 16

Page 5

1.4 Pin Names and Functions

Table 1-1 Pin Names and Functions(2/3)

Pin Name Pin Number Input/Output Functions

TMP86FM26UG

P56 SEG17

P55 SEG18

P54 SEG19

P53 SEG20

P52 SEG21

P51 SEG22

P50 SEG23

P67 STOP5

P66 TXD0 STOP4 SO

P65 RXD0 STOP3 SI BOOT

IOOPORT56

LCD segment output 17

IOOPORT55

LCD segment output 18

IOOPORT54

LCD segment output 19

IOOPORT53

LCD segment output 20

IOOPORT52

LCD segment output 21

IOOPORT51

LCD segment output 22

IOOPORT50

LCD segment output 23

IOIPORT67

STOP5 input

PORT66

UART data output 0

STOP4 input

Serial Data Output

PORT65

UART data input 0

STOP3 input

Serial Data Input

Serial PROM mode control input

P64

SCK

STOP2 INT4

P63 INT3

P62 INT2 ECNT

P61 INT1 ECIN

P60

INT0

P77 SEG8

P76 SEG9

P75 SEG10

P74 SEG11

PORT64

Serial Clock I/O

STOP2 input

External interrupt 4 input

IOIPORT63

External interrupt 3 input

PORT62

External interrupt 2 input

ECNT input

PORT61

External interrupt 1 input

ECIN input

IOIPORT60

External interrupt 0 input

IOOPORT77

LCD segment output 8

IOOPORT76

LCD segment output 9

IOOPORT75

LCD segment output 10

IOOPORT74

LCD segment output 11

P73 SEG12

IOOPORT73

LCD segment output 12

Page 6

Table 1-1 Pin Names and Functions(3/3)

Pin Name Pin Number Input/Output Functions

TMP86FM26UG

P72 SEG13

P71 SEG14

P70 SEG15

SEG7 44 O LCD segment output 7

SEG6 45 O LCD segment output 6

SEG5 46 O LCD segment output 5

SEG4 47 O LCD segment output 4

SEG3 48 O LCD segment output 3

SEG2 49 O LCD segment output 2

SEG1 50 O LCD segment output 1

SEG0 51 O LCD segment output 0

COM3 52 O LCD common output 3

COM2 53 O LCD common output 2

COM1 54 O LCD common output 1

IOOPORT72

LCD segment output 13

IOOPORT71

LCD segment output 14

IOOPORT70

LCD segment output 15

COM0 55 O LCD common output 0

V3 56 I LCD voltage booster pin

V2 57 I LCD voltage booster pin

V1 58 I LCD voltage booster pin

C1 59 I LCD voltage booster pin

C0 60 I LCD voltage booster pin

XIN 2 I Resonator connecting pins for high-frequency clock

XOUT 3 O Resonator connecting pins for high-frequency clock

RESET 8 IO Reset signal

TEST 4 I Test pin for out-going test. Normally, be fixed to low.

VAREF 18 I Analog Base Voltage Input Pin for A/D Conversion

AVDD 19 I Analog Power Supply

VDD 4 I Power Supply

VSS 1 I 0(GND)

Page 7

1.4 Pin Names and Functions TMP86FM26UG

Page 8

2. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.

This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86FM26UG memory is composed Flash, BOOTROM, RAM, DBR(Data buffer register) and

SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the

TMP86FM26UG memory address map.

0000

SFR

RAM

003F

0040

043F

64 bytes

1024

bytes

Special function register includes:

SFR:

I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes:

RAM:

Data memory

Stac k

TMP86FM26UG

DBR

BOOTROM

Flash

0F80

0FFF

3800

3FFF

8000

81FF

8200

FFB0

FFBF

FFC0

FFDF

FFE0

FFFF

128

bytes

2048

bytes

DBR: Data buffer register includes:

Peripheral control registers Peripheral status registers LCD display memory

BOOTROM:

Flash programming control program

Flash:

Program memory The area of 8000

data memory of FLASH.

to 81FFH can be also used as

32768

bytes

Vector table for interrupts

(16 bytes)

Vector table for vector call instructions (32 bytes)

Vector table for interrupts

(32 bytes)

Figure 2-1 Memory Address Map

2.1.2 Program Memory (Flash)

The TMP86FM26UG has a 32768 bytes (Address 8000H to FFFFH) of program memory (Flash ). The area

of 8000H to 81FFH can be used as a 512 bytes data memory of FLASH.

Page 9

2. Operational Description

2.2 System Clock Controller

2.1.3 Data Memory (RAM)

The TMP86FM26UG has 1024bytes (Address 0040H to 043FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area.

The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine.

Example :Clears RAM to “00H”. (TMP86FM26UG)

SRAMCLR: LD (HL), A

TMP86FM26UG

LD HL, 0040H ; Start address setup

LD A, H ; Initial value (00H) setup

LD BC, 03FFH

INC HL

DEC BC

JRS F, SRAMCLR

2.2 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a standby controller.

Clock

generator

XIN

High-frequency clock oscillator

XOUT

XTIN

Low-frequency clock oscillator

XTOUT

Figure 2-2 System Colck Control

2.2.1 Clock Generator

Timing generator control register

TBTCR

0036

Timing

generator

0038

System clocks

Clock generator control

Standby controller

0039

SYSCR2SYSCR1

System control registers

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock.

The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.

Page 10

TMP86FM26UG

(a) Crystal/Ceramic

resonator

Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis-

abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance.

High-frequency clock

XOUTXIN

(b) External oscillator

Figure 2-3 Examples of Resonator Connection

XOUTXIN

(Open)

Low-frequency clock

XTIN

XTOUT

XTIN

XTOUT

(Open)

Page 11

2. Operational Description

2.2 System Clock Controller

2.2.2 Timing Generator

The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions.

2.2.2.1 Configuration of timing generator

1. Generation of main system clock

2. Generation of divider output (

DVO) pulses

3. Generation of source clocks for time base timer

4. Generation of source clocks for watchdog timer

5. Generation of internal source clocks for timer/counters

6. Generation of warm-up clocks for releasing STOP mode

7. LCD

TMP86FM26UG

SYSCK DV7CK

High-frequency

clock fc

Low-frequency

clock fs

The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,

and machine cycle counters.

An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler and the divider are cleared to “0”.

fc or fs

fc/4

1 21 432 87 109 1211 1413 1615

5 6 17 18 19 20 21

Multi-

plexer

Machine cycle countersMain system clock generator

Divider

B0 B1

A0 A1

Y0 Y1

Multiplexer

Warm-up controller

Watchdog timer

Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)

Figure 2-4 Configuration of Timing Generator

Page 12

Timing Generator Control Register

TMP86FM26UG

TBTCR

(0036H)

Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after

76543210

(DVOEN) (DVOCK) DV7CK (TBTEN) (TBTCK) (Initial value: 0000 0000)

DV7CK

release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.

Selection of input to the 7th stage of the divider

0: fc/2 1: fs

[Hz]

2.2.2.2 Machine cycle

Instruction execution and peripheral hardware operation are synchronized with the main system clock.

The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.

1/fc or 1/fs [s]

R/W

Main system clock

State

Machine cycle

Figure 2-5 Machine Cycle

2.2.3 Operation Mode Control Circuit

The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram.

Note 1: When the IDLE0/1/2 and SLEEP0/1/2 modes are started with the EEPCR<ATPWDW> = "0", the CPU wait

period for stabilizing of the power supply of Flash control circuit is executed after being released from these mode.

Note 2: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for stablizing of

the power supply of flash control circuit is executed after the STOP warm-up time.

2.2.3.1 Single-clock mode

S3S2S1S0 S3S2S1S0

Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s].

Page 13

2. Operational Description

2.2 System Clock Controller TMP86FM26UG

(1) NORMAL1 mode

In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.

The TMP86FM26UG is placed in this mode after reset.

(2) IDLE1 mode

In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are

halted; however on-chip peripherals remain active (Operate using the high-frequency clock).

IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF (Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the IDLE1 mode start instruction.

(3) IDLE0 mode

In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.

This mode is enabled by SYSCR2<TGHALT> = "1".

When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.

When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF = “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT interrupt latch is set after returning to NORMAL1 mode.

2.2.3.2 Dual-clock mode

Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.

The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program.

(1) NORMAL2 mode

In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate

using the high-frequency clock and/or low-frequency clock.

(2) SLOW2 mode

In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1 mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.

Page 14

TMP86FM26UG

(3) SLOW1 mode

This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.

Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped.

(4) IDLE2 mode

In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode.

(5) SLEEP1 mode

In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode. In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped.

(6) SLEEP2 mode

The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock.

(7) SLEEP0 mode

In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by setting “1” on bit SYSCR2<TGHALT>.

When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.

When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF = “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT interrupt latch is set after returning to SLOW1 mode.

2.2.3.3 STOP mode

In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The

internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.

STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a

inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the

STOP pin. After

the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction.

Page 15

2. Operational Description

2.2 System Clock Controller TMP86FM26UG

IDLE1

mode

(a) Single-clock mode

IDLE2

mode

SLEEP2

mode

SLEEP1

mode

(b) Dual-clock mode

SYSCR2<TGHALT> = "1"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<XTEN> = "0"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<SYSCK> = "0"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<XEN> = "1"

SYSCR2<IDLE> = "1"

Interrupt

Note 2

IDLE0

mode

NORMAL1

mode

NORMAL2

mode

SLOW2

mode

SLOW1

mode

Reset release

Note 2

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<XTEN> = "1"

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<SYSCK> = "1"

SYSCR2<XEN> = "0"

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<TGHALT> = "1"

RESET

STOP

SLEEP0

mode

Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1

and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.

Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.

Figure 2-6 Operating Mode Transition Diagram

Table 2-1 Operating Mode and Conditions

Operating Mode

Single clock

Dual clock

Oscillator

High

Frequency

RESET

NORMAL1 Operate

IDLE1

STOP Stop Halt –

NORMAL2

IDLE2 Halt

SLOW2

SLEEP2 Halt

SLOW1

SLEEP1

STOP Stop Halt –

Oscillation

Stop

Low

Frequency

Stop

Oscillation

CPU Core TBT

Reset Reset Reset

Operate

HaltIDLE0

Operate with

high frequency

Operate with

low frequency

Operate

Operate with

low frequency

HaltSLEEP0

Other

Peripherals

Operate

Halt

Operate

Halt

Machine Cycle

Time

4/fc [s]

4/fs [s]

Page 16

System Control Register 1

SYSCR176543210

(0038H) STOP RELM RETM OUTEN WUT (Initial value: 0000 00**)

TMP86FM26UG

STOP STOP mode start

RELM

RETM

OUTEN Port output during STOP mode

WUT

Release method for STOP mode

Operating mode after STOP mode

Warm-up time at releasing STOP mode

0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode)

0: Edge-sensitive release 1: Level-sensitive release

0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode

0: High impedance 1: Output kept

Return to NORMAL mode Return to SLOW mode

3 x 2

/fc + (210/fc)

3 x 2

/fs + (23/fs)

R/W

Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting

from SLOW mode to STOP mode.

Note 2: When STOP mode is released with

RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.

Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external

interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as

STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes

High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. Note 9: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for stabilizing of the power sup-

ply of flash control circuit is executed after the STOP warm-up time.(The CPU wait period for FLASH is shown in parenthe-

ses)

System Control Register 2

SYSCR2

(0039H)

Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared

Note 2: *: Don’t care, TG: Timing generator, *; Don’t care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to “1” simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period

Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.

76543210

XEN XTEN SYSCK IDLE

XEN High-frequency oscillator control

XTEN Low-frequency oscillator control

Main system clock select

SYSCK

IDLE

TGHALT

(Write)/main system clock monitor (Read)

CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes)

TG control (IDLE0 and SLEEP0 modes)

TGHALT

0: Turn off oscillation 1: Turn on oscillation

0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)

0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)

0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes)

(Initial value: 1000 *0**)

to “0” when SYSCK = “1”.

of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.

R/W

Page 17

2. Operational Description

2.2 System Clock Controller

Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”. Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals

may be set after IDLE0 or SLEEP0 mode is released.

2.2.4 Operating Mode Control

2.2.4.1 STOP mode

TMP86FM26UG

STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). The

STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is

started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.

1. Oscillations are turned off, and all internal operations are halted.

2. The data memory, registers, the program status word and port output latches are all held in the status in effect before STOP mode was entered.

3. The prescaler and the divider of the timing generator are cleared to “0”.

4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which started STOP mode.

STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releasing STOP mode in edge-sensitive mode.

When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait for stabilizing of the power supply of flash control circuit is executed after the STOP warm-up time.

Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2).

However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode.

Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external

interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.

(1) Level-sensitive release mode (RELM = “1”)

In this mode, STOP mode is released by setting the

STOP pin high or setting the STOP5 to STOP2

pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup.

Even if an instruction for starting STOP mode is executed while

STOP pin input is high or STOP5

to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immedi-

ately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the methods can be used for confirmation.

STOP pin input is low or STOP5 to STOP2 input is high. The following two

1. Testing a port.

2. Using an external interrupt input

Page 18

INT5 (INT5 is a falling edge-sensitive input).

Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.

LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode

TMP86FM26UG

SSTOPH: TEST (P2PRD). 0 ; Wait until the

JRS F, SSTOPH

DI ; IMF ← 0

SET (SYSCR1). 7 ; Starts STOP mode

STOP pin input goes low level

Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.

PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if

JRS F, SINT5 port P20 is at high

LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode.

DI ; IMF ← 0

SET (SYSCR1). 7 ; Starts STOP mode

SINT5: RETI

Only when EEPCR<MNPWDW> is “1”. (The CPU wait period is added.)

STOP pin

XOUT pin

STOP operation

Confirm by program that the STOP pin input is low and start STOP mode.

Figure 2-7 Level-sensitive Release Mode

Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release

mode is not switched until a rising edge of the

Note 3: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for

stablizing of the power supply of flash control circuit is executed after the STOP warm-up time.

(2) Edge-sensitive release mode (RELM = “0”)

In this mode, STOP mode is released by a rising edge of the cations where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the the edge-sensitive release mode, STOP mode is started even when the Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode.

Example :Starting STOP mode from NORMAL mode

Warm up

STOP mode is released by the hardware.

Always released if the STOP pin input is high.

STOP pin input is detected.

CPU

Wait

NORMAL operationNORMAL operation

STOP pin input. This is used in appli-

STOP pin input is high level.

STOP pin. In

DI ; IMF ← 0

LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode

Page 19

2. Operational Description

2.2 System Clock Controller

STOP pin

XOUT pin

Only when EEPCR<MNPWDW> is “1”. (The CPU wait period is added.)

TMP86FM26UG

NORMAL operation

STOP mode started by the program.

Note 1: When the STOP mode is started with the EEPCR<MNPWDW> = "1", the CPU wait period for

STOP mode is released by the following sequence.

STOP operation

Warm up

CPU Wait

STOP mode is released by the hardware at the rising edge of STOP pin input.

NORMAL operation

STOP operation

Figure 2-8 Edge-sensitive Release Mode

stablizing of the power supply of flash control circuit is executed after the STOP warm-up time.

1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on.

2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1<WUT> in accordance with the resonator characteristics.

3. When the EEPCR<MNPWDW> is "1", the CPU wait period is inserted to stabilize the power supply of flash control circuit. During CPU wait, though CPU operations remain halted, the peripheral function operation is resumed, and the counting of the timing generator is restarted. After the CPU wait is finished, normal operation resumes with the instruction following the STOP mode start instruction.

4. When the EEPCR<MNPWDW> is "0", normal operation resumes with the instruction following the STOP mode start instruction after the STOP warm up.

Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the

timing generator are cleared to "0".

Note 2: STOP mode can also be released by inputting low level on the

performs the normal reset operation.

Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed.

The power supply voltage must be at the operating voltage level before releasing STOP mode. The

RESET pin input must also be “H” level, rising together with the power supply voltage. In this

case, if an external time constant circuit has been connected, the increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the input voltage (Hysteresis input).

RESET pin drops below the non-inverting high-level

RESET pin, which immediately

RESET pin input voltage will

Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)

WUT

00 01 10 11

Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up

time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value.

Note 2: The CPU wait period for FLASH is shown in parentheses.

Return to NORMAL Mode Return to SLOW Mode

12.288 + (0.064)

4.096 + (0.064)

3.072 + (0.064)

1.024 + (0.064)

Warm-up Time [ms]

750 + (0.244) 250 + (0.244)

5.85 + (0.244)

1.95 + (0.244)

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