TOSHIBA TMP86CH22UG Technical data

8 Bit Microcontroller

TLCS-870/C Series

TMP86CH22UG

The information contained herein is subject to change without notice. 021023 _ D

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications.

Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A

The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of

human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B

The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C

The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F

For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

Page 2

Revision History

Date Revision

2005/12/8 1 First Release

2006/9/8 2 Contents Revised

2008/8/29

3 Contents Revised

Caution in Setting the UART Noise Rejection Time

When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com-

bination "O" is available but please do not select the combination "–".

The transfer clock generated by timer/counter interrupt is calculated by the following equation : Transfer clock [Hz] = Timer/counter source clock [Hz] ÷ TTREG set value

RXDNC setting

BRG setting

000 fc/13 O O O – 110

(When the transfer clock gen-

erated by timer/counter inter-

rupt is the same as the right

side column) The setting except the aboveOOOO

Transfer

clock [Hz]

fc/8 O – – –

fc/16 O O – –

fc/32OOO–

(No noise rejection)

(Reject pulses shorter than 31/fc[s] as noise)

(Reject pulses shorter than 63/fc[s] as noise)

(Reject pulses shorter

than 127/fc[s] as

noise)

Table of Contents

TMP86CH22UG

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Operational Description

2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Memory Address Map............................................................................................................................... 9

2.1.2 Program Memory (MaskROM).................................................................................................................. 9

2.1.3 Data Memory (RAM)............................................................................................................................... 10

2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Clock Generator...................................................................................................................................... 10

2.2.2 Timing Generator.................................................................................................................................... 12

2.2.2.1 Configuration of timing generator

2.2.2.2 Machine cycle

2.2.3 Operation Mode Control Circuit .............................................................................................................. 13

2.2.3.1 Single-clock mode

2.2.3.2 Dual-clock mode

2.2.3.3 STOP mode

2.2.4 Operating Mode Control ......................................................................................................................... 18

2.2.4.1 STOP mode

2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode

2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)

2.2.4.4 SLOW mode

2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.3.1 External Reset Input ............................................................................................................................... 31

2.3.2 Address trap reset .................................................................................................................................. 32

2.3.3 Watchdog timer reset.............................................................................................................................. 32

2.3.4 System clock reset.................................................................................................................................. 32

3. Interrupt Control Circuit

3.1 Interrupt latches (IL19 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.1 Interrupt master enable flag (IMF) .......................................................................................................... 36

3.2.2 Individual interrupt enable flags (EF19 to EF4) ...................................................................................... 37

Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3.1 Interrupt acceptance processing is packaged as follows........................................................................ 39

3.3.2 Saving/restoring general-purpose registers ............................................................................................ 40

3.3.2.1 Using PUSH and POP instructions

3.3.2.2 Using data transfer instructions

3.3.3 Interrupt return ........................................................................................................................................ 41

3.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.4.1 Address error detection .......................................................................................................................... 42

3.4.2 Debugging .............................................................................................................................................. 42

3.5 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.6 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.7 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4. Special Function Register (SFR)

4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5. I/O Ports

5.1 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2 Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3 Port P3 (P37, P34 to P33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.4 Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.5 Port P6 (P64 to P61) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.6 Port P7 (P76 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6. Watchdog Timer (WDT)

6.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.2 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.2.1 Malfunction Detection Methods Using the Watchdog Timer ................................................................... 64

6.2.2 Watchdog Timer Enable ......................................................................................................................... 65

6.2.3 Watchdog Timer Disable ........................................................................................................................ 66

6.2.4 Watchdog Timer Interrupt (INTWDT)...................................................................................................... 66

6.2.5 Watchdog Timer Reset ........................................................................................................................... 67

6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.3.1 Selection of Address Trap in Internal RAM (ATAS) ................................................................................ 68

6.3.2 Selection of Operation at Address Trap (ATOUT) .................................................................................. 68

6.3.3 Address Trap Interrupt (INTATRAP)....................................................................................................... 68

6.3.4 Address Trap Reset................................................................................................................................ 69

7. Time Base Timer (TBT)

7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.1.1 Configuration .......................................................................................................................................... 71

7.1.2 Control .................................................................................................................................................... 71

7.1.3 Function .................................................................................................................................................. 72

7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.2.1 Configuration .......................................................................................................................................... 73

7.2.2 Control .................................................................................................................................................... 73

8. 18-Bit Timer/Counter (TC1)

8.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.3.1 Timer mode............................................................................................................................................. 79

8.3.2 Event Counter mode............................................................................................................................... 80

8.3.3 Pulse Width Measurement mode............................................................................................................ 81

8.3.4 Frequency Measurement mode .............................................................................................................. 82

9. 8-Bit TimerCounter (TC5, TC6)

9.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.2 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.3.1 8-Bit Timer Mode (TC5 and 6) ................................................................................................................ 91

9.3.2 8-Bit Event Counter Mode (TC5, 6) ........................................................................................................ 92

9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)..................................................................... 92

9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6).................................................................. 95

9.3.5 16-Bit Timer Mode (TC5 and 6) .............................................................................................................. 97

9.3.6 16-Bit Event Counter Mode (TC5 and 6) ................................................................................................ 98

9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6).......................................................... 98

9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ............................................. 101

9.3.9 Warm-Up Counter Mode....................................................................................................................... 103

9.3.9.1 Low-Frequency Warm-up Counter Mode

9.3.9.2 High-Frequency Warm-Up Counter Mode

(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)

(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)

10. Real-Time Clock

10.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10.2 Control of the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11. Asynchronous Serial interface (UART )

11.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.3 Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

11.4 Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.5 Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.6 STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.7 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.8 Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.8.1 Data Transmit Operation .................................................................................................................... 112

11.8.2 Data Receive Operation ..................................................................................................................... 112

11.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

11.9.1 Parity Error.......................................................................................................................................... 113

11.9.2 Framing Error...................................................................................................................................... 113

11.9.3 Overrun Error ...................................................................................................................................... 113

11.9.4 Receive Data Buffer Full..................................................................................................................... 114

11.9.5 Transmit Data Buffer Empty ............................................................................................................... 114

11.9.6 Transmit End Flag .............................................................................................................................. 115

12. Synchronous Serial Interface (SIO)

12.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

iii

12.3 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.3.1 Clock source ....................................................................................................................................... 119

12.3.1.1 Internal clock

12.3.1.2 External clock

12.3.2 Shift edge............................................................................................................................................ 121

12.3.2.1 Leading edge

12.3.2.2 Trailing edge

12.4 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.5 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.6 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 122

12.6.2 4-bit and 8-bit receive modes ............................................................................................................. 124

12.6.3 8-bit transfer / receive mode ............................................................................................................... 125

13. 8-Bit AD Converter (ADC)

13.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

13.3.1 AD Conveter Operation ...................................................................................................................... 130

13.3.2 AD Converter Operation ..................................................................................................................... 130

13.3.3 STOP and SLOW Mode during AD Conversion ................................................................................. 131

13.3.4 Analog Input Voltage and AD Conversion Result ............................................................................... 132

13.4 Precautions about AD Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

13.4.1 Restrictions for AD Conversion interrupt (INTADC) usage ................................................................. 133

13.4.2 Analog input pin voltage range ........................................................................................................... 133

13.4.3 Analog input shared pins .................................................................................................................... 133

13.4.4 Noise countermeasure........................................................................................................................ 133

14. Key-on Wakeup (KWU)

14.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

14.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

14.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15. LCD Driver

15.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

15.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.2.1 LCD driving methods .......................................................................................................................... 139

15.2.2 Frame frequency................................................................................................................................. 140

15.2.3 LCD drive voltage ............................................................................................................................... 141

15.2.4 Adjusting the LCD panel drive capability ............................................................................................ 141

15.3 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

15.3.1 Display data setting ............................................................................................................................ 142

15.3.2 Blanking .............................................................................................................................................. 142

15.4 Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

15.4.1 Initial setting........................................................................................................................................ 143

15.4.2 Store of display data ........................................................................................................................... 143

15.4.3 Example of LCD driver output............................................................................................................. 145

16. Input/Output Circuit

16.1 Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

16.2 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

17. Electrical Characteristics

17.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

17.2 Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

17.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

17.4 LCD Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

17.5 AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

17.6 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

17.7 Timer Counter 1 input (ECIN) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 161

17.8 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

17.9 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

18. Package Dimension

This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI).

CMOS 8-Bit Microcontroller

TMP86CH22UG

Product No.

TMP86CH22UG

1.1 Features

1. 8-bit single chip microcomputer TLCS-870/C series

- Instruction execution time :

- 132 types & 731 basic instructions

2. 18interrupt sources (External : 5 Internal : 13)

3. Input / Output ports (I/O : 32 pins Output : 1 pin)

Large current output: 3pins (Typ. 20mA), LED direct drive

4. Watchdog Timer

5. Prescaler

- Time base timer

- Divider output function

6. 18-bit Timer/Counter : 1ch

- Timer Mode

- Event Counter Mode

- Pulse Width Measurement Mode

- Frequency Measurement Mode

7. 8-bit timer counter : 2 ch

- Timer, Event counter, Programmable divider output (PDO),

ROM

(MaskROM)

16384

bytes

RAM Package OTP MCU Emulation Chip

512

bytes

0.25 µs (at 16 MHz)

122 µs (at 32.768 kHz)

P-LQFP44-1010-0.80B TMP86PH22UG TMP86C923XB

Pulse width modulation (PWM) output,

060116EBP

• The information contained herein is subject to change without notice. 021023_D

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B

• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C

• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E

• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

Page 1

1.1 Features TMP86CH22UG

Programmable pulse generation (PPG) modes

8. 8-bit UART : 1 ch

9. 8-bit SIO: 1 ch

10. 8-bit successive approximation type AD converter (with sample hold)

Analog inputs: 4ch

11. Key-on wakeup : 1 ch

12. LCD driver/controller

- LCD direct drive capability (MAX 23 seg × 4 com)

- 1/4,1/3,1/2duties or static drive are programmably selectable

13. Clock operation

Single clock mode

Dual clock mode

14. Low power consumption operation

STOP mode: Oscillation stops. (Battery/Capacitor back-up.)

SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock

stop.)

SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock

oscillate.)

IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre-

quency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.

IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru-

puts(CPU restarts).

IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter-

ruputs. (CPU restarts).

SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre-

quency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.

SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru-

put.(CPU restarts).

SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by

interruput.

15. Wide operation voltage:

4.5 V to 5.5 V at 16MHz /32.768 kHz

2.7 V to 5.5 V at 8 MHz /32.768 kHz

1.8 V to 5.5 V at 4.2MHz /32.768 kHz

Page 2

1.2 Pin Assignment

TMP86CH22UG

P52 (SEG21)

P51 (SEG22)

P53 (SEG20)

P55 (SEG18)

P56 (SEG17)

P70 (SEG15)

P73 (SEG12)

P57 (SEG16)

P72 (SEG13)

P71 (SEG14)

P54 (SEG19)

(SEG11) P74 (SEG10) P75

(SEG9) P76

COM3 COM2 COM1 COM0

VLC

(

PDO6/PWM6/PPG6/TC6) P33

PDO5/PWM5/TC5) P34

(

DVO) P37

(

3332313029282726252423

34 35 36 37 38 39 40 41 42 43 44

123456789

XIN

VSS

XOUT

VDD

TEST

(XTIN) P21

(XTOUT) P22

RESET

(INT5/STOP) P20

(ECIN/AIN1) P61

(ECNT/AIN2) P62

22 21 20 19 18 17 16 15 14 13 12

Figure 1-1 Pin Assignment

P50(SEG23) P17(SEG24/

SCK)

P16(SEG25/SO) P15(SEG26/SI) P14(SEG27/INT3) P13(SEG28/INT2) P12(SEG29/INT1) P11(SEG30/TXD) P10(SEG31/RXD) P64(AIN4/STOP2) P63(AIN3/INT0)

Page 3

1.3 Block Diagram

TMP86CH22UG

Figure 1-2 Block Diagram

Page 4

1.4 Pin Names and Functions

Table 1-1 Pin Names and Functions(1/3)

Pin Name Pin Number Input/Output Functions

P17 SEG24

SCK

PORT17

LCD segment output 24

Serial Clock I/O

TMP86CH22UG

P16 SEG25 SO

P15 SEG26 SI

P14 SEG27 INT3

P13 SEG28 INT2

P12 SEG29 INT1

P11 SEG30 TXD

P10 SEG31 RXD

P22 XTOUT

PORT16

LCD segment output 25

Serial Data Output

PORT15

LCD segment output 26

Serial Data Input

PORT14

LCD segment output 27

External interrupt 3 input

PORT13

LCD segment output 28

External interrupt 2 input

PORT12

LCD segment output 29

External interrupt 1 input

PORT11

LCD segment output 30

UART data output

PORT10

LCD segment output 31

UART data input

PORT22

Resonator connecting pins(32.768kHz) for inputting external

clock

P21 XTIN

P20

STOP

INT5

P37

DVO

P34 TC5

PDO5/PWM5

P33 TC6

PDO6/PWM6/PPG6

P57 SEG16

P56 SEG17

P55 SEG18

PORT21

Resonator connecting pins(32.768kHz) for inputting external

clock

PORT20

STOP mode release signal input

External interrupt 5 input

OOPORT37

Divider Output

PORT34

TC5 input

PDO5/PWM5 output

PORT33

TC6 input

PDO6/PWM6/PPG6 output

IOOPORT57

LCD segment output 16

IOOPORT56

LCD segment output 17

IOOPORT55

LCD segment output 18

Page 5

1.4 Pin Names and Functions

Table 1-1 Pin Names and Functions(2/3)

Pin Name Pin Number Input/Output Functions

TMP86CH22UG

P54 SEG19

P53 SEG20

P52 SEG21

P51 SEG22

P50 SEG23

P64 AIN4 STOP2

P63 AIN3

INT0

P62 AIN2 ECNT

P61 AIN1 ECIN

IOOPORT54

LCD segment output 19

IOOPORT53

LCD segment output 20

IOOPORT52

LCD segment output 21

IOOPORT51

LCD segment output 22

IOOPORT50

LCD segment output 23

PORT64

AD converter analog input 4

STOP2 input

PORT63

AD converter analog input 3

External interrupt 0 input

PORT62

AD converter analog input 2

ECNT input

PORT61

AD converter analog input 1

ECIN input

P76 SEG9

P75 SEG10

P74 SEG11

P73 SEG12

P72 SEG13

P71 SEG14

P70 SEG15

COM3 37 O LCD common output 3

COM2 38 O LCD common output 2

COM1 39 O LCD common output 1

COM0 40 O LCD common output 0

XIN 2 I Resonator connecting pins for high-frequency clock

IOOPORT76

LCD segment output 9

IOOPORT75

LCD segment output 10

IOOPORT74

LCD segment output 11

IOOPORT73

LCD segment output 12

IOIPORT72

LCD segment output 13

IOOPORT71

LCD segment output 14

IOOPORT70

LCD segment output 15

Page 6

TMP86CH22UG

Table 1-1 Pin Names and Functions(3/3)

Pin Name Pin Number Input/Output Functions

XOUT 3 O Resonator connecting pins for high-frequency clock

RESET 8 I Reset signal

TEST 4 I Test pin for out-going test. Normally, be fixed to low.

VDD 5 I +5V

VSS 1 I 0(GND)

Page 7

1.4 Pin Names and Functions TMP86CH22UG

Page 8

2. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.

This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86CH22UG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special

function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CH22UG memory address map.

0000

SFR

RAM

003F

0040

023F

64 bytes

512

bytes

Special function register includes:

SFR:

I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes:

RAM:

Data memory

Stac k

TMP86CH22UG

0F80

DBR

MaskROM

0FFF

C000

FFB0

FFBF

FFC0

FFDF

FFE0

FFFF

128

bytes

16384

bytes

Figure 2-1 Memory Address Map

2.1.2 Program Memory (MaskROM)

DBR: Data buffer register includes:

Peripheral control registers Peripheral status registers LCD display memory

MaskROM:

Vector table for interrupts

(16 bytes)

Vector table for vector call instructions (32 bytes)

Vector table for interrupts

(32 bytes)

Program memory

The TMP86CH22UG has a 16384 bytes (Address C000H to FFFFH) of program memory (MaskROM ).

Page 9

2. Operational Description

2.2 System Clock Controller

2.1.3 Data Memory (RAM)

The TMP86CH22UG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area.

The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine.

Example :Clears RAM to “00H”. (TMP86CH22UG)

SRAMCLR: LD (HL), A

TMP86CH22UG

LD HL, 0040H ; Start address setup

LD A, H ; Initial value (00H) setup

LD BC, 01FFH

INC HL

DEC BC

JRS F, SRAMCLR

2.2 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a standby controller.

Clock

generator

XIN

High-frequency clock oscillator

XOUT

XTIN

Low-frequency clock oscillator

XTOUT

Figure 2-2 System Colck Control

2.2.1 Clock Generator

Timing generator control register

TBTCR

0036

Timing

generator

System clocks

Clock generator control

Standby controller

0038

0039

SYSCR2SYSCR1

System control registers

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock.

The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.

Page 10

TMP86CH22UG

(a) Crystal/Ceramic

resonator

Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis-

abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance.

High-frequency clock

XOUTXIN

(b) External oscillator

Figure 2-3 Examples of Resonator Connection

XOUTXIN

(Open)

Low-frequency clock

XTIN

XTOUT

XTIN

XTOUT

(Open)

Page 11

2. Operational Description

2.2 System Clock Controller

2.2.2 Timing Generator

The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions.

2.2.2.1 Configuration of timing generator

1. Generation of main system clock

2. Generation of divider output (

DVO) pulses

3. Generation of source clocks for time base timer

4. Generation of source clocks for watchdog timer

5. Generation of internal source clocks for timer/counters

6. Generation of warm-up clocks for releasing STOP mode

7. LCD

TMP86CH22UG

SYSCK DV7CK

High-frequency

clock fc

Low-frequency

clock fs

The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,

and machine cycle counters.

An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler and the divider are cleared to “0”.

fc or fs

fc/4

1 21 432 87 109 1211 1413 1615

5 6 17 18 19 20 21

Multi-

plexer

Machine cycle countersMain system clock generator

Divider

B0 B1

A0 A1

Y0 Y1

Multiplexer

Warm-up controller

Watchdog timer

Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)

Figure 2-4 Configuration of Timing Generator

Page 12

Timing Generator Control Register

TMP86CH22UG

TBTCR

(0036H)

Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after

76543210

(DVOEN) (DVOCK) DV7CK (TBTEN) (TBTCK) (Initial value: 0000 0000)

DV7CK

release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.

Selection of input to the 7th stage of the divider

0: fc/2 1: fs

[Hz]

2.2.2.2 Machine cycle

Instruction execution and peripheral hardware operation are synchronized with the main system clock.

The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.

1/fc or 1/fs [s]

R/W

Main system clock

State

Machine cycle

Figure 2-5 Machine Cycle

2.2.3 Operation Mode Control Circuit

The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram.

2.2.3.1 Single-clock mode

Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s].

S3S2S1S0 S3S2S1S0

(1) NORMAL1 mode

In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.

The TMP86CH22UG is placed in this mode after reset.

Page 13

2. Operational Description

2.2 System Clock Controller TMP86CH22UG

(2) IDLE1 mode

In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are

halted; however on-chip peripherals remain active (Operate using the high-frequency clock).

IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF (Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the IDLE1 mode start instruction.

(3) IDLE0 mode

In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.

This mode is enabled by SYSCR2<TGHALT> = "1".

When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.

When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF = “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT interrupt latch is set after returning to NORMAL1 mode.

2.2.3.2 Dual-clock mode

Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.

The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program.

(1) NORMAL2 mode

In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate

using the high-frequency clock and/or low-frequency clock.

(2) SLOW2 mode

In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1 mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.

(3) SLOW1 mode

This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.

Page 14

TMP86CH22UG

Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped.

(4) IDLE2 mode

In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode.

(5) SLEEP1 mode

In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode. In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped.

(6) SLEEP2 mode

The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock.

(7) SLEEP0 mode

In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by setting “1” on bit SYSCR2<TGHALT>.

When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.

When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF = “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT interrupt latch is set after returning to SLOW1 mode.

2.2.3.3 STOP mode

In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The

internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.

STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a

inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the

STOP pin. After

the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction.

Page 15

2. Operational Description

2.2 System Clock Controller TMP86CH22UG

IDLE1

mode

(a) Single-clock mode

IDLE2

mode

SLEEP2

mode

SLEEP1

mode

(b) Dual-clock mode

SYSCR2<TGHALT> = "1"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<XTEN> = "0"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<SYSCK> = "0"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<XEN> = "1"

SYSCR2<IDLE> = "1"

Interrupt

Note 2

IDLE0

mode

NORMAL1

mode

NORMAL2

mode

SLOW2

mode

SLOW1

mode

Reset release

Note 2

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<XTEN> = "1"

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<SYSCK> = "1"

SYSCR2<XEN> = "0"

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<TGHALT> = "1"

RESET

STOP

SLEEP0

mode

Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1

and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.

Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.

Figure 2-6 Operating Mode Transition Diagram

Table 2-1 Operating Mode and Conditions

Operating Mode

Single clock

Dual clock

Oscillator

High

Frequency

RESET

NORMAL1 Operate

IDLE1

STOP Stop Halt –

NORMAL2

IDLE2 Halt

SLOW2

SLEEP2 Halt

SLOW1

SLEEP1

STOP Stop Halt –

Oscillation

Stop

Low

Frequency

Stop

Oscillation

CPU Core TBT

Reset Reset Reset

Operate

HaltIDLE0

Operate with

high frequency

Operate with

low frequency

Operate

Operate with

low frequency

HaltSLEEP0

Other

Peripherals

Operate

Halt

Operate

Halt

Machine Cycle

Time

4/fc [s]

4/fs [s]

Page 16

System Control Register 1

SYSCR176543210

(0038H) STOP RELM RETM OUTEN WUT (Initial value: 0000 00**)

TMP86CH22UG

STOP STOP mode start

RELM

RETM

OUTEN Port output during STOP mode

WUT

Release method for STOP mode

Operating mode after STOP mode

Warm-up time at releasing STOP mode

0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode)

0: Edge-sensitive release 1: Level-sensitive release

0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode

0: High impedance 1: Output kept

Return to NORMAL mode Return to SLOW mode

3 x 2

/fc

3 x 2

R/W

/fs

R/W

Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting

from SLOW mode to STOP mode.

Note 2: When STOP mode is released with

RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.

Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external

interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as

STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes

High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator.

System Control Register 2

SYSCR2

(0039H)

Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared

Note 2: *: Don’t care, TG: Timing generator, *; Don’t care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to “1” simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period

Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”. Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”. Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals

76543210

XEN XTEN SYSCK IDLE

XEN High-frequency oscillator control

XTEN Low-frequency oscillator control

Main system clock select

SYSCK

IDLE

TGHALT

(Write)/main system clock monitor (Read)

CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes)

TG control (IDLE0 and SLEEP0 modes)

TGHALT

0: Turn off oscillation 1: Turn on oscillation

0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)

0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)

0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes)

(Initial value: 1000 *0**)

to “0” when SYSCK = “1”.

of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.

may be set after IDLE0 or SLEEP0 mode is released.

R/W

Page 17

2. Operational Description

2.2 System Clock Controller

2.2.4 Operating Mode Control

2.2.4.1 STOP mode

TMP86CH22UG

STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP2) which is controlled by the STOP mode release control register (STOPCR). The

STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is

started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.

1. Oscillations are turned off, and all internal operations are halted.

2. The data memory, registers, the program status word and port output latches are all held in the status in effect before STOP mode was entered.

3. The prescaler and the divider of the timing generator are cleared to “0”.

4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which started STOP mode.

STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP2) for releasing STOP mode in edge-sensitive mode.

Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP2). However,

because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode.

Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external

interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.

(1) Level-sensitive release mode (RELM = “1”)

In this mode, STOP mode is released by setting the

STOP pin high or setting the STOP2 pin input

which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup.

Even if an instruction for starting STOP mode is executed while input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the

STOP pin input is low or STOP2 input is high. The following two methods can be used

for confirmation.

1. Testing a port.

2. Using an external interrupt input

INT5 (INT5 is a falling edge-sensitive input).

Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.

STOP pin input is high or STOP2

LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode

SSTOPH: TEST (P2PRD). 0 ; Wait until the

JRS F, SSTOPH

DI ; IMF ← 0

SET (SYSCR1). 7 ; Starts STOP mode

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STOP pin input goes low level

Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.

PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if

JRS F, SINT5 port P20 is at high

LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode.

DI ; IMF ← 0

SET (SYSCR1). 7 ; Starts STOP mode

SINT5: RETI

STOP pin

XOUT pin

TMP86CH22UG

NORMAL

operation

Confirm by program that the STOP pin input is low and start STOP mode.

STOP

operation

Figure 2-7 Level-sensitive Release Mode

Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.

Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release

mode is not switched until a rising edge of the

(2) Edge-sensitive release mode (RELM = “0”)

In this mode, STOP mode is released by a rising edge of the cations where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the the edge-sensitive release mode, STOP mode is started even when the Do not use any STOP2 pin input for releasing STOP mode in edge-sensitive release mode.

Example :Starting STOP mode from NORMAL mode

Warm up

STOP mode is released by the hardware.

Always released if the STOP pin input is high.

STOP pin input is detected.

NORMAL operation

STOP pin input. This is used in appli-

STOP pin input is high level.

STOP pin. In

STOP pin

XOUT pin

STOP mode started by the program.

DI ; IMF ← 0

LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode

NORMAL operation

STOP

operation

Warm up

STOP mode is released by the hardware at the rising edge of STOP pin input.

NORMAL

operation

Figure 2-8 Edge-sensitive Release Mode

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STOP

operation

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