TOSHIBA TC94A23F Technical data

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Toshiba CMOS Digital Integrated Circuit Silicon Monolithic

TC94A23F

Single-chip CD Processor with Built-in Controller

TC94A23F is a single-chip CD processor for digital servo. It

incorporates a 4-bit microcontroller.

The controller features an LCD/LED driver, 4-channel 6-bit AD converter, 2/3-line serial interface, buzzer, interrupt function, and 8-bit timer/counter. The CPU can select one of three crystal oscillator operating clocks (16.9344 MHz, 4.5 MHz, and 75 kHz), facilitating interface with the CD processor.

The CD processor incorporates sync separation protection and interpolation, EFM decoder, error correction, digital equalizer for servo, and servo controller. The CD processor also incorporates a 1-bit DA converter. In combination with RF amp TA2153FN or TA2109F, TC94A23F can very simply configure an adjustment-free CD player.

Thus, the IC is suitable for CD systems for automobiles and radio-cassette players.

Features

Weight: 1.6 g (typ.)

TC94A23F

· Single-chip CD processor with built-in CMOS LCE/LED driver and 4-bit microcontroller

· Operating voltage: At CD on: V

At CD off: V

· Current dissipation: At CD on: I

At CD off: I At CD off: I

· Operating temperature range: Ta = -40~85°C

· Package: QFP100-P-1420-0.65A (0.65-mm pitch, 2.7-mm thick)

· One-time PROM version: TC94AP09F

= 4.5 to 5.5 V (typ. 5.0 V)

= 3.0 to 5.5 V (only CPU on)

= 50 mA (typ.)

= 2 mA (with 4.5 MHz crystal oscillator, only CPU on)

= 0.3 mA (with 75 kHz crystal oscillator, only CPU on)

2002-02-06

4-bit Microcontroller

· Program memory (ROM): 16-bit ´ 8k-step

· Data memory (RAM): 4-bit ´ 512-word

· Instruction execution time: 1.89/1.78/40 ms (all one-word instructions)

· Crystal oscillator frequency: 16.9344 MHz/4.5 MHz/75 kHz

· Stack level: 8

· AD converter: 6-bit ´ 4-channel

· LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 72 segments max

· LED driver: 4-digit ´ 14-segment (max), also used as LCD driver switched by software

· I/O port: CMOS I/O port: 16

N-channel open drain I/O port: 4 (max) Output-only port: 4 (max), also used as CD processor pins Input-only port: 4

· Timer/counter: 8 bit (INTR, instruction cycle, 100/1 kHz selectable as timer clock) 10, 100, or 500 Hz: internal port 2 Hz: Flip-flop port

· Serial interface: Supports 2/3-line method (data length: 4 or 8 bits)

· Buzzer: Four types: 0.75, 1, 1.5, and 3 kHz

Four modes: Continuous, Single-Shot, 10 Hz Intermittent, and 10 Hz Intermittent at 1 Hz Interval)

· Interrupt: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer)

· Back-up mode: three types

Clock Stop (crystal oscillator off) Hardware Wait (crystal oscillator on but CPU in operation) Software Wait (CPU in intermittent operation)

· Reset function: Power-on reset, built-in supply voltage detector (detection voltage = 2.5 V typ.)

CD Processor

· Reliable sync pattern detection, sync signal protection and interpolation

· Built-in EFM decoder and sub code decoder

· High-correction capability using cross interleave read Solomon code (CIRC) logical equation

C1 correction: dual C2 correction: quadruple

· Supports variable speeds.

· Jitter absorption capability of ±6 frames

· Built-in 16 KB RAM

· Built-in digital output circuit

· Built-in L/R independent digital attenuators

· Bilingual audio output (Note)

· Sub code Q data are read-timing free and can be output in sync with audio data. (Note)

· Built-in data slice and analog PLL (adjustment-free VCO used) circuit

· Auto adjustment of loop gain, offset, and balance at focus servo and tracking servo

· RF gain auto adjustment circuit

· Built-in digital equalizer for phase compensation

· Supports different pickups using built-in digital equalizer coefficient RAM.

· Built-in focus and tracking servo control circuit

· Search control supports all modes and realizes high-speed, stable search.

· Lens kick and feed kick use speed control method.

· Built-in AFC circuit and APC circuit for disc motor CLV servo.

· Built-in defect/shock detector

· Built-in 8 times oversampling digital filter and 1-bit DA converter.

TC94A23F

Note: Output pins for sub code Q data and audio data are also used as LCD driver pins. The function of the pins

can be switched by program.

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()(

)

(

)

()X

(

)

()()()(

)

(

)

COM1 (OT1)

COM2 (OT2) COM3 (OT3) COM4 (OT4)

INTR MXO

MXI

M M M M M M M M M

100

Interrupt input

OSC

Power supply to controller

LCD driver/LED driver output port

(LCD: 4 ´ 18 = 72 segments max, LED: 18 segments)

1 5 10 15 20 25 30

M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M

S1 (OT5)

S2 (OT6)

S3 (OT7)

S4 (OT8)

S5 (OT9)

S6 (OT10)

S7 (OT11)

S8 (OT12)

S9 (OT13)

S10 (OT14/ZDET)

S11 (OT15/CLCK)

CD function pins switched togethe

S13 (OT17/SFSY)

S12 (OT16/DATA)

P8-0 (S15/BCK)

S14 (OT18/LRCK)

Power supply to

P8-1 (S16/AOUT)

P8-2 (OT17/MBOV)

controller

P8-3 (OT18/IPF)

I/O ports (16)

P3-0

P1-3

P1-2

P1-1

P1-0

P3-1 (ADin1)

Note: Symbols used for the pins above indicate the following pin functions.

: CD processor-dedicated pin

: Power supply pin

: CD processor tri-state output pin

: CD processor analog input/output pin

: Reference input pin

: Controller-dedicated pin

Note: When the CD is off, the power supply pins for the controller (MV

supply pins (indicated by asterisk *) are off.

) and the power pins supply for the CD oscillator (XV

(

)

(

)

()(

)

(

)

(

)

1 bit DAC

P2-0~P2-3

ROM

RAM

Digital equalizer

Automatic adjustment

circuit

CLV

servo

Sub code decoder

Digital out Audio out

CD Reset

Synchronous

guarantee EFM

decode

16 k SRAM

Correction circuit

IN1

MXO

MXI

P1-3 P1-0

INTR

P4-3 (SCK/SCL)

P4-2

SI0/SI1/SDA

P4-1 (SI2)

P4-0 (ADin4/BUZR)

SBSY

X’tal OSC

Port1

Timer

Interrupt

Cont.

Serial

Interface

Port4

BUZR

MPX

CPU clock

Micon interface

SBSY

CLCK, DATA, SFSY,

Reset

OT19-22

LRCK, BCK, MBOV, IP F

Data Reg (16 bit)

G-Reg. R/W Buf.

ROM

(16 ´ 8192 Step)

RAM

ALU

(4 ´ 512 word)

Program

Counter

Instruction

Decoder

P3-3 (ADin3) P3-2 (ADin2) P3-1 (ADin1)

P3-0

Conv.

Port3

Stack Reg.

(8Level)

Bias

COM1 (OT1)

COM2 (OT2)

ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV , IPF

LCD Driver/Output Port Port8

S2 (OT6)

S1 (OT5)

COM3 (OT3)

COM4 (OT4)

S10 (OT14/ZDET)

S11 (OT15/CLCK)

S13 (OT17/SFSY)

S12 (OT16/DATA)

S14 (OT18/LRCK)

Reset

Power on Reset

P8-0 (S15/BCK)

P8-1 (S16/AOUT)

Pin Function

TC94A23F

Number

97 COM1/OT1

98 COM2/OT2

99 COM3/OT3

100 COM4/OT4

Symbol Pin Name Function and Operation Remarks

LCD common output

/output port

Common signal output pins for the LCD panel. Those pins configure matrix with S1 to S18

and display up to 72 segments. The LCD can be driven by the 1/2 or 1/3 bias

method. When the 1/2 bias method is set, three levels, MV output at 2-ms intervals at a 62.5 Hz cycle. When the 1/3 bias method is set, four levels, MV

, 1/3MVDD, 2/3MVDD, and GND, are

output at 1-ms intervals at a 125 Hz cycle (when either the 4.5 MHz or 75 kHz crystal oscillator is used).

After system reset or clock stop execution is released, the non-selected waveform (bias voltage) is output. The DISP OFF bit is set to 0 and the common signal is output.

These pins can be switched to an output port (Note 1) or LED driver pins by program. They are usually used for digit output to drive the LEDs.

, 1/2MVDD, and GND, are

Bias voltage

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TC94A23F

Number

1~9

Symbol Pin Name Function and Operation Remarks

S1/OT4

S9/OT13

S10/OT14

/ZDET

S11/OT15

/CLCK

S12/OT16

/DATA

S13/OT17

/SFSY

S14/OT18

/LRCK

P8-0/S15

/BCK

P8-1/S16

/AOUT

P8-2/S17

/MBOV

P8-3/S18

/IPF

LCD segment output

/output port

LCD segment output

/output port

/CD signal

I/O port

/LCD segment output

/CD signal

Segment signal output pins for the LCD panel. Those pins configure a matrix with COM1 to

COM4 and display up to 72 segments. When the 1/2 bias method is set, two levels,

and GND, are output. When the 1/3

bias method is set four levels, MV 1/3MV

The S1 to S14 pins can be switched to an output port (Note 1) by program. Port 8 and S15 to S18 pins can be switched pin by pin to an I/O port and segment output pins. When the pins are set to an I/O port, output is N-channel open drain.

The S10 to S14 and P8-0 to P8-3 pins can be switched to CD signal input/output pins by program. Setting the CD10 bit to 1 switches the pins to the LRCK, BCK, and AOUT pins as the CD pins in batches. The other pins can be individually switched according to the S14/S15/S16 segment data.

CLCK: Inputs/outputs sub code P to W data

DATA: Outputs sub code P to W data. SFSY: Outputs frame sync signal for

LRCK: Outputs channel clock (44.1 kHz).

BCK: Outputs bit clock (1.4112 MHz). AOUT: Outputs audio data. MBOV: Outputs buffer-memory-overflow

IPF: Outputs interpolation pointing flag. If

ZDET: Outputs 1-bit DAC zero detection flag.

segment output for the LED driver. The output

(Note 1) After a system reset, pins also used

, 2/3MVDD, and GND, are output.

reading clock.

playback.

When L channel, outputs Low. When R channel, outputs High. The polarity can be inverted by command.

signal. When buffer memory overflows, outputs H.

AOUT output is C2 error detection/correction, outputs High to indicate correction is impossible.

Pins set as an output port are used for

port can increment OT1 to OT18 by

instruction, facilitating access to data in

external RAM and ROM.

as output ports are set to LCD output; pins also used as I/O ports are set to I/O port input.

Input instruction

Bias voltage

2002-02-06

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