TC74ACT299P/F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT299P,TC74ACT299F
8-Bit PIPO Shift Register with Asynchronous Clear
The TC74ACT299 is an advanced high speed CMOS 8-BIT
PIPO SHIFT REGISTER fabricated with silicon gate and
double-layer metal wiring C
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TLL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and
LOAD DATA) controlled by the two selection inputs (S0, S1).
When one or both enable (
outputs are forced to the high-impedance state; however,
sequential operation or clearing of the register is not affected.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
2
MOS technology.
1G
, 2G) are high, the eight I/O
Features (Note 1)(Note 2)
• High speed: f
• Low power dissipation: I
• Compatible with TTL outputs: V
VIH = 2.0 V (min)
• Symmetrical output impedance: |I
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: t
• Pin and function compatible with 74F299
= 130 MHz (typ.) at VCC = 5 V
max
= 8 μA (max) at Ta = 25°C
CC
= 0.8 V (max)
IL
| = IOL = 24 mA (min)
OH
∼
t
−
pLH
pHL
TC74ACT299P
TC74ACT299F
Weight
DIP20-P-300-2.54A : 1.30 g (typ.)
SOP20-P-300-1.27A : 0.22 g (typ.)
Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result.
Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull
down resistors.
Pin Assignment
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IEC Logic Symbol
Truth Table
TC74ACT299P/F
Inputs
Mode
CLR
Z L H H X X X X X Z Z L L
Clear
Hold H L L L L X X X QA0 QH0 QA0 QH0
Shift H L H L L X H H QGn H QGn
Right H L H L L X L L QGn L QGn
Shift H H L L L H X QBn H QBn H
Left H H L L L L X QBn L QBn L
Load H H H X X X X a h a h
L L X L L X X X L L L L
L X L L L X X X L L L L
Function
Select
S1 S0
Outputs Control Serial
1G
(Note)
(Note)
2G
CK
SL SR
Inputs/
Outputs
A/QA H/QH QA’ QH’
Outputs
Note: When one or both output controls are high, the eight input/output terminals are in the high-impedance state;
however sequential or clearing of the register is not affected.
Z: High impedance
Qn0: The level of Qn before the indicated steady-state input conditions were established.
Qnn: The level of Qn before the most recent active transition indicated by ↓ or ↑.
a, h: The level of the steady-state inputs A, H, respectively.
X: Don’t care
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Timing Chart
TC74ACT299P/F
System Diagram
(Note)
(Note) (Note) (Note) (Note)(Note)
Note: Equivalent circuits
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TC74ACT299P/F
Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7.0 V
DC input voltage VIN −0.5 to VCC + 0.5 V
DC output voltage V
Input diode current IIK ±20 mA
Output diode current IOK ±50 mA
DC output current I
DC VCC/ground current ICC ±250 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW
Storage temperature T
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
−0.5 to VCC + 0.5 V
OUT
±50 mA
OUT
−65 to 150 °C
stg
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 4.5 to 5.5 V
Input voltage VIN 0 to VCC V
Output voltage V
Operating temperature T
Input rise and fall time dt/dV 0 to 10 ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
0 to VCC V
OUT
−40 to 85 °C
opr
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Electrical Characteristics
DC Characteristics
Characteristics Symbol
High-level input
voltage
Low-level input
voltage
High-level output
voltage
Low-level output
voltage
3-state output
off-state current
Input leakage
current
Quiescent supply
current
V
⎯
IH
V
⎯
IL
V
OH
V
OL
I
OZ
I
VIN = VCC or GND 5.5 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA
IN
ICC VIN = VCC or GND 5.5 ⎯ ⎯ 8.0 ⎯ 80.0 μA
I
C
I
OH
V
= V
V
V
= V
V
V
V
IN
IL
IN
IL
IN
OUT
I
or
IH
OH
I
OH
I
OL
I
or
IH
OL
I
OL
= VIH or VIL
= VCC or GND
Per input: V
Other input: V
Test Condition Ta = 25°C
V
= −50 μA
= −24 mA
= −75 mA (Note)
= 50 μA
= 24 mA
= 75 mA (Note)
= 3.4 V
IN
or GND
CC
CC
(V)
4.5 to
5.5
4.5 to
5.5
4.5
4.5
5.5
4.5
4.5
5.5
5.5
5.5
Min Typ. Max Min Max
2.0
⎯ ⎯ 0.8 ⎯ 0.8 V
4.4
3.94
⎯
⎯
⎯
⎯
⎯ ⎯ ±0.5 ⎯ ±5.0 μA
⎯ ⎯ 1.35 ⎯ 1.5 mA
⎯ ⎯ 2.0 ⎯ V
4.5
⎯
⎯
0.0
⎯
⎯
TC74ACT299P/F
= −40 to
Ta
85°C
⎯
4.4
⎯
3.80
⎯
3.85
0.1
0.36
⎯
⎯
⎯
⎯
0.44
1.65
⎯
⎯
⎯
0.1
Unit
V
V
Note: This spec indicates the capability of driving 50 Ω transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements
Characteristics Symbol
Minimum pulse width
(CK)
Minimum pulse width
(
CLR )
Minimum set-up time
(SL, SR, A~H)
Minimum set-up time
(S0, S1)
Minimum hold time
(SL, SR, A~H)
Minimum hold time
(S0, S1)
Minimum removal time
(
CLR )
(input: tr = tf = 3 ns)
t
W (L)
t
W (H)
⎯ 5.0 ± 0.5 ⎯ 5.0 5.0 ns
t
W (L)
t
⎯ 5.0 ± 0.5 ⎯ 3.5 3.5 ns
s
t
⎯ 5.0 ± 0.5 ⎯ 6.0 6.5 ns
s
t
⎯ 5.0 ± 0.5 ⎯ 2.0 2.0 ns
h
t
⎯ 5.0 ± 0.5 ⎯ 0.0 0.0 ns
h
⎯ 5.0 ± 0.5 ⎯ 2.0 2.0 ns
t
rem
Test Condition Ta = 25°C
V
⎯ 5.0 ± 0.5 ⎯ 5.0 5.0 ns
(V) Typ. Limit Limit
CC
Ta
−40 to
85°C
=
Unit
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TC74ACT299P/F
AC Characteristics
Characteristics Symbol
Propagation delay
time
(CK-QA’, QH’)
Propagation delay
time
(
CLR -QA’, QH’)
Propagation delay
time
(CK-QA~QH)
Propagation delay
time
(
CLR -QA~QH)
Output enable time
Output disable time
Maximum clock
frequency
Input capacitance CIN ⎯ ⎯ 5 10 ⎯ 10 pF
Bus input capacitance C
Power dissipation
capacitance
(CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Test Condition Ta = 25°C
V
t
pLH
t
pHL
t
pHL
t
pLH
t
pHL
t
pHL
t
pZL
t
pZH
t
pLZ
t
pHZ
f
max
⎯ ⎯ 13 ⎯ ⎯ ⎯ pF
I/O
C
PD
(Note)
⎯ 5.0 ± 0.5 ⎯ 7.2 10.5 1.0 12.0 ns
⎯ 5.0 ± 0.5 ⎯ 6.0 10.0 1.0 11.5 ns
⎯ 5.0 ± 0.5 ⎯ 7.4 11.4 1.0 13.0 ns
⎯ 5.0 ± 0.5 ⎯ 6.3 10.5 1.0 12.0 ns
⎯ 5.0 ± 0.5 ⎯ 7.4 11.4 1.0 13.0 ns
⎯ 5.0 ± 0.5 ⎯ 7.2 9.6 1.0 11.0 ns
⎯ 5.0 ± 0.5 80 120 ⎯ 80 ⎯ MHz
⎯ ⎯ 160 ⎯ ⎯ ⎯ pF
(V) Min Typ. Max Min Max
CC
= −40 to
Ta
85°C
Unit
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
(opr) = CPD･VCC･fIN + I
CC
CC
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Package Dimensions
TC74ACT299P/F
Weight: 1.30 g (typ.)
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Package Dimensions
TC74ACT299P/F
Weight: 0.22 g (typ.)
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TC74ACT299P/F
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• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
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injury or damage to property, including data loss or corruption. Before creating and producing designs and using, customers must
also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document,
the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the “TOSHIBA
Semiconductor Reliability Handbook” and (b) the instructions for the application that Product will be used with or for. Customers are
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