TOSHIBA TC74AC573P, TC74AC573F, TC74AC573FT Technical data
TC74AC573P/F/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC573P,TC74AC573F,TC74AC573FT
Octal D-Type Latch with 3-State Output
The TC74AC573 is an advanced high speed CMOS OCTAL
LATCH fabricated with silicon gate and double-layer metal
wiring C
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
input (LE) and a output enable input (
impedance state.
discharge or transient excess voltage.
2
MOS technology.
It achieves the high speed operation similar to equivalent
These 8-bit D-type latches are controlled by a latch enable
OE
).
When the
All inputs are equipped with protection circuits against static
OE
input is high, the eight outputs are in a high
Features
TC74AC573P
TC74AC573F
• High speed: tpd = 6.0 ns (typ.) at VCC = 5 V
• Low power dissipation: I
• High noise immunity: V
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
• Balanced propagation delays: t
• Wide operating voltage range: V
• Pin and function compatible with 74F573
= 8 μA (max) at Ta = 25°C
CC
NIH
= V
= 28% VCC (min)
NIL
transmission lines.
∼
t
−
pLH
pHL
CC (opr)
= 2 to 5.5 V
TC74AC573FT
Weight
DIP20-P-300-2.54A : 1.30 g (typ.)
SOP20-P-300-1.27A : 0.22 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
1
2007-10-01
Pin Assignment IEC Logic Symbol
(1)
OE
D0
D1
D2
D3
D4
D5
D6
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
CC
OE
LE
D0
D1
D2
D3
D4
D5
D6
D7
(11)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
EN
C1
1D
TC74AC573P/F/FT
(19)
Q0
(18)
Q1
(17)
Q2
(16)
Q3
(15)
Q4
(14)
Q5
(13)
Q6
(12)
Q7
D7
GND
9
10
(top view)
12
11
Q7
LE
Truth Table
Inputs Output
LE D Q
OE
H X X Z
L L X Qn
L H L L
L H H H
X: Don’t care
Z: High impedance
: Q outputs are latched at the time when the LE input is taken to a low logic level.
Q
n
System Diagram
D0
2
D1
3 456789
D2
D3
D4
D5
D6
D7
L
17
D
Q
L
Q2
16
D
D
Q
L
Q3
15
D
Q
L
Q4
14
D
Q
Q5
L
13
D
Q
Q6
L
12
Q
Q7
LE
OE
D
11
1
L
19
D
Q
Q0
L
18
D
Q
Q1
2
2007-10-01
TC74AC573P/F/FT
Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7.0 V
DC input voltage VIN −0.5 to VCC + 0.5 V
DC output voltage V
Input diode current IIK ±20 mA
Output diode current IOK ±50 mA
DC output current I
DC VCC/ground current ICC ±200 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP/TSSOP) mW
Storage temperature T
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
−0.5 to VCC + 0.5 V
OUT
±50 mA
OUT
−65 to 150 °C
stg
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage V
Input voltage V
Output voltage V
Operating temperature T
Input rise and fall time dt/dV
CC
IN
OUT
opr
0 to 100 (V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
2.0 to 5.5 V
0 to V
CC
0 to V
CC
−40 to 85 °C
= 3.3 ± 0.3 V)
CC
0 to 20 (V
= 5 ± 0.5 V)
CC
V
V
ns/V
3
2007-10-01
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