TOSHIBA TB6556F, TB6556FG Technical data

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TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic

TB6556F/FG

3-Phase Full-Wave Sine-Wave PWM Brushless Motor Controller

Features

• Sine-wave PWM control

• Built-in triangular-wave generator

(carrier cycle = f

• Built-in lead angle control function (0° to 58° in 32 steps)

External setting/automatic internal setting

• Built-in dead time function (setting 2.6 µs or 3.8 µs)

• Supports bootstrap circuit

• Overcurrent protection signal input pin

• Built-in regulator (V

• Operating supply voltage range: V

/252 (Hz))

osc

refout

= 5 V (typ.), 30 mA (max))

= 6 V to 10 V

CC

Weight: 0.33 g (typ.)

TB6556F/FG

TB6556FG: TB6556FG is a Pb-free product. The following conditions apply to solderability: *Solderability

1. Use of Sn-63Pb solder bath

*solder bath temperature = 230˚C *dipping time = 5 seconds *number of times = once *use of R-type flux

2. Use of Sn-3.0Ag-0.5Cu solder bath

*solder bath temperature = 245˚C *dipping time = 5 seconds *the number of times = once *use of R-type flux

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Block Diagram

+

G

in

out

PH

2524 26 27

LPF

LA 28

UL

LL

30 29

TB6556F/FG

X

out

HU HV

HW

V

CC

GND

V

refout

RES

I

CW/CCW

SS

FG

EV

Peak hold Filter

14

in

15 21 20 19

2

e

Regulator

1

13 23

11

3

dc

18 22 17 16

System clock

generator

Position detector

Power-on

reset

Internal

reference

voltage

FG

Protection

&

reset

Phase

matching

Rotating direction

ST/SP CW/CCW ERR GB

5-bit AD

Counter

Output waveform generator

Upper limit

Lower limit

6-bit triangular

wave generator

Data

select

Comparator

Phase U

Phase V

Phase W

PWM

HU HV HW

Comparator

120/180

Charger

120°-

turn-on

matrix

Switching 120°/180°

and

gate block

protection

on/off

Setting

dead

time

10

12

Td

U

9

X

6

V

8

Y

5

W

7

Z

4

OS

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Pin Description

∼

Pin No. Symbol Description Remarks

TB6556F/FG

21 HU Positional signal input pin U 20 HV Positional signal input pin V 19 HW Positional signal input pin W

18 CW/CCW

11 RES Reset-signal-input pin

2 Ve Volt age command signal With built-in pull-down resistor 24 Gin 25 G

26 PH Peak hold

27 LPF RC low-pass filter Connect the low-pass filter capacitor (built-in 100 kΩ resistor)

28 LA

29 LL Lower limit for LA Set lower limit for LA (LL = 0 V to 5.0 V) 30 UL Upper limit for LA Set upper limit for LA (UL = 0 V to 5.0 V)

12 OS

3 Idc

14 Xin Inputs clock signal 15 X

23 V

17 FG FG signal output pin Outputs 3 PPR of positional signal

16 REV

9 U Outputs turn-on signal

8 V Outputs turn-on signal

7 W Outputs turn-on signal

6 X Outputs turn-on signal

5 Y Outputs turn-on signal

4 Z Outputs turn-on signal

1 VCC Power supply voltage pin VCC = 6 to 10 V 10 Td Inputs setting dead time L: 3.8 µs, H or OPEN : 1.9 µs 22 SS 120°/180° select signal L: 120° tu rn- o n m o de, H o r OPEN: 1 80° turn-on mode 13 GND Ground pin ⎯

refout

Rotation direction signal input pin

Gain setting I

out

Lead angle setting signal input pin

Inputs output logic select signal

Inputs overcurrent protection signal

Outputs clock signal

out

Outputs reference voltage signal

Reverse rotation detection signal

When positional signal is HHH or LLL, gate block protection operates. With built-in pull-up resistor, built-in digital filter (

L: Forward H: Reverse

L: Reset (output is non-active) operation/halt operation, also used for gate protection, built-in pull-up resistor

signal level at a gain that optimizes the LA

dc

Connect the peak-hold capacitor and discharge resistor to GND, parallel to each other

Sets 0° to 58° in 32 steps

L: Active LOW H: Active HIGH

Inputs DC link current. Reference voltage: 0.5 V With built-in filter (

With built-in feedback resistor

5 V (typ.), 30 mA (max)

Detects reverse rotation.

Select active HIGH or active LOW using the output logic select pin.

1 µs), built-in digital filter (

∼

−

∼

−

1 µs)

500 ns)

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Input/Output Equivalent Ci rcuits

Pin Description Symbol Input/Output Signal Input/Output Internal Circuit

Digital

Positional signal input pin U Positional signal input pin V Positional signal input pin W

Forward/reverse switching input pin

L: Forward (CW) H: Reverse (CCW)

CW/CCW

With Schmitt trigger

HU

Hysteresis 300 mV (typ.)

HV

Digital filter: 500 ns (typ.)

HW

L: 0.8 V (max) H: V

Digital

L: 0.8 V (max) H: V

− 1 V (min)

refout

− 1 V (min)

refout

TB6556F/FG

V

refout

200 kΩ

2.0 kΩ

V

refout

100 kΩ

2.0 kΩ

V

refout

Reset input L: Stops operation (reset)

H: Operates

120°/180° select si g nal L: 120° turn-on mode

H: 180° turn-on mode (OPEN)

Voltage command signal

1.0 V < Ve ≤ 2.1 V Refresh operation (X, Y, Z pins: ON duty of 8%)

RES

SS

V

e

Digital L: 0.8 V (max)

H: V

Digital With Schmitt trigger

Hysteresis: 300 mV (typ.) L: 0.8 V (max)

H: V

Analog Input voltage range 0 to 5.4 V

Input voltage of 5.4 V or higher is clipped to 5.4 V.

refout

− 1 V (min)

100 kΩ

2.0 kΩ

V

refout

200 kΩ

2.0 kΩ

V

CC

100 Ω

150 kΩ

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TB6556F/FG

A

Pin Description Symbol Input/Output Signal Input/Output Internal Circuit

Lead angle setting signal input pin

0 V: 0° 5 V: 58° (5-bit AD)

Gain setting signal input (LA setting)

Peak hold (LA setting)

Gin

G

PH

When LA is fixed externally, connect LL to GND and UL to V input the setting voltage to the LA pin.

Input voltage range: 0 V to 5.0 V (V

)

LA

out

refout

Input voltage of V clipped to V

When LA is fixed automatically, open the LA pin. In this state, the LA pin is used only for confirmation of LA width.

Non-inverted amplifier 25 dB (max)

output voltage

G

out

LOW: GND HIGH: V

CC

Connect the peak-hold capacitor and discharge resistor to GND, parallel to each other. 100 kΩ/0.1µF recommended

.

refout

− 1.7 V

refout

, and then

refout

or higher is

V

CC

100 Ω

200 kΩ

utomatic LA

circuit

CC

G

in

100 Ω

Idc

VCC V

To peak

hold circuit

G

out

V

CC

100 Ω

Low-pass filter (LA setting)

Lower limit for LA LL

LPF

Connect the low-pass filter capacitor (built-in 100 kΩ resistor)

0.1µF recommended

Clip lower limit for LA LL = 0 V to 5.0 V When LL > UL, LA is fixed at LL value.

V

CC

100 kΩ

100 Ω

VCC

100 Ω

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TB6556F/FG

Pin Description Symbol Input/Output Signal Input/Output Internal Circuit

VCC

Upper limit for LA UL

Setting dead time input pin L: 3.8 µs

H or OPEN: 1.9 µs

Output logic select signal input pin

L: Active LOW H: Active HIGH

Overcurrent protection signal input pin

Clock signal input pin Xin

Td

OS

I

dc

Clip upper limit for LA UL = 0 V to 5.0 V When LL > UL, LA is fixed at LL value.

Digital L: 0.8 V (max)

H: V

Digital

L: 0.8 V (max) H: V

Analog Digital filter: 1 µs (typ.) Gate pr otected at 0.5 V or higher

(released at carrier cycle)

refout

− 1 V (min)

100 Ω

V

refout

100 kΩ

2 kΩ

V

refout

100 kΩ

2 kΩ

100 Ω

V

CC

200 kΩ

5 pF

0.5 V

V

refout

G

out

Gin

Comparator

refout

Clock signal output pin X

Operat ing range 2 MHz to 8 MHz (crystal oscillation)

out

X

in

360 kΩ

6

X

out

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TB6556F/FG

Pin Description Symbol Input/Output Signal Input/Output Internal Circuit

VCC VCC

V

CC

Reference voltage signal output pin

Reverse-rotation-detection signal output pin

FG signal output pin FG

V

refout

REV

5 ± 0.5 V (max 30 mA)

Digital Push-pull output: ± 1 mA (max)

V

refout

V

refout

V

refout

100 Ω

refout

100 Ω

Turn-on signal output pin U Turn-on signal output pin V Turn-on signal output pin W Turn-on signal output pin X Turn-on signal output pin Y Turn-on signal output pin Z

U

Analog

V

W

Push-pull output: ± 2 mA (max) X Y

L: 0.78 V (max) Z

H: V

− 0.78 V (min)

refout

V

refout

100 Ω

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