Toshiba Satellite M35X, Satellite M40X, Satellite EAL20 Schematic

A

1 1

B

C

D

E

2 2

Fortworth Banias

EAL20 LA-2462 Schematic

uFC-PGA Dothan / Montara-GM+

3 3

4 4

M11P-128M VRAM / ICH4-M

2004-08-12

REV: 0.1

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

C

D

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

EAL20 LA-2462

147Friday, Se ptember 17, 2004

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0.1

of

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B

C

D

E

Compal Confidential

Model Name : EAL20

Fan Control

page 4

File Nam e : L A-2462

1 1

LCD Conn.

page 20

CRT Conn.

TV-OUT Conn.

page 21

page 21

ATI M11-P

BGA-708 Pin

with 32/64/128MB
On Board VRAM

page 13,14,15,16,17,18

AGP4X/DVO

1.5V 266MHz

TV Encoder

CH-7011A

2 2

IDSEL:AD16
(PIRQE#,
GNT#0,
REQ#0)

IEEE 1394a
VIA VT6301S

page 27

IDSEL:AD18
(PIRQ[G..H]#,
GNT#3/4,
REQ#3/4)

Mini PCI
socket

page 30

IDSEL:AD17
(PIRQB#,
GNT#1,
REQ#1)

1394 Conn.

page 27

3 3

RTC CKT.

page 24

Power O n/Off CKT.

page 37

DC/DC Interface CKT.

4 4

page 38

page 19

3.3V 33 MHz

LAN
RTL8100CL

page 26

RJ45/RJ11

page 26

Touch Pad

PCI BUS

IDSEL:AD20
(PIRQ[A..B]#,
GNT#2,
REQ#2)

CardBus

ENE CB714/CB1410

5 in 1 Slot

page 29

ENE KB910

page 34

Int.KBD

512KB BIOS

Mobile Banias/Dothan

Celeron-M

uFCPGA-478 CPU

H_A#( 3..31) H_D#(0..63)

PSB

400MHz

Intel 855GME

uFCBGA-732

page 6,7,8,9

Hub-Link

Intel ICH4-M

BGA-421

page 28

Slot 0

page 29

LPC BUS

page 36

page 35

page 22,23,24

3.3V 33MHz

SMsC LPC47N217

Super I/ O

PARALLEL

page 33

page 4,5

USB 2.0

3.3V 48MHz

3.3V 24.576MHz

3.3V ATA-100

page 33

Thermal Sensor
ADI ADM1032AR

Memory BUS(DDR)

2.5V DDR200/266/333

IDE

FIR

page 33

page 4

AC-LINK

CDROM
Conn.

page 25

HDD Conn.

page 25

SW DJ Ckt.

page 25

Clock G en erator

Cypress CY28346ZCT-2

page 12

200pin DDR-SO-DIMM X2

BANK 0, 1, 2, 3

USB conn
x2

page 35

USB conn
x1

page 35

AC97 Codec

ALC250 Ver.C

Port 2,3

Port 4

page 10,11

MDC Conn

page 31

AMP
TPA0232

page 32

Audio Board
Conn

LS-2463

page 32

page 31

EAL20 Sub Board

LED/SW Board
Conn
LS-2462

page 36

T/P Board
Conn
LS-2461

page 36

WL-KSW Board

LS-2464

Power C ircuit DC/DC

page 38,39,40,41

42,43,44,45

A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODYOF THE CO MPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION I T CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONIC S, INC .

C

D

Size Docu m e nt Number Re v

Date: Sheet

Compal Electronics, Inc.

Block D iagram

EAL20 LA-2462

247Friday, September 17, 2004

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of

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Voltage Rails

Symbol note:

:means digital ground.

S3

Power Plane

VIN
B+
+CPU_CORE
+VCCP
+1.25VS
+VGA_CORE
+1.35VS 1.35V switched power rail fo r G M CH co re po wer ON O FF OFF
+1.5VALW
+1.5VS
+1.8VS
+2.5V
+2.5VS
+3VALW

+3V
+3V ON ON OFF
+3VS
+5VALW
+5VS
+12VALW
RTCVCC

Note : O N * me an s t h at t h i s p o we r pl ane is ON only with AC power available, oth erwise it is OFF.

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V rail for ProcessorI/O

1.25V switched power rail for DDR Vtt

1.2V/1.0V switched power rail for VGA core power

1.5V always on power rail

1.5V switched power rail for AGP interface

1.8V swi t ched power rail for CPU PLL & Hub-Link

2.5Vpower rail for system DDR

2.5V power rail for VGA DDR

3.3V always on power rail

3.3V switched powerrail

3.3V switched powerrail
5V always on power rail
5V switched powerrail
12V always on power rail
RTC power

S0-S1

N/A

ON OFF
ON
ON
ON

ON
ON
ON
ON
ON OFF
ON

ON
ON
ON
ON

N/A
N/A

OFF
OFF
OFF

ON
OFF
OFF
ON

ON

OFF
ON
OFF
ON
ON

S5

N/A
N/AN/A
OFF
OFF
OFF
OFF

ON*
OFF
OFF
OFF
OFF
ON*

OFF
ON*
OFF
ON*
ONON

:mean s analog ground.
:mea ns reserved.@

FortworthBanias Comparison Table

Item

VGA
VRAM
TV Encoder

*

Descrite

ATIM11P

128MB/64MB

N/A

UMA

N/A

CH7011A

Boar d ID Table for AD channel

PageUMA

13 ~ 16

13 ~ 14

19

Vcc 3.3V +/- 5%

1 1

ICH4-M I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

HEX

A0
A2
D2

ADDRESS

1 0 1 0 0 0 0 X
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X

BID/PID

0
1
2
3
4
5 3.465 V3.135 V

10K +/- 5%Ra

Rb/Rc V min

0

8.2K +/- 5%

AD_BID

0 V

1.412 V 1.560 V
18K +/- 5%
33K +/- 5%
56K +/- 5%

NC 3.300 V

V typ

AD_BID

0 V 0 V

1.486 V

2.121 V

2.533 V

2.800 V

V

AD_BID

2.227 V2.015 V

2.659 V2.406 V

2.940 V2.660 V

max

KB910 I2C / SMBUS ADDRESSING

DEVICE

SM1 24C16
SM1 SMART BATTERY
SM2 ADM0132

CPU THERMAL MONITOR

Exter nal PCI Devices

DEVICE

1394
LAN
CARD BUS

Mini-PCI
AGP BUS

PCI Device ID

D0
D1
D4

D2
N/A

HEX

A0H

98H

00HSM2 AL C250 AUDI O CODE C 0 0 0 0 0 0 0 X b

ADDRESS

1 0 1 0 0 0 0 X b
0 0 0 1 0 1 1 X b16H
1 0 0 1 1 0 0 X b

IDSEL #

AD16
AD17
AD20

AD18
AGP_DEVSEL#

REQ/GNT #

0
1
2
2B5IN1 D4 AD20
3,4

N/A

PIRQ

E
F
A

G,H
A

Board ID

0

*

1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

0.4

0.5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

A

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

Notes List

EAL20 LA-2462

347Friday, Se pt ember 17, 2004

of

0.1

A

P4
U4
V3
R3
V2

W1

T4

W2

Y4
Y1
U1

AA3

Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

R2

P3

T2

P1

T1

U3
AE5

A16
A15

B15
B14

N2

L1

J3

N4

L4

H2

K3

K4

A4

J2
B11

H1

K1

L2

M3

C8

B8

A9

C9

A7

M2

B7
C19
A10
B10
B17

E4

A6
A13
C12
A12

C5

F23
C11
B13

B18
A18
C17

U12A

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#

ADDR GROUP

A25#
A26#
A27#
A28#
A29#
A30#
A31#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADSTB0#
ADSTB1#

ITP_CLK0
ITP_CLK1

BCLK0
BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC
THERMTRIP#

mFCBGA479

HOST CLK

CONTROL GROUP

1 2

R152
56_0402_5%

+VCCP

H_A#[3..31]

H_REQ #[0..4]

H_ADSTB#0<6>
H_ADSTB#1<6>

CLK_CPU_ITP<12>
CLK_CPU_ITP#<12>

CLK_CPU_BCLK<12>
CLK_CPU_BCLK#<12>

H_DEFER#<6>

H_CPURST#<6>

R145

1 2

150_0402_1%

ITP_DBRESET#

1 2

R374
330_0402_5%

H_CPUSLP#<22>

R146 1K_0402_5%@

12

1 2

R378

H_ADS#<6>

H_BNR#<6>
H_BPRI#<6>
H_BR0#<6>

H_DRDY#<6>

H_HIT#<6>

H_HITM#<6>

H_LOCK#<6>

H_RS#0<6>

H_RS#1<6>

H_RS#2<6>

H_TRDY#<6>

R150 0_0402_5%

H_DBSY#<6>
H_DPSLP#<7,22>

H_DPWR#<7>

1K_0402_5%@

H_A#[3..31]<6>

4 4

H_REQ#[0:4]<6>

3 3

+VCCP

+3VALW

ITP_DBRESET#<23>

2 2

H_CPUPWRGD<22>

H_IERR#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2

1 2

H_CPUPWRGD
H_CPUSLP#

ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_PROCHOT#

ITP_TCK
ITP_TDI

Banias

MISC

THERMAL
DIODE

B

DATA GROUP

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#

LINT0/INTR

LINT1/NMI

STPCLK#

SMI#

H_D#[0..63]

H_D#0

A19

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_A20M#
H_IGNNE#

H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>

H_DSTBN#0 <6>
H_DSTBN#1 <6>
H_DSTBN#2 <6>
H_DSTBN#3 <6>
H_DSTBP#0 <6>
H_DSTBP#1 <6>
H_DSTBP#2 <6>
H_DSTBP#3 <6>

H_A20M# <22>
H_FERR# <22>
H_IGNNE# <22>
H_INIT# <22>
H_INTR <22>
H_NMI <22>

H_STPCLK# <22>
H_SMI# <22>

H_D#[0..63] <6>

C

Fan Control circuit

EN_DFAN1<34>

H_FERR#
H_CPUSLP#
H_DPSLP#
H_STPCLK#
H_INIT#
H_SMI#
H_IGNNE#
H_NMI

1 2

R358
10K_0402_5%

C702 100P_0402_50V8J@
C703 100P_0402_50V8J@
C704 100P_0402_50V8J@
C705 100P_0402_50V8J@
C706 100P_0402_50V8J@
C707 100P_0402_50V8J@
C708 100P_0402_50V8J@
C709 100P_0402_50V8J@

C412

0.1U_0402_16V4Z

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

5
6

R364 8.2K_0402_5%

D

R144

54.9_0 4 02_1%

@

1 2

+VCCP

1 2

R149 39.2_0603_1%

1 2

R151 150_0402_1%

Thermal Sensor ADI ADM1032AR

+3VS

2

12

C94

R121

@

1

1

C88

2

2200P_0402_25V7K

10K_0402_5%

0.1U_0402_16V4Z

Joint use LM358A with Power
Battery detect circuit.

PU5B

LM358A_SO8

+

FAN1_ON

1 2

7

0

-

R361 100_0402_5%

W=15mil

H_THERMDA
H_THERMDC

ITP_TMS

ITP_TDI

C410

0.1U_0402_16V4Z

1 2

FANSP EED1<34>

ITP_TDOH_CPURST#

U11

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR_SOP8

Address:1001_100X

2

B

1

2

+3VS

+VCCP+VCCP

R147

54.9_ 0402_1%

@

1 2

8
7
6
5

D20
1N4148_SOD80

ITP_TRST#

12

1 2

R154 680_0402_5%

1 2

R153 27.4_0402_1%

SCLK

SDATA

ALERT#

+5VS

1

C

Q32
FMMT619_SOT23

E

3
12

1 2

R297 10K_0402_5%

1

@

C310
1000P_0402_50V7K

2

Close to Fan Conn.

E

ITP_TCK

D21
1SS355_SOD323

FAN1_VOUT

1

@

C313
1000P_0402_50V7K

2

EC_SMC_2 <31,34>
EC_SMD_2 <31,34>

1

C397
10U_0805_10V4Z

2

JP7

1
2
3

ACES_85205-0300

1 1

A

H_PROCHOT#

1 2

R148 56_0402_5%

+VCCP

+VCCP

B

1 2

R155
56_0402_5%

H_THERMTRIP#

12

R156
56_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODYOF THE CO MPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONIC S, INC .

C

THRMTRI P# <23>

D

Title

Size Docu m e nt Number Re v

Date: Sheet

Compal Electronics, Inc.

INTEL CPU BANIAS ( 1 of 2)

EAL20 LA-2462

Friday, September 17, 2004

E

of

447

0.1

A

B

C

D

E

+CPU_CORE

C97
10U_1206_6.3V6M

0.1U_0402_10V6K

1

C454

2

1

1

C419

2

2

0.1U_0402_10V6K

Title

Size Document Number Re v

Date: Sheet

U12C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

mFCBGA479

C399

0.1U_0402_10V6K

Banias

C437

AA11
AA13
AA15
AA17
AA19
AA21

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC11
AC13
AC15
AC17
AC19

AD10
AD12
AD14
AD16
AD18

AE11
AE13
AE15
AE17
AE19

AF10
AF12
AF14
AF16
AF18

Y22
AA5
AA7
AA9

AB6
AB8

AC9

AD8

AE9

AF8

M4

M5
M21
M24

N3

N6

N22
N23
N26

P2

P5

P21
P24

R1

R4

R6

R22
R25

T3

T5

T21
T23

1

2

Compal Electronics, Inc.

INTELCPU BANIAS (2 of 2)

EAL20 LA-2462

E

T26

VSS

U2

VSS

U6

VSS

U22

VSS

U24

VSS

V1

VSS

V4

VSS

V5

VSS

V21

VSS

V25

VSS

W3

VSS

W6

VSS

W22

VSS

W23

VSS

W26

VSS

Y2

VSS

Y5

VSS

Y21

VSS

Y24

VSS

AA1

VSS

AA4

VSS

AA6

VSS

AA8

VSS

AA10

VSS

AA12

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA20

VSS

AA22

VSS

AA25

VSS

AB3

VSS

AB5

VSS

AB7

VSS

AB9

VSS

AB11

VSS

AB13

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB23

VSS

AB26

VSS

AC2

VSS

AC5

VSS

AC8

VSS

AC10

VSS

AC12

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC21

VSS

AC24

VSS

AD1

VSS

AD4

VSS

AD7

VSS

AD9

VSS

AD11

VSS

AD13

VSS

AD15

VSS

AD17

VSS

AD19

VSS

AD22

VSS

AD25

VSS

AE3

VSS

AE6

VSS

AE8

VSS

AE10

VSS

AE12

VSS

AE14

VSS

AE16

VSS

AE18

VSS

AE20

VSS

AE23

VSS

AE26

VSS

AF2

VSS

AF5

VSS

AF9

VSS

AF11

VSS

AF13

VSS

AF15

VSS

AF17

VSS

AF19

VSS

AF21

VSS

AF24

VSS

0.1

of

547Friday, Se ptember 17, 2004

1

+

2

+CPU_CORE

+CPU_CORE

+CPU_CORE

10U_1206_6.3V6M

+CPU_CORE

10U_1206_6.3V6M

+CPU_CORE

10U_1206_6.3V6M

+CPU_CORE

10U_1206_6.3V6M

Vcc-core
Decoupling

SPCAP,Polymer

+CPU_VCCA

1

C74

2

1

+

C113

@

150U_D2_6.3VM

2

1

+

C333
220U_D2_2VM

@

2

10U_1206_6.3V6M

1

1

C382

C387

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

1

C409

C442

2

2

10U_1206_6.3V6M

1

1

C42

C63

2

2

10U_1206_6.3V6M

1

1

C425

C408

2

2

10U_1206_6.3V6M

1

1

C40

C62

2

2

10U_1206_6.3V6M

1

C71

2

0.01U_0402_16V7K

0.1U_0402_10V6K

1

C457

2

0.1U_0402_10V6K

1

+

C334
220U_D2_2VM

2

1

C38

2

10U_1206_6.3V6M

1

C424

2

10U_1206_6.3V6M

1

C75

2

10U_1206_6.3V6M

1

C373

2

10U_1206_6.3V6M

1

C76

2

10U_1206_6.3V6M

35X10uF

10U_1206_6.3V6M

1

1

C34

2

2

1

C434

2

0.1U_0402_10V6K

1

+

2

10U_1206_6.3V6M

1

C52

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

C80

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

C446

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

C374

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

C77

2

10U_1206_6.3V6M

1

C64

C37

2

0.01U_0402_16V7K

0.1U_0402_10V6K

1

1

C413

2

2

C336
220U_D2_2VM

10U_1206_6.3V6M

1

C443

2

1

C43

2

10U_1206_6.3V6M

1

C444

2

10U_1206_6.3V6M

1

C441

2

10U_1206_6.3V6M

1

C78

2

ESR, mohm

12m ohm/4
5m ohm/35MLCC 0805 X5R

10U_1206_6.3V6M

1

C58

2

0.01U_0402_16V7K

1

C456

C392

2

0.1U_0402_10V6K

D

1

+

C335
220U_D2_2VM

2

1

1

C383

C385

10U_1206_6.3V6M

2

2

10U_1206_6.3V6M

1

1

C41

C39

10U_1206_6.3V6M

2

2

1

1

C386

C384
10U_1206_6.3V6M

2

2

1

1

C375

C51
10U_1206_6.3V6M

2

2

1

1

C445

C79

10U_1206_6.3V6M

2

2

ESL,nHC,uF

3.5nH/44X220uF

0.6nH/35

1

C104

2

0.1U_0402_10V6K

1

C404

2

0.1U_0402_10V6K

1

2

R44 54.9_0402_1%

@

1 2
1 2

R45 54.9_0402_1%@

1 1

Dothan VCCA update(WW45 2003)
Dothan B-Step support 1.5V only for VCCA

2 2

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

+VCCP

12

R66
1K_0402_1%

3 3

R65

2K_0402_1%

4 4

1

C30
1U_0603_10V4Z

2

1 2

1

C29
220P_0402_50V7K

2

12

R88

27.4_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

A

R93

54.9_0402_1%

+1.8VS

+1.5VS

12

R60

27.4_0402_1%

R75

1 2

0_1206_5%

R108

1 2

0_1206_5%@

12

54.9_0402_1%

+CPU_CORE

CPU_VID0<45>
CPU_VID1<45>
CPU_VID2<45>
CPU_VID3<45>
CPU_VID4<45>
CPU_VID5<45>

R58

+CPU_VCCA

+VCCP

PSI#<45>

12

GTL_REF0

COMP0
COMP1
COMP2
COMP3

B

VCCSENSE
VSSSENSE

R158
1K_0402_5%@

U12B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PSI#
VID0

VID1
VID2
VID3
VID4
VID5

GTLREF0
GTLREF1
GTLREF2
GTLREF3

COMP0
COMP1
COMP2
COMP3

RSVD
RSVD
RSVD
RSVD

TEST3

mFCBGA479

Banias

POWER, GROUNG, RESERVED SIGNALS AND NC

D10
D12
D14
D16

E11
E13
E15
F10
F12
F14
F16

K6
L5

L21

M6

M22

N5

N21

P6

P22

R5

R21

T6

T22

U21

D6

D8
D18
D20
D22

E5
E7

E9
E17
E19
E21

F6

F8
F18

E1

E2

F2

F3

G3
G4
H4

AD26

E26

G1

AC1

P25
P26
AB2
AB1

B2
AF7
C14

C3

C16

12

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

0.01U_0402_16V7K

+VCCP

C93

150U_D2_6.3VM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

C

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFORMATIO N IT CO NTAINS

5

4

3

2

1

H_A#[3..31]<4>

H_REQ#[0..4]<4>

D D

HUB_PD[0..10]<22>

C C

CLK_MCH_BCLK#<12>
CLK_MCH_BCLK<12>

B B

+1.35VS

H_A#[3 ..31]
H_REQ#[0..4]

HUB_PD[0..10]

H_ADSTB# 0<4>
H_ADSTB# 1<4>

1 2
1 2

H_DSTBN#0<4>
H_DSTBN#1<4>
H_DSTBN#2<4>
H_DSTBN#3<4>
H_DSTBP#0<4>
H_DSTBP#1<4>
H_DSTBP#2<4>
H_DSTBP#3<4>
H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

H_CPURST#<4>

HUB_PSTRB<22>
HUB_PSTRB#<22>

12

W=10mil

HDVREF

HCCVREF

HAVREF

R390 27.4_0402_1%
R134 27.4_0402_1%

R461 37.4_0402_1%

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HYSWING
HXSWING
HYRCOMP
HXRCOMP

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

CPURST#

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9

HUB_PD10

HI_PSTRB
HI_PSTRB#
HUB_RCOMP
HUB_VSWI NG
HUB_VREF

U14A

Montara-GM(L)

P23

HA#3

T25

HA#4

T28

HA#5

R27

HA#6

U23

HA7#

U24

HA#8

R24

HA#9

U28

HA#10

V28

HA#11

U27

HA#12

T27

HA#13

V27

HA#14

U25

HA#15

V26

HA#16

Y24

HA#17

V25

HA#18

V23

HA#19

W25

HA#20

Y25

HA#21

AA27

HA#22

W24

HA#23

W23

HA#24

W27

HA#25

Y27

HA#26

AA28

HA#27

W28

HA#28

AB27

HA#29

Y26

HA#30

AB28

HA#31

R28

HREQ#0

P25

HREQ#1

R23

HREQ#2

R25

HREQ#3

T23

HREQ#4

AA26

AD29

AE29

T26

K28
B18
H28
B20

K21

J21

J17
Y28
Y22

J28

C27

E22

D18

K27

D26

E21

E18

J25

E25

B25
G19

F15

U7
U4
U3

V3
W2
W6

V6
W7

T3

V5

V4
W3

V2

T2

U2
W1

HOST

HADSTB#0
HADSTB#1

BCLK#
BCLK
HYSWING
HXSWING
HYRCOMP
HXRCOMP

HVREF0
HVREF1
HVREF2
HCCVREF
HAVREF

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
DINV0#
DINV1#
DINV2#
DINV3#

CPURST#
HL_0

HL_1
HL_2
HL_3
HL_4
HL_5
HL_6
HL_7
HL_8
HL_9
HL_10
HLSTB
HLSTB#
HLRCOMP
PSWING
HLVREF

HUB I/F

RG82855GME_uFCBGA732

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8

HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

ADS#

HTRDY#

DRDY#

DEFER#

HITM#

HIT#
HLOCK#
BREQ0#

BNR#

BPRI#

DBSY#

RS#0
RS#1
RS#2

H_D#[0..63]

H_D#0

K22

H_D#1

H27

H_D#2

K25

H_D#3

L24

H_D#4

J27

H_D#5

G28

H_D#6

L27

H_D#7

L23

H_D#8

L25

H_D#9

J24

H_D#10

H25

H_D#11

K23

H_D#12

G27

H_D#13

K26

H_D#14

J23

H_D#15

H26

H_D#16

F25

H_D#17

F26

H_D#18

B27

H_D#19

H23

H_D#20

E27

H_D#21

G25

H_D#22

F28

H_D#23

D27

H_D#24

G24

H_D#25

C28

H_D#26

B26

H_D#27

G22

H_D#28

C26

H_D#29

E26

H_D#30

G23

H_D#31

B28

H_D#32

B21

H_D#33

G21

H_D#34

C24

H_D#35

C23

H_D#36

D22

H_D#37

C25

H_D#38

E24

H_D#39

D24

H_D#40

G20

H_D#41

E23

H_D#42

B22

H_D#43

B23

H_D#44

F23

H_D#45

F21

H_D#46

C20

H_D#47

C21

H_D#48

G18

H_D#49

E19

H_D#50

E20

H_D#51

G17

H_D#52

D20

H_D#53

F19

H_D#54

C19

H_D#55

C17

H_D#56

F17

H_D#57

B19

H_D#58

G16

H_D#59

E16

H_D#60

C16

H_D#61

E17

H_D#62

D16

H_D#63

C18

L28
M25
N24
M28
N28
N27
P27
M23
N25
P28
M26
N23
P26
M27

H_ADS# <4>
H_TRDY# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>

H_D#[0..63] <4>

HOST REF VOLTAGE

+VCCP

R137

1 2

R136
150_0603_1%

1 2

+VCCP

1 2

R427
100_0603_1%

1 2

301_0603_1%

HXSWING

R425

49.9_0603_1%

HAVREF

W=10mil W=10mil

2

C108

0.1U_0402_16V4Z

1

W=10mil

2

C516

0.1U_0402_16V4Z

1

HUB I/F REF VOLTAGE

+1.5VS

R171

80.6_0603_1%

1 2

HUB_VSWI NG

2

0.1U_0402_16V4Z

1 2

0.1U_0402_16V4Z

1 2

C145

1

HUB_VREF

2

C169

1

R172

51.1_0603_1%

R180

40.2_0603_1%

100_0603_1%

W=20mil

2

C146

0.01U_0402_16V7K

1

W=20mil

2

C170

0.01U_0402_16V7K

1

+VCCP

R138
301_0603_1%

1 2

HYSWING

R139

150_0603_1%

1 2

+VCCP

R417

49.9_0603_1%

1 2

R416

1 2

HUB_VSWING

HUB_VREF

2

C106

0.1U_0402_16V4Z

1

HDVREF

2

C494

1

1U_0603_10V4Z

(0.796V)

(0.35V)

W=20mil

2

C490

0.1U_0402_16V4Z

1

(0.7V)(0.7V)

+VCCP

R161

49.9_0603_1%

1 2

HCCVREF

R162

100_0603_1%

1 2

2

C119

1

1U_0603_10V4Z

W=10mil

(0.7V)(0.35V) (0.35V)

2

C122

0.1U_0402_16V4Z

1

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

3

2

INTEL 855GME-HOST(1/4)

Size Document Number Re v

Date: Sheet

EAL20 LA-2462

of

647Friday, Se ptember 17, 2004

1

0.1

5

DVOC_D[0..11]<13,19>
DVOB_D[0 ..11]<13>
AGP_SBA[0..7]<13>

D D

C C

B B

CLK_MCH_66M

R469

33_0402_5%

C565

22P_0402_50V8J

R451 100K_0402_5%

1 2

R434 100K_0402_5%

1 2

R445 100K_0402_5%

+1.5VS

R437 100K_0402_5%

AGP_BUSY#<13,23>

R419

10K_0603_5%

UMA@

Q35

BSN20_SOT23

RTCCLK<23>

2

G

UMA@

reserved for DVO mode

I2C BUS PULL UP DVO/AGP REF Voltage

MDVICLK
MDDCCLK
MDVIDATA
MDDCDATA

2.2K_1206_8P4R_5%

MI2CCLK

A A

MI2CDATA

DVOC_D[0..11]
DVOB_D[0 . .11]
AGP_SBA[0..7]

12

@

1

@

2

AGP_AD14

12

AGP_AD31
DVOBC_CLKINT

AGP_AD30

12

R422 0_0402_5%UMA@

1 2

DVOBC_CLKINT<13,19>

DVOC_CLK#<13,19>
DVOC_HSYNC<13,19>
DVOC_ VSYNC<13,19>

AGPBUSY#

reserved for DVO mode

+1.5VS

1 2

R432

12
12

R426 1K_0402_5%

W=10mil

AGP_REQ#<13>

1 2

AGP_WBF#<13>
AGP_RBF#<13>

+1.5VS

1 2
13

D

S

40.2_0603_1%

RP50

1 8
2 7
3 6
4 5

R429 2.2K_0402_5%
R441 2.2K_0402_5%

5

AGP_ADSTB0<13>
AGP_ADSTB0#<13>
AGP_AD0<13>
AGP_AD1<13>
AGP_CBE#1<13>
AGP_AD14<13>

AGP_AD30<13>

DVOC_CLK<13,19>

AGP_AD18<13>
AGP_AD31<13>

MI2CCLK<13,19>
MI2CDATA<13,19>
MDVICLK<13>
MDVIDATA<13>
MDDCCLK<13>
MDDCDATA<13>

CLK_MCH_66M<12>

AGP_SBSTB<13>
AGP_SBSTB#<13>
AGP_GNT#<13>

AGP_ST2<13>
AGP_ST1<13>
AGP_ST0<13>

AGP_CBE#2<13>

AGP_PAR<13>

+AGP_VREF

+1.5VS

1 2

R442

1K_0603_1%

1 2

DVOB_D0
DVOB_D1
DVOB_D2
DVOB_D3
DVOB_D4
DVOB_D5
DVOB_D6
DVOB_D7
DVOB_D8
DVOB_D9
DVOB_D10
DVOB_D11

AGP_ADSTB0
AGP_ADSTB0#
AGP_AD0
AGP_AD1
AGP_C BE#1
AGP_AD14

AGP_AD30
DVOBC_CLKINT

DVOC_CLK
DVOC_CLK#
DVOC_HSYNC
DVOC_ VSYNC
AGP_AD18
AGP_AD31

MI2CCLK
MI2CDATA
MDVICLK
MDVIDATA
MDDCCLK
MDDCDATA

DVOC_D0
DVOC_D1
DVOC_D2
DVOC_D3
DVOC_D4
DVOC_D5
DVOC_D6
DVOC_D7
DVOC_D8
DVOC_D9
DVOC_D10
DVOC_D11

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_PAR
+AGP_VREF

AGPBUSY#
DVORCOMP
CLK_ MCH_66 M

AGP_SBSTB
AGP_SBSTB#
AGP_GNT#
AGP_REQ#
AGP_ST2
AGP_ST1
AGP_ST0
AGP_WBF#
AGP_RBF#

AGP_C BE#2

R439
1K_0603_1%

+AGP_VREF

2

1

C533

0.1U_0402_16V4Z

4

U14B

Montara-GM(L)

R3

DVOBD0/(NC)

R5

DVOBD1/(NC)

R6

DVOBD2/(NC)

R4

DVOBD3/(NC)

P6

DVOBD4/(NC)

P5

DVOBD5/(NC)

N5

DVOBD6/(NC)

P2

DVOBD7/(NC)

N2

DVOBD8/(NC)

N3

DVOBD9/(NC)

M1

DVOBD10/(NC)

M5

DVOBD11/(NC)

P3

DVOBCLK/(NC)

P4

DVOBCLK#/(NC)

T6

DVOBHSYNC/(NC)

T5

DVOBVSYNC/(NC)

L2

DVOBBLANK#/(NC)

M2

DVOBFLDSTL/(NC)

G2

DVOBCINTR#

M3

DVOBCCLKINT

J3

DVOCCLK

J2

DVOCCLK#

K6

DVOCHSYNC

L5

DVOCVSYNC

L3

DVOCBLANK#

H5

DVOCFLDSTL

K7

MI2CCLK

N6

MI2CDATA

N7

MDVICLK

M6

MDVIDATA

P7

MDDCCLK

T7

MDDCDATA

K5

DVOCD0

K1

DVOCD1

K3

DVOCD2

K2

DVOCD3

J6

DVOCD4

J5

DVOCD5

H2

DVOCD6

H1

DVOCD7

H3

DVOCD8

H4

DVOCD9

H6

DVOCD10

G3

DVOCD11

E5

ADDID0

F5

ADDID1

E3

ADDID2

E2

ADDID3

G5

ADDID4

F4

ADDID5

G6

ADDID6

F6

ADDID7

L7

DVODETECT

D5

DPMS

F1

GVREF

F7

AGPBUSY#

D1

DVORCOMP

Y3

GCLKIN

AA5

RVSD0

F2

RVSD1

F3

RVSD2

B2

RVSD3

B3

RVSD4

C2

RVSD5

C3

GST[1]

C4

GST[0]

D2

RVSD8

D3

RVSD9

D7

RVSD10

L4

RVSD11

RG82855GME_uFCBGA732

+AGP_VREF

4

DVO

BLUE

BLUE#

GREEN

GREEN#

RED#
HSYNC
VSYNC

REFSET

DDCACLK

DAC

DDCADATA

IYAM0
IYAM1
IYAM2
IYAM3
IYAP0
IYAP1
IYAP2
IYAP3
IYBM0
IYBM1
IYBM2
IYBM3
IYBP0
IYBP1
IYBP2
IYBP3

ICLKAM

ICLKAP

ICLKBM

ICLKBP

DDCPCLK

DDCPDATA

LVDS

PANELBKLTCTL

PANELBKLTEN

PANELVDDEN

LVREFH
LVREFL

LVBG

DREFCLK

DREFSSCLK

LCLKCTLA
LCLKCTLB

CLKS

DPWR#/(NC)

DPSLP#

RSTIN#

PWROK

MISCNC

EXTTS0

MCHDETECTVSS

NC10

NC11

RED

LIBG

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

C9
D9
C8
D8
A7
A8
H10
J9
E8
B6
G9

G14
E15
C15
C13
F14
E14
C14
B13
H12
E12
C12
G11
G12
E11
C11
G10
D14
E13
E10
F10

GMCH_LCD_CLK

B4

GMCH_LCD_DATA

C5
G8

F8
A5

D12
F12

B12

LIBG

A10

CLK_MCH_48M

B7

CLK_SSC_66M

B17
H9

LCLKCTLB

C6

AA22
Y23

PCIRST#

AD28
J11

EXTTS

D6
AJ1

B1
AH1
A2
AJ2
A28
AJ28
A29
B29
AH29
AJ29
AA9
AJ4

3

GMCH_CRT_B <21>
GMCH_CRT_G <21>
GMCH_CRT_R <21>
GMCH_CRT_HSYNC <21>

REFSET

GMCH_CRT_VSYN C <21>
GMCH_CRT_CLK <21>

GMCH_CRT_DATA <21>

GMCH_TXOUT0- <20>
GMCH_TXOUT1- <20>
GMCH_TXOUT2- <20>

GMCH_TXOUT0+ <20>
GMCH_TXOUT1+ <20>
GMCH_TXOUT2+ <20>

GMCH_TZOUT0- <20>
GMCH_TZOUT1- <20>
GMCH_TZOUT2- <20>

GMCH_TZOUT0+ <20>
GMCH_TZOUT1+ <20>
GMCH_TZOUT2+ <20>

GMCH_TXCLK- <20>
GMCH_TXCLK+ <20>
GMCH_TZCLK- <20>
GMCH_TZCLK+ <20>

GMCH_LCD_CLK <20>
GMCH_LCD_DATA <20>

GMCH_ENVDD <20>

R409 1.5K_0603_1%

12

CLK_MCH_48M <12>
CLK_SSC_66M <12>

R420
127_0603_1%

1 2

1 2

C507 22P_0402_50V8J

GMCH_ENBKL <34>

+3VS

R421
510_0402_5%

@

1 2

33_0402_5% @

22P_0402_50V8J

R418

C491

@

2

CLK_SSC_66MCLK_MCH_48M

R142

@

33_0402_5%

1 2

2

1

C107

22P_0402_50V8J

unpoped for 1.05V FSB

LCLKCTLB: High for P4, NC for Banias

H_DPWR# <4>
H_DPSLP# <4,22>
PCIRST# <13,19,22,25,27,28,30>

VGATE <12,23,45>

1 2

R423 10K_0402_5%

Isolating AGP singals
(For M11P)

PCIRST#
AGP_ST0
GST0 AGP_ST1

AGP_ST2
GST2 AGP_PAR

+3VS

GST0
GST1
GST2

GPAR

*

U39

M11@

1

OE1#

VCC

2

1A

OE4#

3

1B

4A

4

OE2#

4B

5

2A

OE3#

6

2B

3A

GND73B

FST3125MTCX_SSOP14

1 2

R414 1K_0402_5%M11@

1 2

R406 1K_0402_5%M11@

1 2

R415 1K_0402_5%M11@

1 2

R407 1K_0402_5%M11@

12

R401 1K_0402_5%@

Starp Pin:

+5VS

14

PCIRST#

13
12

GST1

11
10
9

GPAR

8

+1.5VS

(For UMA)

DVODETECT(AGP_PAR):
HIGH for AGP, LOW for DVO

Starp pin list

ST2 ST1 ST0

00

0

0011

0
0

1

11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

3

PSB/Mem/GFX
400 / 266 / 200
400 / 200 / 200
400 / 200 / 133

400 / 333 / 250 *

2

1 2
2

@

1

*

AGP_ST0

R413 1K_0402_5%

*

AGP_ST1

R405 1K_0402_5%

*

AGP_ST2

R430 1K_0402_5%UMA@

*

R412 1K_0402_5%@

AGP_PAR

R411 1K_0402_5%UMA@

1

855GME DVO/AGP Pin Muxing

Ball DVO Mode AGP Mode

R3

DVOBD0

R5

DVOBD1

R6

DVOBD2

R4

DVOBD3

P6

DVOBD4

P5

DVOBD5

N5

DVOBD6

P2

DVOBD7

N2

DVOBD8

N3

DVOBD9

M1

DVOBD10

M5

DVOBD11

P3

DVOBCLK

P4

DVOBCLK#

T6

DVOBHSYNC

T5

DVOBVSYNC

L2

DVOBBLANK

M2

DVOBFLDSTL

G2

DVOBCINTR#

M3

DVOBCCLKINT

J3

DVOCCLK

J2

DVOCCLK#

K6

DVOCHSYNC

L5

DVOCVSYNC

L3

DVOCBLANK

H5

DVOCFLDSTL

K7

MI2CCLK

N6

MI2CDATA

N7

MDVICLK

M6

MDVIDATA

P7

MDDCCLK

T7

MDDCDATA

K5

DVOCD0

K1

DVOCD1

K3

DVOCD2

K2

DVOCD3

J6

DVOCD4

J5

DVOCD5

H2

DVOCD6

H1

DVOCD7

H3

DVOCD8

H4

DVOCD9

H6

DVOCD10

G3

DVOCD11

E5

ADDID0

F5

ADDID1

E3

ADDID2

E2

ADDID3

G5

ADDID4

F4

ADDID5

G6

ADDID6

F6

ADDID7

L7

DVODETECT

D5

DPMS

F2

RVSD1

F3

RVSD2

B2

RVSD3

B3

RVSD4

C2

RVSD5

C3

GST1

C4

GST0

D2

RVSD8

D3

RVSD9

L4

RVSD11

1 2

UMA@

1 2

UMA@
1 2
1 2
1 2

Title

Size Document Number Re v

Date: Sheet

+1.5VS

Compal Electronics, Inc.

INT EL 855GME-AGP&LVDS(2/4)

EAL20 LA-2462

GAD3
GAD2
GAD5
GAD4
GAD7
GAD6
GAD8
GCBE#0
GAD10
GAD9
GAD12
GAD11
GADSTB0
GADSTB0#
GAD0
GAD1
GCBE#1
GAD14
GAD30
GAD13
GADSTB1
GADSTB1#
GAD17
GAD16
GAD18
GAD31
GIRDY#
GDEVSEL#
GTRDY#
GFRAME#
GSTOP#
GAD15
GAD19
GAD20
GAD21
GAD22
GAD23
GCBE#3
GAD25
GAD24
GAD27
GAD26
GAD29
GAD28
GSBA0
GSBA1
GSBA2
GSBA3
GSBA4
GSBA5
GSBA6
GSBA7
GPAR
GPIPE#
GSBSTB
GSBSTB#
GGNT#
GREQ#
GST2
GST1
GST0
GWBF#
GRBF#
GCBE#2

1

747Friday, Se ptember 17, 2004

0.1

of

5

DDR_SMA0<10,11>

D D

C C

DDR REF & SWING VOLTAGE

+2.5V

12

2

C577

0.1U_0402_16V4Z

R175

150_0603_1%

1

60.4_0603_1%

+2.5V

12

12

B B

12

R478

R174
604_0603_1%

2

1

0.1U_0402_16V4Z

R482

60.4_0603_1%

SMRCOMP

W=10mil

SMVSWINGL

C154

W=10mil

(1.25V)

(0.497V)

DDR_SMA1<10,11>
DDR_SMA2<10,11>
DDR_SMA3<10,11>
DDR_SMA4<10,11>
DDR_SMA5<10,11>

DDR_SWE#<10,11>
DDR_SRAS#<10,11>
DDR_SCAS#<10,11>

DDR_CLK0<10>
DDR_CLK0#<10>
DDR_CLK1<10>
DDR_CLK1#<10>

DDR_CLK3<10>
DDR_CLK3#<10>
DDR_CLK4<10>
DDR_CLK4#<10>

DDR_CKE0<10,11>
DDR_CKE1<10,11>
DDR_CKE2<10,11>
DDR_CKE3<10,11>
DDR_SCS#0<10,11>
DDR_SCS#1<10,11>
DDR_SCS#2<10,11>
DDR_SCS#3<10,11>

DDR_SBS0<10,11>
DDR_SBS1<10,11>

DDR_SMA_B1<10,11>
DDR_SMA_B2<10,11>
DDR_SMA_B4<10,11>
DDR_SMA_B5<10,11>

DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7

DDR_SW E#
DDR_SRAS#
DDR_SCAS#

DDR_SBS0
DDR_SBS1

DDR_SDM0
DDR_SDM1
DDR_SDM2
DDR_SDM3
DDR_SDM4
DDR_SDM5
DDR_SDM6
DDR_SDM7

DDR_SMA_B1
DDR_SMA_B2
DDR_SMA_B4
DDR_SMA_B5

SMRCOMP
SMVSWINGL

SMVSWINGH

4

DDR_SDQ[0..63]
DDR_SDQS[0..7]

AC18
AD14
AD13
AD17
AD11
AC13

AD8
AD7
AC6
AC5

AC19

AD5

AB5

AG2
AH5

AH8
AE12
AH17
AE21
AH24
AH27
AD15

AD25
AC21
AC24

AB2

AA2
AC26
AB25

AC3
AD4
AC2

AD2
AB23
AB24

AA3
AB4

AC7

AB7

AC9
AC10
AD23
AD26
AC22
AC25

AD22
AD20

AE5
AE6

AE9
AH12
AD19
AD21
AD24
AH28
AH15

AD16
AC12
AF11
AD10

AC15
AC16

AB1
AJ22

AJ19

DDR_SDQ[0..63] <10> DDR_SMA[6..12] <10,11>
DDR_SDQS[0..7] <10>

U14C

Montara-GM(L)

SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8
SMA9
SMA10
SMA11
SMA12

SDQS0

MEMORY

SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

SWE#
SRAS#
SCAS#

SCK0
SCK0#
SCK1
SCK1#
SCK2
SCK2#
SCK3
SCK3#
SCK4
SCK4#
SCK5
SCK5#

SCKE0
SCKE1
SCKE2
SCKE3
SCS#0
SCS#1
SCS#2
SCS#3

SBA0
SBA1

SDM0
SDM1
SDM2
SDM3
SDM4
SDM5
SDM6
SDM7
SDM8

SMA_B1
SMA_B2
SMA_B4
SMA_B5

RCVENOUT#
RCVENIN#

SMRCOMP
SMVSWINGL

SMVSWINGH

RG82855GME_uFCBGA732

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8

SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63

SDQ64
SDQ65
SDQ66
SDQ67
SDQ68
SDQ69
SDQ70
SDQ71

SMVREF0

DDR_SMA[6..12]
DDR_SDM[0..7]

DDR_SDQ0

AF2

DDR_SDQ1

AE3

DDR_SDQ2

AF4

DDR_SDQ3

AH2

DDR_SDQ4

AD3

DDR_SDQ5

AE2

DDR_SDQ6

AG4

DDR_SDQ7

AH3

DDR_SDQ8

AD6

DDR_SDQ9

AG5

DDR_SDQ10

AG7

DDR_SDQ11

AE8

DDR_SDQ12

AF5

DDR_SDQ13

AH4

DDR_SDQ14

AF7

DDR_SDQ15

AH6

DDR_SDQ16

AF8

DDR_SDQ17

AG8

DDR_SDQ18

AH9

DDR_SDQ19

AG10

DDR_SDQ20

AH7

DDR_SDQ21

AD9

DDR_SDQ22

AF10

DDR_SDQ23

AE11

DDR_SDQ24

AH10

DDR_SDQ25

AH11

DDR_SDQ26

AG13

DDR_SDQ27

AF14

DDR_SDQ28

AG11

DDR_SDQ29

AD12

DDR_SDQ30

AF13

DDR_SDQ31

AH13

DDR_SDQ32

AH16

DDR_SDQ33

AG17

DDR_SDQ34

AF19

DDR_SDQ35

AE20

DDR_SDQ36

AD18

DDR_SDQ37

AE18

DDR_SDQ38

AH18

DDR_SDQ39

AG19

DDR_SDQ40

AH20

DDR_SDQ41

AG20

DDR_SDQ42

AF22

DDR_SDQ43

AH22

DDR_SDQ44

AF20

DDR_SDQ45

AH19

DDR_SDQ46

AH21

DDR_SDQ47

AG22

DDR_SDQ48

AE23

DDR_SDQ49

AH23

DDR_SDQ50

AE24

DDR_SDQ51

AH25

DDR_SDQ52

AG23

DDR_SDQ53

AF23

DDR_SDQ54

AF25

DDR_SDQ55

AG25

DDR_SDQ56

AH26

DDR_SDQ57

AE26

DDR_SDQ58

AG28

DDR_SDQ59

AF28

DDR_SDQ60

AG26

DDR_SDQ61

AF26

DDR_SDQ62

AE27

DDR_SDQ63

AD27

AG14
AE14
AE17
AG16
AH14
AE15
AF16
AF17

AJ24

2

C148

0.1U_0402_16V4Z

1

3

SMVREF0

W=20mil

DDR_SDM[0..7] <10>

2

C142

0.1U_0402_16V4Z

1

2

C149

0.1U_0402_16V4Z

1

+2.5V

12

12

R166
75_0603_1%

R168
75_0603_1%

2

U14D

C1

VSS0

G1

VSS1

L1

VSS2

U1

VSS3

AA1

VSS4

AE1

VSS5

R2

VSS6

AG3

VSS7

AJ3

VSS8

D4

VSS9

G4

VSS10

K4

VSS11

N4

VSS12

T4

VSS13

W4

VSS14

AA4

VSS15

AC4

VSS16

AE4

VSS17

B5

VSS18

U5

VSS19

Y5

VSS20

Y6

VSS21

AG6

VSS22

C7

VSS23

E7

VSS24

G7

VSS25

J7

VSS26

M7

VSS27

R7

VSS28

AA7

VSS29

AE7

VSS30

AJ7

VSS31

H8

VSS32

K8

VSS33

P8

VSS34

T8

VSS35

V8

VSS36

Y8

VSS37

AC8

VSS38

E9

VSS39

L9

VSS40

N9

VSS41

R9

VSS42

U9

VSS43

W9

VSS44

AB9

VSS45

AG9

VSS46

C10

VSS47

J10

VSS48

AA10

VSS49

AE10

VSS50

D11

VSS51

F11

VSS52

H11

VSS53

AB11

VSS54

AC11

VSS55

AJ11

VSS56

J12

VSS57

AA12

VSS58

AG12

VSS59

A13

VSS60

D13

VSS61

F13

VSS62

H13

VSS63

N13

VSS64

R13

VSS65

U13

VSS66

AB13

VSS67

AE13

VSS68

J14

VSS69

P14

VSS70

T14

VSS71

AA14

VSS72

AC14

VSS73

D15

VSS74

H15

VSS75

N15

VSS76

R15

VSS77

U15

VSS78

AB15

VSS79

AG15

VSS80

F16

VSS81

J16

VSS82

P16

VSS83

T16

VSS84

AA16

VSS85

AE16

VSS86

A17

RG82855GME_uFCBGA732

VSS87

D17

VSS88

H17

VSS89

N17

VSS90

1

R17

VSS91

U17

VSS92

AB17

VSS93

AC17

VSS94

F18

VSS95

J18

VSS96

AA18

VSS97

AG18

VSS98

A19

VSS99

D19

VSS100

H19

VSS101

AB19

VSS102

AE19

VSS103

F20

VSS105

J20

VSS106

AA20

VSS107

AC20

VSS108

A21

VSS109

D21

VSS110

H21

VSS111

M21

VSS112

P21

VSS113

T21

VSS114

V21

VSS115

Y21

VSS116

AA21

VSS117

AB21

VSS118

AG21

VSS119

B24

VSS120

F22

VSS121

J22

VSS122

L22

VSS123

N22

VSS124

R22

VSS125

U22

VSS126

W22

VSS127

AE22

VSS128

A23

VSS129

D23

VSS130

AA23

VSS131

AC23

VSS132

AJ23

VSS133

F24

VSS134

H24

VSS135

K24

VSS136

M24

VSS137

P24

VSS138

T24

VSS139

V24

VSS140

AA24

VSS141

AG24

VSS142

A25

VSS143

D25

VSS144

AA25

VSS145

AE25

VSS146

G26

VSS147

J26

VSS148

L26

VSS149

N26

VSS150

R26

VSS151

U26

VSS152

W26

VSS153

AB26

VSS154

A27

VSS155

F27

VSS156

AC27

VSS157

AG27

VSS158

AJ27

VSS159

AC28

VSS160

AE28

VSS161

C29

VSS162

E29

VSS163

G29

VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181

J29
L29
N29
U29
W29
AA29
AJ10
AJ12
AJ18
AJ20
C22
D28
E28
L6
T9
AJ26

Montara-GM(L)

+2.5V

A A

12

12

R185
604_0603_1%

R181
150_0603_1%

W=10mil

SMVSWINGH

2

C171

0.1U_0402_16V4Z

1

5

(2.002V)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

3

2

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

INTEL 855GME DDR(3/4)

EAL20 LA-2462

1

0.1

of

847Friday, Se ptember 17, 2004

5

+1.35VS

D D

+1.35VS

+1.35VS_PLLA

+1.35VS_PLLB

+1.5VS

C C

+1.5VS

+1.5VS

+1.5VS

+2.5V

B B

+3VS

U14E

Montara-GM(L)

J15

VCC0

P13

VCC1

T13

VCC2

N14

VCC3

R14

VCC4

U14

VCC5

P15

VCC6

T15

VCC7

AA15

VCC8

N16

VCC9

R16

VCC10

U16

VCC11

P17

VCC12

T17

VCC13

AA17

VCC14

AA19

VCC15

W21

VCC16

H14

VCC17

V1

VCCHL0

Y1

VCCHL1

W5

VCCHL2

U6

VCCHL3

U8

VCCHL4

W8

VCCHL5

V7

VCCHL6

V9

VCCHL7

D29

VCCAHPLL

Y2

VCCAGPLL

A6

VCCADPLLA

B16

VCCADPLLB

E1

VCCDVO_0

J1

VCCDVO_1

N1

VCCDVO_2

E4

VCCDVO_3

J4

VCCDVO_4

M4

VCCDVO_5

E6

VCCDVO_6

H7

VCCDVO_7

J8

VCCDVO_8

L8

VCCDVO_9

M8

VCCDVO_10

N8

VCCDVO_11

R8

VCCDVO_12

K9

VCCDVO_13

M9

VCCDVO_14

P9

VCCDVO_15

A9

VCCADAC0

B9

VCCADAC1

B8

VSSADAC

A11

VCCALVDS

B11

VSSALVDS

G13

VCCDLVDS0

B14

VCCDLVDS1

J13

VCCDLVDS2

B15

VCCDLVDS3

F9

VCCTXLVDS0

B10

VCCTXLVDS1

D10

VCCTXLVDS2

A12

VCCTXLVDS3

A3

VCCGPIO_0

A4

VCCGPIO_1

VTTLF0
VTTLF1
VTTLF2
VTTLF3
VTTLF4
VTTLF5
VTTLF6
VTTLF7
VTTLF8

VTTLF9
VTTLF10
VTTLF11
VTTLF12
VTTLF13
VTTLF14
VTTLF15
VTTLF16
VTTLF17
VTTLF18
VTTLF19
VTTLF20

VTTHF0

VTTHF1

VTTHF2

VTTHF3

VTTHF4

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7

POWER

VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36

VCCQSM0
VCCQSM1

VCCASM0
VCCASM1

G15
H16
H18
J19
H20
L21
N21
R21
U21
H22
M22
P22
T22
V22
Y29
K29
F29
AB29
A26
A20
A18

A22
A24
H29
M29
V29

AC1
AG1
AB3
AF3
Y4
AJ5
AA6
AB6
AF6
Y7
AA8
AB8
Y9
AF9
AJ9
AB10
AA11
AB12
AF12
AA13
AJ13
AB14
AF15
AB16
AJ17
AB18
AF18
AB20
AF21
AJ21
AB22
AF24
AJ25
AF27
AC29
AF29
AG29

AJ6
AJ8

AD1
AF1

C103 0. 1U_0402_16V4Z

12

4

+VCCP

C96 0.1U_0402_16V4Z

12

C476 0. 1U_0 402_16V4Z

12

C481 0.1U_0402_16V4Z

12

C489 0. 1 U_0402_16V4Z

12

+2.5V

+2.5V_QSM

+1.35VS_ASM

+1.35VS

1

C569

+

150U_D2_6.3VM

2

+1.35VS

W=20mil (90mA)

1

C526

10U_0805_10V4Z

2

(1.8A)

C539

1

2

10U_0805_10V4Z

2

C547

1

0.1U_0402_16V4Z

For VCC

2

C509

0.1U_0402_16V4Z

1

ForVCCHL

2

C544

0.1U_0402_16V4Z

1

3

2

C496

1

0.1U_0402_16V4Z

2

C564

1

0.1U_0402_16V4Z

2

C527

0.1U_0402_16V4Z

1

2

C92

0.1U_0402_16V4Z

1

2

C538

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

C116

220U_D2_4VM_R12 UMA@

2

C517

1

0.1U_0402_16V4Z

W=20mil (0.4A)

1

+

0.1U_0402_16V4Z UMA@

2

2

1

2

1

2

2

C524

0.1U_0402_16V4Z

1 2

R159 1_0805_5% UMA@

ForVCCADPLLA ForVCCADPLLB

C115

2

C512

C553

1

1

0.1U_0402_16V4Z

+1.35VS +1.35VS+1.35VS_ PL LA +1.35VS_PLLB

C111

220U_D2_4VM_R12

UMA@

Closeto ball D29, Y2

+1.5VS +1.5VS +1.5VS

W=40mil (90mA) W=20mil (70mA) W=20mil (90mA)

1

1

+

C550

22U_1206_16V4Z_V1

2

150U_D2_6.3VM

+1.5VS

W=20mil (70mA)

1

C503

2

10U_0805_10V4Z

2

2

1

0.1U_0402_16V4Z

For VCCDVO

2

C532

C531

1

0.1U_0402_16V4Z

For VCCDLVDS

C529

2

C500

0.1U_0402_16V4Z

1

2

C114

UMA@

0.01U_0402_16V7K

1

0.1U_0402_16V4Z

+2.5V

W=20mil (90mA)

1

C542

0.1U_0402_16V4Z

2

UMA@

UMA@

22U_1206_16V4Z_V1

For VCCADAC

2

C492

1

UMA@

2

C523

1

0.1U_0402_16V4Z

For VCCTXLVDS

2

2

C515

C545

0.1U_0402_16V4Z

UMA@

1

1

C513

0.1U_0402_16V4Z

UMA@

UMA@

reserved for GMCH, no need when use external VGA

+2.5V

(1.9A)

1

+

C189

2

150U_D2_6.3VM

2

C581

C558

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

C573

0.1U_0402_16V4Z

1

2

C546

1

0.1U_0402_16V4Z

2

C566

0.1U_0402_16V4Z

1

2

C562

1

0.1U_0402_16V4Z

2

1

2

C528

C534

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

C508

0.1U_0402_16V4Z

1

2

C563

1

0.1U_0402_16V4Z

W=20mil (0.4A)

1

+

2

2

1

2

C543

0.1U_0402_16V4Z

1

1 2

R143 1_0805_5% UMA@

2

C112

1

0.1U_0402_16V4Z UMA@

For VCCALVDS

2

C551

0.01U_0402_16V7K

1

UMA@

2

2

C510

1

1

0.1U_0402_16V4Z

1

+3VS

RG82855GME_uFCBGA732

1

2

2

C505

1

0.1U_0402_16V4Z

5

C501
10U_0805_10V4Z

A A

(72mA)

1

+

C495

2

150U_D2_6.3VM

2

C499

10U_0805_10V4Z

1

2

C493

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

4

2

C497

1

+2.5V_QSM+VCCP

W=20mil W=20mil

2

C584

4.7U_0805_10V4Z

1

0.1U_0402_16V4Z

1 2

R483 0_0603_5%

For VCCQSM

1

C575

2

R499 1_0603_1%

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

3

+1.35VS_ASM

1

C591

2

10U_0805_10V4Z

1

C582

2

0.1U_0402_16V4Z

10U_0805_10V4Z

For VCCASMFor VCCGPIO

2

1

R506 0_0603_5%

C590

2

1 2

+1.35VS+2.5V

Compal Electronics, Inc.

Title

Size Document Number Re v

Date: Sheet

INTE L 85 5GME G MCH(4/ 4)

EAL20 LA-2462

1

0.1

of

947Friday, Se ptember 17, 2004

5

+2.5V +1.25VS_SDREF

DDR_DQ0
DDR_DQ3

DDR_DQS0
DDR_DQ5

DDR_DQ1

D D

DDR_CLK0<8>
DDR_CLK0#<8>

C C

DDR_CKE1<8 , 11>

DDR_SMA5<8,11>
DDR_SMA1<8,11>

DDR_SCS#0<8,11>

DDR_DQ8
DDR_DQ13

DDR_DQS1
DDR_DQ14

DDR_DQ15

DDR_DQ16
DDR_DQ20

DDR_DQS2
DDR_DQ22

DDR_DQ18
DDR_DQ24

DDR_DQ25
DDR_DQS3

DDR_DQ26
DDR_DQ27

DDR_CKE1

DDR_F_SMA12
DDR_F_SMA9

DDR_F_SMA7
DDR_SMA5
DDR_F_SMA3
DDR_SMA1

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#0

DDR_DQ32
DDR_DQ37

DDR_DQS4
DDR_DQ38

DDR_DQ34

DDR_DQ40

+3VS

DDR_DQS5
DDR_DQ42

DDR_DQ43

DDR_DQ52
DDR_DQ49

DDR_DQS6
DDR_DQ55

DDR_DQ50
DDR_DQ63

DDR_DQ58
DDR_DQS7

DDR_DQ56
DDR_DQ62

DDR_CKE3
DDR_SMA12

DDR_SMA9
DDR_SMA7

DDR_SMA3

DDR_SMA10
DDR_SBS0
DDR_SW E#
DDR_SCS#2

B B

SMB_DATA<12,22>

SMB_CLK<12,22>

DDR_CLK3<8>
DDR_CLK3#<8>

DDR_CKE3<8 , 11>
DDR_SMA12<8,11>

A A

DDR_SMA9<8,11>
DDR_SMA7<8,11>

DDR_SMA_B5<8,11>

DDR_SMA3<8,11>

DDR_SMA_B1<8,11>

DDR_SMA10<8,11>
DDR_SBS0<8,11>
DDR_SWE#<8,11>
DDR_SCS#2<8,11>

DDR_CLK4#<8>

DDR_CLK4<8>

A101
A105

A107
A109
A111

A115
A117
A119
A121

B101
B105
B107
B109
B111
B115
B117
B119
B121
B158
B160

JP24

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

A35

CK0_A

A37

CK0#_A

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

85

DU

87

VSS

A89

CK2_A

A91

CK2#_A

93

VDD

A95

CKE1_A

A97

DU/A13_A

A99

A12_A
A9_A

103

VSS
A7_A
A5_A
A3_A
A1_A

113

VDD
A10/AP_A
BA0_A
WE#_A
S0#_A

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

B35

CK0_B

B37

CK0#_B

B95

CKE1_B

B97

DU(A13)_B

B99

A12_B
A9_B
A7_B
A5_B
A3_B
A1_B
A10/AP_B
BA0_B
WE#_B
S0#_B
CK1#_B
CK1_B

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

DU/RESET#

CKE0_A

DU/BA2

A11_A

A8_A
A6_A

A4_A
A2_A
A0_A

BA1_A
RAS#_A
CAS#_A

S1#_A

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#_A

CK1_A

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

SA0_A

SA1_A

SA2_A

CK2_B

CK2#_B

CKE0_B

A11_B

A8_B
A6_B
A4_B
A2_B
A0_B

BA1_B
RAS#_B
CAS#_B

S1#_B
SA0_B
SA1_B
SA2_B

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD
DM1

VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD
DM3

VSS

VDD

VSS
VSS
VDD
VDD

VSS

VDD

DU

VSS

VDD
DM4

VSS

VDD
DM5

VSS

VDD

VSS

VDD
DM6

VSS

VDD
DM7

VSS

VDD

DU

QUASA_CA0184-218Y61

5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70

86
88
90
92
94
A96
98
A100
A102
104
A106
A108
A110
A112
114
A116
A118
A120
A122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
A158
A160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
A194
A196
A198
200
B89
B91
B96
B100
B102
B106
B108
B110
B112
B116
B118
B120
B122
B194
B196
B198

4

+2.5V

DDR_F_SMA11

DDR_F_SMA8
DDR_F_SMA6

DDR_F_SMA0

DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#

4

DDR_DQ2
DDR_DQ7

DDR_DM0
DDR_DQ4

DDR_DQ6
DDR_DQ9

DDR_DQ12
DDR_DM1

DDR_DQ11
DDR_DQ10

DDR_DQ17
DDR_DQ21

DDR_DM2
DDR_DQ19

DDR_DQ23
DDR_DQ28

DDR_DQ29
DDR_DM3

DDR_DQ30
DDR_DQ31

DDR_CKE0

DDR_SMA4
DDR_SMA2

DDR_SCS#1

DDR_DQ36
DDR_DQ33

DDR_DM4
DDR_DQ39

DDR_DQ35
DDR_DQ41DDR_DQ44

DDR_DQ45
DDR_DM5

DDR_DQ47
DDR_DQ46

DDR_DQ48
DDR_DQ53

DDR_DM6
DDR_DQ54

DDR_DQ51
DDR_DQ59

DDR_DQ57
DDR_DM7

DDR_DQ61
DDR_DQ60

DDR_CKE2
DDR_SMA11
DDR_SMA8
DDR_SMA6

DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3

1 2

+2.5V

75_0603_1%

1

C654

2

0.1U_0402_16V4Z

DDR_CKE0 <8,11>

DDR_SMA4 <8,11>
DDR_SMA2 <8,11>

DDR_SCS#1 <8,11>

DDR_CLK1# <8>
DDR_CLK1 <8>

DDR_CKE2 <8,11>
DDR_SMA11 <8,11>
DDR_SMA8 <8,11>
DDR_SMA6 <8,11>
DDR_SMA_B4 <8,11>
DDR_SMA_B2 <8,11>
DDR_SMA0 <8,11>
DDR_SBS1 <8,11>
DDR_SRAS# <8,11>
DDR_SCAS# <8,11>
DDR_SCS#3 <8,11>

+3VS

R589

0.1U_0402_16V4Z

3

DDR_SDQ62
DDR_SDQ56
DDR_SDQS7
DDR_SDQ58

12

1

R580

C655

75_0603_1%

2

DDR_SDQ63
DDR_SDQ50
DDR_SDQ55
DDR_SDQS6

DDR_SDQ49
DDR_SDQ52
DDR_SDQ43 DDR_DQ43
DDR_SDQ42 DDR_DQ42

DDR_SDQS5 DDR_DQS5
DDR_SDQ40 DDR_DQ40
DDR_SDQ44 DDR_DQ44
DDR_SDQ34 DDR_DQ34

DDR_SDQ38 DDR_DQ38
DDR_SDQS4 DDR_DQS4
DDR_SDQ37 DDR_DQ37
DDR_SDQ32 DDR_DQ32

DDR_SW E# D D R_F_SWE#
DDR_SMA10 DDR_F_SMA10

DDR_SBS0 DDR_F_SBS0

10_0804_8P4R_5%

4 5
3 6
2 7
1 8

RP45
10_0804_8P4R_5%

4 5
3 6
2 7
1 8

RP47
10_0804_8P4R_5%

4 5
3 6
2 7
1 8

RP49
10_0804_8P4R_5%

4 5
3 6
2 7
1 8

RP52
10_0804_8P4R_5%

4 5
3 6
2 7
1 8

RP54

RP16

1 8
2 7
3 6
4 5

DDR_DQ62
DDR_DQ56
DDR_DQS7
DDR_DQ58

DDR_DQ63
DDR_DQ50
DDR_DQ55
DDR_DQS6

DDR_DQ49
DDR_DQ52

DDR_DQ60
DDR_DQ61

DDR_DM7

DDR_DQ57 DDR_SDQ57

10_0804_8P4R_5%

10_0804_8P4R_5%

DDR_DQ53
DDR_DQ48
DDR_DQ46
DDR_DQ47

10_0804_8P4R_5%

DDR_DM5
DDR_DQ45
DDR_DQ41
DDR_DQ35

10_0804_8P4R_5%

DDR_DQ39

DDR_DM4
DDR_DQ33
DDR_DQ36

10_0804_8P4R_5%

DDR_SBS1 DDR_F_SBS1

DDR_SMA0 DDR_F_SMA0

10_0804_8P4R_5%

3

RP19

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

10_0804_8P4R_5%

4 5
3 6
2 7

DDR_DQ25

1 8

RP58

10_0804_8P4R_5%

DDR_DQ24

4 5

DDR_DQ18

3 6

DDR_DQ22

2 7
1 8

RP60

1 2

R537 10_0402_5%

1 2

R545 10_0402_5%
R559 10_0402_5%
R565 10_0402_5%

1 2
1 2

10_0804_8P4R_5%

4 5
3 6
2 7
1 8

RP62

10_0804_8P4R_5%

4 5
3 6
2 7
1 8

RP64

DDR_DQ15DDR_SDQ15
DDR_DQ14DDR_SDQ14

DDR_SDQ[0..63]

DDR_SDM[0..7]

DDR_SDQS[0..7]

DDR_SMA6
DDR_SMA8

DDR_SMA11 DDR_F_SMA11

DDR_DQ31
DDR_DQ30

DDR_DM3

DDR_DQ29

10_0804_8P4R_5%

DDR_DQ28
DDR_DQ23
DDR_DQ19

DDR_DM2

10_0804_8P4R_5%

DDR_DQ21
DDR_DQ17
DDR_DQ10
DDR_DQ11

DDR_DQ9

10_0804_8P4R_5%

DDR_DQ4
DDR_DM0
DDR_DQ7
DDR_DQ2

10_0804_8P4R_5%

DDR_DQ[0..63]

DDR_DM[0..7]

DDR_DQS[0..7]

DDR_SMA3 DDR_F_SMA3
DDR_SMA7 DDR_F_SMA7
DDR_SMA9 DDR_F_SMA9
DDR_SMA12 DDR_F_SMA12

DDR_SDQ27 DDR_DQ27
DDR_SDQ26 DDR_DQ26
DDR_SDQS3 DDR_DQS3
DDR_SDQ25

DDR_SDQ24
DDR_SDQ18
DDR_SDQ22
DDR_SDQS2 DDR_DQS2

DDR_SDQ20 DDR_DQ20
DDR_SDQ16 DDR_DQ16

DDR_SDQS1 DDR_DQS1
DDR_SDQ13 DDR_DQ13
DDR_SDQ8 DD R_DQ8
DDR_SDQ1 DD R_DQ1

DDR_SDQ5 DD R_DQ5
DDR_SDQS0 DDR_DQS0
DDR_SDQ3 DD R_DQ3
DDR_SDQ0 DD R_DQ0

DDR_SDQ[0..63]<8>

DDR_SDM[0..7]<8>

DDR_SDQS[0..7]<8>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

2

RP44

18
27
36
45

RP46

18
27
36
45

RP48

18
27
36
45

RP51

18
27
36
45

RP53

18
27
36
45

RP55

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP56

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP57

18
27
36
45

RP59

18
27
36
45

12

R53610_0402_5%

12

R54210_0402_5%

12

R55810_0402_5%

12

R56410_0402_5%

RP61

18
27
36
45

RP63

18
27
36
45

DDR_DQ[0..63] <11>
DDR_DM[0..7] <11>
DDR_DQS[0..7] <11>

2

DDR_SDQ60
DDR_SDQ61

DDR_SDM7

DDR_SDQ59DDR_DQ59
DDR_SDQ51DDR_DQ51
DDR_SDQ54DDR_DQ54

DDR_SDM6DDR_DM6

DDR_SDQ53
DDR_SDQ48
DDR_SDQ46
DDR_SDQ47

DDR_SDM5
DDR_SDQ45
DDR_SDQ41
DDR_SDQ35

DDR_SDQ39

DDR_SDM4
DDR_SDQ33
DDR_SDQ36

DDR_F_SCAS#D DR_SCAS#
DDR_F_SRAS#D DR_SRAS#

DDR_F_SMA6

DDR_F_SMA8

DDR_SDQ31
DDR_SDQ30
DDR_SDM3
DDR_SDQ29

DDR_SDQ28
DDR_SDQ23
DDR_SDQ19

DDR_SDM2

DDR_SDQ21
DDR_SDQ17
DDR_SDQ10
DDR_SDQ11

DDR_SDM1DDR_DM1
DDR_SDQ12DDR_DQ12

DDR_SDQ9

DDR_SDQ6DDR_DQ6

DDR_SDQ4

DDR_SDM0

DDR_SDQ7

DDR_SDQ2

1

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM

EAL20 LA-2462

1

of

10 47Friday, Se ptember 17, 2004

0.1

A

Layo u t note :

Distri bu t e a s close as possible
to DDR-SODIMM.

+2.5V

1 1

1

C608

0.1U_0402_16V4Z

2

+2.5V

1

C593

0.1U_0402_16V4Z

2

1

C633

0.1U_0402_16V4Z

2

1

C556

0.1U_0402_16V4Z

2

1

C634

0.1U_0402_16V4Z

2

1

C594

0.1U_0402_16V4Z

2

1

C570

0.1U_0402_16V4Z

2

1

C607

0.1U_0402_16V4Z

2

1

2

Layo u t note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2

3 3

4 4

+1.25VS

1

C185

0.1U_0402_16V4Z

2

+1.25VS

1

C131

0.1U_0402_16V4Z

2

+1.25VS

1

C213

0.1U_0402_16V4Z

2

+1.25VS

1

C186

0.1U_0402_16V4Z

2

+1.25VS

1

C150

0.1U_0402_16V4Z

2

+1.25VS

1

C227

0.1U_0402_16V4Z

2

1

C202

0.1U_0402_16V4Z

2

1

C157

0.1U_0402_16V4Z

2

1

C133

0.1U_0402_16V4Z

2

1

C219

0.1U_0402_16V4Z

2

1

C207

0.1U_0402_16V4Z

2

1

C230

0.1U_0402_16V4Z

2

A

1

C144

0.1U_0402_16V4Z

2

1

C182

0.1U_0402_16V4Z

2

1

C198

0.1U_0402_16V4Z

2

1

C143

0.1U_0402_16V4Z

2

1

C178

0.1U_0402_16V4Z

2

1

C224

0.1U_0402_16V4Z

2

1

C141

0.1U_0402_16V4Z

2

1

C128

0.1U_0402_16V4Z

2

1

C173

0.1U_0402_16V4Z

2

1

C137

0.1U_0402_16V4Z

2

1

C159

0.1U_0402_16V4Z

2

1

C228

0.1U_0402_16V4Z

2

1

2

1

2

1

2

1

2

1

2

C519

0.1U_0402_16V4Z

+2.5V

1

+

C118
150U_D2_6.3VM

2

C136

0.1U_0402_16V4Z

C203

0.1U_0402_16V4Z

C223

0.1U_0402_16V4Z

C165

0.1U_0402_16V4Z

C123

0.1U_0402_16V4Z

B

1

C502

0.1U_0402_16V4Z

2

+

1

C200

0.1U_0402_16V4Z

2

1

C201

0.1U_0402_16V4Z

2

1

C127

0.1U_0402_16V4Z

2

1

C120

0.1U_0402_16V4Z

2

1

C124

0.1U_0402_16V4Z

2

B

1

C215
150U_D2_6.3VM

2

1

C557

0.1U_0402_16V4Z

2

1

C199

0.1U_0402_16V4Z

2

1

C208

0.1U_0402_16V4Z

2

1

C155

0.1U_0402_16V4Z

2

1

C166

0.1U_0402_16V4Z

2

1

C121

0.1U_0402_16V4Z

2

1

C574

0.1U_0402_16V4Z

2

1

C175

0.1U_0402_16V4Z

2

1

C220

0.1U_0402_16V4Z

2

1

C140

0.1U_0402_16V4Z

2

1

C225

0.1U_0402_16V4Z

2

1

C134

0.1U_0402_16V4Z

2

C

DDR_DQ62
DDR_DQ56
DDR_DQS7
DDR_DQ58

DDR_DQ63
DDR_DQ50

1

C572

0.1U_0402_16V4Z

2

DDR_SCS#2<8,10>

DDR_SWE#<8,10>

DDR_SBS0<8,10>

DDR_SMA_B1<8,10>

DDR_SMA3<8,10>

DDR_SMA_B5<8,10>

DDR_CKE3<8,10>

DDR_CKE1<8,10>
DDR_SMA5<8,10>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODYOF THE CO MPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONIC S, INC .

C

DDR_DQS6

DDR_DQ49
DDR_DQ52
DDR_DQ43
DDR_DQ42

DDR_DQS5
DDR_DQ40
DDR_DQ44
DDR_DQ34

DDR_DQ38
DDR_DQS4
DDR_DQ37
DDR_DQ32

DDR_SCS#2

DDR_SWE#

DDR_SMA10

DDR_SBS0

DDR_SMA_B1

DDR_SMA3

DDR_SMA_B5

DDR_SMA7
DDR_SMA9

DDR_SMA12
DDR_CKE3
DDR_CKE1
DDR_SMA5

DDR_DQ27 DDR_DQ31

DDR_DQ26

DDR_DQS3

DDR_DQ25

DDR_DQ24

DDR_DQ18

DDR_DQ22

DDR_DQS2

DDR_DQ20

DDR_DQ16

DDR_DQ15

DDR_DQ14

DDR_DQS1

DDR_DQ13

DDR_DQ8

DDR_DQ1

DDR_DQ5

DDR_DQS0

DDR_DQ3

DDR_DQ0

RP5

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

RP7

1 8
2 7
3 6
4 5

56_0804_8P4R_5%
RP9

1 8
2 7
3 6
4 5

56_0804_8P4R_5%
RP11

1 8
2 7
3 6
4 5

56_0804_8P4R_5%
RP13

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 2

R173 56_0402_5%

RP15

56_0804_8P4R_5%

RP18

56_0804_8P4R_5%

RP21

56_0804_8P4R_5%

RP24

1 8
2 7
3 6
4 5

56_0804_8P4R_5%
RP26

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 2

R197 56_0402_5%

1 2

R199 56_0402_5%

1 2

R206 56_0402_5%

1 2

R209 56_0402_5%

RP28

1 8
2 7
3 6
4 5

56_0804_8P4R_5%
RP30

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

18
27
36
45

18
27
36
45

18
27
36
45

D

+1.25VS

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 2

R169 56_0402_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 2

R196 56_0402_5%

1 2

R198 56_0402_5%

1 2

R205 56_0402_5%

1 2

R207 56_0402_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

D

RP4

RP6

RP8

RP10

RP12

RP14

RP17

RP20

RP22

RP23

RP25

RP27

RP29

E

DDR_DQ60
DDR_DQ61
DDR_DM7
DDR_DQ57

DDR_DQ59
DDR_DQ51
DDR_DQ54DDR_DQ55
DDR_DM6

DDR_DQ53
DDR_DQ48
DDR_DQ46
DDR_DQ47

DDR_DM5
DDR_DQ45
DDR_DQ41
DDR_DQ35

DDR_DQ39
DDR_DM4
DDR_DQ33
DDR_DQ36

DDR_SCS#1

DDR_SCS#0

18

DDR_SCAS#

27

DDR_SCS#3

36

DDR_SRAS#

45

DDR_SBS1

18

DDR_SMA1

27

DDR_SMA0

36

DDR_SMA2

45

DDR_SMA4

18

DDR_SMA_B4

27

DDR_SMA6

36

DDR_SMA_B2

45

DDR_SMA8

18

DDR_SMA11

27

DDR_CKE0

36

DDR_CKE2

45

DDR_DQ30
DDR_DM3
DDR_DQ29

DDR_DQ28
DDR_DQ23
DDR_DQ19
DDR_DM2

DDR_DQ21
DDR_DQ17
DDR_DQ10
DDR_DQ11

DDR_DM1
DDR_DQ12
DDR_DQ9
DDR_DQ6

DDR_DQ4
DDR_DM0
DDR_DQ7
DDR_DQ2

Title

Size Docu m e nt Number Re v

Friday, September 17, 2004

Date: Sheet

DDR_SMA[6..12]

DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]

DDR_SCS#1 <8,10>

DDR_SCS#0 <8,10>
DDR_SCAS# <8,10>
DDR_SCS#3 <8,10>
DDR_SRAS# <8,10>

DDR_SBS1 <8,10>
DDR_SMA1 <8,10>
DDR_SMA0 <8,10>
DDR_SMA2 <8,10>

DDR_SMA4 <8,10>
DDR_SMA_B4 <8,10>

DDR_SMA_B2 <8,10>

DDR_CKE0 <8,10>
DDR_CKE2 <8,10>

Compal Electronics, Inc.

DDR SODIMM Decoupling

EAL20 LA-2462

E

DDR_SMA[6..12] <8,10>
DDR_DQ[0..63] <10>

DDR_DQS[0..7] <10>

DDR_DM[0..7] <10>

of

11 47

0.1

A

SEL1

00

0

1

10K_0402_5%

VGATE<7,23,45>

+VCCP

SEL0

1

0
1

+3VS

R498

1 2

166.67

200.00

133.33

+3VS

1 2

R496 0_0402_5%

1 2

R497
56_0402_5%@

CLK_ICH_48M<23>
CLK_EXT_SD48<28>

CLK_MCH_48M<7>

CLK_ICH_14M<23>
CLK_14M_SIO<33>

CLK_14M_CODEC<31>

SEL2 CPUCLKC[0..2]

0

0

0
0

1 1

2 2

if pul l high to +VCCP
Change to DTC124EK

3 3

B

+3VS

12

R571

1K_0402_5%

R570

@

1K_0402_5%

R505 10K_0402_5%

C671

1 2

1

2

@

1 2

2

G

0.1U_0402_16V4Z

CPUCLKT[0..2]

166.67

100.00100.00

*

200.001

133.33

+3VS

12

R573

1K_0402_5%

@

R572

1K_0402_5%

13

D

Q38
2N7002_SOT23

S

R532
1K_0402_5%

1 2

1 2

+3VS

SMB_DATA<10,22>

SMB_CLK<10,22>

CLK_ SSC _ 6 6 M<7>

R531 475_0402_1%

1 2

R525 10_0402_5%

1 2

R524 10_0402_5%

1 2

5IN1@

1 2

R526 33_0402_5%

R576 10_0402_5%

1 2

R575 10_0402_5% SIO@

1 2

R574 10_0402_5% @

1 2

C

+3VS

C637
10P_0402_50V8K

1 2

1 2

SLP_S1#<23,34>
STP_PCI#<23>
STP_CPU#<23,45>

R508 33_0402_5%

XTALIN

12

Y5

14.318MHZ_16PF_DSX840GA

XTALOUT

C631
10P_0402_50V8K

1 2

R530 10K_0402_5%

SSC_66M

1 2

CLK_ICH48M

CLK_MCH48M

CLK_ICH14M

U46

2

XTAL_IN

3

XTAL_OUT

54

SEL0

55

SEL1

40

SEL2

25

PWR_DWN#

34

PCI_STOP#

53

CPU_STOP#

28

VTT_PWRGD#

43

MULT0

29

SDATA

30

SCLK

33

3V66_0

35

3V66_1/VCH_CLK

42

IREF

39

48MHZ_USB

38

48MHZ_DOT

56

REF

12

L100_0805_5%

12

L350_0805_5%

+3VS_CLK

D

Width=40 mils

1

2

32

14

37

1

50

VDD_REF

VDD_PCI_08VDD_PCI_1

VDD_CPU_046VDD_CPU_1

VDD_48MHZ

VDD_3V66_019VDD_3V66_1

GND_REF4GND_PCI_09GND_PCI_115GND_3V66_020GND_3V66_131GND_48MHZ36GND_IREF41GND_CPU

47

VDDA

VSSA

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1
CPUCLKT0

CPUCLKC0

3V66_5

3V66_4
3V66_3
3V66_2

PCICLK_F2
PCICLK_F1
PCICLK_F0

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

1

2

0.1U_0402_16V4Z

26

27
45

44
49

48
52

51
24

23
22
21

7
6
5

18
17
16
13
12
11
10

C640
10U_0805_10V4Z

CY28346ZCT-2_TSSOP56

0.1U_0402_16V4Z

1

C625

2

+3V_VDD

1

C599

2

0.1U_0402_16V4Z

CLK_MCH

CLK_M CH#

CLK_BCLK

CLK_BCLK#

CLK_ITP

CLK_ITP#

MCH_66M
AGP_66M
ICH_66M

PCI_ICH

PCI_MINI
PCI_LPC

PCI_SIO
PCI_LAN
PCI_1394
PCI_PCM

E

1

C614

2

0.1U_0402_16V4Z

1 2

L25 0_0805_5%

1

C595
10U_0805_10V4Z

2

1 2

R548
33_0402_5%

R539
33_0402_5%

1 2
1 2

R557
33_0402_5%

R554
33_0402_5%

1 2
1 2

R569
33_0402_5%

R563
33_0402_5%

1 2

1 2
1 2
1 2

1 2

1 2
1 2

1 2
1 2
1 2
1 2

0.1U_0402_16V4Z

1

C605

C600

2

R509 33_0402_5%
R514 33_0402_5% M11@
R515 33_0402_5%

R560 33_0402_5%

R529 33_0402_5% KS@
R534 33_0402_5%

R543 33_0402_5% SIO@
R544 33_0402_5%
R551 33_0402_5%
R552 33_0402_5%

1

C602

2

0.1U_0402_16V4Z

+3VS

CLK_MCH_BCLK <6>

R547

49.9_0402_1%

1 2
1 2

R538 49.9_0402_1%

CLK_MCH_BCLK# <6>
CLK_CPU_BCLK <4>

R556

49.9_0402_1%

1 2
1 2

49.9_0402_1%

R553

CLK_CPU_BCLK# <4>
CLK_CPU_ITP <4>

R568

49.9_0402_1%

1 2
1 2

R562

49.9_0402_1%

CLK_CPU_ITP# <4>

F

0.1U_0402_16V4Z

1

1

C620

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C627

2

CLK_MCH_66M <7>
CLK_AGP_66M <13>
CLK_ ICH _66M <22>

CLK_PCI_ICH <22>

CLK_PCI_MINI <30>
CLK_PCI_LPC <34>

CLK_PCI_SIO <33>
CLK_PCI_LAN <26>
CLK_PCI_1394 <27>
CLK_PCI_PCM <28>

1

C205

C639

2

0.1U_0402_16V4Z

G

0.1U_0402_16V4Z

1

C603

2

H

Clock Generator

4 4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

D

E

F

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

Clock Generator

EAL20 LA-2462

Friday, Se ptember 17, 2004

G

of

12 47

H

0.1

5

(20mils)

12

M11@

1 2

M11P
M11P
M11P

15mil

1 2

SUS_STAT#

R373 10K_0402_5%M11@

AGP_AD0
AGP_AD1
DVOB_D1
DVOB_D0
DVOB_D3
DVOB_D2
DVOB_D5
DVOB_D4
DVOB_D6
DVOB_D9
DVOB_D8
DVOB_D11
DVOB_D10
DVOBC_CLKINT
AGP_AD14
MDDCDATA
DVOC_ VSYNC
DVOC_HSYNC
AGP_AD18
DVOC_D0
DVOC_D1
DVOC_D2
DVOC_D3
DVOC_D4
DVOC_D7
DVOC_D6
DVOC_D9
DVOC_D8
DVOC_D11
DVOC_D10
AGP_AD30
AGP_AD31

DVOB_D7
AGP_CBE# 1
AGP_CBE# 2
DVOC_D5

CLK_AGP_66M
NB_PCIRST#
AGP_REQ#
AGP_GNT#
AGP_PAR
MDDCCLK
MI2CDATA
MDVICLK
MI2CCLK
MDVIDATA
PCI_PIRQA#

AGP_WBF#
STP_AGP#

AGP_BUSY#
AGP_RBF#
AGP_ADSTB0
DVOC_CLK
AGP_ADSTB0#
DVOC_CLK#

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

AGP_SBSTB
AGP_SBSTB#

AGPTEST
AGP_DBIHI

AGP_DBILO

R2SET

R60375_0402_1%
R60475_0402_1%
R36575_0402_1%

VGA_XTALIN

AGP_AD0<7>

AGP_AD1<7>
DVOC_D[0..11]<7,19>
DVOB_D[0 ..11]<7>
AGP_SBA[0..7]<7>

D D

+3VS

C C

B B

A A

CLK_AGP_66M

12

R383
10_0402_5%

@

1

C465
18P_0402_50V8K

2

@

R120 10K_0402_5%

PCIRST#<7,19,22,25,27,28,30>

+AGP_VREF

0.1U_0402_16V4Z

R368 1K_0402_5%M11@

+1.5VS

R377 1K_0402_5%M11@

DVOC_D[0..11]
DVOB_D[0 . .11]
AGP_SBA[0..7]

DVOBC_CLKINT<7,19>

AGP_AD14<7>

MDDCDATA<7>

DVOC_ VSYNC<7,19>
DVOC_HSYNC<7,19>

AGP_AD18<7>

12

M11@

C440

M11@

1 2
1 2

STP_AGP#

AGP_AD30<7>

AGP_AD31<7>

AGP_CBE#1<7>

AGP_CBE#2<7>

CLK_AGP_66M<12>

R382 0_0805_5%

1 2

M11@

AGP_REQ#<7>
AGP_GNT#<7>

AGP_PAR<7>

MDDCCLK<7>

MI2CDATA<7, 19>

MDVICLK<7>

MI2CCLK<7,19>

MDVIDATA<7>

PCI_PIRQA#<22,28>
AGP_WBF#<7>
STP_AGP#<23>

AGP_BUSY#<7,23>
AGP_RBF#<7>

AGP_ADSTB0<7>

DVOC_CLK<7,19>

AGP_ADSTB0#<7>

DVOC_CLK#<7,19>

1

+1.5VS

2

+3VS

M11_TV_CRMA<21>

M11_TV_LUMA<21>

SUS_STAT#<23,35>

5

AGP_ST0<7>
AGP_ST1<7>
AGP_ST2<7>

AGP_SBSTB<7>
AGP_SBSTB#<7>

1 2

R380 47_0402_1%M11@

R369 10K_0402_5%M11@

AGP_DBIHI
AGP_DBILO

R359 715_0603_1%

R379 1K_0402_5%M11@

+3VS

15mil

TESTEN

12

15mil

W26
W25

AA26
AA25
AA27

AG30
AG28

AF28

AD26

W29
W28

AE26
AC26
AH30

AH29
AE29

AD28
AD29
AC28
AC29
AA28
AA29

AF29
AD27
AE28

AB29
AB28

AB25
AB26

AC25

AE11

AF11

AK21

AJ23

AJ22
AK22

AJ24
AK24

AG23
AG24

AK25

AJ25

AH28

AJ29

AH27
AG26

H29
H28

J29

J28
K29
K28

L29

L28
N28
P29
P28
R29
R28
T29
T28
U29
N25
R26
P25
R27
R25
T25
T26
U25
V27

Y26
Y25

N29
U28
P26
U26

M25
N26
V29
V28

M28
V25
M29
V26

Y28
Y29

M26
M27

4

U7A

M10-P/(M9+X)

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE#0
C/BE#1
C/BE#2
C/BE#3

PCICLK
RST#
REQ#
GNT#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
INTA#

WBF#
STP_AGP#

AGP_BUSY#
RBF#
AD_STBF_0
AD_STBF_1
AD_STBS_0
AD_STBS_1

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

ST0
ST1
ST2

SB_STBF
SB_STBS

AGPREF
AGPTEST

DBI_HI
DBI_LO

AGP8X_DET#

DMINUS
DPLUS

THRM

R2SET
C_R

Y_G
COMP_B
H2SYNC
V2SYNC

DDC3CLK
DDC3DATA

SSIN
SSOUT

XTALIN
XTALOUT

TESTEN
SUS_STAT#

M11P_BGA708 M11@

4

(1/6)

PCI/AGPAGP8XCLK

SSC DAC2

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

VREFG/(NC)

ROMCS#

ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8

ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21

ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDSDAC1

ZV_LCDDATA22
ZV_LCDDATA23

ZV_LCDCNTL0

ZV_LCDCNTL1

ZV_LCDCNTL2

ZV_LCDCNTL3

DVOMODE

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN

TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

TXCLK_UN
TXCLK_UP

DIGON

BLON/(BLON#)

DDC2CLK

DDC2DATA

HSYNC
VSYNC

DDC1DATA

DDC1CLK

AUXWIN

TEST_MCLK/(NC)

TEST_YCLK/(NC)

PLLTEST/(NC)

RSTB_MSK/(NC)

1K_0402_5% M11@

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9

TX0M
TX0P
TX1M
TX1P
TX2M
TX2P

TXCM

TXCP

HPD1

RSET

R381

3

STRAP_G

AJ5

STRAP_H

AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2

GPIO10

AH2
AH1
AG3
AG1
AG2

POWER_SEL

AF3

MCLK_SPREAD STRAP_H

AF2

VREFG

AG4
AF5

STRAP_R

AH6

STRAP_S

AJ6

STRAP_T

AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

ZV_LCDCNTL0

AJ10

ZV_LCDCNTL1

AK10

ZV_LCDCNTL2

AJ11

ZV_LCDCNTL3

AH11
AE10

M11_TXOUT0-

AK16

M11_TXOUT0+

AH16

M11_TXOUT1-

AH17

M11_TXOUT1+

AJ16

M11_TXOUT2-

AH18

M11_TXOUT2+

AJ17
AK19
AH19

M11_TXCLK-

AK18

M11_TXCLK+

AJ18

M11_TZOUT0-

AG16

M11_TZOUT0+

AF16

M11_TZOUT1-

AG17

M11_TZOUT1+

AF17

M11_TZOUT2-

AF18

M11_TZOUT2+

AE18
AH20
AG20

M11_TZCLK-

AF19

M11_TZCLK+

AG19

ENVDD

AE12

ENBKL

AG12

AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13

AE13
AE14

R345 100K_0402_5%M11@

AF12

AK27

R

AJ27

G

AJ26

B

AG25
AH25

RSET

AH26

15mil

AF25
AF24

R372 10K_0402_5%

AF26

B6
E8
AE25
AG29

12

15mil

1 2

1 2

1 2

R323

M11@

12

1K_0402_1%

12

R327
1K_0402_1%

M11@

R50 10K_0402_5%@

1 2

R52 10K_0402_5%@

1 2

R53 10K_0402_5%@

1 2

R54 10K_0402_5%@

1 2

R370
499_0603_1%M11@

M11@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

+3VS

M11_TXOUT0- <20>
M11_TXOUT0+ <20>
M11_TXOUT1- <20>
M11_TXOUT1+ <20>
M11_TXOUT2- <20>
M11_TXOUT2+ <20>

M11_TXCLK- <20>
M11_TXCLK+ <20>
M11_TZOUT0- <20>
M11_TZOUT0+ <20>
M11_TZOUT1- <20>
M11_TZOUT1+ <20>
M11_TZOUT2- <20>
M11_TZOUT2+ <20>

M11_TZCLK- <20>
M11_TZCLK+ <20>

ENVDD <20>
ENBKL <34>

M11_CRT_R <21>
M11_CRT_G <21>
M11_CRT_B <21>
M11_CRT_HSYNC <21>
M11_CRT_VSYNC <21>

M11_C R T_ DDC_DATA <21>

M11_CRT_DDC_CLK <21>

+3VS

3

POWER_SEL
High for 1.0V
Low for 1.2V

*

POWER_ SEL <43>

12

R317
100K_0402_5%

M11@

M11_LCD_DATA <20>
M11_LCD_CLK <20>

+3VS

4M32
Samsung: K4D263238E-GC33
Hynix: HY5DU283222AF-33

8M32
Samsung: K4D553238E-JC33
Hynix: HY5DU573222AFM-33

Memory C o nfig.
GPIO10=High, 128MB
GPIO10=Low, 64MB

GPIO10
0

*

0
1
1
0
0

+3VS

R99

1 2

10K_0402_5%

1

C61

0.1U_0402_16V4Z

2

M11@

2

STRAP_G

GPIO10

STRAP_R

STRAP_S

STRAP_T

M11@

+3VS

Pin3 : Reserved for P1819 Spread Rate selection.

2

*

R46 10K_0402_5%M11@

1 2

R42 10K_0402_5%@

1 2

*

R35 10K_0402_5%M11@

1 2

R41 10K_0402_5%@

1 2

R34 10K_0402_5%128M@

1 2

R36 10K_0402_5%64M@

1 2

R320 10K_0402_5%128M@

1 2

R324 10K_0402_5%64M@

1 2

R48 10K_0402_5%M11@

1 2

R49 10K_0402_5%@

1 2

R330 10K_0402_5%@

1 2

R328 10K_0402_5%M11@

1 2

R

S

T

0

0

0

1

1

0

1

1

0

0

0

1

X1

4

VDD

1

OE

27MHZ_15P M11@

C358 0.1U_0402_16V4Z M11@

U33

7
1
8
2

ASM3P1819-SR_SO8M11@

4Mx32 Samsung x4

0

4Mx32 Hynix x4

0

8Mx32 Samsung x4

0

8Mx32 Hynix x4

0

4Mx32 Samsung x2 Ch. A

1

4Mx32 Hynixx2 Ch. A

1

3

OUT

2

GND

DDR SPREAD SPECTRUM

1 2

5

REF

VDD
XIN
XOUT
VSS

4

MODOUT

3

NC

6

PD#

Title

Size Document Number Re v

Custom

Date: Sheet

1

+3VS

M11@

1 2

R119 261_0603_1%

150_0402_1%

1 2

R321 22_0402_5% M11@

1 2

R325 10K_0402_5%@

1 2

R343 10K_0402_5%@

R118

M11@

MCLK_SPREADFREQOUT

12

+3VS

VGA_XTALINFREQOUT

C87

@

15P_0402_50V8J

Compal Electronics, Inc.

ATI M10-P/M11-AGP/DISPLAY(1/4)

EAL20 LA-2462

1

13 47Friday, Se ptember 17, 2004

0.1

of

5

4

3

2

1

NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63

NMDA[0..63]
NMAA[0..13]
NDQMA[0..7]
NDQSA[0..7]

L25
L26
K25
K26

J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10

B10
E13
E12
E10
F12
F11

U7B

M10-P/(M9+X)

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52

C9

DQA53

B9

DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60

E9

DQA61

F9

DQA62

F8

DQA63

M11P_BGA708 M11@

(2/6)

MEMORY INTERFACE

AA12/(AA13)
AA13/(AA12)

AA14/(NC)

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

A

RASA#
CASA#

WEA#
CSA0#
CSA1#

CLKA0

CLKA0#

CLKA1

CLKA1#

DIMA0

DIMA1

MVREFD

MVREFS/(NC)

AA10
AA11

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

CKEA

NMDB[0..63]<18>
NMAB[0..13]<18>
NDQMB[0..7]<18>
NDQSB[0..7]<18>

NMAA0

E22

AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9

NMAA1

B22

NMAA2

B23

NMAA3

B24

NMAA4

C23

NMAA5

C22

NMAA6

F22

NMAA7

F21

NMAA8

C21

NMAA9

A24

NMAA10

C24

NMAA11

A25

NMAA12

E21

NMAA13

B20
C19

NDQMA0

J25

NDQMA1

F29

NDQMA2

E25

NDQMA3

A27

NDQMA4

F15

NDQMA5

C15

NDQMA6

C11

NDQMA7

E11

NDQSA0

J27

NDQSA1

F30

NDQSA2

F24

NDQSA3

B27

NDQSA4

E16

NDQSA5

B16

NDQSA6

B11

NDQSA7

F10

NMRASA#

A19

NMCASA#

E18

NMWEA#

E19

NMCSA0#

E20

NMCSA1#

F20

NMCKEA

B19

CLKA0

R77 10_0402_5%M11@

B21

CLKA0#

R71 10_0402_5%M11@

C20

CLKA1

R64 10_0402_5%M11@

C18

CLKA1#

R68 10_0402_5%M11@

A18
D30

B13

MVREFD

B7

MVREFS

B8

1 2
1 2

1 2
1 2

NMRASA# <17>
NMCASA# <17>
NMWEA# <17>
NMCSA0# <17>
NMCSA1# <17>
NMCKEA <17>

NMCLKA0

NMCLKA0#

NMCLKA1

NMCLKA1#

NMCLKA0 <17>
NMCLKA0# <17>

NMCLKA1 <17>
NMCLKA1# <17>

NMDA[0..63]<17>
NMAA[0..13]<17>
NDQMA[0..7]<17>
NDQSA[0..7]<17>

D D

C C

B B

NMDB[0..63]
NMAB[0..13]
NDQMB[0..7]
NDQSB[0..7]

NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63

U7C

D7

DQB0

F7

DQB1

E7

DQB2

G6

DQB3

G5

DQB4

F5

DQB5

E5

DQB6

C4

DQB7

B5

DQB8

C5

DQB9

A4

DQB10

B4

DQB11

C2

DQB12

D3

DQB13

D1

DQB14

D2

DQB15

G4

DQB16

H6

DQB17

H5

DQB18

J6

DQB19

K5

DQB20

K4

DQB21

L6

DQB22

L5

DQB23

G2

DQB24

F3

DQB25

H2

DQB26

E2

DQB27

F2

DQB28

J3

DQB29

F1

DQB30

H3

DQB31

U6

DQB32

U5

DQB33

U3

DQB34

V6

DQB35

W5

DQB36

W4

DQB37

Y6

DQB38

Y5

DQB39

U2

DQB40

V2

DQB41

V1

DQB42

V3

DQB43

W3

DQB44

Y2

DQB45

Y3

DQB46

AA2

DQB47

AA6

DQB48

AA5

DQB49

AB6

DQB50

AB5

DQB51

AD6

DQB52

AD5

DQB53

AE5

DQB54

AE4

DQB55

AB2

DQB56

AB3

DQB57

AC2

DQB58

AC3

DQB59

AD3

DQB60

AE1

DQB61

AE2

DQB62

AE3

DQB63

M11P_BGA708 M11@

M10-P/(M9+X)

(3/6)

AB12/(AB13)
AB13/(AB12)

MEMORY INTERFACE B

MEMVMODE0
MEMVMODE1

AB10
AB11

AB14/(NC)

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

CKEB
CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB0
DIMB1

MEMTEST

AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9

M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2

E6
B2
J5
G3
W6
W2
AC6
AD2

F6
B3
K6
G1
V5
W1
AC5
AD1

R2
T5
T6
R5
R6
R3
N1

N2
T2

T3

C6
C7

E3
AA3

C8

NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13

NDQMB0
NDQMB1
NDQMB2
NDQMB3
NDQMB4
NDQMB5
NDQMB6
NDQMB7

NDQSB0
NDQSB1
NDQSB2
NDQSB3
NDQSB4
NDQSB5
NDQSB6
NDQSB7

NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCSB1#
NMCKEB

CLKB0
CLKB0#

CLKB1
CLKB1#

15mil

MEMVMODE0
MEMVMODE1

15mil

MEMTEST

15mil

R39 10_0402_5%M11@

1 2

R40 10_0402_5%M11@

1 2

R38 10_0402_5%M11@

1 2

R37 10_0402_5%M11@

1 2

R329 4.7K_0402_5%M11@

1 2

R333 4.7K_0402_5%M11@

1 2

R338 47_0402_1%M11@

1 2

NMRASB# <18>
NMCASB# <18>
NMWEB# <18>
NMCSB0# <18>
NMCSB1# <18>
NMCKEB <18>

NMCLKB0
NMCLKB0#

NMCLKB1
NMCLKB1#

+1.8VS

NMCLKB0 <18>
NMCLKB0# <18>

NMCLKB1 <18>
NMCLKB1# <18>

NMAB0

N5

+2.5VS+2.5VS

12

R341

M11@

1K_0402_1%

20mil 20mil

C362

M11@

A A

0.1U_0402_16V4Z

5

12

1

2

R339

M11@

1K_0402_1%

MVREFSMVREFD

C368

M11@

0.1U_0402_16V4Z

12

R347

M11@

1K_0402_1%

12

1

2

R349

M11@

1K_0402_1%

4

NMCKEA
NMCKEB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

M11@

1 2

R352 10K_0402_5%

M11@

1 2

R315 10K_0402_5%

3

2

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

ATIM10-P/M11-MEMORY(2/4)

EAL20 LA-2462

14 47Friday, Se ptember 17, 2004

1

of

0.1

5

4

3

2

1

+2.5VS

D D

C C

+1.5VS

+VDD_PNLPLL1.8

B B

+VDD_DAC1.8
+VDD_DAC2.5

U7D

B1

VDDR1

B30

VDDR1

A15

VDDR1

A21

VDDR1

A28

VDDR1

A3

VDDR1

A9

VDDR1

AA1

VDDR1

AA4

VDDR1

AA7

VDDR1

AA8

VDDR1

AD4

VDDR1

D5

VDDR1

D8

VDDR1

D11

VDDR1

D13

VDDR1

D14

VDDR1

D17

VDDR1

D20

VDDR1

D23

VDDR1

D26

VDDR1

E27

VDDR1

F4

VDDR1

G7

VDDR1

G10

VDDR1

G13

VDDR1

G15

VDDR1

G19

VDDR1

G22

VDDR1

G27

VDDR1

H10

VDDR1

H13

VDDR1

H15

VDDR1

H17

VDDR1

H19

VDDR1

H22

VDDR1

J1

VDDR1

J23

VDDR1

J24

VDDR1

J4

VDDR1

J7

VDDR1

J8

VDDR1

L27

VDDR1

L8

VDDR1

M4

VDDR1

N4

VDDR1

N7

VDDR1

N8

VDDR1

R1

VDDR1

T4

VDDR1

T7

VDDR1

T8

VDDR1

V4

VDDR1

V7

VDDR1

V8

VDDR1

D19

VDDR1/(CLKAFB)

R4

VDDR1/(CLKBFB)

AC11

VDDC15/(VDDC18)

AC20

VDDC15/(VDDC18)

H11

VDDC15/(VDDC18)

H20

VDDC15/(VDDC18)

L23

VDDC15/(VDDC18)

P8

VDDC15/(VDDC18)

Y23

VDDC15/(VDDC18)

Y8

VDDC15/(VDDC18)

AK12

TPVDD

AJ12

TPVSS

AH24

AVDD

AG21

A2VDD

AH21

A2VDD

AF22

A2VDDQ

AH22

A2VSSN

AJ21

A2VSSN

AF23

A2VSSQ

AH23

AVSSN

AD24

AVSSQ

M11P_BGA708 M11@

M10-P/(M9+X)

(4/6)

I/O POWER

LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)

VDDRH0
VDDRH1

VSSRH0
VSSRH1

MPVDD

MPVSS

PVDD

PVSS

VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3

VDDR4
VDDR4
VDDR4
VDDR4
VDDR4

VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP

LVDDR_18
LVDDR_18

LPVDD

LVSSR
LVSSR
LVSSR
LVSSR
LPVSS

VDD1DI
VDD2DI

VSS1DI
VSS2DI

TXVDDR
TXVDDR

TXVSSR
TXVSSR
TXVSSR

F18
N6

F19
M6

A7
A6

AK28
AJ28

AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7

AC10
AC9
AD10
AD9
AG7

AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27

AE20
AE17
AF21
AE15
AJ20

AF20
AF15
AE19
AE16
AJ19

AE24
AE22

AE23
AE21

AF13
AF14

AG13
AG14
AH12

+2.5VS

+VDD_MEMPLL1.8

+VDD_PLL1.8

+3VS

+1.5VS

change t o + 2.8V (max:350mA)

+LVDDR25
+VDD_PNLIO1.8
+VDD_PNLPLL1.8

+VDD_DAC1.8

+1.5VS

C418

M11@

22U_1206_16V4Z_V1

1

C420

M11@

2

0.1U_0402_16V4Z

1

2

22U_1206_16V4Z_V1

ATI: 22 Ux1, 0.1Ux2, 0.01Ux1, 1000Px1

+3VS

C403

M11@

0.1U_0402_16V4Z

20mil, 30mA

C395

M11@

0.1U_0402_16V4Z

C33

M11@

0.1U_0402_16V4Z

20mil, 83mA

C388

M11@

0.1U_0402_16V4Z

1

C421

M11@

2

0.1U_0402_16V4Z

1

C379

M11@

2

0.1U_0402_16V4Z

1

C57

M11@

2

0.1U_0402_16V4Z

L18

1 2

CHB1608B121_0603@

U36

5

VOUT

1

C396

M11@

2

GND

2

MIC5205-2.8BM5_SOT23-5 M11@

1

2

22U_1206_16V4Z_V1

+VDD_PNLIO1.8

1

2

10U_0805_10V4Z

+VDD_PNLPLL1.8

1

2

10U_0805_10V4Z

+LVDDR25

1

10U_0805_10V4Z

2

SA052050010(MIC5205-2.8BM5), max:150mA

1

C431

M11@

2

1

C366

M11@

2

1

C389

M11@

2

1

C36

M11@

2

1

C430

M11@

0.1U_0402_16V4Z

2

1

C357

M11@

0.01U_0402_16V7K

2

1

C422

M11@

0.1U_0402_16V4Z

2

L7

1 2

CHB1608B121_0603M11@

+2.5VS

1

VIN

4

PG

3

EN

1

C459

M11@

2

0.01U_0402_16V7K

1

C363

M11@

2

0.01U_0402_16V7K

L19

1 2

CHB1608B121_0603M11@

+1.8VS

+3VS

1

C458

M11@

0.01U_0402_16V7K

2

+1.8VS

1

C461

M11@

2

0.01U_0402_16V7K

+2.5VS

20mil

1

C355

M11@

2

10U_0805_10V4Z

+VDD_DAC2.5

20mil, 120mA

1

C429

M11@

2

10U_0805_10V4Z

+VDD_PLL1.8

20mil, 22mA

1

C455

M11@

2

10U_0805_10V4Z

+VDD_DAC1.8

20mil, 74mA20mil, 6mA

1

C432

M11@

2

10U_0805_10V4Z

+VDD_MEMPLL 1. 8

20mil, 6mA

1

C28

M11@

2

10U_0805_10V4Z

1

C426

M11@

0.1U_0402_16V4Z

2

1

C423

M11@

0.1U_0402_16V4Z

2

1

C452

M11@

0.1U_0402_16V4Z

2

1

C435

M11@

0.1U_0402_16V4Z

2

1

C27

M11@

0.1U_0402_16V4Z

2

L21

1 2

CHB1608B121_0603M11@

L22

1 2

CHB1608B121_0603M11@

L20

1 2

CHB1608B121_0603M11@

L6

1 2

CHB1608B121_0603M11@

+2.5VS

+1.8VS

+1.8VS

+1.8VS

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAIN S CONFIDENTI AL

AND TRADE SEC RET IN FOR MA TI ON. T HIS SH EET M AY N OTBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SH EET NOR THE INFO RMATIO N IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.

3

2

ATI M10-P/M11-POWER(3/4)

Size Document Number Re v

Custom

Date: Sheet

EAL20 LA-2462

1

15 47Friday, Se ptember 17, 2004

of

0.1