Toshiba Satellite L670, COMPAL LA-6041P Schematic

A

1 1

B

C

D

E

NALAA

2 2

LA-6041P

3 3

Hamburg 10

REV 1.0

Intel Arrandale /IBEX PEAK

Schematic

2009-10-01 Rev 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

NALAA LA-6041P M/B

148Tuesday, April 13, 2010

E

1.0

of

A

B

C

D

E

Compal Confidential

Model Name : NALAA

Intel Arrandale

Fan Control

APL5607KI-TRG

page 6

Clock Generator

RTM890N-631-GRT

page 13

File Name : LA-6041P

1 1

rPGA-989

page 5,6,7,8,9,10

FDI X8

LCD Conn.

CRT

page 13

page 14

page 15

Intel Ibex Peak

2 2

HDMI Conn.

page 15

HDMI Level Shifter

DMI X4

2.5GHz2.7GHz

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066 MT/s

USB/B

USB port 0,1

3IN1

USB

5V 480MHz

USB

5V 480MHz

PCIe 1x

1.5V 2.5GHz(250MB/s)

SATA port 1

5V 3GHz(300MB/s)

USB port 10

PCIeMini Card WiMax

PCIeMini Card WLAN

SATA HDD

200pin DDRIII-SO-DIMM X2

page 11,12

page 26

page 13

page 30

RTS5138-GR

page 31

USB port 13

page 27

PCIe port 2

page 27

page 25

BANK 0, 1, 2, 3

BT conn

USB port 5

Int. Camera

USB port 11

RJ45

3 3

RTL8105E-GR 10/100M

PCIe port 1

page 28page 28

PCIe 1x

1.5V 2.5GHz(250MB/s)

BGA-951

page 16~24

HD Audio

3.3V 33 MHz

LPC BUS

Power/B

USB/B

4 4

ODD/B

page 34

page 30

page 25

RTC CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

A

page 16

page 35

page 36~44

B

SPI ROM

page 16

Debug Port

page 33

Touch Pad

page 26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ENE KB926 E0

page 32

Int.KBD

page 26

2009/01/23 2010/01/23

C

EC ROM

page 33

SATA port 4

5V 3GHz(300MB/s)

SATA port 5

5V 3GHz(300MB/s)

USB port 3

5V 480MHz

3.3V/1.5V 24MHz

MDC 1.5 Conn

page 26 page 29

Compal Secret Data

Deciphered Date

SATA ODD

page 25

eSATA

page 25

MIC CONN

(LVDS CONN)

page 13

D

Int.

USB

USB port 3

page 25

HDA Codec

ALC259-GR

MIC CONN

page 30

Title

Size Document Number Rev

Date: Sheet

HP CONN

page 30

Compal Electronics, Inc.

Block Diagrams

NALAA LA-6041P M/B

SPK CONN

page 30

E

of

248Tuesday, April 13, 2010

of

248Tuesday, April 13, 2010

of

248Tuesday, April 13, 2010

1.0

5

NALAA Hamburg Intel Arrandale (UMA)

4

B+

3

Ipeak=5A, Imax=3.5A, Iocp min=7.9

2

DESIGN CURRENT 5A

1

+5VALW

D D

N-CHANNEL

SUSP

DESIGN CURRENT 4A

+5VS

SI4800

TPS51125RGER

Ipeak=5A, Imax=3.5A, Iocp min=7.7

WOL_EN#

P-CHANNEL

AO-3413

SUSP

N-CHANNEL

SI4800

C C

P-CHANNEL

AO-3413

P-CHANNEL

AO-3413

VR_ON

ISL62883

Ipeak=48A, Imax=33.6A, Iocp min=57.28

GFXVR_EN

ADP3211AMNR

B B

VTTP_EN#

APW7138NITRL

Ipeak=22A, Imax=15.4A, Iocp min=26

Ipeak=20A, Imax=14A, Iocp min=27.49

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

VGA_ENVDD

DESIGN CURRENT 1.5A

BT_PWR#

DESIGN CURRENT 180mA

DESIGN CURRENT 48A

DESIGN CURRENT 22A

DESIGN CURRENT 20A

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+BT_VCC

+CPU_CORE

+GFX_CORE

+VTT

+1.05VS

RT8209BGQW

SYSON

SUSP

N-CHANNEL

SI4856

Ipeak=9A, Imax=6.3A, Iocp min=9.8

SUSP

G2992F1U

DESIGN CURRENT 9A

DESIGN CURRENT 1.2A

DESIGN CURRENT 1.5A

+1.5V

+1.5VS

+0.75VS

+1.5V_CPU

SUSP#

MP2121DQ

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Deciphered Date

DESIGN CURRENT 1.5A

2

+1.8VS

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Tree

NALAA LA-6041P M/B

348Tuesday, April 13, 2010

1

of

1.0

A

B

C

D

E

Voltage Rails

1 1

power plane

( O MEANS ON X MEANS OFF )

+RTCVCC

+B

+5VALW

+3VALW

+VSB

+1.5V

+5VS

+3VS

+1.5VS

+VGA_CORE

+CPU_CORE

+VTT

BTO Option Table

Function

description

explain

BTO

Bluetooth

Bluetooth MDC

(B)

BT@

RJ11 LAN

LAN

MDC@

HDMI

(Y)

HDMI

IHDMI@

Card Reader Mini Card

Express Card

(W)(R) (E)

Card Reader

CARD@

New Card PCMCIA

WIRELESS

WLAN@

+1.05VS

+1.8VS

+1.1VS

State

S0

2 2

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

O

X

O

XX

X

XX X

+0.75VS

OO

X

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

G3 LOW LOWLOW

HIGH

3 3

EC SM Bus1 address

Device

EC KB926 D3

+3VALW

Smart Battery+3VALW VGA THM Sensor

Address Address

EC SM Bus2 address

Device

PowerPower

EC KB926 D3

+3VS

ADM1032ARMZ

+3VS

PCH

1001 110x b0001 011x b

0100 110x b

PCH SM Bus address

Power

+3VALW

+3VS

4 4

+3VS

Device

PCH

Clock Generator

DDR DIMM0

DDR DIMM1

Express

WLAN/Wim ax/3G

A

Address

1101 001x b

1001 000x b

1001 010x b

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

NALAA LA-6041P M/B

448Tuesday, April 13, 2010

E

1.0

of

5

1 2

R1 20_0402_1%R1 20_0402_1%

1 2

R2 20_0402_1%R2 20_0402_1%

1 2

R4 49.9_0402_1%R4 49.9_0402_1%

1 2

R3 49.9_0402_1%R3 49.9_0402_1%

PECI21

+VTT

XDP_RST#_R

H_PWRGOOD

DRAMPWROK

VTTPWROK_CPU

+VTT

1 2

R18 49.9_0402_1%R18 49.9_0402_1%

For prevent noise issue

C225 100P_0402_50V8JC225 100P_0402_50V8J

1 2

R9 68_0402_5%R9 68_0402_5%

1 2

R36 1K_0402_5%R36 1K_0402_5%

TAPPWRGD

R301.5K_0402_1% R301.5K_0402_1%

750_0402_1%

D D

+VTT

R10

R10 68_0402_5%

68_0402_5% @

@

1 2

H_CPURST#

C C

+1.5V_CPU

R28

1.1K_0402_1%

1.1K_0402_1% NPS@

NPS@

1 2

DRAMPWROK

R29

R29 3K_0402_1%

3K_0402_1% NPS@

NPS@

1 2

R29

R29 750_0402_1%

750_0402_1% PS@

PS@

H_THERMTRIP#21

PMSYNCH18

H_PWRGOOD21

DRAMPWROK18

VTTPWROK_CPU40

BUF_PLT_RST#20

T41PAD T41PAD

12

H_PROCHOT#_D

H_PWRGOOD1_R

12

R250_0402_5% R250_0402_5%

R31

4

H_COMP3

H_COMP2

H_COMP1

H_COMP0

TP_SKTOCC#

CATERR#

H_CPURST#

JCPUB

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

3

MISC THERMAL

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY# PREQ#

TCK TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TDI

A16 B16

CLK_CPU_XDP_R

AR30

CLK_CPU_XDP#_R

AT30

E16 D16

A18 A17

SM_DRAMRST#_CPU

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#_R

AP15

XDP_PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI_R

AT29

XDP_TDO_R

AR27

XDP_TDI_M

AR29

XDP_TDO_M

AP29

AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24 AJ25 AH22 AK23 AH23

CLK_CPU_BCLK 21 CLK_CPU_BCLK# 21

1 2

R41 0_0402_5%@R41 0_0402_5%@

1 2

R42 0_0402_5%@R42 0_0402_5%@

CLK_PEG 17 CLK_PEG# 17

Unused by Clarksfield rPGA989

R6 100_0402_1%R6 100_0402_1%

1 2

R7 24.9_0402_1%R7 24.9_0402_1%

1 2

R8 130_0402_1%R8 130_0402_1%

1 2

12

R12 0_0402_5%R12 0_0402_5%

Routed as a single daisy chain

R312 1K _0402_5%R312 1K _0402_5%

EMI reverse, close to JCPU

CLK_CPU_XDP CLK_CPU_XDP#

DDR3 Compensation Signals Layout Note:Please these resistors near Processor

PM_EXTTS# 11,12

12

+3VS

XDP_DBRESET# 18

XDP_PRDY#

XDP_PREQ#

XDP_TCK

XDP_TMS

XDP_TRST#

XDP_TDI_R

XDP_TDO_R

XDP_TDI_M

XDP_TDO_M

XDP_DBRESET#

2

C7 0.1U_0402_10V6K@C7 0.1U_0402_10V6K@

C8 0.1U_0402_10V6K@C8 0.1U_0402_10V6K@

C9 0.1U_0402_10V6K@C9 0.1U_0402_10V6K@

C10 0.1U_0402_10V6K@C10 0.1U_0402_10V6K@

C11 0.1U_0402_10V6K@C11 0.1U_0402_10V6K@

C12 0.1U_0402_10V6K@C12 0.1U_0402_10V6K@

C13 0.1U_0402_10V6K@C13 0.1U_0402_10V6K@

C14 0.1U_0402_10V6K@C14 0.1U_0402_10V6K@

C15 0.1U_0402_10V6K@C15 0.1U_0402_10V6K@

C17 0.1U_0402_10V6K@C17 0.1U_0402_10V6K@

1 2

SM_DRAMRST#_CPU

100K_0402_5%

JTAG MAPPING

1

NPS@

12

R19 0_0402_5%

D

S

D

S

12

PS@

R127

PM_EXTTS#0

PM_EXTTS#_R

XDP_TDI_R XDP_TDI

XDP_TDO_M

0_0402_5%

XDP_TDI_M

XDP_TDO_R

Scan Chain (Default)

CPU Only

GMCH Only

13

Q41

G

BSS138_NL_SOT23-3

2

PS@

C314

0.047U_0402_16V7K

1 2

R15 10K_0402_5%R15 10K_0402_5%

R13 10K_0402_5%R13 10K_0402_5%

1 2

R20 0_0402_5%R20 0_0402_5%

@

1 2

R21 0_0402_5%

12

R23

@

1 2

R26 0_0402_5%

1 2

R27 0_0402_5%R27 0_0402_5%

STUFF -> R20, R23, R27 NO STUFF -> R21, R26

STUFF -> R20, R21 NO STUFF -> R23, R26, R27

STUFF -> R26, R27 NO STUFF -> R20, R21, R23

RST_GATE 21

PS@C314

PS@

SM_DRAMRST# 11,12

Add on 11/09

+VTT

12

XDP_TDO

Close to JCPU

B B

+3VALW

1 2

C25 0.1U_0402_16V7KC25 0.1U_0402_16V7K

5

U16

VTTPWROK35,40

A A

VTTPWROK

5

U16

1

P

IN1

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

PS@

@

12

R840_0402_5%@R840_0402_5%

4

R33 1.5K_0402_1%

PS@

DRAMPWROK

VTTPWROK_CPU

DRAMPWROK

4

12

C384 1000P_0402_50V7KC384 1000P_0402_50V7K

12

C389 1000P_0402_50V7KC389 1000P_0402_50V7K

H_PWRGOOD TAPPWRGD

+VTT

1

C1

0.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/23 2010/01/23

2

@

Compal Secret Data

R32 1K_0402_5%@R32 1K_0402_5%@

1 2 1 2

R35 0_0402_5%@R35 0_0402_5%@

R11

51_0402_5%

Deciphered Date

12

R1451_0402_5% R1451_0402_5%

12

2

XDP Connector

XDP_PREQ# XDP_PRDY#

XDP_BPM#0 XDP_BPM#1

XDP_BPM#2 XDP_BPM#3

H_PWRGOOD _R TAPPWRGD_R CLK_CPU_XDP CLK_CPU_XDP#

XDP_RST#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

SFF-24Pin

JXDP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23 24

Title

Size Document Number Rev

Custom

Date: Sheet

25

23

GND

26

24

GND

MOLEX_52435-2472

MOLEX_52435-2472 @

@

Compal Electronics, Inc.

CPU CLK/MISC/JTAG/XDP

NALAA LA-6041P M/B

548Tuesday, April 13, 2010

of

1

of

1.0

5

4

3

2

1

D D

DMI_PTX_CRX_N018 DMI_PTX_CRX_N118 DMI_PTX_CRX_N218 DMI_PTX_CRX_N318

DMI_PTX_CRX_P018 DMI_PTX_CRX_P118 DMI_PTX_CRX_P218 DMI_PTX_CRX_P318

DMI_CTX_PRX_N018 DMI_CTX_PRX_N118 DMI_CTX_PRX_N218 DMI_CTX_PRX_N318

DMI_CTX_PRX_P018 DMI_CTX_PRX_P118 DMI_CTX_PRX_P218 DMI_CTX_PRX_P318

C C

B B

A A

FDI_CTX_PRX_N018 FDI_CTX_PRX_N118 FDI_CTX_PRX_N218 FDI_CTX_PRX_N318 FDI_CTX_PRX_N418 FDI_CTX_PRX_N518 FDI_CTX_PRX_N618 FDI_CTX_PRX_N718

FDI_CTX_PRX_P018 FDI_CTX_PRX_P118 FDI_CTX_PRX_P218 FDI_CTX_PRX_P318 FDI_CTX_PRX_P418 FDI_CTX_PRX_P518 FDI_CTX_PRX_P618 FDI_CTX_PRX_P718

FDI_FSYNC018 FDI_FSYNC118

FDI_ INT18

FDI_LSYNC018 FDI_LSYNC118

JCPUA

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

PEG_COMP

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_RBIAS

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0] PEG_RX#[1]

DMI Intel(R) FDI

PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

1 2

R38 49.9_0402_1%R38 49.9_0402_1%

1 2

R39 750_0402_1%R39 750_0402_1%

+5VS

FAN Control Circuit

1A

2

C3

10U_0805_10V4Z

U1

1

EN

GND

2

VIN

EN_DFAN132

+FAN1

10mil

1

C5

C5 10U_0805_10V4Z

10U_0805_10V4Z

2

3

VOUT

4

VSET

G996P11U_SOP8

GND GND GND

1

8 7 6 5

+FAN1

1

C4

C4 1000P_0402_50V7K

1000P_0402_50V7K

2

@

JFAN

1 2 3

4 5

ACES_85204-0300N

@

R34 10K_0402_5%R34 10K_0402_5%

2

C6

0.01U_0402_16V7K

1

@

1 2 3

GND GND

12

FAN_SPEED1 32

+3VS

Security Classification

2009/01/23 2010/01/23

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CPU DMI/FDI/PEG/FAN

NALAA LA-6041P M/B

648Tuesday, April 13, 2010

1

1.0

of

5

JCPUC

DDR_A_D[0..63]11

4

3

JCPUD

DDR_B_D[0..63]12

2

1

AA6

SA_CK[0]

AA7

SA_CK#[0]

P7

DDR_A_D0 DDR_A_D1

D D

C C

B B

DDR_A_BS011 DDR_A_BS111 DDR_A_BS211

DDR_A_CAS#11 DDR_A_RAS#11

DDR_A_WE#11

DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

C10

D10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ10

AL10 AK12

AK8

AK11

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

A10

B10

E10

F10

AJ7 AJ6

AJ9

AL7

AL8

C7 A7

A8 D8

E6 F7 E9 B7 E7 C6

G8

K7

G7

J10

M6 M8

K8 N8 P9

U7

J8

J7

L7

L9 L6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

SA_CKE[0]

Y6

SA_CK[1]

Y5

SA_CK#[1]

P6

SA_CKE[1]

AE2

SA_CS#[0]

AE8

SA_CS#[1]

AD8

SA_ODT[0]

AF9

SA_ODT[1]

DDR_A_DM0

B9

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

D7 H7 M7 AG6 AM7 AN10 AN13

DDR_A_DQS#0

C9

DDR_A_DQS#1

F8

DDR_A_DQS#2

J9

DDR_A_DQS#3

N9

DDR_A_DQS#4

AH7

DDR_A_DQS#5

AK9

DDR_A_DQS#6

AP11

DDR_A_DQS#7

AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8

DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDRA_CLK0 11 DDRB_CLK0 12 DDRA_CLK0# 11 DDRA_CKE0 11 DDRB_CKE0 12

DDRA_CLK1 11 DDRA_CLK1# 11 DDRA_CKE1 11

DDRA_SCS0# 11 DDRA_SCS1# 11 DDRB_SCS1# 12

DDRA_ODT0 11 DDRB_ODT0 12 DDRA_ODT1 11 DDRB_ODT1 12

DDR_A_DM[0..7] 11

DDR_A_DQS#[0..7] 11

DDR_A_DQS[0..7] 11

DDR_A_MA[0..15] 11

DDR_B_BS012 DDR_B_BS112 DDR_B_BS212

DDR_B_CAS#12 DDR_B_RAS#12

DDR_B_WE#12

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AF3

AG1

AK1 AG4 AG3

AH4

AK3

AK4 AM6 AN2

AK5

AK2 AM4 AM3

AP3 AN5

AT4 AN6 AN4 AN3

AT5

AT6 AN7

AP6

AP8

AT9

AT7

AP9

AR10

AT10

AB1

AC5

AC6

AJ3

AJ4

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3

G4

H6

G2

J6

J3 G1 G5

J2

J1

J5

K2

L3 M1

K5 K4

M4

N5

W5

R7

Y7

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

DDR SYSTEM MEMORY - B

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDRB_CLK0# 12

DDRB_CLK1 12 DDRB_CLK1# 12 DDRB_CKE1 12

DDRB_SCS0# 12

DDR_B_DM[0..7] 12

DDR_B_DQS#[0..7] 12

DDR_B_DQS[0..7] 12

DDR_B_MA[0..15] 12

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

A A

Security Classification

2009/01/23 2010/01/23

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Deciphered Date

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CPU DDRIII

NALAA LA-6041P M/B

748Tuesday, April 13, 2010

1

1.0

of

5

4

3

2

1

Material Note (+VTT):

JCPUF

+CPU_CORE

D D

C C

B B

A A

Clarksfield: 65A Clarksfield: 21A

Auburndale:48A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CPU CORE SUPPLY

POWER

SENSE LINES

Auburndale:18A

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31

1.1V RAIL POWER

VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

CPU VIDS

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

G15

AN35

AJ34 AJ35

B15 A15

330uF/ 6mohm, number are 3, power x1, HW x2

(Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)

+

C159 390U_2.5V_M_R10

1 2

C160 390U_2.5V_M_R10

1 2

+

C89 22U_0805_6.3V6MC89 22U_0805_6.3V6M

1 2

C91 22U_0805_6.3V6MC91 22U_0805_6.3V6M

1 2

H_PSI# 43

CPU_VID0 43 CPU_VID1 43 CPU_VID2 43 CPU_VID3 43 CPU_VID4 43 CPU_VID5 43

H_DPRSLPVR_R

VCCSENSE_R

1 2

R62 0_0402_5%R62 0_0402_5%

R65 0_0402_5%R65 0_0402_5%

1 2

R66 0_0402_5%R66 0_0402_5%

1 2

VTT_SENSE 40 VSS_SENSE_VTT 40

CPU_VID6 43 H_DPRSLPVR 43

T43 PADT43 PAD

IMVP_IMON 43

+VTT

C81 10U_0805_10V4KC81 10U_0805_10V4K

1 2

C83 10U_0805_10V4KC83 10U_0805_10V4K

1 2

C85 10U_0805_10V4KC85 10U_0805_10V4K

1 2

C87 10U_0805_10V4KC87 10U_0805_10V4K

1 2

C88 10U_0805_10V4KC88 10U_0805_10V4K

1 2

C90 10U_0805_10V4KC90 10U_0805_10V4K

1 2

C92 10U_0805_10V4KC92 10U_0805_10V4K

1 2

C94 10U_0805_10V4K@C94 10U_0805_10V4K@

1 2

Add on 5/25 for power team request

+CPU_CORE

22U_0805_6.3V6M

1

C144

C148

@

2

22U_0805_6.3V6M

CRB default setting: VID[6:0]=[0100111]

VTT Rail

Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V

H_VTTSELECT = low, 1.1V

H_VTTSELECT = high, 1.05V

1 2

R64 100_0402_1%R64 100_0402_1%

VCCSENSE VSSSENSEVSSSENSE_R

1 2

R67 100_0402_1%R67 100_0402_1%

near CPU

VCCSENSE 43 VSSSENSE 43

22U_0805_6.3V6M

1

C130

C131

@

2

22U_0805_6.3V6M

+CPU_CORE

1

C132

@

2

22U_0805_6.3V6M

1

C129

@

2

1

C149

@

2

22U_0805_6.3V6M

+CPU_CORE

10U_0805_10V4K

1

C71

2

10U_0805_10V4K

1

C72

2

10U_0805_10V4K

1

C73

2

1

2

1

C75

C74

2

10U_0805_10V4K

1

C76

2

10U_0805_10V4K

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

10U_0805_10V4K

1

C98

2

10U_0805_10V4K

1

C99

2

10U_0805_10V4K

1

C100

2

1

C101

2

10U_0805_10V4K

1

C102

2

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M

1

C107

2

22U_0805_6.3V6M

1

C113

2

22U_0805_6.3V6M

1

C108

2

22U_0805_6.3V6M

1

C114

2

22U_0805_6.3V6M

1

C109

C110

2

22U_0805_6.3V6M

1

C115

C116

2

22U_0805_6.3V6M

1

C106

C105

2

22U_0805_6.3V6M

+CPU_CORE

22U_0805_6.3V6M

1

C112

C111

2

22U_0805_6.3V6M

TOP side (under inductor)

+CPU_CORE

330U_D2_2.5VY_R9M

1

+

C121

330U_D2_2.5VY_R9M

2

C122

1

+

330U_D2_2.5VY_R9M

2

C123

330U_D2_2.5VY_R9M

1

+

C124

2

1

+

2

Check list:

+CPU_CORE: 6x 470uF, 12x 22uF, 16x 10uF

+VTT: 4x 330uF, 7x 22uF, 8x 10uF

10U_0805_10V4K

1

C77

2

1

C103

2

10U_0805_10V4K

1

2

1

2

1

C78

C79

2

10U_0805_10V4K

1

C104

C104 2

Co-layout with C123

+CPU_CORE

1

+

C125

C125 220U_6.3V_M

220U_6.3V_M @

@

2

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

5

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/23 2010/01/23

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CPU POWER-1

NALAA LA-6041P M/B

1

848Tuesday, April 13, 2010

1.0

of

5

4

3

2

1

PS@Q33

PS@

8

D

7

D

6

D

5

D

R417

R417 820K_0402_5%

820K_0402_5% PS@

PS@

VCC_AXG_SENSE_R VSS_AXG_SENSE_R

+1.8VS_H_PLL

1U_0402_6.3V4Z

+1.5V+1.5V_CPU

R418

PS@ R418

PS@

1 2

220K_0402_5%

61

Q46A

Q46A PS@

PS@

SUSP

2

2N7002KDW_SOT363-6

R95 0_0402_5%R95 0_0402_5% R94 0_0402_5%R94 0_0402_5%

GFXVR_VID_0 44 GFXVR_VID_1 44 GFXVR_VID_2 44 GFXVR_VID_3 44 GFXVR_VID_4 44 GFXVR_VID_5 44 GFXVR_VID_6 44

GFXVR_EN 44

T42 PADT42 PAD

GFXVR_IMON 44

R687 1K_0402_5%

@

1U_0402_6.3V4Z

1

C134

C135

C133

1U_0402_6.3V4Z

+VTT

1

2

1

2

C135

2

1U_0402_6.3V4Z

(Place these capacitors under CPU socket Edge, top layer)

C143

10U_0805_10V4K

C145

22U_0805_6.3V6M

(Place these capacitors under CPU socket, top layer)

1U_0402_6.3V4Z

1

C152

C151

C152

2

+VSB

SUSP 35,42

1 2 1 2

12

1U_0402_6.3V4Z

1

C136

2

+VTT

4.7U_0603_6.3V6K

1

C153

2

2.2U_0603_6.3V4Z

near CPU

R82 100_0402_1%R82 100_0402_1%

R69 100_0402_1%R69 100_0402_1%

1 2

R50 330_0402_5%R50 330_0402_5%

22U_0805_6.3V6M

1

C138

2

1

C155

2

22U_0805_6.3V6M

1

C139

2

22U_0805_6.3V6M

R71 0_0805_5%R71 0_0805_5%

C137

1U_0402_6.3V4Z

C154

1 2

VCC_AXG_SENSE 44 VSS_AXG_SENSE 44

1 2

+1.5V_CPU

1

C217

2

1

+

390U_2.5V_M_R10

2

+1.8VS

12

+GFX_CORE

C230 0.1U_0402_16V4ZC230 0.1U_0402_16V4Z

1 2

C218 0.1U_0402_16V4ZC218 0.1U_0402_16V4Z

1 2

C205 0.1U_0402_16V4ZC205 0.1U_0402_16V4Z

1 2

C186 0.1U_0402_16V4ZC186 0.1U_0402_16V4Z

1 2

PJ30

@PJ30

@

2

112

JUMP_43X79

+1.5V

Q33

1

S

2

S

3

+GFX_CORE

47P_0402_50V8J

C118

C118 @

@

1

2

C95

12

C119

C119 @

@

47P_0402_50V8J

12

C93

C93 @

@

22U_0805_6.3V6M

1

C127

2

1U_0402_6.3V4Z

C117

1U_0402_6.3V4Z

1

C96

2

10U_0805_6.3V6M

22U_0805_6.3V6M

1

2

C120

C141

1

C86

C86 10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VTT

1

2

1

C142

22U_0805_6.3V6M

2

2N7002KDW_SOT363-6

AT21 AT19 AT18

AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16

AM21 AM19 AM18 AM16

AL21

AL19

AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

J24 J23

H25

47P_0402_50V8J

12

C97

C97 @

D D

47P_0402_50V8J

390U_2.5V_M_R10

C C

B B

@

+GFX_CORE

1

+

C185

2

47P_0402_50V8J

22U_0805_6.3V6M

470_0805_5%

PS@ Q46B

PS@

SUSP

JCPUG

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36

VTT1_45 VTT1_46 VTT1_47

R424

PS@

1 2

3

Q46B

5

4

Auburndale:22A

GRAPHICS

Clarksfield: 5A

Auburndale:3A

FDI PEG & DMI

1

C267

10U_0805_10V4K

2

PS@

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_DPRSLPVR

GRAPHICS VIDs

POWER

DDR3 - 1.5V RAILS

Clarksfield: 21A

+VTT

K26

VTT1_48

J27

VTT1_49

C146

22U_0805_6.3V6M

1

2

1

C147

22U_0805_6.3V6M

2

H27 G28 G27 G26 F26 E26 E25

J26

VTT1_50

J25

VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58

(Place these capacitors under CPU socket, top layer)

A A

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

Auburndale:18A

Clarksfield: 0.6A

Auburndale:1.35A

1.1V1.8V

4

1

C472

2

PS@

0.1U_0402_25V6

VAXG_SENSE

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

S G

FDS6676AS_SO8

12

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

Security Classification

2009/01/23 2010/01/23

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CPU POWER-2

NALAA LA-6041P M/B

948Tuesday, April 13, 2010

1

1.0

of

5

JCPUI

K27

VSS161

K9

VSS162

K6

VSS163

D D

C C

B B

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

H_NCTF1 H_NCTF2

H_NCTF6 H_NCTF7

PADT4PAD PADT5PAD

PADT6PAD PADT7PAD

4

JCPUH

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

VSS8

AR17

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

T4 T5

T6 T7

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

3

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

2

WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1

CFG0

R743.01K_0402_1% @ R743.01K_0402_1% @

1 2

1 2 1 2

CFG1 CFG2 CFG3

R753.01K_0402_1% @ R753.01K_0402_1% @

CFG4

R763.01K_0402_1% @ R763.01K_0402_1% @

CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11

CFG13 CFG14 CFG15 CFG16 CFG17 CFG18

Reserve via for test

RSVD17 RSVD18

CFG0 - PCI-Express Configuration Select

*1:Single PEG 0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

JCPUE

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

RSVD9

H17

RSVD10

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 @

@

(SA_DIMM_VREF) (SB_DIMM_VREF)

1

AJ13

RSVD32

AJ12

RSVD33

AH25

RSVD34

AK26

RSVD35

AL26

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

KEY RSVD62 RSVD63 RSVD64 RSVD65

AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD_TP_59 RSVD_TP_60

RESERVED

Reserve via for test

VSS

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

RSVD64 RSVD65

*:Default

A A

Security Classification

2009/01/23 2010/01/23

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CPU GND/RESERVED

NALAA LA-6041P M/B

1

1.0

of

10 48Tuesday, April 13, 2010

5

+VREF_DQA

1

C157

C156

2

0.1U_0402_16V4Z

D D

close to JDDRL.1

C C

B B

A A

+3VS

C181

DDR_A_BS27

DDRA_CLK07 DDRA_CLK0#7

DDR_A_BS07

DDR_A_CAS#7

DDRA_SCS1#7

DDR_A_WE#7

1

C182

2

2.2U_0603_6.3V4Z

DDR_A_D0 DDR_A_D1

1

DDR_A_DM0

2

DDR_A_D2 DDR_A_D3

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R90

1 2

10K_0402_5%

1

2

0.1U_0402_16V4Z

5

R91

10K_0402_5%

+1.5V

+0.75VS

12

JDDRH

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-U2SN-7F_204P

FOX_AS0A626-U2SN-7F_204P @

@

VREF_CA

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1 CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1 BOSS2

A15 A14

A11

A7

A6 A4

A2 A0

S0#

NC

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

+DDR_VREF_CA_DIMMA

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

+0.75VS

4

DDR3 SO-DIMM A Standard Type

+1.5V

12

R83

1K_0402_1%

PS@

DDRA_CKE1 7DDRA_CKE07

DDRA_CLK1 7 DDRA_CLK1# 7

DDR_A_BS1 7 DDR_A_RAS# 7

DDRA_SCS0# 7 DDRA_ODT0 7

DDRA_ODT1 7

C161

2.2U_0603_6.3V4Z

close to JDDRL.126

PM_EXTTS# 5,12

PM_SMBDATA 12,13,17,27 PM_SMBCLK 12,13,17,27

+V_DDR3_DIMM_REF

R89

1 2

0_0402_5%

1

C162

2

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SM_DRAMRST# 5,12

3

DDR_A_DQS[0..7]7

DDR_A_DQS#[0..7]7

DDR_A_D[0..63]7

DDR_A_DM[0..7]7

DDR_A_MA[0..15]7

Layout Note: Place near JDDRH

+1.5V

+

C268 390U_2.5V_M_R10

1 2

C166 10U_0805_6.3V6MC166 10U_0805_6.3V6M

1 2

C168 10U_0805_6.3V6MC168 10U_0805_6.3V6M

1 2

C171 10U_0805_6.3V6MC171 10U_0805_6.3V6M

1 2

C174 10U_0805_6.3V6MC174 10U_0805_6.3V6M

1 2

C176 10U_0805_6.3V6MC176 10U_0805_6.3V6M

1 2

C178 10U_0805_6.3V6MC178 10U_0805_6.3V6M

1 2

Compal Secret Data

2009/01/23 2010/01/23

3

Compal Secret Data

Deciphered Date

M1 Circuit

+1.5V

12

R79

1K_0402_1%

12

R81

1K_0402_1%

Layout Note: Place these 4 Caps near Command and Control signals of JDDRH

+1.5V +0.75VS

C164 0.1U_0402_16V4ZC164 0.1U_0402_16V4Z

C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z

C21 68P_0402_50V8JC21 68P_0402_50V8J

For EMI Request

2

+V_DDR3_DIMM_REF

1 2

2

1

12

R78 0_0402_5%R78 0_0402_5%

12

R80 0_0402_5%R80 0_0402_5%

Layout Note: Place near JDDRH.203 and 204

C165 10U_0805_6.3V6MC165 10U_0805_6.3V6M

C169 1U_0402_6.3V4ZC169 1U_0402_6.3V4Z

C172 1U_0402_6.3V4ZC172 1U_0402_6.3V4Z

C175 1U_0402_6.3V4ZC175 1U_0402_6.3V4Z

C177 1U_0402_6.3V4ZC177 1U_0402_6.3V4Z

C22 68P_0402_50V8JC22 68P_0402_50V8J

+VREF_DQB

+VREF_DQA

1 2

12

For EMI Request

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM0

NALAA LA-6041P M/B

11 48Tuesday, April 13, 2010

1

of

1.0

A

+VREF_DQB

1

2

C183

1 1

C183

2.2U_0603_6.3V4Z

close to JDDRH.1

2 2

3 3

4 4

DDRB_CKE07

DDR_B_BS27

DDRB_CLK07 DDRB_CLK0#7

DDR_B_WE#7 DDR_B_CAS#7

DDRB_SCS1#7

+3VS

2.2U_0603_6.3V4Z

1

C207

2

0.1U_0402_16V4Z

1

C208

2

1

2

C184

0.1U_0402_16V4Z

R98

R98 10K_0402_5%

10K_0402_5%

R99

1 2

10K_0402_5%

A

DDR_B_D0 DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

1 2

+0.75VS

+1.5V

JDDRL

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-UASN-7F_204P

FOX_AS0A626-UASN-7F_204P @

@

VREF_CA

VSS

DQ4

DQ5

VSS

DQS0#

DQS0

VSS

DQ6

DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1 CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1 BOSS2

A15 A14

A11

A7

A6 A4

A2 A0

S0#

NC

+1.5V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

B

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

+DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

+0.75VS

B

Standard Type DDR3 SO-DIMM B

SM_DRAMRST# 5,11

DDRB_CKE1 7

DDRB_CLK1 7 DDRB_CLK1# 7

DDR_B_BS1 7 DDR_B_RAS# 7DDR_B_BS07

DDRB_SCS0# 7 DDRB_ODT0 7

DDRB_ODT1 7

R97

1 2

1

2

C188

C187

close to JDDRH.126

PM_EXTTS# 5,11

PM_SMBDATA 11,13,17,27 PM_SMBCLK 11,13,17,27

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+V_DDR3_DIMM_REF

0_0402_5%

1

2

C

DDR_B_DQS#[0..7]7

DDR_B_DQS[0..7]7

DDR_B_D[0..63]7

DDR_B_DM[0..7]7

DDR_B_MA[0..15]7

Layout Note: Place near JDDRL

+1.5V

2009/01/23 2010/01/23

C

@

+

C189 330U_B2_2.5VM_R15M

1 2

C192 10U_0805_6.3V6MC192 10U_0805_6.3V6M

1 2

C194 10U_0805_6.3V6MC194 10U_0805_6.3V6M

1 2

C197 10U_0805_6.3V6MC197 10U_0805_6.3V6M

1 2

C200 10U_0805_6.3V6MC200 10U_0805_6.3V6M

1 2

C202 10U_0805_6.3V6MC202 10U_0805_6.3V6M

1 2

C204 10U_0805_6.3V6MC204 10U_0805_6.3V6M

1 2

Compal Secret Data

Deciphered Date

Layout Note: Place these 4 Caps near Command and Control signals of JEERL

D

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4ZC196 0.1U_0402_16V4Z

1 2

C199 0.1U_0402_16V4ZC199 0.1U_0402_16V4Z

1 2

C23 68P_0402_50V8JC23 68P_0402_50V8J

1 2

For EMI Request

D

E

Layout Note: Place near JDDRL.203 and 204

+0.75VS+1.5V

C191 10U_0805_6.3V6MC191 10U_0805_6.3V6M

1 2

C195 1U_0402_6.3V4ZC195 1U_0402_6.3V4Z

12

C198 1U_0402_6.3V4ZC198 1U_0402_6.3V4Z

12

C201 1U_0402_6.3V4ZC201 1U_0402_6.3V4Z

12

C203 1U_0402_6.3V4ZC203 1U_0402_6.3V4Z

12

C24 68P_0402_50V8JC24 68P_0402_50V8J

12

For EMI Request

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM1

NALAA LA-6041P M/B

12 48Tuesday, April 13, 2010

E

of

1.0

A

Clock Generator

1 1

+1.5VS +1.5VS_CK505

Prevent noise coupling

CLK_DOT17 CLK_DOT#17

CLK_48M_CR31

2 2

CLK_SATA17 CLK_SATA#17

PCH_CLK_DMI17

PCH_CLK_DMI#17

1 2

1

2

CARD@

R390 33_0402_5%

B

C

D

E

F

For SED For SED

FBMH1608HM601-T_0603

+3VS +3VS_CK505 +1.05VS +1.05VS_CK505

1 2

FBMH1608HM601-T_0603

1 2

For SED

C231

C231 1U_0402_6.3V6K

1U_0402_6.3V6K

CLK_48M_CR_R

H_STP_CPU#

R100

@ R401

@ 0_0603_5%

0_0603_5%

R126

+1.05VS_CK505

+3VS_CK505

R401

0.1U_0402_16V4Z

1

C210

C209

2

10U_0805_10V4Z

1 2

0.1U_0402_16V4Z

1

C213

C214

2

1U_0402_6.3V6K

+1.5VS_CK505

U5

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

RTM890N-631-GRT_QFN32_5X5

0.1U_0402_16V4Z

1

C211

2

0.1U_0402_16V4Z

1

C215

2

0.1U_0402_16V4Z

SA00003HQ10

C212

For SED For SED

1

12

C251

C251 47P_0402_50V8J

2

47P_0402_50V8J

250mA

+1.05VS_CK505

+3VS_CK505

32

SCL

31

SDA

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_SRC

30 29 28 27 26 25

24 23 22 21 20 19 18 17

REF_0/CPU_SEL

CKPWRGD/PD#

VDD_CPU_IO

FBMH1608HM601-T_0603

CPU_SEL

1 2

CLK_XTAL_IN CLK_XTAL_OUT

CK_PWRGD

+1.5VS_CK505

1 2

R101

R10233_0402_5% R10233_0402_5%

10U_0805_10V4Z

1

C219

C220

2

0.1U_0402_16V4Z

PM_SMBCLK 11,12,17,27

PM_SMBDATA 11,12,17,27

CLK_14M_PCH 17

CLK_XTAL_IN

C223

22P_0402_50V8J

0.1U_0402_16V4Z

1

C221

C222

2

CLK_XTAL_OUT

2

14.318MHZ_16PF_7A14300083

1

CLK_BCLK 17 CLK_BCLK# 17

Y1

1 2

0.1U_0402_16V4Z

1

2

12

C252

C252 47P_0402_50V8J

47P_0402_50V8J

Routing the trace at

2

least 10mil

C224

C224 22P_0402_50V8J

22P_0402_50V8J

1

2N7002KDW_SOT363-6

G

+3VS_CK505

12

R110

R110 10K_0402_5%

10K_0402_5%

CK_PWRGD

3

Q35B

5

4

Silego Have Internal Pull-Up

H_STP_CPU#

CPU_SEL

IDT Have Internal Pull-Down

(Default)

0 133MHz

1

100MHz 100MHz

H

CLK_ENABLE# 43

+3VS_CK505

R10510K_0402_5% R10510K_0402_5%

12

R11910K_0402_5% @ R11910K_0402_5% @

12

+1.05VS

R10610K_0402_5% R10610K_0402_5%

12

CPU_1/1#CPU_SEL CPU_0/0#

133MHz

LCD/PANEL BD. Conn.

0.1U_0402_16V4Z

+LCD_VDD

Q1A

R112

100K_0402_5%

12

61

3 3

2N7002KDW_SOT363-6

UMA_ENVDD19

R107

R107 150_0603_5%

150_0603_5%

2

5

1 2

+3VS

12

R108

R108 100K_0402_5%

100K_0402_5%

1 2

R109 47K_0402_5%R109 47K_0402_5%

3

Q1B

Q1B 2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

4

C228

0.1U_0402_16V7K

0.01U_0402_25V7K

C228

C229

+3VS_LVDS_CAM

0_0603_5%

R391

+3VS

1 2

W=60mils

2

S

G

1

Q17

2

AO3413_SOT23

1

D

1 3

+LCD_VDD

2

W=60mils

1

C233

0.1U_0402_16V4Z

2

LCD_TXOUT0+19 LCD_TXOUT0-19 LCD_TXOUT1+19 LCD_TXOUT1-19 LCD_TXOUT2+19 LCD_TXOUT2-19

LCD_TZOUT0+19 LCD_TZOUT0-19 LCD_TZOUT1+19 LCD_TZOUT1-19 LCD_TZOUT2+19 LCD_TZOUT2-19

+LCD_INV

USB20_P11_R USB20_N11_R

W=20mils

Calpella PCH request 100K ohm

Reserve for EMI request

R93 0_0402_5%R93 0_0402_5%

4 4

USB20_N1120

USB20_P1120

A

1 2

L55

@L55

@

1

4

WCM-2012-900T_0805

R92 0_0402_5%R92 0_0402_5%

1 2

B

Prevent EC damage

USB20_N11_R

2

USB20_P11_R

3

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

BKOFF#32

2009/01/23 2010/01/23

1 2

R24

R24 33_0402_5%

33_0402_5%

10K_0402_5%

E

1 2

C270

JLVDS

2

4

6

8

10

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

R113

Compal Secret Data

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GMD

GND

ACES_87242-4001-09

ACES_87242-4001-09 @

@

BKOFF#_R

12

Deciphered Date

1

3

5

7

9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41

+LCDVDD_R

C312

68P_0402_50V8J

LCD_TXCLK+ 19 LCD_TXCLK- 19

LCD_TZCLK+ 19 LCD_TZCLK- 19

LCD_EDID_CLK 19 LCD_EDID_DATA 19 INT_MIC_CLK 29

INT_MIC_DATA 29

PCH_PWM 19

BKOFF#_R

+LCD_INV

Rated Current MAX:1000mA

1

2

F

L2

FBMA-L11-201209-221LMA30T_0805

1

C255

0.1U_0402_25V6

2

Title

Size Document Number Rev

Custom

Date: Sheet

+LCDVDD_R

1

2

INT_MIC_CLK

INT_MIC_DATA

AZ5125-02S.R7G_SOT23-3

680P_0402_50V7K

B+

12

Clock Generator (CK505)/ LVDS CONN

G

For EMI request

1

C301

C301 680P_0402_50V7K

680P_0402_50V7K

2

Compal Electronics, Inc.

NALAA LA-6041P M/B

1.5A

L1

12

0_0805_5%

C226

0.1U_0402_16V4Z

D58

2

3

C302

+LCD_VDD

1

C227

4.7U_0805_10V4Z

2

1

+3VS

1

2

13 48Tuesday, April 13, 2010

H

C269

0.1U_0402_16V4Z

of

1.0

A

CRT CONNECTOR

B

C

D

E

1

D3

DAN217_SC59

CRT_R_L

CRT_G_L

CRT_B_L

1

C243

2

2.2P_0402_50V8C

DAN217_SC59

2

3

@

1

2

2.2P_0402_50V8C

C245

C245 @

@

1 1

L3

UMA_CRT_R19

UMA_CRT_G19

UMA_CRT_B19

12

R139

R138

150_0402_1%

2 2

1 2

C244 0.1U_0402_16V4ZC244 0.1U_0402_16V4Z

UMA_CRT_HSYNC19

UMA_CRT_VSYNC19

3 3

12

R140

150_0402_1%

SN74AHCT1G125GW_SOT353-5

1

C239

C238

2

2.2P_0402_50V8C

150_0402_1%

+CRT_VCC

2.2P_0402_50V8C

1

5

P

4

OE#

A2Y

G

U6

3

+CRT_VCC

5

P

A2Y

SN74AHCT1G125GW_SOT353-5

G

3

1 2

NBQ100505T-800Y-N_2P

L4

1 2

NBQ100505T-800Y-N_2P

L5

1 2

NBQ100505T-800Y-N_2P

1

C240

2

2.2P_0402_50V8C

R141 10K_0402_5%R141 10K_0402_5%

D_CRT_HSYNC

1

4

OE#

U7

1

C242

C241

2

2.2P_0402_50V8C

12

1 2

L6 10_0402_5%L6 10_0402_5%

1 2

L7 10_0402_5%L7 10_0402_5%

+3VS

D4

DAN217_SC59

2

@

1

C246

C246 @

@

2

10P_0402_50V8J

1

3

1

2

1

D5

DAN217_SC59

2

3

@

HSYNC

VSYNCD_CRT_VSYNC

10P_0402_50V8J

+3VS

+CRT_VCC

+5VS

2

3

CRT_R_L

CRT_DDC_DAT CRT_G_L

HSYNC CRT_B_L

VSYNC

CRT_DDC_CLK

+CRT_VCC_R +CRT_VCC

D6

RB491D_SOT23-3

If=1A

F1

1

1.1A_6V_MINISMDC110F-2

21

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

16 17

30mil

1

C237

0.1U_0402_16V4Z@

JCRT

RGND ID0 Red GGND SDA Green BGND Hsync Blue +5V Vsync res SGND SCL GND

GND GND

SUYIN_070546FR015S263ZR

2

@

+CRT_VCC

12

R146

2.2K_0402_5%

2

Q2A

UMA_CRT_DATA19

UMA_CRT_CLK19

33P_0402_50V8K

4 4

A

1

C247

2

@

B

5

Q2B

4

2N7002KDW_SOT363-6

1

C248

C248 33P_0402_50V8K

33P_0402_50V8K

2

@

61

2N7002KDW_SOT363-6

3

C249

470P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

CRT_DDC_DAT

CRT_DDC_CLK

1

C250

C250 470P_0402_50V8J

470P_0402_50V8J

2

@

R147

2.2K_0402_5%

Compal Secret Data

2009/01/23 2010/01/23

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CRT

NALAA LA-6041P M/B

14 48Tuesday, April 13, 2010

E

1.0

of

5

450

420

450

460

340

400

420

0_0402_5%IHDMI@

Pre-amp

12

R158

2.2K_0402_5%

IHDMI@

12

R154

2.2K_0402_5%

@

R157

2

3

R173

R175

2

3

R180

2dB

CG20CG1 CG0

0

1

0

D D

*

C C

UMA_DVI_TXC-

UMA_DVI_TXC+

B B

UMA_DVI_TXD0-

UMA_DVI_TXD0+

1

0

1

0

1

+3VS +3VS +3VS

12

R131

2.2K_0402_5%

@

HDMI_CG2 HDMI_CG1 HDMI_CG0

12

R132

2.2K_0402_5%

IHDMI@

Swing

0

1

0

1

0

1

0

1

1 2

L8

@ L8

@

1

4

OCE2012120YZF_0805

1 2

L9

@ L9

@

1

4

OCE2012120YZF_0805

1 2

0

+3VS

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

Slew-rate

0

-3dB

-4dB

0

10K_0402_5%

Shortest trace

Longest trace

12

R167

2.2K_0402_5%

IHDMI@

12

R163

2.2K_0402_5%

@

R161

12

@

HDMI Connector

UMA_DVI_TXD1-

UMA_DVI_TXD1+

A A

UMA_DVI_TXD2-

UMA_DVI_TXD2+

1 2

L10

@ L10

@

1

4

OCE2012120YZF_0805

1 2

L11

@ L11

@

1

4

OCE2012120YZF_0805

1 2

5

0_0402_5%IHDMI@

R182

2

3

R183

R187

2

3

R188

2

3

2

3

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

HDMI_HPD

+HDMI_5V_OUT

HDMI_SDATA HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK+ HDMI_R_D0-

HDMI_R_D0+ HDMI_R_D1-

HDMI_R_D1+ HDMI_R_D2-

HDMI_R_D2+

PCH_HDMI_HPD

4

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042MR019S153ZL@

4

UMA_HDMI_DATA19

GND GND GND GND

3

+3VS

0.1U_0402_16V4Z

1

C256

IHDMI@

10U_0805_10V4Z

HDMI_CG0 HDMI_CG1

1 2

3.9K_0402_1% IHDMI@

PCH_HDMI_HPD19,21

UMA_HDMI_CLK19

3.9K_0402_1% IHDMI@

HDMI_CG2

UMA_DVI_TXC+ UMA_DVI_TXC-

UMA_DVI_TXD2+ UMA_DVI_TXD2-

UMA_DVI_TXD1+ UMA_DVI_TXD1-

UMA_DVI_TXD0+ UMA_DVI_TXD0-

20 21 22 23

2

+3VS

R160

PMEG2010AEH_SOD123 IHDMI@

2 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C266

C266 IHDMI@

IHDMI@

2

U10

2

VCC3V

11

VCC3V

15

VCC3V

21

VCC3V

26

VCC3V

33

VCC3V

40

VCC3V

46

VCC3V

3

FUNCTION1

4

FUCNTION2

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

10

ANALOG2

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

ASM1442 QFN_48P_7X7

ASM1442 QFN_48P_7X7 IHDMI@

IHDMI@

D53

1.1A_6V_MINISMDC110F-2

0.1U_0402_16V4Z

1

C257

C257 IHDMI@

IHDMI@

2

0.1U_0402_16V4Z

1

2

C258

C258 IHDMI@

IHDMI@

0.1U_0402_16V4Z

1

2

C262

C262 IHDMI@

IHDMI@

0.1U_0402_16V4Z

1

C263

C263 IHDMI@

IHDMI@

2

0.1U_0402_16V4Z

OE*

SCL_SINK

SDA_SINK

HPD_SINK

DDC_EN

FUNCTION3 FUNCTION4

1

2

C261

C261 IHDMI@

IHDMI@

25

28

29

30

32

34 35

For UMA HDMI level shift display compatibility issue

48

IN_D4+

47

IN_D4-

45

IN_D3+

44

IN_D3-

42

IN_D2+

41

IN_D2-

39

IN_D1+

38

IN_D1-

THERMAL_PAD

F2

IHDMI@F2

IHDMI@

2 1

2009/01/23 2010/01/23

3

+HDMI_5V_OUT+5VS

1

C259

C259 IHDMI@

IHDMI@

0.1U_0402_16V4Z

2

Compal Secret Data

Deciphered Date

49

0.1U_0402_16V4Z

2

1

C260

C260 IHDMI@

IHDMI@

0.1U_0402_16V4Z

2

OE#

@

12

R159 10K_0402_5%

HDMI_SCLK

HDMI_SDATA

HDMI_HPD_R

HDMI_EQ0 HDMI_EQ1

HDMI_TXC+ HDMI_TXC-

HDMI_TX2+ HDMI_TX2-

HDMI_TX1+ HDMI_TX1-

HDMI_TX0+ HDMI_TX0-

C264

@

R122 2.2K_0402_5%

R123 2.2K_0402_5%

@

R177 10K_0402_5%

R168 4.7K_0402_5%

IHDMI@

HDMI_TXC-

IHDMI@

IHDMI@ C279 0.1U_0402_16V7K

C279 0.1U_0402_16V7K C280 0.1U_0402_16V7K

C280 0.1U_0402_16V7K IHDMI@

IHDMI@ C281 0.1U_0402_16V7K

C281 0.1U_0402_16V7K C282 0.1U_0402_16V7K

C282 0.1U_0402_16V7K IHDMI@

IHDMI@ C283 0.1U_0402_16V7K

C283 0.1U_0402_16V7K C284 0.1U_0402_16V7K

C284 0.1U_0402_16V7K IHDMI@

IHDMI@ C285 0.1U_0402_16V7K

C285 0.1U_0402_16V7K C286 0.1U_0402_16V7K

C286 0.1U_0402_16V7K

+5VS

2

1

74AHCT1G125GW_SOT353-5

2

2N7002KDW_SOT363-6

+HDMI_5V_OUT

IHDMI@

1 2

IHDMI@

1 2

12

1 2

R148 2.2K_0402_5%

1 2 1 2

5

P

A2Y

G

@

3

+3VS

12

IHDMI@

1

U9

HDMI_HPD_R

4

OE#

Title

Size Document Number Rev

Date: Sheet

OE#

Q51A

IHDMI@

+3VS

11/16 Add circuit to control OE# pin for save power consumption

12

R37

R37 10K_0402_5%

10K_0402_5% IHDMI@

IHDMI@

61

2

R170

R170 IHDMI@

IHDMI@ 100K_0402_5%

100K_0402_5%

1 2

*

UMA_HDMI_TXC+ 19 UMA_HDMI_TXC- 19

UMA_HDMI_TX2+ 19 UMA_HDMI_TX2- 19

UMA_HDMI_TX1+ 19 UMA_HDMI_TX1- 19

UMA_HDMI_TX0+ 19 UMA_HDMI_TX0- 19

1 2

R96 1K_0402_1%@ R96 1K_0402_1%@

1 2

R691 0_0402_5%

IHDMI@

Compal Electronics, Inc.

HDMI Connector

NALAA LA-6041P M/B

1

HDMI_HPD_R

1

C430

C430 IHDMI@

IHDMI@

0.1U_0402_16V4Z

2

EQ0

0

1

0

1

R165

2.2K_0402_5%

2.2K_0402_5% IHDMI@

IHDMI@

HDMI_EQ1 HDMI_EQ0

R164

2.2K_0402_5%

@

HDMI_HPD

R186

100K_0402_5%

@

1

EqualizationEQ1

12dB

9dB

6dB

3dB

+3VS +3VS

12

R162

2.2K_0402_5%

2.2K_0402_5% IHDMI@

IHDMI@

12

R166

2.2K_0402_5%

@

2

C265

0.1U_0402_16V4Z

0.1U_0402_16V4Z IHDMI@

IHDMI@

1

1 2

of

15 48Tuesday, April 13, 2010

of

15 48Tuesday, April 13, 2010

of

15 48Tuesday, April 13, 2010

12

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