Toshiba P300, P305 Schematics
1
2
3
4
5
6
7
8
VCC_CORE
+1.5V
AA
+1.05V
+1.25V
+1.8VSUS
+1.8V
+3VPCU
+3V_S5
+3VSUS
+3V
+5VPCU
+5V_S5
+5V
+SMDDR_VTERM
+SMDDR_VREF
BB
CC
HP
Page 30
MIC JACK
DD
Page 30
INT SPK
Page 29
Reserve MIC
Page 29
Reserve MIC
Page 29
1
HDMI CEC
SPK AMP
Page 29
Page 19
INT MIC
Page 19
DAUGHTER
BOARD
DAUGHTER
BOARD
DAUGHTER
BOARD
HDMI Level Shift
LCD PANEL
SATA - HDD
SATA - ODD
LAN/B USB
Finger Printer
(FTB)
Bluetooth
New Card
M/B USB2
(FTB)
TV/ROBSON
Port-A
Port-B
2
Page 21
CRT
Page 20
Page 19
Page 22
Page 22
USB-0
Page 26
Camera
WLAN
Felica
M/B USB
AUDIO CODEC
(CX20561)
FM TUNER
& MDC
USB-3
Page 19
USB-5
Page 25
USB-1
Page 26
USB-2
Page 26
USB-9
Page 27
USB-7
Page 27
USB-4
Page 26
USB-6
Page 27
USB-8
Page 25
Page 29
Port-C
Page 29
MDC BoardRJ11
SATA
SATA
Reserve FM
3
BL5M Block Diagram
Intel
PENRYN
uFCPGA
FSB(667/800MHZ)
SDVO
CRT
LVDS
USB 2.0
Azalia
Page 30
Page 29
FANVR
NB
CANTIGA
Page 5,7,8,9,10,11
DMI(x2/x4)
SB
ICH9M
Page 12, 13, 14, 15
LPC
WPC8763LDG
KeyFLASH
Kill SW
Board
Page 27Page 3
Page 26Page 28Page 28
4
Page 3,4
ROM
PCI-E 16X Lan
533/ 667 MHZ DDR II
PCI-Express
PCI Bus
32.768KHz
Page 28
CIR
G-Sensor
Page 22
5
CLOCK GENERATOR
CK505
ICS9LPR363
VGA CONNECTOR
(FOX)
DDRII-SODIMM1
DDRII-SODIMM2
Page 16, 17
MINI CARD-3
UMA HD-DVD
Page 25
PCIE-2
PCIE-6PCIE-5
MINI CARD-1
WLAN
Page 25
MINI CARD-2
UMA TV/ROBSON
PCMCIA
Controller
(CB 1410)
Page 23Page 24
PCMCIA
Page 23Page 24Page 24
6
Page 2
Page 18
MINI CARD-4
ROBSON
(FTB)
PCIE-4
Page 25
Card
Reader/1394
(OZ129T)
5 IN 11394
LCD/LED
Page 25
PCIE-1PCIE-3
NEW CARD
CRT
HDMI
LAN
Page 27
Connector
Marvell LAN
10/100/Giga
88E8040T/88E8055
Transformer
LED Board
Low Cost Board
MMB Board
Power Board
Touch Pad
Board
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Block Diagram
Block Diagram
Block Diagram
Date:Sheet of
Date:Sheet of
Date:Sheet of
7
Page 26
LAN/RJ11/RJ45/USB/RF DAUGHTER BOARD
RJ45 RJ11 USB
Page 26
Page 26
DAUGHTER
Page 26
Page 26
Page 26
BOARD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
RF
1A
1A
137Tuesday, March 04, 2008
137Tuesday, March 04, 2008
137Tuesday, March 04, 2008
8
1A
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
5
Clock
Generator
L19PBY160808T-301Y-N_6L19PBY160808T-301Y-N_6
+3V
DD
C23427p_4C23427p_4
C25827p_4C25827p_4
10/30 Change Value and need change PN
CC
ICS9LPRS365
(ALPRS365K13)
Pin 4
PCI2/TME
PCI-3
Pin 5
Pin 6
PCI-4/27M_SEL
Pin 7
PCIF-5/ITP_EN
BB
CG_XIN PCI_CLK_SIO_R
21
Y3
CL=20p
14.318MHZY314.318MHZ
CG_XOUT
RTM875T-606
(AL000875K06)
PCI2/TME
internal PD
PCI-3/SRC5_EN
internal PD
PCI-4/27M_SEL
internal PD
PCIF-5/ITP_EN
internal PD
PULL HIGHPULL DOWN
NO OVERCLOCKINGNORMAL RUN
PIN37/38 IS SRC5
PIN 17/18 IS 27MHz
PIN 46/47 IS CPUITPPIN 46/47 IS SRC8
(default)
VDD_CK_VDD_48
C286
C286
10u/10V_8
10u/10V_8
PCLK_DEBUG(25)
T84T84
PCLK_OZ129(23)
PCLK_591(29)
PCLK_ICH(15)
CLKUSB_48(16)
14M_ICH(16)
PIN37/38 IS
PCI_STOP/CPU_STOP
PIN 17/18
IS SRC/DOT
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
(default)
(default)
(default)
PCLK_OZ129
PCLK_ICH
R31633_4R31633_4
R3112.2K_4R3112.2K_4
R24510K_4R24510K_4
R24633_4R24633_4
C2650.1u/10V_4C2650.1u/10V_4
C2790.1u/10V_4C2790.1u/10V_4
C27510u/10V_8C27510u/10V_8
C2400.1u/10V_4C2400.1u/10V_4
C2770.1u/10V_4C2770.1u/10V_4
C2410.1u/10V_4C2410.1u/10V_4
C2390.1u/10V_4C2390.1u/10V_4
R29433_4R29433_4
R306*33_4R306*33_4
R30733_4R30733_4
R30810K_4R30810K_4
R30933_4R30933_4
R31033_4R31033_4
4
C257
C257
*10u/10V_8
*10u/10V_8
U12
U12
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
61
VDD_REF
39
VDD_SRC
55
VDD_CPU
12
VDD_96_IO
20
VDD_PLL3_IO
26
VDD_SRC_IO_1
45
VDD_SRC_IO_3
36
VDD_SRC_IO_2
49
VDD_CPU_IO
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/SRC5_EN
7
PCIF5/ITP_EN
60
XTAL_IN
59
XTAL_OUT
10
USB_48/FSA
57
FSB/TEST/MODE
62
REF0/FSC/TESTSEL
8
VSS_PCI
11
VSS_48
15
VSS_IO
19
VSS_PLL3
52
VSS_CPU
23
VSS_SRC1
29
VSS_SRC2
42
VSS_SRC3
58
VSS_REF
ICS9LPRS365BGLFT
ICS9LPRS365BGLFT
PCLK_OZ129
PCLK_591
HIGH 27MHz
LOW SRC
PCLK_ICH
CK505
CK505
SRC5/PCI_STOP#
SRC5#/CPU_STOP#
CKPWRGD/PWRDWN#
<MAIN>:ICS9LPRS365BGLFT QCI:ALPRS365K13
<SECOND>:SLG8SP512TTR: QCI:AL8SP512K05
+3V
+3V
+3V
11/01 Modify
VDD_CK_VDD_48
+1.05V_VDD
PCLK_DEBUG_RPCLK_DEBUG
PCLK_PCM_R
PCLK_OZ129_R
PCLK_591_RPCLK_591
PCLK_ICH_R
CG_XIN
CG_XOUT
FSA
FSB
FSC
R31810K_4R31810K_4
R319*10K_4R319*10K_4
R325*10K_4R325*10K_4
R32110K_4R32110K_4
R326*10K_4R326*10K_4
R31710K_4R31710K_4
IO_VOUT
SCLK
CPU0
CPU0#
CPU1
CPU1#
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC11/CR#_H
SRC11#/CR#_G
SRC9
SRC9#
SRC7/CR#_F
SRC7#/CR#_E
SRC6
SRC6#
SRC4
SRC4#
SRC3/CR#_C
SRC3#/CR#_D
SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
SDA
C268
C268
10u/10V_8
10u/10V_8
3
48
CGCLK_SMB
64
CGDAT_SMB
63
PM_STPPCI#
38
PM_STPCPU#
37
CLK_CPU_BCLK_R
54
CLK_CPU_BCLK#_R
53
CLK_MCH_BCLK_R
51
CLK_MCH_BCLK#_R
50
CLK_PCIE_MINI3_R
47
CLK_PCIE_MINI3#_R
46
CLK_PCIE_3GPLL#_R
35
CLK_PCIE_3GPLL_R
34
CLK_MCH_OE#_R
33
NEW_CLKREQ#_R
32
CLK_PCIE_NEW_R
30
CLK_PCIE_NEW_R#
31
CLK_PCIE_MINI2_R
44
CLK_PCIE_MINI2#_R
43
CLK_PCIE_MINI_R
41
CLK_PCIE_MINI#_R
40
CLK_PCIE_LAN_R
27
CLK_PCIE_LAN#_R
28
CLK_PCIE_ICH_R
24
CLK_PCIE_ICH#_R
25
CLK_PCIE_SATA_R
21
CLK_PCIE_SATA#_R
22
DREFSSCLK_R
17
DREFSSCLK#_R
18
DREFCLK_R
13
DREFCLK#_R
14
56
C276
C276
0.1u/10V_4
0.1u/10V_4
C238
C238
0.1u/10V_4
0.1u/10V_4
C227
C227
C274
C274
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
RP340X2RP340X2
RP350X2RP350X2
RP36IV@0X2RP36IV@0X2
RP390X2RP390X2
R261475/F_4R261475/F_4
R300475/F_4R300475/F_4
RP410X2RP410X2
RP370X2RP370X2
RP380X2RP380X2
RP400X2RP400X2
RP420X2RP420X2
RP450X2RP450X2
RP43IV@0X2RP43IV@0X2
1
3
1
3
1
3
1
3
3
1
1
3
1
3
3
1
3
1
3
1
3
1
2
4
2
4
2
4
2
4
4
2
2
4
2
4
4
2
4
2
4
2
4
2
DREFSSCLK_R
DREFSSCLK#_R
C278
C278
0.1u/10V_4
0.1u/10V_4
2
+1.05V_VDD
C242
C242
0.1u/10V_4
0.1u/10V_4
PM_STPPCI#(16)
PM_STPCPU#(16)
CLK_CPU_BCLK(3)
CLK_CPU_BCLK#(3)
CLK_MCH_BCLK(5)
CLK_MCH_BCLK#(5)
CLK_PCIE_MINI3(25)
CLK_PCIE_MINI3#(25)
CLK_PCIE_3GPLL#(6)
CLK_PCIE_3GPLL(6)
CLK_MCH_OE#(6)
NEW_CLKREQ#(28)
CLK_PCIE_NEW(28)
CLK_PCIE_NEW#(28)
CLK_PCIE_MINI2(25)
CLK_PCIE_MINI2#(25)
CLK_PCIE_MINI(25)
CLK_PCIE_MINI#(25)
CLK_PCIE_LAN(24)
CLK_PCIE_LAN#(24)
CLK_PCIE_ICH(15)
CLK_PCIE_ICH#(15)
CLK_PCIE_SATA(14)
CLK_PCIE_SATA#(14)
DREFCLK(6)
DREFCLK#(6)
CK_PWRGD(16)
RP44IV@0X2RP44IV@0X2
RP47EV@0X2RP47EV@0X2
1
BOM Option Table
To SB
L18PBY160808T-301Y-N_6 L18PBY160808T-301Y-N_6
+1.05V
PM_STPPCI#
PM_STPCPU#
NEW_CLKREQ#_R
Reference
R2472.2K_4R2472.2K_4
R2482.2K_4R2482.2K_4
R30510K_4R30510K_4
Description
INT VGA
IV@
EXT VGAEV@
+3V
To CPU
To NB
To MINI3
To NB
To New Card
To MINI2
To WLAN
To LAN
To SB
To SB
To NB
2
1
4
3
4
3
2
1
DREFSSCLK(6)
DREFSSCLK#(6)
CLK_MXM(19)
CLK_MXM#(19)
To NB
To VGA Card
FREQ. SEL
TABLE
BSEL Frequency Select Table
+1.05V
CPU_BSEL0(3)
R3310_4R3310_4
R327*56_4R327*56_4
R3221K_4R3221K_4
CLK_BSEL0
MCH_BSEL0(6)
Clock Gen
I2C
SDATA(16,21,25,28)
FSCFSBFSAFrequency
0
0
AA
0
0
1
0
1
1
1
0
1
000
1
266Mhz0
1
133Mhz
1
166Mhz
0
200Mhz
400Mhz
011
1
Reserved
1
100Mhz
CPU_BSEL1(3)
+1.05V
CPU_BSEL2(3)
+1.05V
R2410_4R2410_4
R255*0_4R255*0_4
R2401K_4R2401K_4
R2420_4R2420_4
R244*0_4R244*0_4
R2431K_4R2431K_4
CLK_BSEL1
CLK_BSEL2
MCH_BSEL1(6)
SCLK(16,21,25,28)
MCH_BSEL2(6)
333Mhz
5
4
3
+3V
R254
Q19
Q19
2
RHU002N06
RHU002N06
3
+3V
Q21
Q21
2
RHU002N06
RHU002N06
3
R254
10K_4
10K_4
1
1
CGDAT_SMB
R253
R253
10K_4
10K_4
CGCLK_SMB
2
CGDAT_SMB(13)
CGCLK_SMB(13)
11/01 Del C3195
PCLK_591
C291*33p/50V_4C291*33p/50V_4
CLKUSB_48
C293*33p/50V_4C293*33p/50V_4
14M_ICH
C231*33p/50V_4C231*33p/50V_4
PCLK_ICH
C300*33p/50V_4C300*33p/50V_4
PCLK_DEBUG
C269*33p/50V_4C269*33p/50V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Date:Sheet of
Date:Sheet of
Date:Sheet of
PROJECT : BL5M Montevina
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
1
237Monday, March 10, 2008
237Monday, March 10, 2008
237Monday, March 10, 2008
1A
1A
1A
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
H_A#[3..16](5)
DD
H_ADSTB#0(5)
H_REQ#[0..4](5)
H_A#[17..35](5)
H_ADSTB#1(5)
H_A20M#(14)
H_FERR#(14)
H_IGNNE#(14)
H_STPCLK#(14)
H_INTR(14)
H_NMI(14)
CC
H_SMI#(14)
R654*51/F_4R654*51/F_4
R637*51/F_4R637*51/F_4
+1.05V
12/22 REV_2A Add
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
R2140_4R2140_4
H_INTR
H_NMI
H_SMI#
T59T59
T58T58
T61T61
T60T60
T132T132
T133T133
T15T15
5
H_GTLREF2
AA4
AB2
AA3
D22
L5
L4
K5
M3
N2
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D3
F6
J4
J1
J3
U24A
U24A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
Penryn_1p0
Penryn_1p0
ADDR GROUP_0
ADDR GROUP_0
ADDR GROUP_1
ADDR GROUP_1
ICH
ICH
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
DBR#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
HIT#
TCK
TDI
TDO
TMS
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BREQ#
H_IERR#
H_INIT#
H_LOCK#
H_CPURST#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
H_PROCHOT#_D
H_THERMDA
H_THERMDC
CPU_PM_THRMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
R4670_4R4670_4
4
H_ADS#(5)
H_BNR#(5)
H_BPRI#(5)
H_DEFER#(5)
H_DRDY#(5)
H_DBSY#(5)
H_BREQ#(5)
H_INIT#(14)
H_LOCK#(5)
H_CPURST#(5)
H_RS#0(5)
H_RS#1(5)
H_RS#2(5)
H_TRDY#(5)
H_HIT#(5)
H_HITM#(5)
T56T56
T57T57
T66T66
T62T62
T64T64
T67T67
CLK_CPU_BCLK(2)
CLK_CPU_BCLK#(2)
GTLREF_CTL(4)
ZS2 Default no use this function
R47256_4R47256_4
Connect it to CPU DBR# is for ITP debug port
or CPU interposer (like ICE) to reset the system
SYS_RST#XDP_DBRESET#
SYS_RST#(16)
GTLREF_CTL
+1.05V
11/01 Modify
12/22 REV_2A Add
+1.05V
R643
R643
*10K/F_4
*10K/F_4
R653*10K/F_4R653*10K/F_4
3
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0(5)
H_DSTBP#0(5)
H_DINV#0(5)
11/01 Modify
+1.05V
Layout note:
H_GTLREF: Zo=55 ohm,L<0.5"
2/3*VCCP+-2%
R57
R57
H_DSTBN#1(5)
1K/F_4
1K/F_4
H_DSTBP#1(5)
H_DINV#1(5)
+1.05V
R412
H_GTLREF2
3
Q56
Q56
*2N7002
*2N7002
1
R412
*1K/F_4
*1K/F_4
R393
R393
*2K/F_4
*2K/F_4
+3V
R101
R101
*100K/F_4
*100K/F_4
2
Q27
Q27
2
MMBT3904
MMBT3904
1 3
R58
R58
2K/F_4
2K/F_4
CPU_BSEL0(2)
CPU_BSEL1(2)
CPU_BSEL2(2)
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_GTLREF
CPU_TEST1
T18T18
CPU_TEST2
T14T14
CPU_TEST3
T13T13
CPU_TEST4
T16T16
CPU_TEST5
T65T65
CPU_TEST6
T113T113
CPU_TEST7
T55T55
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
AD26
AF26
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
C23
D25
C24
AF1
A26
B22
B23
C21
C3
2
H_D#[0..63]
U24B
U24B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Penryn_1p0
Penryn_1p0
MISC
MISC
DATA GRP 0
DATA GRP 0
DATA GRP 1
DATA GRP 1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
1
H_D#[0..63](5)
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
H_DSTBN#2
Y26
H_DSTBP#2
AA26
H_DINV#2
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
H_DSTBN#3
AE25
H_DSTBP#3
AF24
H_DINV#3
AC20
COMP0
COMP1
COMP2
COMP3
ICH_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
PSI#
R6127.4/F_6R6127.4/F_6
R5954.9/F_4R5954.9/F_4
R20027.4/F_6R20027.4/F_6
R20154.9/F_4R20154.9/F_4
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
PSI#
H_DSTBN#2(5)
H_DSTBP#2(5)
H_DINV#2(5)
H_DSTBN#3(5)
H_DSTBP#3(5)
H_DINV#3(5)
ICH_DPRSTP#(6,14,32)
H_DPSLP#(14)
H_DPWR#(5)
H_CPUSLP#(5)
PSI#(32)
Layout note:
ICH_DPRSTP# , Daisy Chain
(SB>PowerIC>NB>CPU)
BOM Option Table
Reference
Quad Core
COMP0,COMP2 : 24.9 1% ohm
COMP1,COMP3 : 49.9 1% ohm
Dual Core
COMP0,COMP2 : 27.4 1% ohm
COMP1,COMP3 : 54.9 1% ohm
Layout note:
comp0,2: Zo=27.4ohm, L<0.5"
comp1,3: Zo=55ohm, L<0.5"
N/A
Description
H_PWRGD(14)
N/A
12/22 REV_2A Del R215
11/01 Modify
Thermal Trip
DELAY_VR_PWRGOOD(6,16,32)
BB
Processor
hot
AA
11/01 Modify
11/01 Modify
H_PROCHOT#_D
+1.05V
3
2
+1.05V
1
R478
R478
2
56.2/F_4
56.2/F_4
1 3
R475*0_4R475*0_4 R44210K_4R44210K_4
No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side
+1.05V
No use PROCHOT CPU side still PU 56ohm.
Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
R468
R468
side
56_4
56_4
R465*2.2K_4R465*2.2K_4
R461*0_4R461*0_4
Q41
Q41
FDV301N
FDV301N
R473
R473
1K_4
1K_4
Q40
Q40
MMBT3904
MMBT3904
SYS_SHDN#CPU_PM_THRMTRIP#
PM_THRMTRIP#
+1.05V
R466
R466
*10K_4
*10K_4
SYS_SHDN#(31)
PM_THRMTRIP#(6,14)
H_PROCHOT#(32)
D30
D30
*BAS316
*BAS316
R462
R462
100K_6
100K_6
10/23 Add
SYSFANON#(19)
CPU FAN
CTRL
VFAN(29)
11/01 Modify
+1.05V
12
R213
R213
*51/F_4
*51/F_4
H_CPURST#
12/22 REV_2A Del R212
+5V
U1
C112.2u/6.3V_6C112.2u/6.3V_6
R70_4R70_4
Reserve 1K for XDP function
XDP_TDO
R199*51/F_4R199*51/F_4
XDP_TDI
R19756_4R19756_4
XDP_TMS
R20354.9/F_4R20354.9/F_4
XDP_TCK
R19656_4R19656_4
XDP_TRST#
R20256_4R20256_4
10/30 Add ESD solution.
10/14 Change reference to follow BL5S
TH_FAN_POWER
3
VIN2VO
5
GND
1
6
/FON
4
G995U1G995
FANPWR = 1.6*VSET
VSET
GND
7
GND
8
GND
C416
C416
10u/10V_8
10u/10V_8
C417
C417
0.01u/16V_4
0.01u/16V_4
FANSIG(29)
D3
VPORT_6D3VPORT_6
2 1
11/01 Modify
+1.05V
21
VPORT_6
VPORT_6
D29
D29
FANSIG
C415
C415
*0.01u/16V_4
*0.01u/16V_4
+3V
R435
R435
10K_4
10K_4
CN17
CN17
1
2
3
FAN_CON
FAN_CON
12/18 REV_2A R415 DNI
5
4
3
21
*VPORT_6D4*VPORT_6
D4
CPU Thermal monitorXDP
+3V+3V
R456200_6R456200_6
R444
R444
10K_4
10K_4
U22
U22
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
*MAX6657
*MAX6657
ADDRESS:
98H
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
Date:Sheet of
LM86VCC
C4280.1u/10V_4C4280.1u/10V_4
C430
C430
2200p/50V_4
2200p/50V_4
H_THERMDA
H_THERMDC
1
VCC
2
DXP
3
DXN
5
GND
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
1
1A
1A
337Monday, March 10, 2008
337Monday, March 10, 2008
337Monday, March 10, 2008
1A
2ND_MBCLK(29)
2ND_MBDATA(29)
THERM_ALERT#(16)
2ND_MBDATA#
2ND_MBCLK#
LM86VCC
7
8
1
5
U21
U21
SDAT
SCLK
VCC
GND
LM95245
LM95245
Q38
Q38
RHU002N06
RHU002N06
+3V
2
3
3
Q37RHU002N06Q37RHU002N06
NS LM95245 PU this pin
+3V
R443*0_4R443*0_4
R45310K_4R45310K_4
+3V
R451330_4R451330_4
+3V
SYS_SHDN#(31)
THER_SHD#
4
OVT
THERM_ALERT#_R
6
ALERT
H_THERMDA
2
DXP
H_THERMDC
3
DXN
2
1
2
2ND_MBCLK#
2ND_MBDATA#
1
2
13
Q39MMBT3904Q39MMBT3904
R446
R446
10K_4
10K_4
THERM_ALERT#_R
THER_SHD#
NS LM95245 : AL095245000
SCMC EMC1402 : AL001402000
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
5
4
3
2
1
BOM Option Table
Reference
N/A
Description
N/A
Need NC 20PCS 10u before A1 BOM released(A0 all stuff)
DD
CC
CTL
BB
AA
U24D
U24D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn_1p0
Penryn_1p0
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
Place these parts reference
to Intel demo board.
C166
C456
C456
10u/10V_8
10u/10V_8
C454
C454
10u/10V_8
10u/10V_8
C455
C455
10u/10V_8
10u/10V_8
C470
C470
10u/10V_8
10u/10V_8
C138
C138
+
+
330u/2.5V_7343
330u/2.5V_7343
C479
C479
10u/10V_8
10u/10V_8
C159
C159
10u/10V_8
10u/10V_8
C452
C452
10u/10V_8
10u/10V_8
C468
C468
10u/10V_8
10u/10V_8
C166
10u/10V_8
10u/10V_8
C127
C127
10u/10V_8
10u/10V_8
C141
C141
10u/10V_8
10u/10V_8
C480
C480
10u/10V_8
10u/10V_8
VCC_CORE
+
+
C137
C137
330u/2.5V_7343
330u/2.5V_7343
C478
C478
10u/10V_8
10u/10V_8
C153
C153
10u/10V_8
10u/10V_8
C146
C146
10u/10V_8
10u/10V_8
C450
C450
10u/10V_8
10u/10V_8
C475
C475
C160
C160
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
C476
C476
C477
C477
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
C481
C481
C165
C165
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
C464
C464
C467
C467
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
VCC_CORE Bulk CAPs place
to BOT of CPU centeral
12/18 REV_2A Add C137,C138
R656*0_4R656*0_4
R6570_4R6570_4
GTLREF_CTLCTL
GTLREF_CTL(3)
12/22 REV_2A Add R657
Penryn CPU Power Status and max current table
POWER PLANE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCCA
VCCP
VCCP
S0
S3
S4/S5
X
X
O
O
O
O
O
O
O
X
X
X
X
X
X
X
X
X
X
X
X
Voltage
VID
VID
VID
VID
+1.5V
+1.05V
+1.05V
I(max)
47A
50A
TBD
67A
130mA
4.5A
2.5A
Standard Voltage CPU
SV Design Target
Extreme Edition CPU
EE Design Target
Before VCC Stable
After VCC Stable
C466
C466
10u/10V_8
10u/10V_8
C117
C117
10u/10V_8
10u/10V_8
C140
C140
10u/10V_8
10u/10V_8
C465
C465
10u/10V_8
10u/10V_8
Note
C142
C142
10u/10V_8
10u/10V_8
C161
C161
10u/10V_8
10u/10V_8
C162
C162
10u/10V_8
10u/10V_8
C469
C469
10u/10V_8
10u/10V_8
VCC_CORE
C126
C126
10u/10V_8
10u/10V_8
VCC_CORE
C128
C128
10u/10V_8
10u/10V_8
VCC_CORE
C453
C453
10u/10V_8
10u/10V_8
VCC_CORE
C451
C451
10u/10V_8
10u/10V_8
VCC_CORE VCC_CORE
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A10
A12
A13
A15
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
C10
C12
C13
C15
C17
C18
D10
D12
D14
D15
D17
D18
E10
E12
E13
E15
E17
E18
E20
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
A7
A9
B7
B9
C9
D9
E7
E9
F7
F9
U24C
U24C
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn_1p0
Penryn_1p0
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
CPU_G21
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
+VCCA_PROC
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
.
R1210_4R1210_4
H_VID0(32)
H_VID1(32)
H_VID2(32)
H_VID3(32)
H_VID4(32)
H_VID5(32)
H_VID6(32)
VCC_CORE
R161
R161
100/F_6
100/F_6
R155
R155
100/F_6
100/F_6
Layout Note:
Route VCCSENSE and VSSSENSE traces at
27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
(See Penryn EMTS Rev:1.0 Table7,8 for voltage and current)
(See Penryn EMTS Rev:1.0 Table-3 for VID table)
5
4
3
2
Layout Note:
Inside CPU center cavity in 2 rows
C107
C107
0.1u/10V_4
0.1u/10V_4
C173
C173
0.1u/10V_4
0.1u/10V_4
+1.05V
+1.05V
C108
C108
0.1u/10V_4
0.1u/10V_4
C106
C106
0.1u/10V_4
0.1u/10V_4
11/01 Modify
C174
C174
0.1u/10V_4
0.1u/10V_4
11/01 Modify
C172
C172
0.1u/10V_4
0.1u/10V_4
11/01 Del R3033
+1.05V
+
+
C462
C462
270u/2V_7343
270u/2V_7343
R530_6R530_6
C58
C58
C56
C56
0.01u/16V_4
0.01u/16V_4
10u/10V_8
10u/10V_8
VCCSENSE(32)
VSSSENSE(32)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
Date:Sheet of
VCCP Bulk CAP
close to Pin
+1.5V
Place 0.01u
near pin-B26
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
437Monday, March 10, 2008
437Monday, March 10, 2008
1
437Monday, March 10, 2008
1A
1A
1A
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
5
4
3
2
1
BOM Option Table
Reference
N/A
U23A
M11
AD14
AA8
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AC1
AE3
AC3
AE11
AE8
AG2
AD6
N12
P13
N10
Y10
Y12
Y14
AF3
C12
E11
A11
B11
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
J1
J2
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
N8
L7
M3
Y3
Y6
Y7
W2
Y9
C5
E3
U23A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA_1p2
CANTIGA_1p2
HOST
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_D#[63..0](3)
DD
11/01 Modify
+1.05V
R441
R441
221/F_4
221/F_4
CC
BB
R440
R440
100/F_4
100/F_4
R45
R45
24.9/F_4
24.9/F_4
H_SWING
C423
C423
0.1u/10V_4
0.1u/10V_4
H_RCOMP
0.3125*VCCP
W:10,S:20 , L<0.5"
W:10,S:20 , L<0.5"
11/01 Modify
+1.05V
R447
R447
1K/F_4
1K/F_4
R448
2K/F_4
2K/F_4
AA
R4490_4R4490_4R448
2/3*VCCP
W:10,S:20 , L<0.5"
H_AVREF
H_DVREF
H_CPURST#(3)
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
H_A#[35..3](3)
H_ADS#(3)
H_ADSTB#0(3)
H_ADSTB#1(3)
H_BNR#(3)
H_BPRI#(3)
H_BREQ#(3)
H_DEFER#(3)
H_DBSY#(3)
CLK_MCH_BCLK(2)
CLK_MCH_BCLK#(2)
H_DPWR#(3)
H_DRDY#(3)
H_HIT#(3)
H_HITM#(3)
H_LOCK#(3)
H_TRDY#(3)
H_DINV#[3..0](3)
H_DSTBN#[3..0](3)
H_DSTBP#[3..0](3)
H_REQ#[4..0](3)
H_RS#[2..0](3)H_CPUSLP#(3)
Description
N/A
5
4
3
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
2
Date:Sheet of
PROJECT : BL5M Montevina
1A
1A
537Monday, March 10, 2008
537Monday, March 10, 2008
537Monday, March 10, 2008
1
1A
5
U23B
MCH_RSVD1
T42T42
MCH_RSVD2
T34T34
MCH_RSVD3
T33T33
MCH_RSVD4
T44T44
MCH_RSVD5
T9T9
MCH_RSVD6
T11T11
MCH_RSVD7
T12T12
MCH_RSVD8
T17T17
MCH_RSVD9
T10T10
MCH_RSVD14
T27T27
DD
MCH_BSEL0(2)
MCH_BSEL1(2)
CC
PM_SYNC#(16)
ICH_DPRSTP#(3,14,32)
PM_EXTTS#0(13)
PM_EXTTS#1(13)
DELAY_VR_PWRGOOD(3,16,32)
PLT_RST#_NB(15)
PM_THRMTRIP#(3,14)
PM_DPRSLPVR(16,32)
NB Thermal trip pin
No use Thermal trip NB side can
NC.(NB has ODT)
PM_DPRSTP#
The Daisy chain topology should
be routed from ICH9M to IMVP ,
then to (G)MCH and CPU, in that
BB
AA
order.
Check list note : CL_REF=0.35V
MCH_CLVREF_R SM_VREF
+1.8VSUS +1.8VSUS
R464
R464
80.6/F_4
80.6/F_4
R463
R463
*20/F_4
*20/F_4
MCH_BSEL2(2)
MCH_CFG_5(11)
MCH_CFG_6(11)
MCH_CFG_7(11)
MCH_CFG_9(11)
MCH_CFG_10(11)
MCH_CFG_12(11)
MCH_CFG_13(11)
MCH_CFG_16(11)
MCH_CFG_19(11)
MCH_CFG_20(11)
R740_4R740_4
R4450_4R4450_4
R1410_4R1410_4
R1580_4R1580_4
R49100_4R49100_4
R66*0_4R66*0_4
R910_4R910_4
+1.05V
R140
R140
1K/F_4
1K/F_4
R139
R139
C121
C121
511/F_6
511/F_6
0.1u/10V_4
0.1u/10V_4
R460
R460
*20/F_4
*20/F_4
M_RCOMP#M_RCOMP SM_RCOMP_VOL
R459
R459
80.6/F_4
80.6/F_4
5
MCH_RSVD15
T32T32
MCH_RSVD17
T5T5
MCH_RSVD20
T25T25
MCH_RSVD21
T6T6
MCH_RSVD22
T116T116
MCH_RSVD23
T26T26
MCH_RSVD24
T114T114
MCH_RSVD25
T115T115
JTAG_TCK
T37T37
JTAG_TDI
T39T39
JTAG_TDO
T45T45
JTAG_TMS
T47T47
MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
MCH_CFG_3
T20T20
MCH_CFG_4
T28T28
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
T23T23
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
T19T19
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
T22T22
MCH_CFG_15
T21T21
MCH_CFG_16
MCH_CFG_17
T24T24
MCH_CFG_18
T31T31
MCH_CFG_19
MCH_CFG_20
PM_SYNC#_R
ICH_DPRSTP#_R
PM_EXTTS#0_1_EC_RPM_EXTTS#0
TS#DIMM0_1_RPM_EXTTS#1
RST_IN#_MCH
THRMTRIP#_R
DPRSLPVR_R
TP_MCH_NC1
T124T124
TP_MCH_NC2
T125T125
TP_MCH_NC3
T127T127
TP_MCH_NC4
T128T128
TP_MCH_NC5
T121T121
TP_MCH_NC6
T52T52
TP_MCH_NC7
T126T126
TP_MCH_NC8
T120T120
TP_MCH_NC9
T53T53
TP_MCH_NC10
T119T119
TP_MCH_NC11
T118T118
TP_MCH_NC12
T117T117
TP_MCH_NC13
T111T111
TP_MCH_NC14
T107T107
TP_MCH_NC15
T103T103
TP_MCH_NC16
T110T110
TP_MCH_NC17
T8T8
TP_MCH_NC18
T106T106
TP_MCH_NC19
T7T7
TP_MCH_NC20
T105T105
TP_MCH_NC21
T102T102
TP_MCH_NC22
T109T109
TP_MCH_NC23
T108T108
TP_MCH_NC24
T104T104
TP_MCH_NC25
T4T4
SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not
meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K.
12/19 REV_2A Chanhe net to +1.8VSUS
R4761K/F_4R4761K/F_4
+1.8VSUS
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
T24
B31
M1
AY21
B2
BG23
BF23
BH18
BF18
AL34
AK34
AN35
AM35
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
R29
B7
N33
P32
AT40
AT11
T20
R32
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
CANTIGA_1p2
CANTIGA_1p2
R156*0_6R156*0_6
R14710K/F_4R14710K/F_4
R154
R154
10K/F_4
10K/F_4
R470
R470
3.01K/F_4
3.01K/F_4
R471
R471
1K/F_4
1K/F_4
U23B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD14
RSVD15
RSVD17
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
+SMDDR_VREF
+1.8VSUS
SM_RCOMP_VOH
C440
C440
0.01u/16V_4
0.01u/16V_4
C435
C435
0.01u/16V_4
0.01u/16V_4
4
M_CLK_DDR0
AP24
SA_CK_0
M_CLK_DDR1
AT21
SA_CK_1
M_CLK_DDR3
AV24
SB_CK_0
M_CLK_DDR4
AU20
SB_CK_1
M_CLK_DDR#0
AR24
SA_CK#_0
M_CLK_DDR#1
AR21
SA_CK#_1
M_CLK_DDR#3
AU24
SB_CK#_0
M_CLK_DDR#4
AV20
SB_CK#_1
M_CKE0
BC28
SA_CKE_0
M_CKE1
AY28
SA_CKE_1
M_CKE3
AY36
SB_CKE_0
M_CKE4
RSVD
RSVD
DDR CLK/ CONTROL/COMPENSATION
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_SSCLK#
ME JTAG
ME JTAG
CLK
CLK
CFG
CFG
DMI
DMI
PM
PM
GRAPHICS VID
GRAPHICS VID
MEHDA
MEHDA
NC
NC
MISC
MISC
BB36
SB_CKE_1
M_CS#0
BA17
SA_CS#_0
M_CS#1
AY16
SA_CS#_1
M_CS#2
AV16
SB_CS#_0
M_CS#3
AR13
SB_CS#_1
M_ODT0
BD17
SA_ODT_0
M_ODT1
AY17
SA_ODT_1
M_ODT2
BF15
SB_ODT_0
M_ODT3
AY13
SB_ODT_1
M_RCOMP
BG22
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_PWROK
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_PWROK
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
HDA_BCLK
HDA_RST#
HDA_SYNC
M_RCOMP#
BH21
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
SM_VREF
AV42
SM_VREF
SM_PWROK
AR36
SM_REXT
BF17
SM_REXT
MCH_SM_DRAMRST#
BC36
DREFCLK
B38
DREFCLK#
A38
DREFSSCLK
E41
DREFSSCLK#
F41
CLK_PCIE_3GPLL
F43
PEG_CLK
CLK_PCIE_3GPLL#
E43
DMI_TXN0
AE41
DMI_TXN1
AE37
DMI_TXN2
AE47
DMI_TXN3
AH39
DMI_TXP0
AE40
DMI_TXP1
AE38
DMI_TXP2
AE48
DMI_TXP3
AH40
DMI_RXN0
AE35
DMI_RXN1
AE43
DMI_RXN2
AE46
DMI_RXN3
AH42
DMI_RXP0
AD35
DMI_RXP1
AE44
DMI_RXP2
AF46
DMI_RXP3
AH43
B33
T36T36
B32
T41T41
G33
T35T35
F33
T43T43
E33
T46T46
C34
T40T40
CL_CLK0
AH37
CL_CLK
CL_DATA0
AH36
CL_DATA
MPWROK
AN36
CL_RST#0
AJ35
CL_RST#
MCH_CLVREF_R
AH34
CL_VREF
DDPC_CTRLCLK
N28
DDPC_CTRLDATA
M28
SDVO_CTRLCLK
G36
SDVO_CTRLDATA
E36
CLK_MCH_OE#
K36
CLKREQ#
MCH_ICH_SYNC#
H36
TSATN#
B12
TSATN#
HDA_BIT_CLK_HDMI
B28
HDA_RST#_HDMI
B30
HDA_SDIN_HDMI
B29
HDA_SDI
HDA_SDOUT_HDMI
C29
HDA_SDO
HDA_SYNC_HDMI
A28
<Checklist ver0.8>
If TSATN# is not used, then it must be terminated
with a 56- pull-up resistor to VCCP.
TSATN#
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
SM_REXT
SM_PWROK only for DDR3.(DDR2 PD only)
C444
C444
2.2u/6.3V_6
2.2u/6.3V_6
C438
C438
2.2u/6.3V_6
2.2u/6.3V_6
SM_PWROK
4
RP49EV@0X2RP49EV@0X2
RP27EV@0X2RP27EV@0X2
10/14 Add
T30T30
R65499/F_4R65499/F_4
R149
R149
*12K/F_4
*12K/F_4
R143
R143
10K/F_6
10K/F_6
M_CLK_DDR0(13)
M_CLK_DDR1(13)
M_CLK_DDR3(13)
M_CLK_DDR4(13)
M_CLK_DDR#0(13)
M_CLK_DDR#1(13)
M_CLK_DDR#3(13)
M_CLK_DDR#4(13)
M_CKE0(12,13)
M_CKE1(12,13)
M_CKE3(12,13)
M_CKE4(12,13)
M_CS#0(12,13)
M_CS#1(12,13)
M_CS#2(12,13)
M_CS#3(12,13)
M_ODT0(12,13)
M_ODT1(12,13)
M_ODT2(12,13)
M_ODT3(12,13)
SM_DRAMRST# only for
DDR3.(DDR2 NC).
T38T38
DREFCLK(2)
DREFCLK#(2)
DREFSSCLK(2)
DREFSSCLK#(2)
CLK_PCIE_3GPLL(2)
CLK_PCIE_3GPLL#(2)
DMI_TXN[3:0](15)
DMI_TXP[3:0](15)
DMI_RXN[3:0](15)
DMI_RXP[3:0](15)
4
3
2
1
4
3
2
1
CL_CLK0(16)
CL_DATA0(16)
MPWROK(16)
CL_RST#0(16)
DDPC_CTRL for HDMI port C
SDVO_CTRL for HDMI port B
DDPC_CTRLDATA(11)
SDVO_CTRLCLK(20)
SDVO_CTRLDATA(11,20)
CLK_MCH_OE#(2)
MCH_ICH_SYNC#(16)
HDA_BIT_CLK_HDMI(14)
HDA_RST#_HDMI(14)
HDA_SDIN_HDMI(14)
HDA_SDOUT_HDMI(14)
HDA_SYNC_HDMI(14)
+1.05V
R45056_4 R45056_4
+3V
R14410K_4 R14410K_4
R14210K_4 R14210K_4
R13610K_4 R13610K_4
HWPG_1.8V(29,34)
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M for
iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be supplied
with 3.3V if and only if (G)MCH's HDA is not connected to
ICH9M. Consequently, only 1.5V audio/modem codecs can
be used on the platform.
IV&EV Dis/Enable LVDS setting(See DG 1.0 P190 Table 103)
+3V
IV&EV Dis/Enable CRT setting(See DG 1.0 P190 Table 103)
+3V
3
CRT I/F
INT_CRT_DDCCLK(18)
INT_CRT_DDCDAT(18)
INT_HSYNC(18)
INT_VSYNC(18)
HSYNC/VSYNC serial R place close to NB
R145IV@0_4R145IV@0_4
R160IV@2.37K/F_4R160IV@2.37K/F_4
R104IV@10K_4R104IV@10K_4
R103IV@10K_4R103IV@10K_4
R102EV@0_4R102EV@0_4
R105EV@0_4R105EV@0_4
R90IV@2.2K_4R90IV@2.2K_4
R89IV@2.2K_4R89IV@2.2K_4
R122EV@0_4R122EV@0_4
R133EV@0_4R133EV@0_4
R137EV@0_4R137EV@0_4
R138EV@0_4R138EV@0_4
R125EV@0_4R125EV@0_4
R127EV@0_4R127EV@0_4
3
LVDS I/F
INT_LVDS_PWM(18)
INT_LVDS_BLON(18)
INT_LVDS_EDIDCLK(18)
INT_LVDS_EDIDDATA(11,18)
INT_LVDS_DIGON(18)
INT_TXLCLKOUT-(18)
INT_TXLCLKOUT+(18)
INT_TXUCLKOUT-(18)
INT_TXUCLKOUT+(18)
LVDS_VREFH
LVDS_VREFL
LVDS_IBG
L_CTRL_CLK
L_CTRL_DATA
TV_DCONSEL_0
TV_DCONSEL_1
INT_CRT_DDCCLK
INT_CRT_DDCDAT
HSYNC_A
VSYNC_A
INT_TXLOUT0-(18)
INT_TXLOUT1-(18)
INT_TXLOUT2-(18)
INT_TXLOUT0+(18)
INT_TXLOUT1+(18)
INT_TXLOUT2+(18)
INT_TXUOUT0-(18)
INT_TXUOUT1-(18)
INT_TXUOUT2-(18)
INT_TXUOUT0+(18)
INT_TXUOUT1+(18)
INT_TXUOUT2+(18)
T54T54
INT_TV_Y/G(22)
INT_TV_C/R(22)
INT_CRT_BLU(18)
INT_CRT_GRN(18)
INT_CRT_RED(18)
R126IV@30.1/F_4R126IV@30.1/F_4
R128IV@30.1/F_4R128IV@30.1/F_4
10/14 Add
10/14 Add
INT_LVDS_PWM
INT_LVDS_BLON
L_CTRL_CLK
L_CTRL_DATA
INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA
INT_LVDS_DIGON
LVDS_IBG
LVDS_VBG
T51T51
LVDS_VREFH
LVDS_VREFL
INT_TXLCLKOUTÂINT_TXLCLKOUT+
INT_TXUCLKOUTÂINT_TXUCLKOUT+
INT_TXLOUT0ÂINT_TXLOUT1ÂINT_TXLOUT2ÂINT_TXLOUT3-
T122T122
INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+
INT_TXLOUT3+
T123T123
INT_TXUOUT0ÂINT_TXUOUT1ÂINT_TXUOUT2ÂINT_TXUOUT3-
T49T49
INT_TXUOUT0+
INT_TXUOUT1+
INT_TXUOUT2+
INT_TXUOUT3+
T48T48
INT_TV_Y/G
INT_TV_C/R
TV_DCONSEL_0
TV_DCONSEL_1
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
CRT_IRTN
INT_CRT_DDCCLK
INT_CRT_DDCDAT
HSYNC_AINT_HSYNC
CRTIREF
VSYNC_AINT_VSYNC
For IV @ Connect to 30.1ohm
For EV@ NC
U23C
U23C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA_1p2
CANTIGA_1p2
For EV@
CRT R/G/B
USE 0 ohm R
R92150/F_4R92150/F_4
R123150/F_4R123150/F_4
R124150/F_4R124150/F_4
R9475/F_4R9475/F_4
R95150/F_4R95150/F_4
R96150/F_4R96150/F_4
R1291K_4R1291K_4
For IV@ USE 1.02K ohm R
For EV@ USE 0 ohm R
2
LVDS
LVDS
TV
TV
For IV@
CRT R/G/B
USE 150 1%ohm R
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
CRTIREF
2
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
VGA
VGA
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
03/14 REV_3A Add
UMA W/ TV
UMA W/O TV 75/F75/F75/F
Discrete 75/F75/F75/F
EXP_A_COMPX
T37
T36
PEG_RXN0
H44
PEG_RXN1
J46
PEG_RXN2
L44
PEG_RXN3
L40
PEG_RXN4
N41
PEG_RXN5
P48
PEG_RXN6
N44
PEG_RXN7
T43
PEG_RXN8
U43
PEG_RXN9
Y43
PEG_RXN10
Y48
PEG_RXN11
Y36
PEG_RXN12
AA43
PEG_RXN13
AD37
PEG_RXN14
AC47
PEG_RXN15
AD39
PEG_RXP0
H43
PEG_RXP1
J44
PEG_RXP2
L43
PEG_RXP3
L41
PEG_RXP4
N40
PEG_RXP5
P47
PEG_RXP6
N43
PEG_RXP7
T42
PEG_RXP8
U42
PEG_RXP9
Y42
PEG_RXP10
W47
PEG_RXP11
Y37
PEG_RXP12
AA42
PEG_RXP13
AD36
PEG_RXP14
AC48
PEG_RXP15
AD40
C_PEG_TXN0_H
J41
C_PEG_TXN1_H
M46
C_PEG_TXN2_H
M47
C_PEG_TXN3_H
M40
C_PEG_TXN4
M42
C_PEG_TXN5
R48
C_PEG_TXN6
N38
C_PEG_TXN7
T40
C_PEG_TXN8
U37
C_PEG_TXN9
U40
C_PEG_TXN10
Y40
C_PEG_TXN11
AA46
C_PEG_TXN12
AA37
C_PEG_TXN13
AA40
C_PEG_TXN14
AD43
C_PEG_TXN15
AC46
C_PEG_TXP0_H
J42
C_PEG_TXP1_H
L46
C_PEG_TXP2_H
M48
C_PEG_TXP3_H
M39
C_PEG_TXP4
M43
C_PEG_TXP5
R47
C_PEG_TXP6
N37
C_PEG_TXP7
T39
C_PEG_TXP8
U36
C_PEG_TXP9
U39
C_PEG_TXP10
Y39
C_PEG_TXP11
Y46
C_PEG_TXP12
AA36
C_PEG_TXP13
AA39
C_PEG_TXP14
AD42
C_PEG_TXP15
AD46
C_PEG_TXN0_H
C_PEG_TXP0_H
C_PEG_TXN2_H
C_PEG_TXP2_H
C_PEG_TXN1_H
C_PEG_TXP1_H
C_PEG_TXN3_H
C_PEG_TXP3_H
UMA iHDMI I/F
75/F
L<0.5" , If PCIE not support
still connect to +VCC_PEG
R15049.9/F_4R15049.9/F_4
C505EV@0.1u/10V_4C505EV@0.1u/10V_4
C191EV@0.1u/10V_4C191EV@0.1u/10V_4
C500EV@0.1u/10V_4C500EV@0.1u/10V_4
C193EV@0.1u/10V_4C193EV@0.1u/10V_4
C202EV@0.1u/10V_4C202EV@0.1u/10V_4
C195EV@0.1u/10V_4C195EV@0.1u/10V_4
C197EV@0.1u/10V_4C197EV@0.1u/10V_4
C209EV@0.1u/10V_4C209EV@0.1u/10V_4
C211EV@0.1u/10V_4C211EV@0.1u/10V_4
C181EV@0.1u/10V_4C181EV@0.1u/10V_4
C183EV@0.1u/10V_4C183EV@0.1u/10V_4
C205EV@0.1u/10V_4C205EV@0.1u/10V_4
C185EV@0.1u/10V_4C185EV@0.1u/10V_4
C207EV@0.1u/10V_4C207EV@0.1u/10V_4
C503EV@0.1u/10V_4C503EV@0.1u/10V_4
C499EV@0.1u/10V_4C499EV@0.1u/10V_4
C504EV@0.1u/10V_4C504EV@0.1u/10V_4
C190EV@0.1u/10V_4C190EV@0.1u/10V_4
C501EV@0.1u/10V_4C501EV@0.1u/10V_4
C192EV@0.1u/10V_4C192EV@0.1u/10V_4
C203EV@0.1u/10V_4C203EV@0.1u/10V_4
C194EV@0.1u/10V_4C194EV@0.1u/10V_4
C196EV@0.1u/10V_4C196EV@0.1u/10V_4
C208EV@0.1u/10V_4C208EV@0.1u/10V_4
C210EV@0.1u/10V_4C210EV@0.1u/10V_4R1350_4R1350_4
C180EV@0.1u/10V_4C180EV@0.1u/10V_4
C182EV@0.1u/10V_4C182EV@0.1u/10V_4
C204EV@0.1u/10V_4C204EV@0.1u/10V_4
C184EV@0.1u/10V_4C184EV@0.1u/10V_4
C206EV@0.1u/10V_4C206EV@0.1u/10V_4
C502EV@0.1u/10V_4C502EV@0.1u/10V_4
C498EV@0.1u/10V_4C498EV@0.1u/10V_4
To HDMI
C188IV@0.1u/10V_4C188IV@0.1u/10V_4
C189IV@0.1u/10V_4C189IV@0.1u/10V_4
C186IV@0.1u/10V_4C186IV@0.1u/10V_4
C187IV@0.1u/10V_4C187IV@0.1u/10V_4
C219IV@0.1u/10V_4C219IV@0.1u/10V_4
C216IV@0.1u/10V_4C216IV@0.1u/10V_4
C224IV@0.1u/10V_4C224IV@0.1u/10V_4
C222IV@0.1u/10V_4C222IV@0.1u/10V_4
R229IHM@0_4R229IHM@0_4
R94
R95R95
150/F 150/F
1
BOM Option Table
Reference
+1.05V_VCC_PEG
PEG_RXN0(19)
PEG_RXN1(19)
PEG_RXN2(19)
PEG_RXN3(19)
PEG_RXN4(19)
PEG_RXN5(19)
PEG_RXN6(19)
PEG_RXN7(19)
PEG_RXN8(19)
PEG_RXN9(19)
PEG_RXN10(19)
PEG_RXN11(19)
PEG_RXN12(19)
PEG_RXN13(19)
PEG_RXN14(19)
PEG_RXN15(19)
PEG_RXP0(19)
PEG_RXP1(19)
PEG_RXP2(19)
PEG_RXP3(19)
PEG_RXP4(19)
PEG_RXP5(19)
PEG_RXP6(19)
PEG_RXP7(19)
PEG_RXP8(19)
PEG_RXP9(19)
PEG_RXP10(19)
PEG_RXP11(19)
PEG_RXP12(19)
PEG_RXP13(19)
PEG_RXP14(19)
PEG_RXP15(19)
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
TMDSB_DATA2#
TMDSB_DATA2
TMDSB_DATA0#
TMDSB_DATA0
TMDSB_DATA1#
TMDSB_DATA1
TMDSB_CLK#
TMDSB_CLK
Port-B_HPD#PEG_RXP3
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
Date:Sheet of
Description
INT VGAIV@
EXT VGAEV@
IHM@INT HDMI
EV_IV@EV&IV diff. value
PEG_TXN0(19)
PEG_TXN1(19)
PEG_TXN2(19)
PEG_TXN3(19)
PEG_TXN4(19)
PEG_TXN5(19)
PEG_TXN6(19)
PEG_TXN7(19)
PEG_TXN8(19)
PEG_TXN9(19)
PEG_TXN10(19)
PEG_TXN11(19)
PEG_TXN12(19)
PEG_TXN13(19)
PEG_TXN14(19)
PEG_TXN15(19)
PEG_TXP0(19)
PEG_TXP1(19)
PEG_TXP2(19)
PEG_TXP3(19)
PEG_TXP4(19)
PEG_TXP5(19)
PEG_TXP6(19)
PEG_TXP7(19)
PEG_TXP8(19)
PEG_TXP9(19)
PEG_TXP10(19)
PEG_TXP11(19)
PEG_TXP12(19)
PEG_TXP13(19)
PEG_TXP14(19)
PEG_TXP15(19)
TMDSB_DATA2#(20)
TMDSB_DATA2(20)
TMDSB_DATA0#(20)
TMDSB_DATA0(20)
TMDSB_DATA1#(20)
TMDSB_DATA1(20)
TMDSB_CLK#(20)
TMDSB_CLK(20)
12/22 REV_2A Swap net
Port-B_HPD#(20)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
637Friday, March 14, 2008
637Friday, March 14, 2008
1
637Friday, March 14, 2008
1A
1A
1A
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2
1
BOM Option Table
Reference
N/A
Description
N/A
M_A_DQ[63:0](13)
DD
U23D
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AN12
AM13
AJ11
AJ12
AJ9
AJ8
U23D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA_1p2
CANTIGA_1p2
BD21
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
M_A_BS#1
M_A_BS#2
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_BS#0(12,13)
M_A_BS#1(12,13)
M_A_BS#2(12,13)
M_A_RAS#(12,13)
M_A_CAS#(12,13)
M_A_WE#(12,13)
M_A_DM[7:0](13)
M_A_DQS[7:0](13)
M_A_DQS#[7:0](13)
M_A_A[14:0](12,13)
M_A_DQ0 M_A_BS#0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
CC
BB
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ[63:0](13)
U23E
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BH12
BF11
AM2
AM3
AH3
BG8
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AJ3
U23E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CANTIGA_1p2
CANTIGA_1p2
M_B_BS#0
BC16
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_BS#1
M_B_BS#2
M_B_RAS#
M_B_CAS#
M_B_WE#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_BS#0(12,13)
M_B_BS#1(12,13)
M_B_BS#2(12,13)
M_B_RAS#(12,13)
M_B_CAS#(12,13)
M_B_WE#(12,13)
M_B_DM[7:0](13)
M_B_DQS[7:0](13)
M_B_DQS#[7:0](13)
M_B_A[14:0](12,13)
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
5
4
3
2
Date:Sheet of
PROJECT : BL5M Montevina
1A
1A
737Monday, March 10, 2008
737Monday, March 10, 2008
737Monday, March 10, 2008
1
1A
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
5
4
3
2
1
BOM Option Table
Reference
12/19 REV_2A Chanhe net to +1.8VSUS
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
+VGFX_CORE_INT+1.8VSUS
1.8V Internal connect to power
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C449
C460
C460
10u/6.3V_8
10u/6.3V_8
C104
C104
0.1u/10V_4
0.1u/10V_4
C89
C89
IV@0.47u/6.3V_4
IV@0.47u/6.3V_4
+VGFX_CORE_INT
+
+
C43
C43
IV@330u/2.5V_7343
IV@330u/2.5V_7343
NB Power Status and max current table(1/3)
POWER PLANE
VCC(EXT_VGA)
VCC(INT_VGA)
VCC_AXG
VCC_SM(800)(DDRII-667) 2.6A
(See NB EDS Rev:1.0 Section 10.1 for max current)
(See NB EDS Rev:1.0 Section 12.2 for DC voltage)
C62
C62
C57
C57
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
C449
10u/6.3V_8
10u/6.3V_8
C116
C116
0.22u/6.3V_4
0.22u/6.3V_4
C72
C72
IV@1u/16V_6
IV@1u/16V_6
C53
C53
0.22u/6.3V_4
0.22u/6.3V_4
+
+
C42
C42
IV@330u/2.5V_7343
IV@330u/2.5V_7343
S0
O
O
O
O
O XO
C79
C79
0.22u/6.3V_4
0.22u/6.3V_4
S3
X
X
X
O
C61
C61
0.1u/10V_4
0.1u/10V_4
C96
C96
0.22u/6.3V_4
0.22u/6.3V_4
C67
C67
IV@10u/10V_8
IV@10u/10V_8
U23G
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17
T16
Y15
V15
U15
U14
T14
U23G
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
POWER
POWER
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
U23F
AG34
AC34
AB34
AA34
AM33
AK33
AJ33
AG33
AF33
AE33
AC33
AA33
W33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
Y34
V34
U34
Y33
V33
U33
T32
U23F
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
CANTIGA_1p2
CANTIGA_1p2
VCC CORE
VCC CORE
+1.05V_VCC_GMCH
AM32
VCC_NCTF_1
AL32
VCC_NCTF_2
AK32
VCC_NCTF_3
AJ32
VCC_NCTF_4
AH32
VCC_NCTF_5
AG32
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
+VGFX_CORE_INT
+VGFX_CORE_INT
R63IV@10/F_6R63IV@10/F_6
R55IV@10/F_6R55IV@10/F_6
POWER
POWER
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC NCTF
VCC NCTF
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
+1.05V_VCC_GMCH
DD
CC
R134
R134
0_4
0_4
BB
12/19 REV_2A Del R101
+
+
C111
C111
330u/2.5V_7343
330u/2.5V_7343
C113
C113
22u/6.3V_8
22u/6.3V_8
C73
C73
IV@10u/6.3V_8
IV@10u/6.3V_8
Close to GMCH
S4/S5
Voltage
X
X
+1.05V
X
+1.05V
X
+1.8VSUS
Close to each pins
C134
C134
0.47u/10V_6
0.47u/10V_6
+1.8VSUS+1.8VSUS
Close to GMCH
R520_1206R520_1206
+
+
C64
C64
270u/2V_7343
270u/2V_7343
Close to GMCH
C71
C63
C63
IV@0.1u/10V_4
IV@0.1u/10V_4
I(max)
2178mA+1.05V
2899mA
8700mA
3A
C71
IV@0.1u/10V_4
IV@0.1u/10V_4
Note
Graphics Core
1mA+1.8VSUSVCC_SM(Standby)Self Refresh during S3
C144
C144
C133
C133
1u/16V_6
1u/16V_6
1u/16V_6
1u/16V_6
+1.05V+1.05V_VCC_GMCH
See Page 9 EV&IV table
R83
R83
EV@0_6
EV@0_6
R84
R84
EV@0_6
EV@0_6
Place close to the GMCH
and different location
R48IV@0_1206R48IV@0_1206
R100
R100
EV@0_6
EV@0_6
DR8
DR9
IV@
Description
INT VGA
EXT VGAEV@
+1.05V+VGFX_CORE_INT
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially
AA
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
5
2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
and VSS_AXG_SENSE PD with 10ohm for Intel suggest
CANTIGA_1p2
CANTIGA_1p2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
4
3
2
Date:Sheet of
PROJECT : BL5M Montevina
1A
1A
837Tuesday, March 04, 2008
837Tuesday, March 04, 2008
1
837Tuesday, March 04, 2008
1A
5
+
+
IV@0.1u/10V_4
IV@0.1u/10V_4
+3V_A_TV_CRT
C488
C488
C433
C433
IV@0.1u/10V_4
IV@0.1u/10V_4
C434
C434
IV@0.01u/16V_4
IV@0.01u/16V_4
R165
R165
EV@0_4
EV@0_4
R469
R469
EV@0_4
EV@0_4
DR1
DR7
+1.05V
L33IV@BLM18PG181SN1D_6L33IV@BLM18PG181SN1D_6
+3V
C427
C427
IV@10u/10V_8
IV@10u/10V_8
DD
L36IV@10uh_8L36IV@10uh_8
+1.05V
C175
C175
IV@220u/2.5V_7343
IV@220u/2.5V_7343
+1.05VM_DPLLB
R370_6R370_6
+1.05V
+1.05V
CC
+1.05V
+3V
+1.5V
BB
+1.5V
+1.5V
+1.05V
AA
+1.8VSUS
+1.05VM_MCH_PLL2
R390_6R390_6
R1090_6R1090_6
R458IV@0_6R458IV@0_6
R479IV@0_6R479IV@0_6
R4740_6R4740_6
L34IV@BLM18PG181SN1D_6L34IV@BLM18PG181SN1D_6
C457
C457
IV@10u/6.3V_8
IV@10u/6.3V_8
L35BLM18PG181SN1D_6L35BLM18PG181SN1D_6
R484IV@0_6R484IV@0_6
+
+
R440_6R440_6
L5BLM18PG181SN1D_6L5BLM18PG181SN1D_6
C36
C36
C77
C77
100u/10V_7343
100u/10V_7343
*10u/6.3V_8
*10u/6.3V_8
C92
C92
C91
C91
*2.2u/6.3V_6
*2.2u/6.3V_6
10u/6.3V_8
10u/6.3V_8
C432
C432
C431
C431
IV@0.1u/10V_4
IV@0.1u/10V_4
IV@0.01u/16V_4
IV@0.01u/16V_4
C459
C459
IV@0.1u/10V_4
IV@0.1u/10V_4
02/28 REV_3A Modify
C442
C442
C443
C443
0.01u/16V_4
0.01u/16V_4
0.1u/10V_4
0.1u/10V_4
R4901/F_4R4901/F_4
5
C48
C48
4.7u/10V_6
4.7u/10V_6
R42*0.5/F_6R42*0.5/F_6
C49
C49
0.1u/10V_4
0.1u/10V_4
C68
C68
10u/6.3V_8
10u/6.3V_8
C86
C86
0.1u/10V_4
0.1u/10V_4
C446
C446
IV@0.1u/10V_4
IV@0.1u/10V_4
C494
C494
0.1u/10V_4
0.1u/10V_4
C490
C490
10u/10V_8
10u/10V_8
C471
C471
IV@1u/6.3V_4
IV@1u/6.3V_4
C66
C66
4.7u/10V_6
4.7u/10V_6
C50
C50
0.1u/10V_4
0.1u/10V_4
*22u/6.3V_8
*22u/6.3V_8
C60
C60
1u/6.3V_4
1u/6.3V_4
C447
C447
IV@0.01u/16V_4
IV@0.01u/16V_4
C485
C485
0.1u/10V_4
0.1u/10V_4
+1.05VM_HPLL
+1.05VM_MPLL
C38
C38
+1.05VM_MPLL_RC
IV@1000p/50V_4
IV@1000p/50V_4
+1.05VM_A_SM
+1.05VM_A_SM_CK
+3V_TV_DAC
R457
R457
EV@0_4
EV@0_4
DR5
+1.5V_VCC_HDA
R480
R480
IF iHDMI not used,HDA
connect ot GND(DG1.0 P277)
EV@0_4
EV@0_4
DR12
+1.5V_TVDAC
+1.5V_QDAC
R477
R477
EV@0_4
EV@0_4
DR6
+1.05VM_PEGPLL
+1.05VM_PEGPLL_RC
+1.8VSUS_DLVDS
R483
R483
EV@0_4
EV@0_4
DR2
4
+3V_A_TV_CRT
L11IV@10uh_8L11IV@10uh_8
+
+
C130
C130
IV@220u/2.5V_7343
IV@220u/2.5V_7343
C487
C487
4
C437
C437
IV@0.1u/10V_4
IV@0.1u/10V_4
C169
C169
IV@0.1u/10V_4
IV@0.1u/10V_4
C45
C45
0.1u/10V_4
0.1u/10V_4
C436
C436
IV@0.01u/16V_4
IV@0.01u/16V_4
+1.05VM_DPLLA
R164
R164
EV@0_4
EV@0_4
DR10DR11
+1.05VM_DPLLA
+1.05VM_DPLLB
+1.05VM_HPLL
+1.05VM_MPLL
+1.8VSUS_TXLVDS
R4920_8R4920_8
+1.5V
NB Power Status and max current table(2/3)(NB left side)
POWER PLANE
VCCA_CRT_DAC
VCCA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VCCA_PEG_BG414uA+1.5V
VCCA_PEG_PLL50mA+1.05V
VCCA_SM(DDRII-800)
VCCA_SM_CK(800)
VCCA_TV_DAC
VCC_HDA
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS
C492
C492
0.1u/10V_4
0.1u/10V_4
+1.05VM_MCH_PLL2
+1.05VM_PEGPLL
S0
O
O
O
O
O
O
O
OXX
O
O
O
O
O
O
O
O
+1.5V_VCCA_PEG_BG
+1.05VM_PEGPLL
+1.05VM_A_SM
+1.05VM_A_SM_CK
+3V_TV_DAC
+1.5V_VCC_HDA
+1.5V_TVDAC
+1.5V_QDAC
+1.8VSUS_DLVDS
S3
X
X
X
X
X
X
O
X
X
X
X
X
X
X
O
S4/S5
X
X
X
X
X
X
X
XXO
X
X
X
X
X
X
X
XXX
U23H
U23H
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
AD48
VCCA_PEG_BG
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS_1
L37
VCCD_LVDS_2
CANTIGA_1p2
CANTIGA_1p2
Voltage
+3.3V
+3.3V
+1.05V
+1.05V
+1.05V
+1.05V
+1.8VSUS
+1.05V
+1.05V157mA
+1.8VSUS60mA
I(max)
73mA
5mA
64.8mA
64.8mA
24mA
139.2mA
13.2mA
720mA+1.05V
26mA
79mA+3.3V
50mA+1.5V
35mA+1.5V
125uA+1.5V
50mA+1.05V
3
3
CRTPLLA PEGA SM
CRTPLLA PEGA SM
A LVDS
A LVDS
POWER
POWER
A CK
A CK
TV
TV
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
Note
(DDRII-667) 480mA
(DDRII-667) 24mAO
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
DMI
DMI
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT
VTT
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
AXF
VCC_TX_LVDS
VCC_HV_1
VCC_HV_2
VCC_HV_3
HV
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
PEG
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VTTLF1
VTTLF2
VTTLF3
VTTLF
VTTLF
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
C52
C52
0.47u/6.3V_4
0.47u/6.3V_4
C420
C420
2.2u/6.3V_6
2.2u/6.3V_6
+1.05VM_AXF
+1.8VSUS_VCC_SM_CK
+1.8VSUS_TXLVDS
+1.05VM_AXF
B22
B21
A21
+1.8VSUS_VCC_SM_CK
BF21
BH20
BG20
BF20
+1.8VSUS_TXLVDS
K47
+3V_VCC_HV
C35
B35
A35
+1.05V_VCC_PEG
V48
U48
V47
U47
U46
+1.05V_VCC_DMI
AH48
AF48
AH47
AG47
A8
L1
AB2
C47
C47
0.47u/6.3V_4
0.47u/6.3V_4
EXT&INT VGA Power Plane Option table
POWER PLANE
VCCA_CRT_DAC
VCCD_LVDS
VCC_TX_LVDS
VCCA_LVDS
VCCD_TVDAC
VCCA_TV_DAC
VCCD_QDAC
VCCA_DAC_BG
VCC_AXG
VCC_AXG_NCTF
VCCA_DPLLA
VCCA_DPLLB
VCC_HDA
EXT VGA->Disable TV/CRT/LVDS/HDMI(See DG 1.0 P190 Table 103)
INT VGA->Disable TV/Enable CRT( See DG1.0 P208 Table 118)
INT VGA->Disable HDMI(See DG 1.0 P277 section 3.10.4)
C46
C46
0.47u/6.3V_4
0.47u/6.3V_4
EXT VGA
+1.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3V_VCC_HV
0.1u/10V_4
0.1u/10V_4
+1.05V_VCC_PEG
+1.05V_VCC_DMI
C51
C51
0.47u/6.3V_4
0.47u/6.3V_4
INT VGA
+3V
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.5V
+3V
+1.5V
+3V
+1.05V
+1.05V
+1.05V
+1.05V
+1.5V
C463
C463
2
2
C422
C422
4.7u/10V_6
4.7u/10V_6
C429
C429
0.1u/10V_4
0.1u/10V_4
R489
R489
EV@0_4
EV@0_4
DR3
DR4
C164
C164
4.7u/10V_6
4.7u/10V_6
MARK
DR1
DR2
DR3
DR4
DR5
DR6
DR7
Page 8
DR8
DR9 Page 8
DR10
DR11
For iHDMI
DR12
11/01 Del R3432
+1.05V_SD
R4910_8R4910_8
+1.05V
+1.05V
+1.8VSUS
12/19 REV_2A Chanhe net to +1.8VSUS
+1.8VSUS
+1.05V
21
CH751H-40PT
CH751H-40PT
D31
D31
12/22 REV_2A Change D31 P/N
+3V
+1.05V
+1.05V_VCC_PEG
*91nh_32X25
*91nh_32X25
+1.05V
S0
S3
S4/S5
Voltage
X
X
O
O
X
X
O
X
O
O
X
O
O
X
X
O
X
X
O
X
X
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
Date:Sheet of
+
+
C421
C421
C419
C419
270u/2V_7343
270u/2V_7343
4.7u/10V_6
4.7u/10V_6
L310.1uh_8L310.1uh_8
C424
C424
C426
C426
1u/6.3V_4
1u/6.3V_4
*10u/10V_8
*10u/10V_8
L321uh_8L321uh_8
R4521/F_4 R4521/F_4
+1.8VSUS_SMCK_RC
C425
C425
10u/10V_8
10u/10V_8
L38IV@0.1uh_8L38IV@0.1uh_8
C493
C493
C486
C486
IV@1000p/50V_4
IV@1000p/50V_4
IV@10u/6.3V_8
IV@10u/6.3V_8
R48110_4R48110_4
R4820_6 R4820_6
+1.05V_VCC_PEG
C176
C176
+
+
C177
C177
10u/6.3V_8
10u/6.3V_8
220u/2.5V_7343
220u/2.5V_7343
R1830_8R1830_8
C491
C491
0.1u/10V_4
0.1u/10V_4
L37
L37
C482
C482
+
+
C495
C495
*220u/2.5V_7343
*220u/2.5V_7343
*10u/10V_8
*10u/10V_8
NB Power Status and max current table(3/3)(NB Right side)
POWER PLANE
VTT
VCCA_AXF
VCC_SM_CK(800)
VCC_TX_LVDS
VCC_HV
VCC_PEG
VCC_DMI
(See NB EDS Rev:1.0 Section 10.1 for max current)
(See NB EDS Rev:1.0 Section 12.2 for DC voltage)
1
BOM Option Table
Reference
IHM@INT HDMI
I(max)
FSB at 1067MHz
852mA
+1.05V
322mA
+1.05V
124mA
+1.8VSUS
+1.8VSUS
+3V
+1.05V
+1.05V
(DDRII-667) 120mA
119mA
106mA
1782mA
456mA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
1
Description
INT VGAIV@
EXT VGAEV@
Note
937Tuesday, March 04, 2008
937Tuesday, March 04, 2008
937Tuesday, March 04, 2008
1A
1A
1A
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
5
4
3
2
1
BOM Option Table
U23J
U23I
U23I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
AF47
VSS_8
DD
CC
BB
AA
5
AD47
AB47
BD46
BA46
AY46
AV46
AR46
AM46
BF44
AH44
AD44
AA44
BC43
AV43
AU43
AM43
BG42
AY42
AT42
AN42
AJ42
AE42
BD41
AU41
AM41
AH41
AD41
AA41
BG40
BB40
AV40
AN40
AT39
AM39
AJ39
AE39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
BF37
BB37
AW37
AT37
AN37
AJ37
BG36
BD36
AK15
AU36
G47
V46
R46
P46
H46
F46
Y44
U44
T44
M44
F44
C43
N42
Y41
U41
T41
M41
G41
B41
H40
E40
N39
B39
Y38
U38
T38
F38
C38
H37
C37
Y47
T47
N47
L47
J43
L42
L39
J38
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CANTIGA_1p2
CANTIGA_1p2
VSS
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
4
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
BG21
AW21
AU21
AP21
AN21
AH21
AF21
AB21
BC20
BA20
AW20
AT20
AJ20
AG20
BG19
BG17
BC17
AW17
AT17
BA16
AU16
AN16
BG15
AC15
W15
BG14
AA14
BG13
BC13
BA13
AN13
AJ13
AE13
BF12
AV12
AT12
AM12
AA12
BD11
BB11
AY11
AN11
AH11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BC9
AN9
AM9
AD9
BH8
R21
M21
G21
Y20
N20
K20
F20
C20
A20
A18
R17
M17
H17
C17
N16
K16
G16
E16
A15
C14
N13
G13
E13
A12
Y11
N11
G11
C11
BF9
BB8
AV8
AT8
L12
J21
L13
J12
G9
B9
U23J
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
CANTIGA_1p2
CANTIGA_1p2
3
VSS
VSS
VSS NCTF
VSS NCTF
VSS SCB
VSS SCB
NC
NC
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_6
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AJ6
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A47
MCH_VSS_351
MCH_VSS_352
MCH_VSS_353
MCH_VSS_354
MCH_VSS_355
R1060_4R1060_4
R1200_4R1200_4
R970_4R970_4
R1300_4R1300_4
R460_4R460_4
2
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
Date:Sheet of
Reference
N/A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
1
Description
1037Tuesday, March 04, 2008
1037Tuesday, March 04, 2008
1037Tuesday, March 04, 2008
N/A
1A
1A
1A
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
5
North Bridge Strap Pin Configuration Table
(See DG 1.0 P295 Table 184)
(See NB EDS 1.0 P187 Table 74)
Pin Name
DD
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CC
CFG10
CFG11
CFG12
CFG13
CFG[15:14]
CFG16
CFG[18:17]
BB
CFG19
CFG20
SDVO_CTRLDATA
L_DDC_DATA
DDPC_CTRLDATA
FSB Frequency Select
Reserved
DMI X2 Select
iTPM Host Interface
ME TLS Confidentiality
Reserved
PCI Express Graphics
Lane Reversal
PCIE Loopback enable
Reserved
ALLZ
XOR
Reserved
FSB Dynamic ODT
Reserved
DMI Lane Reversal
Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIE
SDVO Present
Local Flat Panel(LFP) Present
Digital Display Present
[000]= FSB 1066MHz [010] = FSB 800MHz [011] = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = iTPM Host Interface is enabled
1 = iTPM Host Interface is disabled(Default)
0 = AMT Firmware will use TLS cipher suite with no confidentiality
1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)
0 = Reverse Lanes
1 = Normal operation(Default)
0 = Enabled
1 = Disabled (Default)
0 = ALLZ mode enable
1 = disable(Default)
0 = XOR mode enable
1 = disable(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = Normal (Default)
1 = Lanes Reversed
0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is
operational (Default)
1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating
simultaneously via PEG port
0 = No SDVO/HDMI/DP Device Present(Default)
1 = SDVO/HDMI/DP Device present
0 = LFP Disable(Default)
1 = LFP Card Present;PCIE disable
0 = Digital display(HDMI/DP) device absent(Default)
1 = Digital display(HDMI/DP) device present
4
3
2
1
BOM Option Table
Reference
N/A
Description
N/A
PU<4.02K> PD <2.21K>ConfigurationStrap descriptionNote
See Page 2 FSB selection table
MCH_CFG_5(6)
MCH_CFG_6(6)
MCH_CFG_7(6)
MCH_CFG_9(6)
MCH_CFG_10(6)
MCH_CFG_12(6)
MCH_CFG_13(6)
MCH_CFG_16(6)
MCH_CFG_19(6)
MCH_CFG_20(6)
SDVO_CTRLDATA(6,20)
INT_LVDS_EDIDDATA(6,18)
DDPC_CTRLDATA(6)
R93*4.02K/F_4R93*4.02K/F_4
R99*10K/F_4R99*10K/F_4
R98*4.02K/F_4R98*4.02K/F_4
R454*4.02K/F_4R454*4.02K/F_4
R455*4.02K/F_4R455*4.02K/F_4
R76*4.02K/F_4R76*4.02K/F_4
R77*4.02K/F_4R77*4.02K/F_4
R75*4.02K/F_4R75*4.02K/F_4
R72*4.02K/F_4R72*4.02K/F_4
R73*4.02K/F_4R73*4.02K/F_4
R146*2.2K/F_4R146*2.2K/F_4
R166*2.2K/F_4R166*2.2K/F_4
R71*2.2K/F_4R71*2.2K/F_4
+3V
+3V
+3V
+3V
+3V
Enable iTPM Table
AA
PAGE
11
13
14
Net Name
MCH_CFG_6
SPI_MOSI
CLGPIO5
PU & PD NOTE
PD 10K to GND
PU 20K to +3V_S5SB Strap pin
PU 10K to +3V_S5SB Strap pin
5
NB Strap pin
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date:Sheet of
Date:Sheet of
4
3
2
Date:Sheet of
PROJECT : BL5M Montevina
1A
1A
1137Monday, March 10, 2008
1137Monday, March 10, 2008
1137Monday, March 10, 2008
1
1A
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
1
DDR2 Dual channel A/B PU
2
3
4
5
6
7
8
AA
DDRII A CHANNELDDRII B CHANNEL
+SMDDR_VTERM +SMDDR_VTERM
C156
C156
C135
C83
C83
0.1u/10V_4
0.1u/10V_4
BB
CC
DD
C90
C90
C131
C131
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
M_CKE1(6,13)
M_A_BS#2(7,13)
M_CKE0(6,13) M_A_BS#0(7,13)
M_A_BS#1(7,13)
M_B_BS#0(7,13)
M_B_BS#1(7,13)
M_B_BS#2(7,13)
C168
C168
0.1u/10V_4
0.1u/10V_4
M_A_A3
M_A_A1
M_A_A9
M_A_A8
M_A_A2
M_A_A4
M_A_A6
M_A_A5
M_A_A12
M_A_A0
M_B_A10
M_B_A3
M_B_A5
M_B_A0
M_B_A7
M_B_A11
M_B_A8
M_B_A1
M_B_A4
M_B_A2
M_B_A12
C125
C125
C150
C150
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
RP1756X2RP1756X2
1
3
RP2256X2RP2256X2
1
3
RP2056X2RP2056X2
1
3
RP2956X2RP2956X2
1
3
RP2556X2RP2556X2
1
3
RP3056X2RP3056X2
1
3
RP1556X2RP1556X2
1
3
RP1456X2RP1456X2
1
3
RP1956X2RP1956X2
1
3
RP1356X2RP1356X2
1
3
RP2156X2RP2156X2
1
3
RP2456X2RP2456X2
1
3
RP1856X2RP1856X2
1
3
RP2656X2RP2656X2
1
3
C85
C85
0.1u/10V_4
0.1u/10V_4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
C94
C94
0.1u/10V_4
0.1u/10V_4
C135
0.1u/10V_4
0.1u/10V_4
+SMDDR_VTERM
+SMDDR_VTERM
0.1u/10V_4
0.1u/10V_4
M_A_A[13..0]
M_B_A[13..0]
C84
C84
0.1u/10V_4
0.1u/10V_4
C157
C157
0.1u/10V_4
0.1u/10V_4
M_A_A[13..0](7,13)
M_B_A[13..0](7,13)
C87
C87
0.1u/10V_4
0.1u/10V_4
C171
C143
C143
C88
C88
C102
C167
C167
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
M_A_A7
M_A_A11
M_CKE3(6,13)
M_ODT1(6,13)
M_CS#1(6,13)
M_ODT3(6,13)
M_CS#3(6,13)
M_A_WE#(7,13)
M_A_CAS#(7,13)
M_CS#0(6,13)
M_A_RAS#(7,13)
M_B_WE#(7,13)
M_B_CAS#(7,13)
M_CKE4(6,13)
M_ODT2(6,13)
M_B_RAS#(7,13)
M_ODT0(6,13)
M_CS#2(6,13)
M_B_A9
M_A_A10
M_B_A6
M_A_A13
M_B_A13
C102
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
RP2356X2RP2356X2
RP3156X2RP3156X2
RP656X2RP656X2
RP756X2RP756X2
RP1656X2RP1656X2
RP1256X2RP1256X2
RP1156X2RP1156X2
RP1056X2RP1056X2
RP2856X2RP2856X2
RP956X2RP956X2
RP556X2RP556X2
RP856X2RP856X2
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
C93
C93
0.1u/10V_4
0.1u/10V_4
C152
C152
0.1u/10V_4
0.1u/10V_4
+SMDDR_VTERM
C163
C163
0.1u/10V_4
0.1u/10V_4
C171
0.1u/10V_4
0.1u/10V_4
C124
C124
0.1u/10V_4
0.1u/10V_4
C101
C101
0.1u/10V_4
0.1u/10V_4
C147
C147
0.1u/10V_4
0.1u/10V_4
C158
C158
0.1u/10V_4
0.1u/10V_4
C122
C122
0.1u/10V_4
0.1u/10V_4
M_A_A14(7,13)
M_B_A14(7,13)
1
R15156_4R15156_4
R14856_4R14856_4
2
+SMDDR_VTERM
3
4
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5M Montevina
PROJECT : BL5M Montevina
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
DDR RES. ARRAY
DDR RES. ARRAY
DDR RES. ARRAY
Date:Sheet of
Date:Sheet of
5
6
Date:Sheet of
7
PROJECT : BL5M Montevina
1A
1A
1237Monday, March 10, 2008
1237Monday, March 10, 2008
1237Monday, March 10, 2008
8
1A
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