Toshiba M55 Schematics

A

1 1

B

C

D

E

Boston

LA-2721 Schematics Document

2 2

Intel Dothan / Alviso GM(PM) / DDR-1 / ICH6-M

(nVIDIA NV44MV / ATi M24C)

Rev:1.0

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

Boston LA-2721

下午

E

of

1532005/5/6 11:47:55

1.0

A

B

C

D

E

Compal confidential

File Name : LA-2721

CRT/TV-OUT

1 1

page 15

Fan Conn

page 38

Intel Dothan CPU

page 4,5

H_A#(3..31) H_D#(0..63)

FSB

400 / 533 Mhz

Thermal Se nsor
ADM1032ARM

page 4

Clock Generator
ICS954226

page 14

NV44MV/M24C

VGA Board

page 16

LCD CONN

page 16

Intel Alviso
GM( GML,PM)

PCBGA 1257

page 6,7,8,9,10

DMI

DDR-1

333 Mhz

Signal Channel DDR-1

DDR-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12,13

Docking
Audio

page 31

AMP & Audio Jack

page 32

MARVELL LAN

2 2

IDSEL:PCI_AD18
GNT#1
REQ#1
IRQG#
IRQH#

Mini PCI
socket

page 29

3 3

page 28

IDSEL: PCI_AD20
GNT#2
REQ#2
IRQA#
IRQB#
IRQC#
IRQD#

1394
Conn.

page 24

88E8036RJ45 CONN
88E8053

page 27

PCI BUS

TI Controller

PCI7411/6411/4510/1510

Slot 0

page 26

5in1 CardReader
Slot

Power On/Off CKT.

page 39

DC/DC Interface CKT.

page 42

Power Circuit DC/DC

4 4

page 44~50

RTC CKT.

page 41

Power OK CKT.

page 41

PCI-E BUS

page 23,24

page 25

SMsC LPC47N217
LPC47N207

page 33,34

FIR

page 38

Intel ICH6-M

mBGA-609

page 17,18,19,20

LPC BUS

ENE KB910

Touch Pad
CONN.

page 36

USB 2.0

USB 2.0

AC-LINK

SATA

PATA

page 35

USB conn x 4

Audio CKT
ALC250-D

Int. KBD

page 36

BIOS

page 37

page 39

BT Conn

MDC

page 36

page 30

page 35

SATA to PATA

88SA8040

page 21

CDROM
Connector

page 22

PATA HDD

conn

page 21

Docking CONN.

*RJ-11 / 45(LED*2)
*COMPOSITE Video Out
*LINE IN / OUT
*PS/2
*Print port
*1394
*USB
*DC JACK

page 39

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

Boston LA-2721

下午

E

of

2532005/5/6 11:47:56

1.0

A

Voltage Rails

Power Plane Description

1 1

2 2

VIN
B+
+CPU_CORE
+1.05VS
+DDRVTT 1.25V switched power rail for DDR terminator
+1.5VALW 1.5V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+DDRVCC
+2.5VS
+3VALW
+3V
+3VS
+5VALW
+5VS
+5VCD 5V switched power rail for CDROM
+12VALW 12V always on power rail
+RTC V C C RTC power
+5VAMP 5V switched power rail for amplifier O N OFF OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC or batte ry power rail for power circuit.
Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

2.5V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S5

N/A N/A N/A

ON OFF
ON OFF
ON OFF OF F
ON
ON OFF OF F
ON OFF OF F
ON
ON
ON
ON
ON
ON

ON ONON

N/AN/AN/A
OFF
OFF

ON*ON

OFF

ON

OFF

OFF
ON ON*

OFF

ON
OFF

OFF

ON

ON*

OFF

OFFON
OFF OFFON
ONON ON*

C

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

D

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 1%Ra/Rc/Re

Rb / Rd / Rf V min

AD_BID

0

8.2K +/- 1%
18K +/- 1%
33K +/- 1%
56K +/- 1%
100K +/- 1%
200K +/- 1%

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

E

SLP_S4# SLP_S5# +VA LW +V +VS Clock

0 V

HIGH

LOWLOWLOW

ON

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

ON

Vtyp

AD_BID

0 V 0.100 V

0.503 V

0.819 V

ON

ON

ON

OFF

OFF

V

AD_BID

0.538 V

0.875 V

ON ON

ON

OFF

OFF

OFF

max

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

LOW

OFF

OFF

OFF

BOARD ID Table

External PCI Devices

Device IDSEL # REQ # / GNT # Interrupts

CardBus
1394
Card reader
Mini-PCI

AD20
AD20
AD20
AD18

2
2
2
1

PIRQA/PIRQB/PIRQC/PIRQD
PIRQA/PIRQB/PIRQC/PIRQD
PIRQA/PIRQB/PIRQC/PIRQD
PIRQG/PIRQH

0
1
2
3
4
5
6

Board ID

3 3

7

PCB Revision

0.1

0.2

0.3

1.0

SKU ID Table

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b
1011 000Xb

EC SM Bus2 address

Device

ADM1032
2'nd Battery
Docking

1001 110X b0001 011X b
1001 011X b
1010 000X b

SKU_ID

0
1
2
3

SKU_ID1

10
10C
10G
10GC

1
Button

0123456

1

5
7

3
Button

8
C
9

D

4
5
6

ICH6M SM Bus address

Device

4 4

Clock Generator
( ICS 952623)

DDR DIMM0

DDR DIMM1

A

Address

1101 001Xb

1001 000Xb
1001 001Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

C

7

Compal Secret Data

Deciphered Date

D

7
Button

0
23
4
6

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes

Boston LA-2721

下午

E

of

3532005/5/6 11:47:55

1.0

5

H_A#[3..31]<6>

D D

H_REQ#[0..4]<6>

C C

H_RS#[0..2]<6>

B B

A A

H_A#[3..31]

H_REQ#[0..4]

H_RS#[0..2]

H_ADSTB#0<6>
H_ADSTB#1<6>

CLK_CPU_BCLK<14>
CLK_CPU_BCLK#<14>

H_ADS#<6>
H_BNR#<6>

H_BPRI#<6>

H_BR0#<6>

H_DEFER#<6>

H_DRDY#<6>

H_HIT#<6>
H_HITM#<6>

H_LOCK#<6>

H_CPURST#<6>

H_TRDY#<6>

H_DBSY#<6>
H_DPSLP#<18>
H_DPRSTP#<18>
H_DPWR#<6>

H_PWRGOOD<18>
H_CPUSLP#<6,18>

H_THERMTRIP#<6,18>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_IERR#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2

ITP_DBRRESET#

PRO_CHOT#
H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

THERMDA
THERMDC

AA3
AA2

AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

AE5

A16
A15

B15
B14

B11

C19
A10
B10
B17

A13
C12
A12

F23
C11
B13

B18
A18
C17

W1
W2

M3

M2
G1

4

JP23A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#
A8#

T4

A9#
A10#

Y4

A11#

Y1

A12#

U1

A13#
A14#

Y3

A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#

ADDR GROUP

A25#
A26#
A27#
A28#
A29#
A30#
A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#
ADSTB1#

ITP_CLK0
ITP_CLK1

BCLK0

HOST CLK

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4
A4

J2

H1
K1
L2

C8
B8
A9
C9

A7
B7

E4
A6

C5

CONTROL GROUP

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO

TYCO_1612365-1_Dothan

TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC
THERMTRIP#

Dothan

MISC

THERMAL
DIODE

DATA GROUP

LEGACY CPU

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#

FERR#

IGNNE#

INIT#

LINT0
LINT1

STPCLK#

SMI#

A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR

NMI

H_STPCLK#

H_SMI#

3

H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>

H_DSTBN#0 <6>
H_DSTBN#1 <6>
H_DSTBN#2 <6>
H_DSTBN#3 <6>
H_DSTBP#0 <6>
H_DSTBP#1 <6>
H_DSTBP#2 <6>
H_DSTBP#3 <6>

H_A20M# <18>
H_FERR# <18>
H_IGNNE# <18>
H_INIT# <18>
H_INTR <18>

H_STPCLK# <18>
H_SMI# <18>

H_D#[0..63]

2200P_0402_50V7K

EC_SMB_CK2<30,35,40>

EC_SMB_DA2<30,35,40>

R614 0_0402_5%

12

2

H_D#[0..63] <6>

1

C553

THERMDA

2

THERMDC

Reserve for debug
C677 close to South Bridge (U13)

H_NMI <18>

Reserve for debug
C675, C678, C679, C681 ~ C686
close to CPU (JP13)

U37

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

ITP_TDI
ITP_TDO
H_CPURST#
ITP_TMS
PRO_CHOT#
H_PWRGOOD
H_IERR#

ITP_DBRRESET#

ITP_TRST#

ITP_TCK
TEST1
TEST2

H_SMI#
H_INIT#

NMI
H_A20M#
H_INTR
H_IGNNE#

H_STPCLK#

H_PWRGOOD

H_CPUSLP#

+3VS

1

C552

0.1U_0402_16V4Z

2

1

VDD1

6

ALERT#

4

THERM#

5

GND

R73 150_0402_5%
R74 54.9_0402_1%@
R72 54.9_0402_1%@
R71 39.2_0603_1%
R77 56_0402_5%
R67 200_0402_5%
R69 56_0402_5%

R70 150_0402_5%

R75 680_0402_5%
R76 27.4_0402_1%
R68 1K_0402_5%@
R65 1K_0402_5%@

H_FERR#

C677 220P_0402_50V8J

C678 180P_0402_50V8J@
C679 180P_0402_50V8J@
C675 680P_0402_50V8J
C681 180P_0402_50V8J@
C682 180P_0402_50V8J@
C683 180P_0402_50V8J@
C684 180P_0402_50V8J@
C685 180P_0402_50V8J@
C686 180P_0402_50V8J@

12

12
12
12
12
12
12
12
12
12

1

12

R490

10K_0402_5%@

+1.05VS

12
12
12
12
12
12
12

+3VS

12

12
12
12
12

THERMDA & THERMDC Trace / Space = 10 / 10 mil

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

Boston LA-2721

下午

1

of

4532005/5/6 11:47:59

1.0

5

JP23B

1

2

+1.05VS

C500

VCCSENSE
VSSSENSE

GTL_REF0

COMP0
COMP1
COMP2
COMP3

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

COMP0
COMP1
COMP2
COMP3

Dothan

R390 54.9_0402_1%@

1 2

R391 54.9_0402_1%@

1 2

+VCCA

D D

1.5V FOR DOTHAN-B

1 2

+1.5VS

R454 0_1206_5%

1

C501

2

0.01U_0402_16V7K

C C

+1.05VS

R388
1K_0402_1%

B B

A A

1 2

R389 2K_0402_1%

10U_0805_6.3V6M

+CPU_CORE

PSI#<50>
CPU_VID0<50>

CPU_VID1<50>
CPU_VID2<50>

12

CPU_VID3<50>
CPU_VID4<50>
CPU_VID5<50>

CPU_BSEL0<14>
CPU_BSEL1<14>

R444 27.4_0402_1%

1 2

R441 54.9_0402_1%

1 2

R392 27.4_0402_1%

1 2

R393 54.9_0402_1%

1 2

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils

5

4

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

+1.05VS

1

+

2

150U_D2_6.3VM

POWER, GROUNG, RESERVED SIGNALS AND NC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

Vcc-core
Decoupling

SPCAP,Polymer
MLCC 0805 X5R

0.1U_0402_16V4Z

1

C72

C431

2

+CPU_CORE

1

+

C38

2

330U_D_2VM

+CPU_CORE

10U_0805_6.3V6M

1

C464

2

+CPU_CORE

10U_0805_6.3V6M

1

C495

2

+CPU_CORE

10U_0805_6.3V6M

1

C436

2

+CPU_CORE

10U_0805_6.3V6M

1

C84

2

+CPU_CORE

10U_0805_6.3V6M

1

C83

2

1

2

0.1U_0402_16V4Z

3

+

C64
330U_D_2VM

10U_0805_6.3V6M

1

C463

2

10U_0805_6.3V6M

1

C475

2

10U_0805_6.3V6M

1

C485

2

10U_0805_6.3V6M

1

C57

2

10U_0805_6.3V6M

1

C54

2

330U_D_2VM

1

+

C43

2

1

1

C498

2

2

10U_0805_6.3V6M

1

1

C479

2

2

10U_0805_6.3V6M

1

1

C462

2

2

10U_0805_6.3V6M

1

1

C80

2

2

10U_0805_6.3V6M

1

1

C82

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C497

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C70

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C494

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C56

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C79

2

10U_0805_6.3V6M

C496

C71

C60

C55

C58

1

2

1

2

1

2

1

2

1

2

1

C465

2

10U_0805_6.3V6M

1

C474

2

10U_0805_6.3V6M

1

C435

2

10U_0805_6.3V6M

1

C434

2

10U_0805_6.3V6M

1

C78

2

10U_0805_6.3V6M

1

2

C466

C478

C484

C81

C59

C,uF ESR, mohm ESL,nH

3X330uF 7m ohm/2 3.5nH/2
35X10uF 5m ohm/35 0.6nH/35

1

C67

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C62

2

Compal Secret Data

0.1U_0402_16V4Z

1

C73

2

2005/05/06 2006/05/06

3

1

C65

2

0.1U_0402_16V4Z

Deciphered Date

0.1U_0402_16V4Z

1

C77

C75

2

1

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C61

C66

2

2

+CPU_CORE

1

C53

2

0.1U_0402_16V4Z

1

JP23C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22
AA5
AA7

AA9
AA11
AA13
AA15
AA17
AA19
AA21

AB6

AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC9
AC11
AC13
AC15
AC17
AC19

AD8
AD10
AD12
AD14
AD16
AD18

AE9
AE11
AE13
AE15
AE17
AE19

AF8
AF10
AF12
AF14
AF16
AF18

M4

M5
M21
M24

N3

N6
N22
N23
N26

P2

P5
P21
P24

R1
R4

R6
R22
R25

T3

T5
T21
T23

TYCO_1612365-1_Dothan

Title

Dothan Processor in mFCPGA479

Size Document Number Rev

Date: Sheet of

Dothan

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Compal Electronics, Inc.

Boston LA-2721

下午

T26

VSS

U2

VSS

U6

VSS

U22

VSS

U24

VSS

V1

VSS

V4

VSS

V5

VSS

V21

VSS

V25

VSS

W3

VSS

W6

VSS

W22

VSS

W23

VSS

W26

VSS

Y2

VSS

Y5

VSS

Y21

VSS

Y24

VSS

AA1

VSS

AA4

VSS

AA6

VSS

AA8

VSS

AA10

VSS

AA12

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA20

VSS

AA22

VSS

AA25

VSS

AB3

VSS

AB5

VSS

AB7

VSS

AB9

VSS

AB11

VSS

AB13

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB23

VSS

AB26

VSS

AC2

VSS

AC5

VSS

AC8

VSS

AC10

VSS

AC12

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC21

VSS

AC24

VSS

AD1

VSS

AD4

VSS

AD7

VSS

AD9

VSS

AD11

VSS

AD13

VSS

AD15

VSS

AD17

VSS

AD19

VSS

AD22

VSS

AD25

VSS

AE3

VSS

AE6

VSS

AE8

VSS

AE10

VSS

AE12

VSS

AE14

VSS

AE16

VSS

AE18

VSS

AE20

VSS

AE23

VSS

AE26

VSS

AF2

VSS

AF5

VSS

AF9

VSS

AF11

VSS

AF13

VSS

AF15

VSS

AF17

VSS

AF19

VSS

AF21

VSS

AF24

VSS

5532005/5/6 11:47:54

1

1.0

5

H_RS#[0..2]

H_A#[3..31]<4>
H_REQ#[0..4]<4>

D D

C C

CLK_MCH_BCLK#<14>
CLK_MCH_BCLK<14>

B B

A A

(5mil:15mil) (12mil:10mil)

H_VREF H_XSWING

1

C414

0.1U_0402_16V4Z

2

H_A#[3..31]
H_REQ#[0..4]

H_ADSTB#0<4>
H_ADSTB#1<4>

H_DSTBN#0<4>
H_DSTBN#1<4>
H_DSTBN#2<4>
H_DSTBN#3<4>
H_DSTBP#0<4>
H_DSTBP#1<4>
H_DSTBP#2<4>
H_DSTBP#3<4>
H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

H_CPURST#<4>
H_ADS#<4>

H_TRDY#<4>

H_DPWR#<4>
H_DRDY#<4>

H_DEFER#<4>

H_HITM#<4>
H_HIT#<4>
H_LOCK#<4>
H_BR0#<4>
H_BNR#<4>

H_BPRI#<4>

H_DBSY#<4>

H_CPUSLP#<4,18>

+1.05VS

12

R387
100_0603_1%

12

R385
200_0603_1%

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_RS#[0..2] <4>

U4A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

Alviso

ALVISO_BGA1257R3PM@

1

C437

0.1U_0402_16V4Z

2

HOST

HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF

+1.05VS

12

12

R395
221_0603_1%

R394
100_0603_1%

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

J11
C1
C2
T1
L1
D1
P1

4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_XSWING
H_YSWING

H_D#[0..63]

Reserve for DDR2

+DDRVCC

R54 24.9_0402_1%
R53 54.9_0402_1%
R56 24.9_0402_1%
R55 54.9_0402_1%

1 2
1 2

12
12

H_D#[0..63] <4>

R352 40.2_0402_1%@

1 2

R368 40.2_0402_1%

1 2

@

R384 80.6_0402_1%

1 2

R386 80.6_0402_1%

1 2

+1.05VS

3

DMI_ITX_MRX_N0<19>
DMI_ITX_MRX_N1<19>
DMI_ITX_MRX_N2<19>
DMI_ITX_MRX_N3<19>

DMI_ITX_MRX_P0<19>
DMI_ITX_MRX_P1<19>
DMI_ITX_MRX_P2<19>
DMI_ITX_MRX_P3<19>

DMI_MTX_IRX_N0<19>
DMI_MTX_IRX_N1<19>
DMI_MTX_IRX_N2<19>
DMI_MTX_IRX_N3<19>

DMI_MTX_IRX_P0<19>
DMI_MTX_IRX_P1<19>
DMI_MTX_IRX_P2<19>
DMI_MTX_IRX_P3<19>

DDRA_CLK1<11>
DDRA_CLK2<11>

DDRB_CLK1<12>
DDRB_CLK2<12>

DDRA_CLK1#<11>
DDRA_CLK2#<11>

DDRB_CLK1#<12>
DDRB_CLK2#<12>

DDRA_CKE0<11>
DDRA_CKE1<11>
DDRB_CKE0<12>
DDRB_CKE1<12>

DDRA_SCS#0<11>
DDRA_SCS#1<11>
DDRB_SCS#0<12>
DDRB_SCS#1<12>

(10mil:20mil)

H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil

+1.05VS

12

R399
221_0603_1%

4

H_YSWING

1

C443

0.1U_0402_16V4Z

2

(12mil:10mil)

12

R397
100_0603_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

U4B

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

DDRA_SCS#0
DDRA_SCS#1
DDRB_SCS#0
DDRB_SCS#1

M_OCDCOMP0
M_OCDCOMP1

M_RCOMPN
M_RCOMPP
SMVREF

M_XSLEW
M_YSELW

+DDRVCC

R398

1K_0402_1%

R396

1K_0402_1%

2005/05/06 2006/05/06

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

ALVISO_BGA1257

R3PM@

12

0.1U_0402_16V4Z

12

C445

1

2

Compal Secret Data

Deciphered Date

DMIDDR MUXING

DREF_SSCLKP
DREF_SSCLKN

SMVREF

1

C450

0.1U_0402_16V4Z

2

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN

DREF_CLKP

CLK

NC

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11

2

CLK_DREF_SSC
CLK_DREF_SSC#

CFG0

G16

MCH_CLKSEL1

H13

MCH_CLKSEL0

G14
F16
F15

CFG5

G15

CFG6

E16

CFG7

D17
J16

CFG9

D15
E15
D14

CFG12

E14

CFG13

H12
C14
H15

CFG16 CFG6

J15
H14

CFG18

G22

CFG19

G23
D23
G25
G24
J17
A31
A30
D26
D25

J23

EXT_TS#0

J21

EXT_TS#1

H22

H_THERMTRIP#

F5
AD30
AE29

CLK_DREF_96M#

A24

CLK_DREF_96M

A23

CLK_DREF_SSC

D37

CLK_DREF_SSC#

C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG[2:0]
CFG5
CFG6
CFG7

CFG9

CFG[13:12]

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

Title

Size Document Number Rev

Date: Sheet of

1

R32 0_0402_5%VGA@

1 2

R33 0_0402_5%VGA@

1 2

MCH_CLKSEL1 <14>
MCH_CLKSEL0 <14>

CFG0

R378 10K_0402_5%

1 2

CFG5

R371 1K_0402_5%@

1 2

R373 1K_0402_5%@

CFG7
CFG9
CFG12
CFG13
CFG16

1 2

R361 1K_0402_5%@

1 2

R376 1K_0402_5%@

1 2

R382 1K_0402_5%@

1 2

R381 1K_0402_5%@

1 2

R377 1K_0402_5%@

1 2

CFG[17:3]: internal pull-up

CFG18

R46 1K_0402_5%@

CFG19

1 2

R45 1K_0402_5%@

1 2

CFG[19:18]: internal pull-down

PM_BMBUSY# <19>

H_THERMTRIP# <4,18>

VGATE <14,19,50>

PLT_RST# <16,17,19,21,22,24,27,34,35>

CLK_DREF_96M# <14>

CLK_DREF_96M <14>

CLK_DREF_SSC <14>

CLK_DREF_SSC# <14>

EXT_TS#0

R354 10K_0402_5%

EXT_TS#1

1 2

R351 10K_0402_5%

1 2

Refer to sheet 14 for FSB
frequency select
Low = DMI x 2

High = DMI x 4
Low = DDR-II

High = DDR-I
Low = DT/Transportable CPU

High = Mobile CPU
Low = Reverse Lane

High = Normal Operation
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V

Low = 1.05V (Default)
High = 1.2V

Compal Electronics, Inc.

Alviso HOST(1/5)
Boston LA-2721

下午

1

+1.5VS

+1.05VS

+2.5VS

+2.5VS

*
*

*

*

*

*

*

*

1.0

6532005/5/6 11:47:58

5

4

3

2

1

DDRA_SDQ[0..63]<11>

DDRA_SDM[0..7]<11>

DDRA_SDQS[0..7]<11>

D D

C C

B B

DDRA_SMA[0..13]<11>

DDRA_SBS0<11>
DDRA_SBS1<11>

DDRA_SCAS#<11>
DDRA_SRAS#<11>

DDRA_SWE#<11>

DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SDQS[0..7]
DDRA_SMA[0..13] DDRB_SMA[0..13]

AK15

SA_BS0#

AK16

SA_BS1#

AL21

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13 DDRB_SMA13

AJ37

AP35

AL29

AP24

AP9
AP4

AJ2

AD3

AK36
AP33
AN29
AP23

AM8
AM4

AJ1

AE5

AK35
AP34
AN30
AN23

AN8
AM5
AH1

AE4

AL17
AP17
AP18
AM17
AN18
AM18

AL19
AP20
AM19

AL20
AM16
AN20
AM20
AM15

AN15
AP16

AF29

AF28
AP15

SA_BS2#
SA_DM0

SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

U4C

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257R3PM@

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

DDRB_SMA[0..13]<12>

DDRB_SBS0<12>
DDRB_SBS1<12>

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12

DDRB_SCAS#<12>
DDRB_SRAS#<12>

DDRB_SWE#<12>

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23
AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14

AF15

AF14
AH16

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

U4D

AE31

SBDQ0

AE32

SBDQ1

AG32

SBDQ2

AG36

SBDQ3

AE34

SBDQ4

AE33

SBDQ5

AF31

SBDQ6

AF30

SBDQ7

AH33

SBDQ8

AH32

SBDQ9

AK31

SBDQ10

AG30

SBDQ11

AG34

SBDQ12

AG33

SBDQ13

AH31

SBDQ14

AJ31

SBDQ15

AK30

SBDQ16

AJ30

SBDQ17

AH29

SBDQ18

AH28

SBDQ19

AK29

SBDQ20

AH30

SBDQ21

AH27

SBDQ22

AG28

SBDQ23

AF24

SBDQ24

AG23

SBDQ25

AJ22

SBDQ26

AK22

SBDQ27

AH24

SBDQ28

AH23

SBDQ29

AG22

SBDQ30

AJ21

SBDQ31

AG10

SBDQ32

AG9

SBDQ33

AG8

SBDQ34

AH8

SBDQ35

AH11

SBDQ36

AH10

SBDQ37

AJ9

SBDQ38

AK9

SBDQ39

AJ7

SBDQ40

AK6

SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR SYSTEM MEMORY B

ALVISO_BGA1257R3PM@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Alviso DDR(2/5)
Boston LA-2721

下午

7532005/5/6 11:47:55

1

1.0

5

+3VS +2.5VS

12

R36

2.2K_0402_5%

NOVGA@

D D

C C

+2.5VS

B B

2.2K_0402_5%

NOVGA@

LDDC_CLK

GMCH_ENBKL<16,35>

GMCH_TV_LUMA<15>
GMCH_TV_CRMA<15>

R41 2.2K_0402_5%

1 2

R43 2.2K_0402_5%

1 2

R357 2.2K_0402_5%

1 2

R44 2.2K_0402_5%

1 2

R39 100K_0402_5%

1 2

R347 1.5K_0402_1%

1 2

R379 75_0402_1%

1 2

R370 150_0402_1%

1 2

R372 150_0402_1%

1 2

R332

+2.5VS

G

2

1 2

S

GMCH_LCD_CLK

13

D

Q46
BSS138_SOT23NOVGA@

GMCH_CRT_CLK<15>
GMCH_CRT_DATA<15>
GMCH_CRT_B<15>

GMCH_CRT_G<15>
GMCH_CRT_R<15>
GMCH_CRT_VSYNC<15>

GMCH_CRT_HSYNC<15>

GMCH_CRT_CLK
GMCH_CRT_DATA

2

G

LBKLT_EN

1 3

D

S

Q9 BSS138_SOT23

NOVGA@

GMCH_TV_LUMA
GMCH_TV_CRMA

LCTLB_DATA
LCTLA_CLK

LBKLT_EN
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

+3VS

R327

1 2

R364 4.99K_0402_1%

GMCH_CRT_CLK
GMCH_CRT_DATA

R355 150_0402_1%
R360 150_0402_1%
R367 150_0402_1%

4.7K_0402_5%

NOVGA@

GMCH_LCD_CLK <16>

GMCH_TV_COMPS

+2.5VS
CLK_MCH_3GPLL#<14>

CLK_MCH_3GPLL<14>

12

GMCH_ENVDD< 16>

GMCH_TXCLK-<16>
GMCH_TXCLK+<16>

GMCH_TXOUT0-<16>
GMCH_TXOUT1-<16>
GMCH_TXOUT2-<16>

GMCH_TXOUT0+<16>
GMCH_TXOUT1+<16>
GMCH_TXOUT2+<16>

12
12
12

4

R40 3K_0402_1%@

1 2

R349 3K_0402_1%@

1 2

R366 0_0402_5%

1 2

R359 255_0402_1%

TV_REFSET

12

REFSET

LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
GMCH_ENVDD
LIBG

GMCH_TXCLK­GMCH_TXCLK+

GMCH_TXOUT0­GMCH_TXOUT1­GMCH_TXOUT2-

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

H24

H25
AB29
AC29

A15

C16

A17

B15

B16

B17

E24

E23

E21

D21

C20

B20

A19

B19

H21

G21

E25

C23

C22

C33

C31

B30

B29

C25

C24

B34

B33

B32

A34

A33

B31

C29

D28

C27

C28

D27

C26

J18

J20

F25

F23
F22
F26

F28
F27

U4G

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

ALVISO_BGA1257R3PM@

3

EXP_RXN0/SDVO_TVCLKIN#

MISCTVVGALVDS

EXP_RXN1/SDVO_INT#

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN

EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

PCI - EXPRESS GRAPHICS

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_COMPI

EXP_ICOMPO

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

2

PCIE_MTX_C_GRX_N[0..15]<16>
PCIE_MTX_C_GRX_P[0..15]<16>

PCEI_GTX_C_MRX_N[0..15]<16>
PCEI_GTX_C_MRX_P[0..15]<16>

PEG_COMP

D36
D34

PCEI_GTX_C_MRX_N0

E30

PCEI_GTX_C_MRX_N1

F34

PCEI_GTX_C_MRX_N2

G30

PCEI_GTX_C_MRX_N3

H34

PCEI_GTX_C_MRX_N4

J30

PCEI_GTX_C_MRX_N5

K34

PCEI_GTX_C_MRX_N6

L30

PCEI_GTX_C_MRX_N7

M34

PCEI_GTX_C_MRX_N8

N30

PCEI_GTX_C_MRX_N9

P34

PCEI_GTX_C_MRX_N10

R30

PCEI_GTX_C_MRX_N11

T34

PCEI_GTX_C_MRX_N12

U30

PCEI_GTX_C_MRX_N13

V34

PCEI_GTX_C_MRX_N14

W30

PCEI_GTX_C_MRX_N15

Y34

PCEI_GTX_C_MRX_P0

D30

PCEI_GTX_C_MRX_P1

E34

PCEI_GTX_C_MRX_P2

F30

PCEI_GTX_C_MRX_P3

G34

PCEI_GTX_C_MRX_P4

H30

PCEI_GTX_C_MRX_P5

J34

PCEI_GTX_C_MRX_P6

K30

PCEI_GTX_C_MRX_P7

L34

PCEI_GTX_C_MRX_P8

M30

PCEI_GTX_C_MRX_P9

N34

PCEI_GTX_C_MRX_P10

P30

PCEI_GTX_C_MRX_P11

R34

PCEI_GTX_C_MRX_P12

T30

PCEI_GTX_C_MRX_P13

U34

PCEI_GTX_C_MRX_P14

V30

PCEI_GTX_C_MRX_P15

W34

PCIE_MTX_GRX_N0

E32

PCIE_MTX_GRX_N1

F36

PCIE_MTX_GRX_N2

G32

PCIE_MTX_GRX_N3

H36

PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4

J32

PCIE_MTX_GRX_N5

K36

PCIE_MTX_GRX_N6

L32

PCIE_MTX_GRX_N7

M36

PCIE_MTX_GRX_N8

N32

PCIE_MTX_GRX_N9

P36

PCIE_MTX_GRX_N10

R32

PCIE_MTX_GRX_N11

T36

PCIE_MTX_GRX_N12

U32

PCIE_MTX_GRX_N13

V36

PCIE_MTX_GRX_N14

W32

PCIE_MTX_GRX_N15

Y36

PCIE_MTX_GRX_P0

D32

PCIE_MTX_GRX_P1

E36

PCIE_MTX_GRX_P2

F32

PCIE_MTX_GRX_P3

G36

PCIE_MTX_GRX_P4

H32

PCIE_MTX_GRX_P5

J36

PCIE_MTX_GRX_P6

K32

PCIE_MTX_GRX_P7

L36

PCIE_MTX_GRX_P8

M32

PCIE_MTX_GRX_P9

N36

PCIE_MTX_GRX_P10

P32

PCIE_MTX_GRX_P11

R36

PCIE_MTX_GRX_P12

T32

PCIE_MTX_GRX_P13

U36

PCIE_MTX_GRX_P14

V32

PCIE_MTX_GRX_P15

W36

1 2

R31 24.9_0402_1%

C16 0.1U_0402_16V4ZVGA@

1 2

C18 0.1U_0402_16V4ZVGA@

1 2

C20 0.1U_0402_16V4ZVGA@

1 2

C23 0.1U_0402_16V4ZVGA@

1 2

C26 0.1U_0402_16V4ZVGA@

1 2

C28 0.1U_0402_16V4ZVGA@

1 2

C31 0.1U_0402_16V4ZVGA@

1 2

C36 0.1U_0402_16V4ZVGA@

1 2

C14 0.1U_0402_16V4ZVGA@

1 2

C17 0.1U_0402_16V4ZVGA@

1 2

C19 0.1U_0402_16V4ZVGA@

1 2

C22 0.1U_0402_16V4ZVGA@

1 2

C24 0.1U_0402_16V4ZVGA@

1 2

C27 0.1U_0402_16V4ZVGA@

1 2

C29 0.1U_0402_16V4ZVGA@

1 2

C34 0.1U_0402_16V4ZVGA@

1 2

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]

+1.5VS

C326 0.1U_0402_16V4ZVGA@

1 2

C331 0.1U_0402_16V4ZVGA@

1 2

C341 0.1U_0402_16V4ZVGA@

1 2

C357 0.1U_0402_16V4ZVGA@

1 2

C365 0.1U_0402_16V4ZVGA@

1 2

C374 0.1U_0402_16V4ZVGA@

1 2

C388 0.1U_0402_16V4ZVGA@

1 2

C402 0.1U_0402_16V4ZVGA@

1 2

C317 0.1U_0402_16V4ZVGA@

1 2

C329 0.1U_0402_16V4ZVGA@

1 2

C335 0.1U_0402_16V4ZVGA@

1 2

C347 0.1U_0402_16V4ZVGA@

1 2

C362 0.1U_0402_16V4ZVGA@

1 2

C371 0.1U_0402_16V4ZVGA@

1 2

C383 0.1U_0402_16V4ZVGA@

1 2

C400 0.1U_0402_16V4ZVGA@

1 2

1

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

A A

2.2K_0402_5%

NOVGA@

LDDC_DATA

R28

+2.5VS

G

2

1 2

S

GMCH_LCD_DATA

13

D

Q6
BSS138_SOT23NOVGA@

5

+3VS

1 2

R25

4.7K_0402_5%

NOVGA@

GMCH_LCD_DATA <16>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Alviso PCI-E(3/5)
Boston LA-2721

下午

8532005/5/6 11:47:55

1

1.0

5

4

3

2

1

U4E

+1.05VS

D D

C C

+1.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

B B

+1.5VS_DPLLA

1

2

+1.5VS_HPLL

A A

1

2

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

60mA

C358

22U_1206_16V4Z_V1

60mA

C52

22U_1206_16V4Z_V1

T29
R29
N29

M29

K29
J29
V28

U28

T28

R28

P28
N28
M28

L28

K28

J28
H28
G28

V27
U27

T27
R27

P27
N27
M27

L27

K27

J27
H27

K26
H26

K25

J25

K24

K23

K22

K21

W20

U20

T20

K20

V19
U19

K19

W18

V18

T18

K18

K17

AC1
AC2

B23
C35
AA1
AA2

R348
0_0603_5%

1 2

1

C364

2

0.1U_0402_16V4Z

R57
0_0603_5%

1 2

1

C50

2

0.1U_0402_16V4Z

5

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA1257R3PM@

+1.5VS

+1.5VS

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

POWER

VCCA_CRTDAC0
VCCA_CRTDAC1

+1.5VS_DPLLB

1

C15

2

22U_1206_16V4Z_V1

+1.5VS_MPLL

1

C451

2

22U_1206_16V4Z_V1

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

VSSA_CRTDAC

60mA

60mA

VCCHV0
VCCHV1
VCCHV2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

R37
0_0603_5%

1 2

1

C323

2

0.1U_0402_16V4Z

R400
0_0603_5%

1 2

1

C440

2

0.1U_0402_16V4Z

120mA

24mA

60mA

10mA
2mA

60mA

70mA

+1.5VS

+1.5VS

+3VS_DAC

+1.5VS

+2.5VS

+1.5VS_DDRDLL

+1.5VS_PEG

0.47U_0603_16V4Z

+1.5VS_3GPLL

+2.5VS_3GBG

+2.5VS_DAC

0.47U_0603_16V4Z

+1.5VS_DDRDLL

+1.5VS_3GPLL

4

+1.05VS

C44

1

2

1

C46

2

C49

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1

C25

2

22U_1206_16V4Z_V1

1

C306

2

10U_1206_16V4Z

1

2

1

C51

2

1

2

R337

0.5_0603_1%

1 2

1

C343

2

0.1U_0402_16V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U4F

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

VTT8

N11

VTT9

M11

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

ALVISO_BGA1257R3PM@

R42
0_0603_5%

1 2

C378

0.1U_0402_16V4Z

+3GPLL

Issued Date

POWER

+1.5VS_PEG

+1.5VS

22U_1206_16V4Z_V1

R336
0_0603_5%

1 2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9

V1.8_DDR_CAP6

AP8

V1.8_DDR_CAP4

AM1

V1.8_DDR_CAP3

AE1

V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP1

AM37

1000mA

4.7U_0805_10V4Z

C12

+1.5VS

1

2

1

2

2005/05/06 2006/05/06

3

1

C307

2

+2.5VS_3GBG

1

2

Compal Secret Data

C13

4.7U_0805_10V4Z

1 2

R338 0_0603_5%
C309

0.1U_0402_16V4Z

C310

0.1U_0402_16V4Z

+DDRVCC

330U_D2E_2.5VM

C42

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R30

470U_D2_2.5VM

1 2

0_1206_5%

0.15mA

Deciphered Date

C311

0.1U_0402_16V4Z

12

12

C334

0.1U_0402_16V4Z

+DDRVCC

2200mA

0.1U_0402_16V4Z

C483

1

2

+2.5VS

1

2

+

C355

C315

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

VCCA_LVDS (Ball A35)

+2.5VS_DAC

1

C394

2

4.7U_0805_10V4Z

VCC_SYNC(Ball H20)

C439

0.1U_0402_16V4Z

12

12

C438

1

+

C11

2

Reserve for debug

+2.5VS

4.7U_0805_10V4Z

12

+1.5VS

21

D28

RB751V_SOD323@

1 2

R575 1K_0402_5%@

2

12

C413

1

C324

2

0.01U_0402_16V7K

1

C381

2

0.1U_0402_16V4Z

+1.05VS

C369

22U_1206_16V4Z_V1

0.1U_0402_16V4Z

1

2

C353

1

2

VCCHV(Ball A21,B21,B22)

VCCA_CRTD AC(Ball F19 ,E19)

+1.5VS

1

2

+1.05VS

1

C412

2

2.2U_0603_6.3V6K

+3VS

1

+

2

C350

0.1U_0402_16V4Z

L1

CHB1608U301_0603

1 2

C32
150U_D2_6.3VM

C21

4000mA

2.2U_0603_6.3V6K

1

C348

2

1

C409

2

0.1U_0402_16V4Z

1

C373

2

4.7U_0805_10V4Z

1

2

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

C354

1

2

0.1U_0402_16V4Z

1

C339

C406

2

1

C407

2

0.1U_0402_16V4Z

C368

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C401

2

1

C340

2

4.7U_0805_10V4Z

1

C418

2

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C426

2

1

C351

2

1

C344

2

0.1U_0402_16V4Z

VCCTX_LVDS(Ball A27,A28,B28)

R375
0_0603_5%

1

C376

2

0.1U_0402_16V4Z

1 2

1

C380

2

0.022U_0402_16V7K

+2.5VS

VCCD_TVDAC (Ball D19)

0.1U_0402_16V4Z

1

C395

2

1

C397

2

0.022U_0402_16V7K

1

2

0.1U_0402_16V4Z

1

C359

2

1

C375

2

0.022U_0402_16V7K

VCCDQ_TVDAC (Ball H17)VCCD_LVDS(Ball A25,B25,B26)

950mA

1

C405

2

2.2U_0603_6.3V6K

1

C390

2

2.2U_0603_6.3V6K

1

C372

2

2.2U_0603_6.3V6K

VCCA_TVDAC VCCA_TVBG (Ball H18)

120mA

+3VS_DAC

1

1

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

下午

C392

C391

2

0.1U_0402_16V4Z

Alviso POWER(4/5)
Boston LA-2721

1

C386

2

1

1

C384

2

0.022U_0402_16V7K

of

9532005/5/6 11:47:54

1.0

5

4

3

2

1

U4H

+1.05VS

D D

C C

B B

+1.05VS

A A

L12

VTT_NCTF17

M12

VTT_NCTF16

N12

VTT_NCTF15

P12

VTT_NCTF14

R12

VTT_NCTF13

T12

VTT_NCTF12

U12

VTT_NCTF11

V12

VTT_NCTF10

W12

VTT_NCTF9

L13

VTT_NCTF8

M13

VTT_NCTF7

N13

VTT_NCTF6

P13

VTT_NCTF5

R13

VTT_NCTF4

T13

VTT_NCTF3

U13

VTT_NCTF2

V13

VTT_NCTF1

W13

VTT_NCTF0

Y12

VSS_NCTF68

AA12

VSS_NCTF67

Y13

VSS_NCTF66

AA13

VSS_NCTF65

L14

VSS_NCTF64

M14

VSS_NCTF63

N14

VSS_NCTF62

P14

VSS_NCTF61

R14

VSS_NCTF60

T14

VSS_NCTF59

U14

VSS_NCTF58

V14

VSS_NCTF57

W14

VSS_NCTF56

Y14

VSS_NCTF55

AA14

VSS_NCTF54

AB14

VSS_NCTF53

L15

VSS_NCTF52

M15

VSS_NCTF51

N15

VSS_NCTF50

P15

VSS_NCTF49

R15

VSS_NCTF48

T15

VSS_NCTF47

U15

VSS_NCTF46

V15

VSS_NCTF45

W15

VSS_NCTF44

Y15

VSS_NCTF43

AA15

VSS_NCTF42

AB15

VSS_NCTF41

L16

VSS_NCTF40

M16

VSS_NCTF39

N16

VSS_NCTF38

P16

VSS_NCTF37

R16

VSS_NCTF36

T16

VSS_NCTF35

U16

VSS_NCTF34

V16

VSS_NCTF33

W16

VSS_NCTF32

Y16

VSS_NCTF31

AA16

VSS_NCTF30

AB16

VSS_NCTF29

R17

VSS_NCTF28

Y17

VSS_NCTF27

AA17

VSS_NCTF26

AB17

VSS_NCTF25

AA18

VSS_NCTF24

AB18

VSS_NCTF23

AA19

VSS_NCTF22

AB19

VSS_NCTF21

AA20

VSS_NCTF20

AB20

VSS_NCTF19

R21

VSS_NCTF18

Y21

VSS_NCTF17

AA21

VSS_NCTF16

AB21

VSS_NCTF15

Y22

VSS_NCTF14

AA22

VSS_NCTF13

AB22

VSS_NCTF12

Y23

VSS_NCTF11

AA23

VSS_NCTF10

AB23

VSS_NCTF9

Y24

VSS_NCTF8

AA24

VSS_NCTF7

AB24

VSS_NCTF6

Y25

VSS_NCTF5

AA25

VSS_NCTF4

AB25

VSS_NCTF3

Y26

VSS_NCTF2

AA26

VSS_NCTF1

AB26

VSS_NCTF0

V25

VCC_NCTF10

W25

VCC_NCTF9

L26

VCC_NCTF8

M26

VCC_NCTF7

N26

VCC_NCTF6

P26

VCC_NCTF5

R26

VCC_NCTF4

T26

VCC_NCTF3

U26

VCC_NCTF2

V26

VCC_NCTF1

W26

VCC_NCTF0

ALVISO_BGA1257R3PM@

5

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+DDRVCC

+1.05VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AD2
AE2
AH2

AN2

AA3
AB3
AC3

AF4
AN4

AP5

AA6
AC6
AE6

AA7
AG7
AK7
AN7

AA9
AC9
AE9
AH9
AN9
D10

AA10

H11

AL2

AJ3

AL5

AJ6

AL8

L10
Y10

F11
Y11

U4I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257
VSS256
VSS255
VSS254
VSS253
VSS252

A3

VSS251

C3

VSS250
VSS249
VSS248
VSS247
VSS246

C4

VSS245

H4

VSS244

L4

VSS243

P4

VSS242

U4

VSS241

Y4

VSS240
VSS239
VSS238

E5

VSS237

W5

VSS236
VSS235
VSS234

B6

VSS233

J6

VSS232

L6

VSS231

P6

VSS230

T6

VSS229
VSS228
VSS227
VSS226
VSS225

G7

VSS224

V7

VSS223
VSS222
VSS221
VSS220
VSS219

C8

VSS218

E8

VSS217

L8

VSS216

P8

VSS215

Y8

VSS214
VSS213

A9

VSS212

H9

VSS211

K9

VSS210

T9

VSS209

V9

VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

ALVISO_BGA1257R3PM@

VSS

2005/05/06 2006/05/06

3

VSSALVDS

Compal Secret Data

B36
AA11

VSS195

AF11

VSS194

AG11

VSS193

AJ11

VSS192

AL11

VSS191

AN11

VSS190

B12

VSS189

D12

VSS188

J12

VSS187

A14

VSS186

B14

VSS185

F14

VSS184

J14

VSS183

K14

VSS182

AG14

VSS181

AJ14

VSS180

AL14

VSS179

AN14

VSS178

C15

VSS177

K15

VSS176

A16

VSS175

D16

VSS174

H16

VSS173

K16

VSS172

AL16

VSS171

C17

VSS170

G17

VSS169

AF17

VSS168

AJ17

VSS167

AN17

VSS166

A18

VSS165

B18

VSS164

U18

VSS163

AL18

VSS162

C19

VSS161

H19

VSS160

J19

VSS159

T19

VSS158

W19

VSS157

AG19

VSS156

AN19

VSS155

A20

VSS154

D20

VSS153

E20

VSS152

F20

VSS151

G20

VSS150

V20

VSS149

AK20

VSS148

C21

VSS147

F21

VSS146

AF21

VSS145

AN21

VSS144

A22

VSS143

D22

VSS142

E22

VSS141

J22

VSS140

AH22

VSS139

AL22

VSS138

H23

VSS137

AF23

VSS136

B24

VSS135

D24

VSS134

F24

VSS133

J24

VSS132

AG24

VSS131

AJ24

VSS130

Deciphered Date

2

AL24

AN24

A26
E26
G26

B27
E27
G27

W27
AA27
AB27
AF27

AG27

AJ27
AL27

AN27

E28

W28
AA28
AB28

AC28

A29
D29
E29

G29
H29

P29
U29
V29

W29
AA29

AD29
AG29

AJ29

AM29

C30

Y30
AA30
AB30

AC30

AE30
AP30

D31

E31

G31

H31

K31

M31

N31

P31

R31

U31

V31

W31
AD31
AG31

AL31

A32
C32

Y32
AA32
AB32

J26

F29

L29

F31

J31
L31

T31

U4J

VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

ALVISO_BGA1257

R3PM@

VSS

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Alviso POWER(5/5)
Boston LA-2721

下午

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

1

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

10 532005/5/6 11:47:54

1.0

of

5

4

3

2

1

+DDRVCC

DDRA_DQ1
DDRA_DQ5

DDRA_DQS0
DDRA_DQ7

D D

DDRA_CLK1<6>
DDRA_CLK1#<6>

C C

DDRA_CKE1<6>

DDRA_SBS0<7>
DDRA_SWE#<7>
DDRA_SCS#0<6>

B B

A A

D_CK_SDATA<12,14>
D_CK_SCLK<12,14>

DDRA_DQ3
DDRA_DQ13

DDRA_DQ9
DDRA_DQS1

DDRA_DQ15
DDRA_DQ11

DDRA_DQ16
DDRA_DQ20

DDRA_DQS2
DDRA_DQ18

DDRA_DQ22
DDRA_DQ25

DDRA_DQ29
DDRA_DQS3

DDRA_DQ27
DDRA_DQ30

DDRA_CKE1
DDRA_SMA12

DDRA_SMA9
DDRA_SMA7

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#

DDRA_SMA13
DDRA_DQ36

DDRA_DQ33
DDRA_DQS4

DDRA_DQ38
DDRA_DQ35

DDRA_DQ41
DDRA_DQ44

DDRA_DQS5
DDRA_DQ46

DDRA_DQ47

DDRA_DQ52
DDRA_DQ53

DDRA_DQS6
DDRA_DQ54

DDRA_DQ50
DDRA_DQ60

DDRA_DQ56
DDRA_DQS7

DDRA_DQ57
DDRA_DQ62

D_CK_SDATA
D_CK_SCLK

5

+3VS

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

1
3
5
7
9

JP7

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

AMP_1565917-1

DIMM0

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5
VSS
DM8

CB6
VDD

CB7

DU/RESET#

VSS
VSS
VDD
VDD

CKE0

DU/BA2

VSS

VDD

BA1

RAS#
CAS#

VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5
VSS

DQ46
DQ47

VDD

CK1#

CK1
VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

DQ61

DM7
VSS

DQ62
DQ63

VDD

SA0

SA1

SA2

A11

S1#

A8
A6

A4
A2
A0

DU

DU

+DDRVCC +DDRVCC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDRA_DQ0
DDRA_DQ4

DDRA_DM0
DDRA_DQ6

DDRA_DQ2
DDRA_DQ8

DDRA_DQ12
DDRA_DM1

DDRA_DQ14
DDRA_DQ10

DDRA_DQ17
DDRA_DQ21

DDRA_DM2
DDRA_DQ19

DDRA_DQ23
DDRA_DQ24

DDRA_DQ28
DDRA_DM3

DDRA_DQ26
DDRA_DQ31

DDRA_CKE0
DDRA_SMA11

DDRA_SMA8
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1DDRA_SCS#0

DDRA_DQ37
DDRA_DQ32

DDRA_DM4
DDRA_DQ39

DDRA_DQ34
DDRA_DQ45

DDRA_DQ40
DDRA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ49
DDRA_DQ48

DDRA_DM6
DDRA_DQ55

DDRA_DQ51
DDRA_DQ61

DDRA_DQ58
DDRA_DM7

DDRA_DQ63
DDRA_DQ59

+DIMM_VREF

12

12

1

2

C298

0.1U_0402_16V4Z

DDRA_CKE0 <6>

DDRA_SBS1 <7>
DDRA_SRAS# <7>
DDRA_SCAS# <7>
DDRA_SCS#1 <6>

DDRA_CLK2# <6>
DDRA_CLK2 <6>

R321

1K_0402_1%

R322

1K_0402_1%

DDRA_SDQ0
DDRA_SDQ1

DDRA_SDM0
DDRA_SDQS0

DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ20
DDRA_SDQ21

DDRA_SDQS2
DDRA_SDM2

DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ31
DDRA_SDQ30

DDRA_SDQ37
DDRA_SDQ36
DDRA_SDQ33
DDRA_SDQ32

DDRA_SDQS4
DDRA_SDM4

DDRA_SDQ46
DDRA_SDQ42
DDRA_SDQ47
DDRA_SDQ43

DDRA_SDQ52
DDRA_SDQ49
DDRA_SDQ53
DDRA_SDQ48

DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQS7
DDRA_SDM7 DDRA_SDQ63

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

3

RP1

1 8
2 7
3 6
4 5

1 4
2 3

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 4
2 3

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 4
2 3

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 4
2 3

DDRA_DQ0
DDRA_DQ1
DDRA_DQ4DDRA_SDQ4
DDRA_DQ5DDRA_SDQ5

10_0804_8P4R_5%

RP2

DDRA_DM0
DDRA_DQS0

10_0404_4P2R_5%

RP6

DDRA_DQ14
DDRA_DQ15
DDRA_DQ10
DDRA_DQ11

10_0804_8P4R_5%

RP7

DDRA_DQ16
DDRA_DQ17
DDRA_DQ20
DDRA_DQ21

10_0804_8P4R_5%

RP8

DDRA_DQS2

10_0404_4P2R_5%
RP12

DDRA_DQ26
DDRA_DQ27
DDRA_DQ31

DDRA_DQ30

10_0804_8P4R_5%
RP16

DDRA_DQ37

DDRA_DQ36

DDRA_DQ33

10_0804_8P4R_5%

RP17

DDRA_DQS4

DDRA_DM4

10_0404_4P2R_5%
RP21

DDRA_DQ46

DDRA_DQ42

DDRA_DQ47

DDRA_DQ43

10_0804_8P4R_5%
RP22

DDRA_DQ52

DDRA_DQ49

DDRA_DQ53

DDRA_DQ48

10_0804_8P4R_5%
RP24

DDRA_DQ54

DDRA_DQ55

DDRA_DQ50

DDRA_DQ51

10_0804_8P4R_5%

RP26

DDRA_DQS7

DDRA_DM7

10_0404_4P2R_5%

DDRA_DM2

Compal Secret Data

Deciphered Date

DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ3

DDRA_SDQ8
DDRA_SDQ13
DDRA_SDQ12
DDRA_SDQ9

DDRA_SDM1
DDRA_SDQS1

DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ22
DDRA_SDQ23

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ28
DDRA_SDQ29

DDRA_SDM3
DDRA_SDQS3

DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ35
DDRA_SDQ34

DDRA_SDQ41
DDRA_SDQ45 DDRA_DQ45
DDRA_SDQ44
DDRA_SDQ40

DDRA_SDQS5 DDRA_ DQS5

DDRA_SDQS6
DDRA_SDM6

DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ56
DDRA_SDQ58

DDRA_SDQ57
DDRA_SDQ59

DDRA_SDQ62

2

RP3

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP4

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP5

1 4
2 3

10_0404_4P2R_5%
RP9

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP10

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP11

1 4
2 3

10_0404_4P2R_5%

RP18

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP19

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
10_0404_4P2R_5%

2 3
1 4

RP20

RP23

1 4
2 3

10_0404_4P2R_5%

RP25

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP27

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

DDRA_DQ6
DDRA_DQ7
DDRA_DQ2
DDRA_DQ3

DDRA_DQ8
DDRA_DQ13
DDRA_DQ12
DDRA_DQ9

DDRA_DM1
DDRA_DQS1

DDRA_DQ18

DDRA_DQ19
DDRA_DQ22
DDRA_DQ23

DDRA_DQ24
DDRA_DQ25
DDRA_DQ28
DDRA_DQ29

DDRA_DM3
DDRA_DQS3

DDRA_DQ38
DDRA_DQ39
DDRA_DQ35
DDRA_DQ34DDRA_DQ32

DDRA_DQ41
DDRA_DQ44

DDRA_DQ40

DDRA_DM5DDRA_SDM5

DDRA_DQS6
DDRA_DM6

DDRA_DQ60
DDRA_DQ61
DDRA_DQ56
DDRA_DQ58

DDRA_DQ57
DDRA_DQ63
DDRA_DQ59
DDRA_DQ62

Title

Size Document Number Rev

Date: Sheet of

DDRA_SMA4
DDRA_SMA6
DDRA_SMA8
DDRA_SMA11

DDRA_SRAS#
DDRA_SBS1
DDRA_SMA0
DDRA_SMA2

DDRA_SCAS#
DDRA_SCS#1

DDRA_SMA5
DDRA_SMA7
DDRA_SMA9
DDRA_SMA12

DDRA_SBS0
DDRA_SMA10
DDRA_SMA1
DDRA_SMA3

DDRA_SWE#
DDRA_SCS#0

DDRA_SMA13
DDRA_CKE1
DDRA_CKE0

DDRA_DQ[0..63]
DDRA_DM[0..7]
DDRA_DQS[0..7]

DDRA_SDQ[0..63]<7>
DDRA_SDM[0..7]<7>
DDRA_SDQS[0..7]<7>
DDRA_SMA[0..13]<7>

Compal Electronics, Inc.

DDR-SODIMM SLOT0
Boston LA-2721

下午

RP57

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP60

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

56_0404_4P2R_5%

1 4
2 3

RP62
56_0804_8P4R_5%

1 8
2 7
3 6
4 5

RP13

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

RP14

RP15

2 3
1 4

56_0404_4P2R_5%

1 2

R48 56_0402_5%

1 2

R47 56_0402_5%

1 2

R369 56_0402_5%

DDRA_DQ[0..63] <12>

DDRA_DM[0..7] <12>

DDRA_DQS[0..7] <12>

DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SDQS[0..7]
DDRA_SMA[0..13]

11 532005/5/6 11:47:58

1

+DDRVTT

1.0

A

+DDRVTT

RP40

DDRA_DQ1
DDRA_DQ0
DDRA_DQ5
DDRA_DQ4

1 1

DDRA_DQ3
DDRA_DQ2
DDRA_DQ13
DDRA_DQ8

DDRA_DQ16
DDRA_DQ17
DDRA_DQ20
DDRA_DQ21

DDRA_DQ22

2 2

DDRA_DQ23
DDRA_DQ25
DDRA_DQ24

DDRB_SMA11
DDRB_SMA8
DDRB_SMA6
DDRB_SMA4

DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
DDRB_SRAS#

3 3

DDRB_SCAS#
DDRB_SCS#1
DDRB_SCS#0
DDRB_SMA13

DDRA_DQ36
DDRA_DQ37
DDRA_DQ33
DDRA_DQ32

DDRA_DQ35
DDRA_DQ34
DDRA_DQ41
DDRA_DQ45

4 4

DDRA_DQS6
DDRA_DM6
DDRA_DQ54
DDRA_DQ55

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP42

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP47

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP50

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP56

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP59

4 5
3 6
2 7
1 8

56_0804_8P4R_5%
RP63

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP64

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP66

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP70

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

A

RP41

45
36
27
18

56_0804_8P4R_5%

RP44

45
36
27
18

56_0804_8P4R_5%
RP45

45
36
27
18

56_0804_8P4R_5%
RP49

45
36
27
18

56_0804_8P4R_5%

RP52

45
36
27
18

56_0804_8P4R_5%
RP53

45
36
27
18

56_0804_8P4R_5%
RP58

45
36
27
18

56_0804_8P4R_5%

RP61

45
36
27
18

56_0804_8P4R_5%

RP65

45
36
27
18

56_0804_8P4R_5%
RP67

45
36
27
18

56_0804_8P4R_5%
RP68

45
36
27
18

56_0804_8P4R_5%
RP69

45
36
27
18

56_0804_8P4R_5%

DDRA_DQS0
DDRA_DM0
DDRA_DQ7
DDRA_DQ6

DDRA_DQ9
DDRA_DQ12
DDRA_DQS1
DDRA_DM1

DDRA_DQ15
DDRA_DQ14
DDRA_DQ11
DDRA_DQ10

DDRA_DQS2
DDRA_DM2
DDRA_DQ18
DDRA_DQ19

DDRA_DQ29
DDRA_DQ28
DDRA_DQS3
DDRA_DM3

DDRA_DQ27
DDRA_DQ26
DDRA_DQ30
DDRA_DQ31

DDRB_SMA12
DDRB_SMA9
DDRB_SMA7
DDRB_SMA5

DDRB_SMA3
DDRB_SMA1
DDRB_SBS0
DDRB_SWE#

DDRA_DQS4
DDRA_DQ38

DDRA_DQ39

DDRA_DQ44
DDRA_DQ40
DDRA_DQS5
DDRA_DM5

DDRA_DQ46
DDRA_DQ42
DDRA_DQ47
DDRA_DQ43

DDRA_DQ52
DDRA_DQ49
DDRA_DQ53
DDRA_DQ48

+DDRVTT

B

DDRA_DQ[0..63]<11>
DDRA_DM[0..7]<11>
DDRA_DQS[0..7]<11>
DDRB_SMA[0..13]<7>

RP72

RP73

B

DDRB_SMA10

12

R38356_0402_5%

DDRB_CKE1

12

R36556_0402_5%

DDRB_CKE0

12

R36256_0402_5%

RP71

DDRA_DQ50

45

DDRA_DQ51

36

DDRA_DQ60

27

DDRA_DQ61

18

56_0804_8P4R_5%

45
36
27
18

56_0804_8P4R_5%

45
36
27
18

56_0804_8P4R_5%

DDRA_DQ[0..63]
DDRA_DM[0..7]
DDRA_DQS[0..7]
DDRB_SMA[0..13]

DDRA_DQ56DDRA_DM4
DDRA_DQ58
DDRA_DQS7
DDRA_DM7

DDRA_DQ57
DDRA_DQ63
DDRA_DQ62
DDRA_DQ59

C

+DDRVCC +DDRVCC

DDRB_CLK1<6>
DDRB_CLK1#<6>

DDRB_CKE1<6>

DDRB_SBS0<7>
DDRB_SWE#<7>
DDRB_SCS#0<6>

D_CK_SDATA<11,14>
D_CK_SCLK<11,14>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

C

+DIMM_VREF

DDRA_DQ1
DDRA_DQ5

DDRA_DQS0
DDRA_DQ7

DDRA_DQ3
DDRA_DQ13

DDRA_DQ9
DDRA_DQS1

DDRA_DQ15
DDRA_DQ11

DDRA_DQ16
DDRA_DQ20

DDRA_DQS2
DDRA_DQ18

DDRA_DQ22
DDRA_DQ25

DDRA_DQ29
DDRA_DQS3

DDRA_DQ27
DDRA_DQ30

DDRB_CKE1
DDRB_SMA12

DDRB_SMA9
DDRB_SMA7

DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0
DDRB_SMA13

DDRA_DQ36
DDRA_DQ33

DDRA_DQS4
DDRA_DQ38

DDRA_DQ35
DDRA_DQ41

DDRA_DQ44
DDRA_DQS5

DDRA_DQ46
DDRA_DQ47

DDRA_DQ52
DDRA_DQ53

DDRA_DQS6
DDRA_DQ54

DDRA_DQ50
DDRA_DQ60

DDRA_DQ56
DDRA_DQS7

DDRA_DQ57
DDRA_DQ62

D_CK_SDATA
D_CK_SCLK

+3VS

Compal Secret Data

JP20

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP_1565918-1

Deciphered Date

D

DU/RESET#

DU/BA2

D

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

VSS

VSS

VDD

VDD

CKE0

VSS

VDD

BA1

RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD
CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

A11

S1#

E

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122
124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

DDRA_DQ0
DDRA_DQ4

DDRA_DM0
DDRA_DQ6

DDRA_DQ2
DDRA_DQ8

DDRA_DQ12
DDRA_DM1

DDRA_DQ14
DDRA_DQ10

DDRA_DQ17
DDRA_DQ21

DDRA_DM2
DDRA_DQ19

DDRA_DQ23
DDRA_DQ24

DDRA_DQ28
DDRA_DM3

DDRA_DQ26
DDRA_DQ31

DDRB_CKE0
DDRB_SMA11

DDRB_SMA8
DDRB_SMA6

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1

DDRA_DQ37
DDRA_DQ32

DDRA_DM4
DDRA_DQ39

DDRA_DQ34
DDRA_DQ45

DDRA_DQ40
DDRA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ49
DDRA_DQ48

DDRA_DM6
DDRA_DQ55

DDRA_DQ51
DDRA_DQ61

DDRA_DQ58
DDRA_DM7

DDRA_DQ63
DDRA_DQ59

+3VS

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDR-SODIMM SLOT1
Boston LA-2721

下午

+DIMM_VREF

1

C297

0.1U_0402_16V4Z

2

DDRB_CKE0 <6>

DDRB_SBS1 <7>
DDRB_SRAS# <7>
DDRB_SCAS# <7>
DDRB_SCS#1 <6>

DDRB_CLK2# <6>
DDRB_CLK2 <6>

E

1.0

12 532005/5/6 11:47:58

A

B

C

D

E

Layout note :

Distribute as clo se as possible
to DDR-SODIMM.

+DDRVCC

1 1

1

C316

0.1U_0402_16V4Z

2

1

C313

0.1U_0402_16V4Z

2

1

C304

0.1U_0402_16V4Z

2

1

C411

0.1U_0402_16V4Z

2

1

C460

0.1U_0402_16V4Z

2

+DDRVCC+DDRVCC

1

C449

0.1U_0402_16V4Z

2

1

C448

0.1U_0402_16V4Z

2

1

C396

0.1U_0402_16V4Z

2

1

C300

0.1U_0402_16V4Z

2

1

C377

0.1U_0402_16V4Z

2

1

C457

0.1U_0402_16V4Z

2

1

C337

0.1U_0402_16V4Z

2

1

C349

0.1U_0402_16V4Z

2

1

+

C35
150U_D2_6.3VM

2

1

+

C8
150U_D2_6.3VM

2

Layout note :

2 2

3 3

Place one cap close to every 2 pull up resistors termination to
+1.25V

+DDRVTT

1

2

+DDRVTT

1

2

+DDRVTT

1

2

+DDRVTT

1

2

C338

0.1U_0402_16V4Z

C308

0.1U_0402_16V4Z

C455

0.1U_0402_16V4Z

C442

0.1U_0402_16V4Z

1

C305

0.1U_0402_16V4Z

2

1

C314

0.1U_0402_16V4Z

2

1

C454

0.1U_0402_16V4Z

2

1

C458

0.1U_0402_16V4Z

2

1

C366

0.1U_0402_16V4Z

2

1

C325

0.1U_0402_16V4Z

2

1

C430

0.1U_0402_16V4Z

2

1

C40

0.1U_0402_16V4Z

2

1

C422

0.1U_0402_16V4Z

2

1

C379

0.1U_0402_16V4Z

2

1

C459

0.1U_0402_16V4Z

2

1

C301

0.1U_0402_16V4Z

2

1

C452

0.1U_0402_16V4Z

2

1

C345

0.1U_0402_16V4Z

2

1

C456

0.1U_0402_16V4Z

2

1

C425

0.1U_0402_16V4Z

2

1

C389

0.1U_0402_16V4Z

2

1

C408

0.1U_0402_16V4Z

2

1

C403

0.1U_0402_16V4Z

2

1

C420

0.1U_0402_16V4Z

2

1

C303

0.1U_0402_16V4Z

2

1

C453

0.1U_0402_16V4Z

2

1

C419

0.1U_0402_16V4Z

2

1

C370

0.1U_0402_16V4Z

2

1

C387

0.1U_0402_16V4Z

2

1

C416

0.1U_0402_16V4Z

2

1

C433

0.1U_0402_16V4Z

2

1

C382

0.1U_0402_16V4Z

2

+DDRVTT

1

2

C39

0.1U_0402_16V4Z

+DDRVTT

1

C361

0.1U_0402_16V4Z

2

1

C33

0.1U_0402_16V4Z

2

1

C333

0.1U_0402_16V4Z

2

1

C37

0.1U_0402_16V4Z

2

1

C356

0.1U_0402_16V4Z

2

1

C428

0.1U_0402_16V4Z

2

1

C327

0.1U_0402_16V4Z

2

1

C30

0.1U_0402_16V4Z

2

1

C398

0.1U_0402_16V4Z

2

1

C446

0.1U_0402_16V4Z

2

1

C410

0.1U_0402_16V4Z

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

DDR SODIMM Decoupling
Boston LA-2721

下午

E

of

13 532005/5/6 11:47:56

1.0

A

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

*

1 1

0

*

0

0
0
1
1

+3VS

CLKSEL1

CLKSEL0

A

CLKSEL2

CLK_PCI0

CLK_PCI2

CLK_PCI1

+3VS

2

1 3

D

R439
0_0402_5%@

R448
0_0402_5%@

1 2

R401 10K_0402_5%

1 2

R420 10K_0402_5%

1 2

R466 10K_0402_5%

1 2

R419 10K_0402_5%

2 2

3 3

CK_SCLK<19>

4 4

CLK_ICH_48M<19>
CLK_SD_48M<24>

CLK_14M_CODEC<30>

R457

4.7K_0402_5%

G

1 2

S

Q51
2N7002_SOT23

R422

4.7K_0402_5%

1 2
1 2

R455

4.7K_0402_5%

1 2
1 2

11
1
1
00

30P_0402_50V8J

D_CK_SCLK

+1.05VS

R432

1 2

R440
0_0402_5%

+1.05VS

R450

1 2

R456
0_0402_5%

B

1

C461

2

2.2U_0603_6.3V6K

+CLK_VDD2

MHz

100
133
166
200

SRC

PCI

MHz

MHz

100 33.3
100

33.3

100

33.3

100

33.3

Table : ICS 95 4226AGT

C511

30P_0402_50V8J

CLK_PCI_MINI<29>
CLK_PCI_SIO<33,34>
CLK_PCI_PCM<24>
CLK_PCI_LPC<35>

CLK_PCI_ICH<17>
D_CK_SCLK<11,12>

D_CK_SDATA<11,12>

+3VS

1K_0402_5%@
R429

0_0402_5%

1 2

1K_0402_5%@
R451

0_0402_5%

1 2

1 2

C510

1 2

Y4

14.318MHZ_16PF_DSX840GA

12

CLK_ICH_48M

CLK_14M_CODEC CLKSEL0

CK_SDATA<19>

12

12

B

R402 12_0402_5%

1 2

R403 12_0402_5%

1 2

R463 12_0402_5%

CLK_PCI_MINI CLK_PCI4

CLK_PCI_ICH
D_CK_SCLK

D_CK_SDATA

MCH_CLKSEL1 <6>
CPU_BSEL1 <5>

MCH_CLKSEL0 <6>
CPU_BSEL0 <5>

1 2

R430 33_0402_5%

1 2

R431 33_0402_5%

1 2

R467 33_0402_5%

1 2

R410 33_0402_5%

1 2

R411 33_0402_5%

+3VS

2

G

1 3

D

S

Q50
2N7002_SOT23

C

+CLK_VDD48 +CLK_VDDREF

1 2

R465 1_0402_5%

1 2

R412 2.2_0402_5%

12

R464 475_0402_1%

R449

4.7K_0402_5%

1 2

5IN1@

1 2

D_CK_SDATA

1

C470

2

0.047U_0402_16V7K

+CLK_VDD1

+CLK_VDD1

+CLK_VDDREF

15mil

+CLK_VDD48

15mil

XTALIN
XTALOUT

CLKSEL2CLK_SD_48M

CLKSEL1

CLK_PCI3CLK_PCI_SIO
CLK_PCI2CLK_PCI_PCM
CLK_PCI1CLK_PCI_LPC

CLK_PCI0

CLKIREF

15mil

+3VS

U35

21

VDDPCIEX_0

28

VDDPCIEX_1

34

VDDPCIEX_2

1

VDDPCI_0

7

VDDPCI_1

42

VDDCPU

48

VDDREF

11

VDD48

50

X1

49

X2

12

FS_A/USB_48MHz

53

REF1/FSLC/TEST_SEL

16

FSLB/TEST_MODE

5

PCICLK5

4

PCICLK4

3

PCICLK3

56

PCICLK2/REQ_SEL

9

SELPCIEX_LCDCLK#/PCICLK_F1

8

ITP_EN/PCICLK_F0

46

SCLK

47

SDATA

39

IREF

13

GND_0

29

GND_1

2

GND_2

45

GND_3

51

GND_4

6

GND_5

ICS954226AGT_TSSOP56

D

1

C505

0.047U_0402_16V7K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

R443 0_0805_5%

1 2

+3VS

VDDA
GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

CPUCLKT2_ITP/PCIEXT6

CPUCLKC2_ITP/PCIEXC6

PEREQ1#/PCIEXT5
PEREQ2#/PCIEXC5

PCIEXT4

PCIEXC4

SATACLKT
SATACLKC

PCIEXT3

PCIEXC3

PCIEXT2

PCIEXC2

PCIEXT1

PCIEXC1

LCDCLK_SS/PCIEX0T

LCDCLK_SS/PCIEX0C

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0

2005/05/06 2006/05/06

E

1

C468

2.2U_0603_6.3V6K

2

1

37
38

55
54

41
40

44
43

36
35

33
32

31
30

26
27

24
25

22
23

19
20

17
18

14
15

10
52

2

STP_PCI#
STP_CPU#

CLK_CPU1
CLK_CPU1#

CLK_CPU0
CLK_CPU0#

CLK_CPU2
CLK_CPU2#

CLK_SRC5
CLK_SRC5#

CLK_SRC4
CLK_SRC4#

CLK_SRC3
CLK_SRC3#

CLK_SRC2
CLK_SRC2#

CLK_SRC1
CLK_SRC1#

CLK_SRC0
CLK_SRC0#

CLK_DOT
CLK_DOT#

CLK_REF CLK_14M_SIO

1

C472

0.047U_0402_16V7K

2

+CLK_VCCA

40mil

C515

2.2U_0603_6.3V6K

R473 33_0402_5%

1 2

R472 33_0402_5%

1 2

R475 33_0402_5%

1 2

R474 33_0402_5%

1 2

R471 33_0402_5%@

1 2

R470 33_0402_5%@

1 2

R469 33_0402_5%

1 2

R468 33_0402_5%

1 2

R414 33_0402_5%

1 2

R413 33_0402_5%

1 2

R434 33_0402_5%

1 2

R433 33_0402_5%

1 2

R416 33_0402_5%

1 2

R415 33_0402_5%

1 2

R436 33_0402_5%

1 2

R435 33_0402_5%

1 2

R418 33_0402_5%

1 2

R417 33_0402_5%

1 2

R438 33_0402_5%

1 2

R437 33_0402_5%

1 2

1 2

R461 12_0402_5%

1 2

R462 12_0402_5%

Compal Secret Data

Deciphered Date

E

F

1 2

R483

2.2_0402_5%

1

C506

2

0.047U_0402_16V7K

PM_STP_PCI# <19>
PM_STP_CPU# <19,50>

CLK_ICH_14M

F

1

C471

0.047U_0402_16V7K

2

+CLK_VDD1

+3VS

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_DREF_SSC
CLK_DREF_SSC#

CLK_DREF_96M
CLK_DREF_96M#

1 2

+3VS

R421 10K_0402_5%

VTT_POWERGD#

CLK_14M_SIO <33,34>

CLK_ICH_14M <19>

G

40mil

+CLK_VDD1

1

C503

0.047U_0402_16V7K

2

R442 0_0805_5%

1 2

CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_PCIE_LAN <27>
CLK_PCIE_LAN# <27>

CLK_PCIE_SATA <18>
CLK_PCIE_SATA# <18>

CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>

CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>

CLK_PCIE_ICH <19>
CLK_PCIE_ICH# <19>

CLK_DREF_SSC <6>
CLK_DREF_SSC# <6>

CLK_DREF_96M <6>
CLK_DREF_96M# <6>

Title

Size Document Number Rev

Date: Sheet

1

C504

0.047U_0402_16V7K

2

1

C477

2

2.2U_0603_6.3V6K

2

G

1 3

D

S

Q47
2N7002_SOT23

Compal Electronics, Inc.

Clock Generator
Boston LA-2721

下午

G

Clock Generator

40mil

1

C473

2

0.047U_0402_16V7K

CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#

VGATE <6,19,50>

+CLK_VDD2

1 2

R485 49.9_0402_1%

1 2

R484 49.9_0402_1%

1 2

R487 49.9_0402_1%

1 2

R486 49.9_0402_1%

1 2

R482 49.9_0402_1%@

1 2

R481 49.9_0402_1%@

1 2

R480 49.9_0402_1%

1 2

R479 49.9_0402_1%

1 2

R405 49.9_0402_1%

1 2

R404 49.9_0402_1%

1 2

R424 49.9_0402_1%

1 2

R423 49.9_0402_1%

1 2

R407 49.9_0402_1%

1 2

R406 49.9_0402_1%

1 2

R426 49.9_0402_1%

1 2

R425 49.9_0402_1%

1 2

R409 49.9_0402_1%

1 2

R408 49.9_0402_1%

1 2

R428 49.9_0402_1%

1 2

R427 49.9_0402_1%

H

1

C476

2

0.047U_0402_16V7K

of

14 532005/5/6 11:47:58

H

1.0

A

CRT Connector

1 1

VGA_CRT_R<16>
GMCH_CRT_R<8>

VGA_CRT_G<16>
GMCH_CRT_G<8>

VGA_CRT_B<16>
GMCH_CRT_B<8>

1 2

R15 0_0402_5%NO VGA@

1 2

R24 0_0402_5%NO VGA@

1 2

R16 0_0402_5%NO VGA@

DOCKIN#<35,40>

Close to VGA conn.

VGA_CRT_R
VGA_CRT_G

2 2

3 3

1 2

R10 0_0402_5%WOD@

1 2

R21 0_0402_5%WOD@

1 2

R12 0_0402_5%WOD@

Pop with No-Docking

CRT_R
CRT_G
CRT_BVGA_CRT_B

VGA_CRT_HSYNC<16>

GMCH_CRT_HSYNC<8>

VGA_CRT_VSYNC<16>

GMCH_CRT_VSYNC<8>

+3VS

+2.5VS

GMCH_CRT_DATA<8>

VGA_DDC_DATA<16>

VGA_DDC_CLK<16>

GMCH_CRT_CLK<8>

DOCKIN#

1 2

VGA_DDC_DATA

1 2

0_0402_5% NOVGA@

B

1

SEL

15

OE#

4

1A

7

2A

9

3A

12

4A

8

GND

WD@

1 2

R26 39_0402_5%NOVGA@

1 2

R22 39_0402_5%NOVGA@

U3

FSAV330MTC_TSSOP16

16

VCC

2

1B1

5

2B1

11

3B1

14

4B1

3

1B2

6

2B2

10

3B2

13

4B2

1 2

C299 0.1U_0402_16V4Z

Close to VGA conn.

R270_0402_5% VGA@

12

R230_0402_5% NOVGA@

12

R140_0402_5%NOVGA@

G

2

4.7K_0402_5%

13

D

S

G

2

BSS138_SOT23

13

D

S

Q3

BSS138_SOT23

R9

+5VS

C10

D_CRT_R
D_CRT_G
D_CRT_B

R7

150_0402_1%

12

R11

Q5

0.1U_0402_16V4Z

1 2

WD@

12

R18

150_0402_1%

C296 0.1U_0402_16V4Z

+5VS

12

R19

4.7K_0402_5%

D_CRT_R
D_CRT_G
D_CRT_B

D_CRT_R <40>
D_CRT_G <40>
D_CRT_B <40>

12

12

R8

150_0402_1%

+5VS

1

5

P

4

OE#

A2Y

G

U33

SN74AHCT1G125GW_SOT353-5

3

1 2

DSUB_12_DATA

DSUB_15_CLKVGA_DDC_CLK

C

R4 470_0402_1%

1 2

R320 470_0402_1%

1 2

R5 470_0402_1%

1 2

CRT_R

CRT_B

R319 10K_0402_5%

+5VS

1

5

P

4

OE#

A2Y

G

U32
SN74AHCT1G125GW_SOT353-5

3

2

1

12

D_CRT_HSYNC

D_CRT_VSYNC

8P_0402_50V8K

8P_0402_50V8K

2

C671

C672

1

8P_0402_50V8K

2

C673

1

L20

FCM2012C-800_0805

L21

FCM2012C-800_0805

L22

FCM2012C-800_0805

D

1 2
1 2
1 2

8P_0402_50V8K

D_CRT_HSYNC <40>

D_CRT_VSYNC <40>

VGA_DDC_DATA

VGA_DDC_CLK

C670

CRT Board

+5VS

R611

1 2

W=40mils

0_1206_5%

+3VS

DSUB_12_DATA
DSUB_15_CLK
HSYNC

VSYNC
CRT_R_L
CRT_G_LCRT_G
CRT_B_L

1

C669

2

8P_0402_50V8K

1

1

C668

2

2

8P_0402_50V8K

D_CRT_VSYNC VSYNC

+2.5VS

G

2

13

D

S

BSS138_SOT23 NOVGA@

+2.5VS

G

2

13

D

S

Q8

BSS138_SOT23 NOVGA@

JP2

1
2
3
4
5
6
7
8
9
10
11
12

ACES_85201-1205

For EMI request

1 2

L18 FCM1608C-121T_0603

1 2

L19 FCM1608C-121T_0603

10P_0402_50V8J

D_DDC_DATA

Q7

12

R290_0402_5% VGA@

D_DDC_CLK

12

R340_0402_5% VGA@

E

HSYNCD_CRT_HSYNC

1

C667

2

D_DDC_DATA <40>

D_DDC_CLK <40>

1

C666
10P_0402_50V8J

2

Close to VGA conn.

C85

1 2

22P_0402_50V8J

VGA_TV_LUMA<16>
GMCH_TV_LUMA<8>

VGA_TV_CRMA<16>
GMCH_TV_CRMA<8>

4 4

1 2

R17 0_0402_5%NOVGA@

1 2

R20 0_0402_5%NOVGA@

Close to VGA conn.

A

12

R66

150_0402_1%

12

R63

150_0402_1%

C87
100P_0402_25V8K

B

L2

L3

C76
100P_0402_25V8K

@

1 2

FBM-11-160808-121T_0603

1 2

FBM-11-160808-121T_0603

C86

CRMA_1
LUMA_1

1 2

C88
22P_0402_50V8J

@

C89

100P_0402_25V8K

100P_0402_25V8K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

C

TV-OUT Conn.

JP24

4

4

3

3

2

2

1

1

ALLTO_C10877-104A1-L_4P

Compal Secret Data

Deciphered Date

6
5

3. Y (luminance+sync)

5

4. C (crominance)

1. Y ground

2. C ground

6

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

CRT & TVout Connector
Boston LA-2721

下午

15 532005/5/6 11:47:56

E

1.0

5

LCD POWER CIRCUIT

R1
300_0402_5%

NOVGA@

Q2

2N7002_SOT23

NOVGA@

BKOFF#<35>

+LCDVDD

12

13

D

S

BKOFF# DISPO FF#

D D

C C

B B

GMCH_ENVDD<8>

+3VALW

0.01U_0402_16V7K

NOVGA@

2

G

R3
100K_0402_5%

1 2

NOVGA@

D1
RB751V_SOD323

21

GMCH_ENVDD

U2

1

5

P

OE#

A2Y

1

C5

2

1

C3

2

0.047U_0402_16V7K

NOVGA@

+3VS

12

R6

4.7K_0402_5%

G

3

LCD/PANEL BD. Conn.

+3VS

1

C4

0.1U_0402_16V4Z@

A A

2

+LCDVDD

GMCH_LCD_CLK<8>
GMCH_LCD_DATA<8>

DAC_BRIG<35>
INVT_PWM<35>

GMCH_LCD_CLK
GMCH_LCD_DATA

DAC_BRIG
INVT_PWM

DISPOFF#

B+

4

SN74AHCT1G125GW_SOT353-5

NOVGA@

4

R2

1 2

100_0402_5%

NOVGA@

JP4

2
4
6
8
10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88242-3000

NOVGA@

G

2

1
3
5
7
9

+3VS

S

D

1 3

1

C2

2

Q1

NOVGA@

AO3413_SOT23

4.7U_0805_10V4Z

NOVGA@

GMCH_TXOUT0- <8>
GMCH_TXOUT0+ <8>

GMCH_TXOUT1- <8>
GMCH_TXOUT1+ <8>

GMCH_TXOUT2+ <8>
GMCH_TXOUT2- <8>

GMCH_TXCLK- <8>
GMCH_TXCLK+ <8>

+LCDVDD

1

2

C1

0.1U_0402_16V4Z

NOVGA@

PLTRST_VGA#<19>
PLT_RST#<6,17,19,21,22,24,27,34,35>

3

PCIE_MTX_C_GRX_N[0..15]<8>
PCIE_MTX_C_GRX_P[0..15]<8>

PCEI_GTX_C_MRX_N[0..15]<8>
PCEI_GTX_C_MRX_P[0..15]<8>

2

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCEI_GTX_C_MRX_N[0..15]

PCEI_GTX_C_MRX_P[0..15]

1

VGA BOARD Conn.

JP19

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
123 124
125 126
127 128
129 130
131 132
133 134
135 136
137 138
139 140
141 142
143 144
145 146
147 148
149 150
151 152
153 154
155 156
157 158
159 160

ACES_88081-1600VGA@

VGA_DDC_CLK
VGA_DDC_DATA

VGA_TV_LUMA
VGA_TV_CRMA
VGA_CRT_VSYNC

VGA_CRT_HSYNC
SUSP#
GMCH_ENBKL

+3VS

+5VS

+5VALW

PCIE_MTX_C_GRX_P0

PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1

PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4

PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5

PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P6

PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7

PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8

PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

B+

VGA_DDC_CLK <15>
VGA_DDC_DATA <15>

VGA_TV_LUMA <15>
VGA_TV_CRMA <15>
VGA_CRT_VSYNC <15>

VGA_CRT_HSYNC <15>
SUSP# <26,30,32,35,37,38,42,49>
GMCH_ENBKL <8,35>

+1.5VS
DVI_DET <40>
DVI_SCLK <40>
DVI_SDATA <40>

CLK_PCIE_VGA <14>
CLK_PCIE_VGA# <14>

VGA_CRT_R<15>
VGA_CRT_G<15>
VGA_CRT_B<15>

DVI_TXC+< 40>
DVI_TXC-<40>

DVI_TXD0+<40>
DVI_TXD0-<40>

DVI_TXD1+<40>
DVI_TXD1-<40>

DVI_TXD2+<40>
DVI_TXD2-<40>

R38 0_0402_5%VGA@
R35 0_0402_5%@

+3VALW

+2.5VS

1 2
1 2

B+

DAC_BRIG
DISPOFF#

INVT_PWM
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0

PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1

PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2

PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3

PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4

PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5

PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6

PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7

PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8

PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9

PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10

PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11

PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12

PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13

PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14

PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/06 2006/05/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

VGA / LCD CONN.
Boston LA-2721

下午

16 532005/5/6 11:47:55

1

1.0