Toshiba M50 Schematics

A

1 1

B

C

D

E

HAZ00/HTW01

2 2

LA-2861

3 3

REV 1.0 Schematic

UFC-PGA Dothan/ RC410MD(RC410MB)/ SB450

2005-07-11 Rev.1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Black Diagram

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

B

Thursday, A ugus t 04, 2005

D

Date: Sheet

142

E

of

A

B

C

D

E

HAZ00 & HTW01 LA-2861 FUNCTION BLOCK DIAGRAM

4 4

CRT Conn.

page 13

LCD Conn

page 12

LVDS & TV-OUT Conn.

3 3

2 2

CARDBUS

CB1410

PAGE 20

CARD BUS
SOCKET

PAGE 21

TSB43AB21

PAGE 22

1394-Port

PAGE 22

page 12

PCI BUS

33MHz (3.3V)

LAN

RTL8100CL

PAGE 19

Mini PCI
FOR WLAN

PAGE 23

INTEL
Celeron 479 pin

FSB

400MHz

ATI-RC410MB

VGA M10P Embeded

707 pin BGA

A-Link Express x 4

2.5GHz(1.2V)

Bandwidth 500MB

ATI-SB450

564 pin BGA

PAGE 21,22,23,24,25

LPC BUS 33MHz (3.3V)

Embedded
Controller

ENE KB910

PAGE 29

PAGE 4,5,6

PAGE 6,7,8

Thermal Sensor
ADM1032ARM

400/533/667MHz
(1.8V)

Memory Bus

480MHz(5V)

Primary
ATA-100 (5V)

Secondary
ATA-100 (5V)

AC-LINK

14.318MHz(3.3V)

Clock Generator
ICS951411AGT

PAGE 5

SO-DIMM x 2(DDRII)

BANK 0,1,2,3

USB 2.0 Port *3
0,2,4

IDE HDD

HAZ00 IDE ODD

BL10E IDE ODD

AC97 CODEC

ALC 250

PAGE 36

PAGE 26

PAGE 26

PAGE 26

PAGE 24

PAGE 11

PAGE 9,10

CPU VID

Audio Amplifier

APA2068

PAGE 5

PAGE 25

FANController

RTC Battery

DC/DC Interface

LID/Kill Switch
Power Buttom

DCIN&DETECTOR

BATT CONN/OTP

CHARGER

3V/5V/12V

DDR_1.8V/0.9VEP

1.8VCORE

1.5V/PROCHOT

CPU_CORE

PAGE 33

PAGE 14

PAGE 34

PAGE 31

PAGE 35

PAGE 36

PAGE 37

PAGE 38

PAGE 40

PAGE 39

PAGE 40

PAGE 41

RJ-45

PAGE 19

1 1

A

B

BIOS(1M)

& I/O PORT

PAGE 30

Scan KB

PAGE 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

MDC

Connector

Deciphered Date

PAGE 33

Compal Electronics, Inc.

Title

Black Diagram

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

B

Thursday, A ugus t 04, 2005

D

Date: Sheet

242

E

of

A

B

C

D

E

Rb

0

NC7

SIGNAL

HIGH

LOW

LOW

AD_BID

0.436 V

0.712 V

1.036 V

1.935 V

2.500 V

SLP_S5#STATE

HIGHHIGH

HIGH

HIGH

HIGH

LOWLOW

minV

0 V

+VALW

ON

ON

ON

ON

ON

+V

ON

ON

ON

OFF

OFF

AD_BID

0.503 V

0.819 V

1.650 V1.453 V

2.200 V

3.300 V

typV

0 V

+VSSLP_S3#

ON

OFF

OFF

OFF

Clock

ONON

LOW

OFF

OFF

OFF

V

AD_BID

0.289 V0.250 V0.216 V

0.538 V

0.875 V

1.264 V1.185 V

1.759 V

2.341 V

3.300 V

max

0 V

Voltage Rails

Power Plane Description

1 1

2 2

VIN
B+
+CPU_CORE
+CPUVID
+VGA_CORE ON OFF OFF1.0V/1.2V switched power rail for VGA chip
+1.2VS 1 .2 VS fo r PCI-Express OFFON OF F
+0.9VS 0.9V switched power rail
+1.5VS
+1.8VS 1.8VS switched power rail OFFOFFON
+1.8VALW 1.8V always on power rail ON *ONON
+1.8V
+3VALW
+3VS

+5VS
+12VALW
+RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC or batte ry power rail for power circuit.
Core voltage for CPU

1.2V switched power rail for CPU AGTL Bus

DOTHAN B

1.8V power rail

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

RTC power

S1 S3 S5

ON
ON ONONON
ON OFF
ON OFF

ON OFF OF F
ON OFF OF F

ON ON
ON
ON
ON+5VALW
ON
ON
ON

OFF
ON
OFF
ON
ON

ON

OFF
OFF

OFF
ON*ON
OFF
ON*
OFF
ON*12V always on power rail
ON

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID Table for AD channel

Vcc
Ra

Board ID

0
1
2
3
4
5
6

3.3V +/- 5%
100K +/- 5%

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

External PCI Devices

Device IDSEL # REQ # / GNT # Interrupts

TI 1410

LAN
Mini-PCI(WLAN)
1394

AD20

AD22

AD18
AD16

2

1PIRQG

3
0

PIRQA/PIRQB

PIRQF/PIRQG
PIRQA

Board ID

0
1
2
3
4

3 3

5
6
7

PCB Revision

0.1, 0.2

0.3

1.0

EC SM Bus1 address

Device

Smart Battery

Address Address

EC SM Bus2 address

Device

ADM1032

1001 110X b0001 011X b

SKU ID

0
1
2

SKU Status

HDD Password

0
1

NO
Yes

3
4
5

1 Buttons

6
7 7 Buttons

SB450 SM Bus address

4 4

Device

Clock Generator
(ICS951413BGLFT)

DDR DIMM0

DDR DIMM1

A

Address

1101 001Xb

1010 0100b
1010 0110b

A4
A6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Notes List

HAZ00/BL10E (LA2861) 1.0

Thursday, A ugus t 04, 2005

342

E

of

5

4

H_D#[0..63]

H_D#[0..63] 6

3

2

1

+3VS

H_A#[3..31]6

H_REQ#[0..4]6

H_RS#[0..2]6

D D

C C

B B

A A

H_A#[3..31]
H_REQ#[0..4]
H_RS#[0..2]

H_ADSTB#06
H_ADSTB#16

CLK_BCLK11

CLK_BCLK#11

H_ADS#6
H_BNR#6

H_BPRI#6

H_DEFER#6

H_DRDY#6

H_HIT#6
H_HITM#6

H_LOCK#6

H_RESET#6,14

H_TRDY#6

H_DBSY#6

H_DPWR#6

H_PWRGOOD14

H_CPUSLP#14

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_BR0#

H_IERR#
H_RESET#

H_RS#0
H_RS#1
H_RS#2

ITP_DBRRESET#

H_DPSLP#

H_DPRSTP#

PREQ#

PROCHOT#
H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

THERMDA
THERMDC
H_THERMTRIP#

JP19A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#

FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0 6
H_DINV#1 6
H_DINV#2 6
H_DINV#3 6

H_DSTBN#0 6
H_DSTBN#1 6
H_DSTBN#2 6
H_DSTBN#3 6
H_DSTBP#0 6
H_DSTBP#1 6
H_DSTBP#2 6
H_DSTBP#3 6

H_A20M# 14
H_FERR# 14
H_IGNNE# 14
H_INIT# 14
H_INTR 14
H_NMI 14

H_STPCLK# 14
H_SMI# 14

R68

47K_0402_5%@

1 2

C260

0.1U_0603_25V7K@

+1.05VS

H_THERMTRIP#

+1.05VS +CPU_CORE

12

12

R69
47K_0402_5%

MAINPWON 15,34,35,37,38

1

C

2

B

Q22

E

2SC2411K_SC59

3

1 2

R67
56_0402_5%

Place Caps Close to CPU Socket

C263 180P_0402_50V8J

1 2

C255 180P_0402_50V8J

1 2

C264 180P_0402_50V8J

1 2

C254 180P_0402_50V8J

1 2

C262 180P_0402_50V8J

1 2

C257 180P_0402_50V8J

1 2

C261 180P_0402_50V8J@

1 2

C256 180P_0402_50V8J

1 2

C265 180P_0402_50V8J

1 2

C640 180P_0402_50V8J

1 2

H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_IGNNE#
H_PWRGOOD
H_FERR#

2200P_0402_50V7K

EC_SMB_CK228
EC_SMB_DA228

CPU_STP#11,14,40

C503

1

THERMDA

2

THERMDC

2
3
8
7

R166
470_0402_5%

H_FERR#
PREQ#
H_DPSLP#
H_BR0#
H_DPRSTP#
ITP_TDI
ITP_TDO
H_RESET#
ITP_TMS
PROCHOT#
H_IERR#

H_PWRGOOD

H_CPUSLP#

ITP_DBRRESET#

ITP_TRST#

ITP_TCK
TEST1
TEST2

H_D#0

A19

1

C502

0.1U_0402_16V4Z

2

U26

D+
D­SCLK
SDATA

ADM1032ARM_RM8

12

1

VDD1

6

ALERT#

4

THERM#

5

GND

+1.05VS

R172

1 2

Q27

2

3 1

MMBT3904_SOT23

R72 56_0402_5%
R77 56_0402_5%@
R62 200_0402_5%

1 2

R70 200_0402_5%

1 2

R71 56_0402_5%@
R79 150_0402_5%
R78 54.9_0402_1%@
R63 54.9_0402_1%@
R64 40.2_0402_1%
R66 56_0402_5%
R75 56_0402_5%
R82 200_0402_5%
R81 200_0402_5%

1 2

R76 150_0402_5%@

R80 680_0402_5%
R65 27.4_0402_1%
R61 1K_0402_5%@
R294 1K_0402_5%@

470_0402_5%

2

H_DPSLP#

Q26
MMBT3904_SOT23

3 1

12
12

12
12
12
12
12
12
12
12

12

12
12
12
12

12

R303

10K_0402_5%@

+1.05VS

+3VS

THERMDA & THERMDC Trace / Space = 10 / 10 mil

5

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Dothan(1/2)

Size Document Number R ev

HAZ00/BL10E (LA2861) 1.0

Custom

2

Date: Sheet

442Monday, August 08, 2005

1

of

5

JP19B

R45 54.9_0402_1%@

1 2

R44 54.9_0402_1%@

1 2

D D

1.5V FOR DOTHAN-B

+VCCA

+1.5VS

0.01U_0402_16V7K

C C

R249
1K_0402_1%

B B

1 2

R250 2K_0402_1%

C495

+1.05VS

12

20mils

1

2

+CPU_CORE

CPU_BSEL07,11
CPU_BSEL111

VCCSENSE
VSSSENSE

+1.05VS

C489

1

10U_0805_6.3V6M

2

PSI#40

CPU_VID040
CPU_VID140
CPU_VID240
CPU_VID340
CPU_VID440
CPU_VID540

Width 12mils spacing 15mils

GTL_REF0

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

Dothan

4

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

+1.05VS

1

+

2

150U_D2_6.3VM

POWER, GROUNG, RESERVED SIGNALS AND NC

330U_D_2VM

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

Vcc-core
Decoupling

SPCAP,Polymer
MLCC 0805 X5R

0.1U_0402_16V4Z

1

C211

C467

2

+CPU_CORE

330U_D_2VM

1

+

C180

2

+CPU_CORE

10U_0805_6.3V6M

1

C193

2

+CPU_CORE

10U_0805_6.3V6M

1

C214

2

+CPU_CORE

10U_0805_6.3V6M

1

C206

2

+CPU_CORE

10U_0805_6.3V6M

1

C477

2

+CPU_CORE

10U_0805_6.3V6M

1

C475

2

0.1U_0402_16V4Z

1

C459

2

0.1U_0402_16V4Z

3

330U_D_2VM@

1

2

1

C192

2

10U_0805_6.3V6M

1

C215

2

10U_0805_6.3V6M

1

C207

2

10U_0805_6.3V6M

1

C479

2

10U_0805_6.3V6M

1

C451

2

10U_0805_6.3V6M

+

C492

330U_D_2VM@

1

C194

2

10U_0805_6.3V6M

1

C216

2

10U_0805_6.3V6M

1

C465

2

10U_0805_6.3V6M

1

C480

2

10U_0805_6.3V6M

1

C473

2

1

2

10U_0805_6.3V6M

+

C209

C195

C217

C464

C481

C469

1

+

C466

2

1

1

C196

2

2

10U_0805_6.3V6M

1

1

C218

2

2

10U_0805_6.3V6M

1

1

C463

2

2

10U_0805_6.3V6M

1

1

C478

2

2

10U_0805_6.3V6M

1

1

C474

2

2

10U_0805_6.3V6M

4 x 330uF(12mOhm/4)

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C,uF ESR, mohm ESL,nH

4X330uF 7m ohm/2 3.5nH/2
35X10uF 5m ohm/35 0.6nH/35

1

C205

2

0.1U_0402_16V4Z

1

1

C199

2

2

0.1U_0402_16V4Z

1

C210

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C212

1

C197

2

10U_0805_6.3V6M

1

C219

2

10U_0805_6.3V6M

1

C462

2

10U_0805_6.3V6M

1

C460

2

10U_0805_6.3V6M

1

C472

2

10U_0805_6.3V6M

1

2

1

C198

2

1

C220

2

1

C461

2

1

C482

2

1

C468

2

1

C201

2

0.1U_0402_16V4Z

2

1

C454

2

0.1U_0402_16V4Z

1

C453

2

0.1U_0402_16V4Z

1

C452

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C470

C191

2

0.1U_0402_16V4Z

+CPU_CORE

1

C471

2

JP19C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

R275 27.4_0402_1%

A A

1 2

R274 54.9_0402_1%

1 2

R243 27.4_0402_1%

1 2

R245 54.9_0402_1%

1 2

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils

5

COMP0
COMP1
COMP2
COMP3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Dothan(2/2)

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

B

2

Date: Sheet

542Monday, August 08, 2005

1

of

A

H_A#[3..31]4

H_REQ#[0..4]4

H_RS#[0..2]4

12

12

A

U21A

G28

CPU_A3#

H26

CPU_A4#

G27

CPU_A5#

G30

CPU_A6#

G29

CPU_A7#

G26

CPU_A8#

H28

CPU_A9#

J28

CPU_A10#

H25

CPU_A11#

K28

CPU_A12#

H29

CPU_A13#

J29

CPU_A14#

K24

CPU_A15#

K25

CPU_A16#

F29

CPU_REQ0#

G25

CPU_REQ1#

F26

CPU_REQ2#

F28

CPU_REQ3#

E29

CPU_REQ4#

H27

CPU_ADSTB0#

M28

CPU_A17#

K29

CPU_A18#

K30

CPU_A19#

J26

CPU_A20#

L28

CPU_A21#

L29

CPU_A22#

M30

CPU_A23#

K27

CPU_A24#

M29

CPU_A25#

K26

CPU_A26#

N28

CPU_A27#

L26

CPU_A28#

N25

CPU_A29#

L25

CPU_A30#

N24

CPU_A31#

L27

CPU_ADSTB1#

F25

CPU_ADS#

F24

CPU_BNR#

E23

CPU_BPRI#

E25

CPU_DEFER#

G24

CPU_DRDY#

F23

CPU_DBSY#

E27

CPU_LOCK#

C11

CPU_CPURSET#

D23

CPU_RS2#

G23

CPU_RS1#

E26

CPU_RS0#

F22

CPU_TRDY#

D26

CPU_HIT#

E24

CPU_HITM#

D11

CPU_COMP_N

B11

CPU_COMP_P

H22

CPU_VREF

D25

RESERVED0

E11

RESERVED1

G22

CPU_DPWR#

R38

49.9_0402_1%

***

R37
100_0402_1%

ADDR. GROUP

ADDR. GROUP

PART 1 OF 6

0

1

CPU I/F

CONTROLMISC.

RC410MD

216CPP4AKA21HK_BGA707

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9

***

R30

12

R234

12

CPU_VREF

1

C123

2

C121

H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15

H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17

H_A#18

H_A#19

H_A#20

H_A#21

H_A#22

H_A#23

H_A#24

H_A#25

H_A#26

H_A#27

H_A#28

H_A#29

H_A#30

H_A#31

H_RS#2
H_RS#1
H_RS#0

HSCOMP

HRCOMP

+1.05VS

1

2

1U_0402_6.3V4Z

1 1

H_ADSTB#04

2 2

H_ADSTB#14

H_ADS#4
H_BNR#4
H_BPRI#4
H_DEFER#4
H_DRDY#4
H_DBSY#4

H_LOCK#4
H_RESET#4,14

H_TRDY#4
H_HIT#4
H_HITM#4

3 3

+1.05VS

24.9_0402_1%

49.9_0402_1%

220P_0402_50V9J

Place C close
to Ball H22

H_DPWR#4

4 4

CPU_VREF
Trace=12Mil
Space=15Mil

CPU_VREF

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#

DATA GROUP 0

CPU_D14#
CPU_D15#

CPU_DBI0#
CPU_DSTBN0#
CPU_DSTBP0#

CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#

DATA GROUP 1

CPU_D29#
CPU_D30#
CPU_D31#

CPU_DBI1#
CPU_DSTBN1#
CPU_DSTBP1#

CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#

DATA GROUP 2

CPU_DBI2#
CPU_DSTBN2#
CPU_DSTBP2#

CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

DATA GROUP

3

CPU_DBI3#
CPU_DSTBN3#
CPU_DSTBP3#

B

H_D#[0..63] 4
H_DINV#[0..3] 4
H_DSTBN#[0..3] 4
H_DSTBP#[0..3] 4

H_D#0

E28

H_D#1

D28

H_D#2

D29

H_D#3

C29

H_D#4

D30

H_D#5

C30

H_D#6

B29

H_D#7

C28

H_D#8

C26

H_D#9

B25

H_D#10

B27

H_D#11

C25

H_D#12

A27

H_D#13

C24

H_D#14

A24

H_D#15

B26

H_DINV#0

C27

H_DSTBN#0

A28

H_DSTBP#0

B28

H_D#16

C19

H_D#17

C23

H_D#18

C20

H_D#19

C22

H_D#20

B22

H_D#21

B23

H_D#22

C21

H_D#23

B24

H_D#24

E21

H_D#25

B21

H_D#26

B20

H_D#27

G19

H_D#28

F21

H_D#29

B19

H_D#30

E20

H_D#31

D21

H_DINV#1

A21

H_DSTBN#1

D22

H_DSTBP#1

E22

H_D#32

C18

H_D#33

F19

H_D#34

E19

H_D#35

A18

H_D#36

D19
B18
C17
B17
E17
B16
C15
A15
B15
F16
G18
F18
C16
D18
E18

E16
D16
C14
B14
E15
D15
C13
E14
F13
B13
A12
C12
E12
D13
D12
B12
E13
F15
G15

H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46

H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2

H_D#48

H_D#49

H_D#50

H_D#51

H_D#52

H_D#53

H_D#54

H_D#55

H_D#56

H_D#57

H_D#58

H_D#59

H_D#60

H_D#61

H_D#62

H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3

+1.2VS

SB_A_RXN0

SB_A_RXP0

SB_A_RXN1

SB_A_RXP1
NB_A_RXN0
NB_A_RXP0
NB_A_RXN1
NB_A_RXP1

Place R
Close to Ball

C430 0.1U_0402_10V6K

C427 0.1U_0402_10V6K

CLK_NB_ALINK#11
CLK_NB_ALINK11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

ATI recommendation R40, R41

PCE_RXISET

R2910K_0402_1%

12

PCE_TXISET

R348.25K_0402_1%

12

PCE_NCAL

R3382.5_0402_1%

12

PCE_PCAL

R28150_0402_1%

12

C432

1 2

C429

1 2

0.1U_0402_10V6K

0.1U_0402_10V6K

SB_A_RXN[0..1]
SB_A_RXP[0..1]

NB_A_RXN[0..1]
NB_A_RXP[0..1]

1 2

1 2

To SB A-PCIE Link

2005/03/01 2006/03/01

C

J4
J5

L4

K4
L5

L6

M4
M5

P4
N4

P5
P6

R4
R5

T3
T4

U5
U6

V4
V5

W3
W4

Y5
Y6

AA4
AA5

AB3
AB4

AC5
AC6

AD4
AD5

10 mils
10 mils
10 mils

10 mils

NB_A_TXN0
NB_A_TXP0
NB_A_TXN1
NB_A_TXP1

AJ12
AK13
AG12
AH12

AJ11

AJ10
AK10

AK9

AG10

AG9

AF10

AE9

L2
K2

SB_A_RXN[0..1] 14
SB_A_RXP[0..1] 14

NB_A_RXN[0..1] 14
NB_A_RXP[0..1] 14

Compal Secret Data

Deciphered Date

U21C

GFX_RX0N
GFX_RX0P

GFX_RX1N
GFX_RX1P

GFX_RX2N
GFX_RX2P

GFX_RX3N
GFX_RX3P

GFX_RX4N
GFX_RX4P

GFX_RX5N
GFX_RX5P

GFX_RX6N
GFX_RX6P

GFX_RX7N
GFX_RX7P

GFX_RX8N
GFX_RX8P

GFX_RX9N
GFX_RX9P

GFX_RX10N
GFX_RX10P

GFX_RX11N
GFX_RX11P

GFX_RX12N
GFX_RX12P

GFX_RX13N
GFX_RX13P

GFX_RX14N
GFX_RX14P

GFX_RX15N
GFX_RX15P

PCE_ISET
PCE_TXISET
PCE_NCAL
PCE_PCAL

SB_TX0N
SB_TX0P
SB_TX1N
SB_TX1P

SB_RX0N
SB_RX0P
SB_RX1N
SB_RX1P

SB_CLKN
SB_CLKP

D

PART 3 OF 6

PCI EXPRESS I/F

RC410MD

A-LINK EXPRESS I/F

216CPP4AKA21HK_BGA707

D

E

N2

GFX_TX0N

N1

GFX_TX0P

R2

GFX_TX1N

P2

GFX_TX1P

T1

GFX_TX2N

R1

GFX_TX2P

U2

GFX_TX3N

T2

GFX_TX3P

V1

GFX_TX4N

V2

GFX_TX4P

W2

GFX_TX5N

W1

GFX_TX5P

AA2

GFX_TX6N

Y2

GFX_TX6P

AB1

GFX_TX7N

AA1

GFX_TX7P

AC2

GFX_TX8N

AB2

GFX_TX8P

AD1

GFX_TX9N

PCI EXPRESS I/F

GFX_TX10N
GFX_TX10P

GFX_TX11N
GFX_TX11P

GFX_TX12N
GFX_TX12P

GFX_TX13N
GFX_TX13P

GFX_TX14N
GFX_TX14P

GFX_TX15N
GFX_TX15P

GPP_TX0N/SB_TX2N
GPP_TX0P/SB_TX2P
GPP_TX1N/SB_TX3N
GPP_TX1P/SB_TX3P

GPP_RX0N/SB_RX2N
GPP_RX0P/SB_RX2P
GPP_RX1N/SB_RX3N
GPP_RX1P/SB_RX3P

AD2

GFX_TX9P

AE2
AE1

AG2
AF2

AH1
AG1

AJ2
AH2

AJ4
AJ3

AJ5
AK4

M1

GFX_CLKN

M2

GFX_CLKP

AJ9
AJ8
AF6
AE6
AK6

GPP_TX2N

AJ6

GPP_TX2P

AF4

GPP_TX3N

AE4

GPP_TX3P

AG8
AF8
AG7
AG6
AJ7

GPP_RX2N

AK7

GPP_RX2P

AH4

GPP_RX3N

AG4

GPP_RX3P

Compal Electronics, Inc.

Title

RC410MD-FSB, PCIE,A-PCIE

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

B

Monday, August 08, 2005

Date: Sheet

E

642

of

A

DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]

DDR_SMA[0..17]

1 1

+1.8V

12

R42

1

C172

1K_0603_1%

1K_0603_1%

2 2

+1.8V

R242

12

***

61.9_0603_1%

R237

12

3 3

C435

61.9_0603_1%

Place these R and C
close to relative Ball.

FSB SPEED

100MHZ

133MHZ

4 4

2

0.1U_0402_10V6K

12

R46

1

C174

2

0.1U_0402_10V6K

MEM_COMPN
MEM_COMPP

1

1

C450

2

2

0.47U_0603_10V7K

NB STRAPING PINS

BM_REQ# NB_CRT_HSYNC NB_CRT_VSYNC

0
0

BM_REQ#

NB_CRT_HSYNC

NB_CRT_VSYNC

DDR_DQ[0..63] 9,10
DDR_DQS[0..7] 9,10
DDR_DQS#[0..7] 9,10
DDR_DM[0..7] 9,10

DDR_SMA[0..17] 9,10

DDR_SRAS#9,10
DDR_SCAS#9,10
DDR_SWE#9,10

DDR_CLK0#9
DDR_CLK09

DDR_CLK1#9
DDR_CLK19

DDR_CLK3#10

+DDR_VREF

DDR_CLK310
DDR_CLK4#10

DDR_CLK410

DDR_SCKE09
DDR_SCKE19
DDR_SCKE29,10
DDR_SCKE39,10

DDR_SCS#09
DDR_SCS#19
DDR_SCS#29,10
DDR_SCS#39,10
DDR_ODT09
DDR_ODT19,10
DDR_ODT29
DDR_ODT39,10

MEM_VMODE: 1.8V: DDR2

MEM_CAP1
MEM_CAP2

0.47U_0603_10V7K

0
0

R223 4.7K_0402_5%@

1 2

R222 4.7K_0402_5%

1 2

R20 4.7K_040 2_5%

1 2

R228

1 2

4.7K_0402_5%

MMBT3904_SOT23

A

R43 1K_0402_5%

+1.8V

0
1

+3VS

12

R227

4.7K_0402_5%

Q35

3 1

1 2

MEM_CAP1
MEM_CAP2
MEM_COMPP
MEM_COMPN
+DDR_VREF

R229

2

4.7K_0402_5%

DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_SMA13
DDR_SMA14
DDR_SMA15
DDR_SMA16
DDR_SMA17

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

DDR_ODT0
DDR_ODT1

DDR_ODT2
DDR_ODT3

DDR_DQS#0
DDR_DQS0

DDR_DQS#1
DDR_DQS1

DDR_DQS#2
DDR_DQS2

DDR_DQS#3
DDR_DQS3

DDR_DQS#4
DDR_DQS4

DDR_DQS#5
DDR_DQS5

DDR_DQS#6
DDR_DQS6

DDR_DQS#7
DDR_DQS7

+3VS

12

10mil
10mil
10mil
10mil
20mil

U21B

AK27

MEM_A0

AJ27

MEM_A1

AH26

MEM_A2

AJ26

MEM_A3

AH25

MEM_A4

AJ25

MEM_A5

AH24

MEM_A6

AH23

MEM_A7

AJ24

MEM_A8

AJ23

MEM_A9

AH27

MEM_A10

AH22

MEM_A11

AJ22

MEM_A12

AF28

MEM_A13

AJ21

MEM_A14

AG27

MEM_A15

AJ28

MEM_A16

AH21

MEM_A17

AJ29

MEM_RAS#

AG28

MEM_CAS#

AH30

MEM_WE#

AC26

MEM_CK0N

AC25

MEM_CK0P

AF16

MEM_CK1N

AE16

MEM_CK1P

V29

MEM_CK2N

V30

MEM_CK2P

AC24

MEM_CK3N

AC23

MEM_CK3P

AG17

MEM_CK4N

AF17

MEM_CK4P

W29

MEM_CK5N

W28

MEM_CK5P

AH20

MEM_CKE0

AJ20

MEM_CKE1

AE24

MEM_CKE2

AE21

MEM_CKE3

AH29

MEM_CS#0

AG29

MEM_CS#1

AH28

MEM_CS#2

AF29

MEM_CS#3

AG30

MEM_ODT0

AE28

MEM_ODT1

AC30

MEM_ODT2/RSV2

Y30

MEM_ODT3/RSV3

AD28

MEM_VMODE

AJ14

MEM_CAP1

N30

MEM_CAP2

AJ15

MEM_COMPP

AE29

MEM_COMPN

AB27

MEM_VREF

AH17

MEM_DQS0N

AJ18

MEM_DQS0P

AF15

MEM_DQS1N

AE14

MEM_DQS1P

AE22

MEM_DQS2N

AF22

MEM_DQS2P

AF26

MEM_DQS3N

AE25

MEM_DQS3P

W26

MEM_DQS4N

W27

MEM_DQS4P

AB30

MEM_DQS5N

AB29

MEM_DQS5P

R25

MEM_DQS6N

P25

MEM_DQS6P

R30

MEM_DQS7N

R29

MEM_DQS7P

CPU_BSEL0 5,11

B

PART 2 OF

6

ADDRESS

MEMORY I/F

RC410MD

DATA CLKMISC

216CPP4AKA21HK_BGA707

STRP_DATA

NB_DDC_CLK

MMBT3904_SOT23

B

DATA

4.7K_0402_5%

4.7K_0402_5%@

Q5

3 1

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8

MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63

MEM_DM0

MEM_DM1

MEM_DM2

MEM_DM3

MEM_DM4

MEM_DM5

MEM_DM6

MEM_DM7

R225

1 2

R220

1 2

1 2

2

2K_0402_5%

R11

C

AJ16
AH16
AJ19
AH19
AH15
AK16
AH18
AK19
AF13
AF14
AE19
AF19
AE13
AG13
AF18
AE17
AF20
AF21
AG23
AF24
AG19
AG20
AG22
AF23
AD25
AG25
AE27
AD27
AE23
AD24
AE26
AD26
AA25
Y26
W24
U25
AA26
Y25
V26
W25
AC28
AC29
AA29
Y29
AD30
AD29
AA30
Y28
U27
T27
N26
M27
U26
T26
P27
P26
U29
T29
P29
N29
U28
T28
P28
N27

AJ17
AG15
AE20
AF25
Y27
AB28
R26
R28

DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7

NB_LUMA12

NB_CRMA12

1 2

R27 75_0402_1%

NB_CRT_R13
NB_CRT_G13
NB_CRT_B13

NB_CRT_HSYNC13

NB_CRT_VSYNC13

1 2

R232 715_0402_1%

NB_DDC_CLK13
NB_DDC_DATA13

CLK_NB_14M11

CLK_NB_BCLK11
CLK_NB_BCLK#11

NB_EDID_CLK12

NB_EDID_DATA12

R230

1 2

Low: Normal Mode(Fixed)
High: Test Mode

R219

1 2

4.7K_0402_5%
R226

1 2

+3VS

4.7K_0402_5%
R23

1 2

4.7K_0402_5%@

C422

12

15P_0402_50V8D@

10_0402_5%

R217 10K_0402_5%

NB_EDID_CLK
NB_EDID_DATA
NB_DVI_DDCDATA
STRP_DATA
TESTMODE

4.7K_0402_5%

NB_EDID_CLK

NB_EDID_DATA

NB_DVI_DDCDATA

U19

1

NC

2

A1

3

A2

4

VSS

AT24C04N-10SI-2.7_SO8~D@

NB_COMPS

NB_DDC_CLK
NB_DDC_DATA

12

1 2

0.1U_0402_10V6K@

VCC

SDA

RSET

15mil

R218

WP

SCL

C420

8
7
6
5

F9
D9
E9

F10
E10
D10

C3
B3

B10

B2
C2

G1

F1
G2

J1

K1

D2
C1
H3
D1
C4

AH13

AJ13

R22

1 2

4.7K_0402_5%

2

1

**

+3VS

STRP_DATA: DEBUG STRAP
DEFAULT: 1
0: MEMORY CHA NNEL STRAPING
1: E2PROM STRAPING

NB_DDC_CLK: CPU VCC SEL
DEFAULT: 1 1: DESKTOP CPU 0: MOBILE CPU

SB_PWRGD# 16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

U21D

Y
C
COMP

RED
GREEN
BLUE

DACHSYNC
DACVSYNC

RSET
DACSCL

DACSDA

OSCIN

OSCOUT
TVCLKIN
CPU_CLKP

CPU_CLKN

I2C_CLK
I2C_DATA
DDC_DATA
STRP_DATA
TESTMODE
THERMALDIODE_P
THERMALDIODE_N

+3VS

12

R214

1K_0402_5%@

NB_EDID_CLK
STRP_DATA

D

CRT & TV

I/F

CLK. GEN.

216CPP4AKA21HK_BGA707

LVDS_ENBKL

LVDS_ENVDD

D

PART 4 OF 6

RC410MD

SUS_STAT#

NB_PWRGD

E

TXCLK_UN
TXCLK_UP

TXCLK_LN
TXCLK_LP

BMREQ#

TMDS_HPD

+1.8V

R236

4.7K_0402_5%

1 2

+3VALW

14

U5A

P

A

O

B

G

SN74LVC08APW_TSSOP14

7

B4
A4
B5
C6
B6
A6
B7
A7
F7
F8

E5
F5
D5
C5
E6
D6
E7
E8
G6
F6

G3
E2
F2

A3
AH14
E3

H2

J2

3

2 1

2 1

LVDS_ENBKL
LVDS_ENVDD

NB_TXOUT0­NB_TXOUT0+
NB_TXOUT1­NB_TXOUT1+
NB_TXOUT2­NB_TXOUT2+

NB_TXCLK­NB_TXCLK+

1 2
1 2

NB_RST#
SUS_STAT#
NB_PWRGD

BM_REQ#

12

R216

10K_0402_5%

D21

CH751H-40_SC76
D20

NB_RST#

CH751H-40_SC76

ENBKL 28

NB_TXOUT0- 12
NB_TXOUT0+ 12
NB_TXOUT1- 12
NB_TXOUT1+ 12
NB_TXOUT2- 12
NB_TXOUT2+ 12

NB_TXCLK- 12
NB_TXCLK+ 12

R21 4.7K_0402_5%@
R224

NB_RST# 14
NB_PWRGD 16

BM_REQ# 14

4.7K_0402_5%@

NB_SUS_STAT# 15

LVDS

POWERGOOD

TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P

LVDS_BLON

LVDS_DIGON

LVDS_BLEN

SYSRESET#
SUS_STAT#

1
2

***

+3VALW

14

U5B

4

P

A

6

O

5

B

G

SN74LVC08APW_TSSOP14

7

Compal Electronics, Inc.

Title

RC410MD-DDR/DISP/MISC

Size Document Number Re v

Date: Sheet

HAZ00/BL10E (LA2861) 1.0

Custom

Monday, August 08, 2005

NB_ENVDD 12

E

742

of

A

C53

220U_D_6.3VM

0.1U_0402_16V4Z

+1.05VS

1

2

0.1U_0402_16V4Z

1

+

2

C47

1

2

+1.2VS

0.1U_0402_16V4Z

+AVDDQ

1

C57

2

1U_0402_6.3V4Z

C650

22U_1206_6.3V6M

1

2

A

5A

+1.05VS

5A

+AVDD

2

C46

+CPVDD
+MPVDD

1

1U_0402_6.3V4Z

ATI recommend 2.2uF

1

C29

0.1U_0402_16V4Z

2

+LPVDD

1

C30

C33

1U_0402_6.3V4Z

2

10U_0805_10V4Z

+1.2VS

M13
M15
M17
M19
N12
N14
N16
N18
P13
P15
P17
P19
R12
R14
R16
R18
T13
T15
T17
T19
U12
U14
U16
U18
V13
V15
V17

V19
W12
W14
W16
W18

A10

F11

F12

F17

G11

G12

G13

G14

G16

G17

G20

H11

H12

H13

H14

H16

H17

H19

H23

H24

L23

L24

N23

P23

P24

C9

B8

D8

H21

AB26

1

C44

2

L6

1 2

CHB2012U170_0805

U21E

VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE

VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU

AVDD
AVDDQ

AVDDDI
CPVDD

MPVDD

+AVDD

1

C32

1U_0402_6.3V4Z

2

L5

+1.8VS

1 2

CHB2012U170_0805

CORE PWR

216CPP4AKA21HK_BGA707

+1.8VS

1 2

C65 10U_0805_10V4Z

1 2

C64 10U_0805_10V4Z

1 2

C75 0.1U_0402_16V4Z

1 2

C107 0.1U_0402_16V4Z

1 2

C88 0.1U_0402_16V4Z

1 2

C90 0.1U_0402_16V4Z

1 2

C104 0.1U_0402_16V4Z

1 1

1 2

C73 0.1U_0402_16V4Z

1 2

C74 0.1U_0402_16V4Z

1 2

C105 0.1U_0402_16V4Z

1 2

C36 0.1U_0402_16V4Z

1 2

C55 0.1U_0402_16V4Z

1 2

C89 0.1U_0402_16V4Z

1 2

C71 0.1U_0402_16V4Z

1 2

C106 0.1U_0402_16V4Z

1 2

C49 0.1U_0402_16V4Z

1 2

C50 0.1U_0402_16V4Z

1 2

C79 10U_0805_10V4Z

1 2

C118 10U_0805_10V4Z

1 2

C80 0.1U_0402_16V4Z

2 2

1 2

C100 0.1U_0402_16V4Z

1 2

C131 0.1U_0402_16V4Z

1 2

C91 0.1U_0402_16V4Z

1 2

C69 0.1U_0402_16V4Z

1 2

C133 0.1U_0402_16V4Z

1 2

C150 0.1U_0402_16V4Z

1 2

C151 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4Z

1 2

C95 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

1 2

C144 0.1U_0402_16V4Z

1 2

C59 0.1U_0402_16V4Z

Place C between
Ball D8,C8

+1.8VS

3 3

4 4

L8

1 2

CHB1608U301_0603

C48

C54

1

1

2

2

0.1U_0402_16V4Z

B

PART 5 OF

6

POWER

RC410MD

+3VS

1

+

C289
470U_D2_2.5VM

2

B

MEM I/F PWR

CPU I/F

VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM

PWR

+CPVDD

LVDDR18D
LVDDR18A
LVDDR18A

C137

0.1A

VDD_18
VDD_18
VDD_18
VDD_18

VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12

0.75A

VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18

VDDR3
VDDR3

LPVDD

PLLVDD

1

C648

10U_0805_10V4Z

2

1

C138

2

10U_0805_10V4Z

+1.8V

2A

AB23
AB24
AC13
AC16
AC19
AC21
AC22
AD13
AD16
AD19
AD21
AD22
AD23
AK21
AK24
AK28
T23
T24
V23
V24
Y23
Y24

AB22
AB9
J22
J9

2.25A

AB7
AC7
AC8
AD9
H4
H5
J6
K6
L7
L8
M7
M8
P7
P8
T7
T8
W7
W8

AB8
AC10
AC9
AD10
AE11
AF11
AG11
U7
U8
Y7
Y8

0.1A

G4
G5
J8
C7
H7
H8
H10

0.1U_0402_16V4Z

1

2

1

1

2

2

1U_0402_6.3V4Z

C

**

1 2

C87 0.1U_0402_16V4Z

1 2

C103 0.1U_0402_16V4Z

1 2

C149 0.1U_0402_16V4Z

L4

1 2

CHB1608U301_0603

+1.2VS

+VDDQ
+LPVDD

+PLLVDD

C649

L11

1 2

CHB1608U301_0603

C114

0.1U_0402_16V4Z

1 2

C134 0.1U_0402_16V4Z

1 2

C135 0.1U_0402_16V4Z

1 2

C58 0.1U_0402_16V4Z

1 2

C67 0.1U_0402_16V4Z

1 2

C31 10U_0805_10V4Z

1 2

C28 10U_0805_10V4Z

L7

1 2

CHB1608U301_0603

1 2

C70 0.1U_0402_16V4Z

1 2

C56 1U_0402_6.3V4Z

1 2

C68 0.1U_0402_16V4Z

1 2

C63 0.1U_0402_16V4Z

1 2

C62 0.1U_0402_16V4Z

1 2

C51 0.1U_0402_16V4Z

1 2

C45 10U_0805_10V4Z

20mils

20mils

ATI recommend separate pure power

20mils

1 2

CHB2012U170_0805

1

C37

0.1U_0402_16V4Z

2

1

C158

2

+1.8VS

+3VS+VDDQ

L37

+1.8VS

1U_0402_6.3V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

+1.8V

1 2

C115 10U_0805_10V4Z

1 2

C72 10U_0805_10V4Z

1 2

C119 10U_0805_10V4Z

1 2

C93 10U_0805_10V4Z

1 2

C166 0.1U_0402_16V4Z

1 2

C76 0.1U_0402_16V4Z

1 2

C124 0.1U_0402_16V4Z

1 2

C152 0.1U_0402_16V4Z

1 2

C132 0.1U_0402_16V4Z

1 2

C117 0.1U_0402_16V4Z

1 2

C122 0.1U_0402_16V4Z

1 2

C139 0.1U_0402_16V4Z

1 2

C110 0.1U_0402_16V4Z

1 2

C86 0.1U_0402_16V4Z

1 2

C77 0.1U_0402_16V4Z

1 2

C130 0.1U_0402_16V4Z

1 2

C129 0.1U_0402_16V4Z

+1.8VS

C641

10U_0805_10V4Z

2005/03/01 2006/03/01

1 2

C141 0.1U_0402_16V4Z

1 2

C140 0.1U_0402_16V4Z

+1.2VS

1 2

C61 10U_0805_10V4Z

1 2

C418 10U_0805_10V4Z

1 2

C66 10U_0805_10V4Z

1 2

C23 10U_0805_10V4Z

1 2

C417 10U_0805_10V4Z

1 2

C22 1U_0402_6.3V4Z

1 2

C25 1U_0402_6.3V4Z

1 2

C85 0.1U_0402_16V4Z

1 2

C43 0.1U_0402_16V4Z

1 2

C84 0.1U_0402_16V4Z

1 2

C102 0.1U_0402_16V4Z

1 2

C41 0.1U_0402_16V4Z

1 2

C42 0.1U_0402_16V4Z

1 2

C78 0.1U_0402_16V4Z

1 2

C40 0.1U_0402_16V4Z

+

1 2

470U_D2_2.5VM

C414

+

1 2

470U_D2_2.5VM

C15

Place L close to Ball AB26
Place C between Ball AB26,AA27

L12

1 2

CHB1608U301_0603

1

1

1

C175

C159

0.1U_0402_16V4Z

2

2

2

1U_0402_6.3V4Z

Compal Secret Data

Deciphered Date

+1.8VS+MPVDD

D

D

A13
A16
A19

A22
A25
A29

AA23
AA24
AA28
AC11
AC12
AC14
AC15
AC17
AC18
AC20
AC27
AD11
AD12
AD14
AD15
AD17
AD18
AD20
AE30
AF12

AF27
AG14
AG16
AG18
AG21
AG24
AG26
AH11

AJ1

AJ30
AK12
AK15
AK18

AK2
AK22
AK25
AK29

B30

D14

D17

D20

D24

D27

F27

F30

G10

H15

H18

J23

J24

J27

J30

K23

M12
M14
M16
M18
M23
M24
M26
N13
N15
N17
N19
P12
P14
P16
P18

C60

0.1U_0402_16V4Z

E

U21F

VSS
VSS
VSS

A2

VSS
VSS
VSS
VSS

A9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B1

VSS
VSS
VSS
VSS
VSS
VSS
VSS

D3

VSS

D4

VSS
VSS

F3

VSS
VSS

F4

VSS
VSS
VSS
VSS
VSS
VSS
VSS

J3

VSS
VSS
VSS

K8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

216CPP4AKA21HK_BGA707

+PLLVDD

1

1

2

C81

1U_0402_6.3V4Z

2

Title

RC410MB PWR/GND

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

Custom

Date: Sheet

PART 6 OF 6

GOUNDRC410MD

+1.8VS

L10

1 2

CHB1608U301_0603

1

C82

10U_0805_10V4Z

2

Compal Electronics, Inc.

Thursday, August 04, 2005

E

R13

VSS

R15

VSS

R17

VSS

R19

VSS

R23

VSS

R24

VSS

R27

VSS

T12

VSS

T14

VSS

T16

VSS

T18

VSS

T30

VSS

U13

VSS

U15

VSS

U17

VSS

U19

VSS

U23

VSS

U24

VSS

V12

VSS

V14

VSS

V16

VSS

V18

VSS

V27

VSS

V28

VSS

W13

VSS

W15

VSS

W17

VSS

W19

VSS

W23

VSS

W30

VSS

AA3

VSSA

AA7

VSSA

AA8

VSSA

AB5

VSSA

AB6

VSSA

AC3

VSSA

AD3

VSSA

AD7

VSSA

AD8

VSSA

AE8

VSSA

AF3

VSSA

AF5

VSSA

AF7

VSSA

AF9

VSSA

AG5

VSSA

AH10

VSSA

AH3

VSSA

AH5

VSSA

AH6

VSSA

AH7

VSSA

AH8

VSSA

AH9

VSSA

K5

VSSA

L3

VSSA

M3

VSSA

N5

VSSA

N6

VSSA

N7

VSSA

N8

VSSA

P3

VSSA

R3

VSSA

R7

VSSA

R8

VSSA

T5

VSSA

T6

VSSA

U3

VSSA

V3

VSSA

V7

VSSA

V8

VSSA

W5

VSSA

W6

VSSA

Y3

VSSA

C10

AVSSN

B9

AVSSQ

C8

AVSSDI

J7

LPVSS

G7

LVSSR

G8

LVSSR

G9

LVSSR

H9

PLLVSS

H20

CPVSS

AA27

MPVSS

1

C116

10U_0805_10V4Z

2

of

842

A

B

C

D

E

F

G

H

12

12

C176 22U_1206_6.3V6M

1

2

+1.8V

R13

1K_0402_5%

R14

1K_0402_5%

C177 22U_1206_6.3V6M

1

2

2

C19

0.1U_0402_16V4Z

1

C18 0.1U_0402_16V4Z

1

2

DDR_SCKE07

DDR_SWE#7,10
DDR_SCAS#7,10

DDR_SCS#17
DDR_ODT27

DDR_DQS#6
DDR_DQS6

DDR_DQ50 DDR_DQ55
DDR_DQ54

DDR_DQ61
DDR_DM7 DDR_DQS#7
DDR_DQ62

SB_SMDATA10,11,15
SB_SMCLK10,11,15

DDR_DQ58

+3VS

Layout Note:
Place near JDIM1

+1.8V

1 1

C148

470U_D2_2.5VM

2 2

3 3

4 4

1

+

2

+0.9VS

C447 0.1U_0402_16V4Z

1

2

DDR_SCKE37,10

DDR_SCS#27,10

DDR_ODT37,10

C143 0.1U_0402_16V4Z

1

2

C445 0.1U_0402_16V4Z

1

2

C154 0.1U_0402_16V4Z

C101 0.1U_0402_16V4Z

C162 0.1U_0402_16V4Z

C163 0.1U_0402_16V4Z

C111 0.1U_0402_16V4Z

1

1

2

C439 0.1U_0402_16V4Z

C438 0.1U_0402_16V4Z

1

1

2

2

RP1

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP2

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP3

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP4

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

1

2

C437 0.1U_0402_16V4Z

1

2

+0.9VS

1

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to V_DDR_MCH_REF

C443 0.1U_0402_16V4Z

C444 0.1U_0402_16V4Z

1

1

2

2

DDR_SCKE1
DDR_SCKE3 DDR_SCKE2

DDR_SMA17

DDR_SMA9
DDR_SMA2
DDR_SMA5

DDR_SMA15
DDR_SMA0
DDR_SRAS#
DDR_SCAS#

DDR_SCS#2
DDR_SMA13
DDR_SCS#1
DDR_ODT3

1

2

C436 0.1U_0402_16V4Z

1

2

1 2

56_0402_5%

C96 0.1U_0402_16V4Z

1

2

C161 0.1U_0402_16V4Z

1

2

RP11

56_1206_8P4R_5%
RP12

56_1206_8P4R_5%
RP13

56_1206_8P4R_5%
RP14

56_1206_8P4R_5%

R40

DDR_SCKE0

45
36

DDR_SMA11DDR_SMA14

27

DDR_SMA12

18

DDR_SMA6DDR_SMA7

45

DDR_SMA8

36

DDR_SMA4

27

DDR_SMA3

18

DDR_SMA10

45

DDR_SMA1

36

DDR_SMA16

27

DDR_SWE#

18

45
36
27
18

C113 0.1U_0402_16V4Z

1

2

C156 0.1U_0402_16V4Z

1

2

DDR_SCS#0
DDR_ODT0
DDR_ODT1
DDR_SCS#3

DDR_ODT2

C145 0.1U_0402_16V4Z

1

2

C94 0.1U_0402_16V4Z

1

2

C642 0.1U_0402_16V4Z

1

2

C83 0.1U_0402_16V4Z

1

1

2

2

DDR_SCKE2 7,10

DDR_ODT1 7,10
DDR_SCS#3 7,10

C136 0.1U_0402_16V4Z

C643 0.1U_0402_16V4Z

1

2

C120 0.1U_0402_16V4Z

1

2

DDR_VREF1

C644 0.1U_0402_16V4Z

1

2

C108 0.1U_0402_16V4Z

C147 0.1U_0402_16V4Z

1

1

2

2

Layout Note:
Place these resistor
closely JDIM2,all
trace length<750 mil

Layout Note:
Place these resistor
closely JDIM2,all
trace length Max=1.3"

+1.8V +1.8V

DDR_VREF1

JP16

1

VREF

3

C185

1

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

DIMMA
Reverse

DDR_DQ10
DDR_DQ14

DDR_DQS#1

DDR_DQS1
DDR_DQ9

DDR_DQ13
DDR_DQ1

DDR_DQ0

DDR_DQS#0

DDR_DQS0
DDR_DQ3 DDR_DQ6

DDR_DQ2 DDR_DQ7

DDR_DQ16
DDR_DQ20

DDR_DQS#2

DDR_DQS2
DDR_DQ23

DDR_DQ19
DDR_DQ28

DDR_DQ25
DDR_DM3

DDR_DQ26
DDR_DQ27

DDR_SCKE0

DDR_SMA17
DDR_SMA12

DDR_SMA9 DDR_SMA7
DDR_SMA8

DDR_SMA5
DDR_SMA3
DDR_SMA1

DDR_SMA10
DDR_SMA15
DDR_SWE#

DDR_SCAS#
DDR_SCS#1

DDR_ODT2
DDR_DQ32

DDR_DQ36

DDR_DQS#4

DDR_DQS4
DDR_DQ38

DDR_DQ35
DDR_DQ45

DDR_DQ40
DDR_DM5

DDR_DQ43
DDR_DQ52

2.2U_0805_10V6K

C187 0.1U_0402_16V4Z

1

2

DQ12
DQ13

CK0#
DQ14

DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS

NC
DM2
VSS

VSS

VSS

VSS

VSS
VDD

VDD

A11

A7
A6

VDD

A4
A2
A0

VDD

BA1
S0#

VDD

VDD

NC
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO

SA1

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_DQ15
DDR_DQ12

DDR_DM1
DDR_DQ8

DDR_DQ11
DDR_DQ4

DDR_DQ5
DDR_DM0
DDR_CLK1

DDR_CLK1#

DDR_DQ17
DDR_DQ21

DDR_DM2
DDR_DQ22

DDR_DQ18
DDR_DQ29

DDR_DQ24
DDR_DQS#3

DDR_DQS3
DDR_DQ30

DDR_DQ31

DDR_SCKE1

DDR_SMA14
DDR_SMA11
DDR_SMA6
DDR_SMA4

DDR_SMA2
DDR_SMA0

DDR_SMA16
DDR_SRAS#
DDR_SCS#0

DDR_ODT0
DDR_SMA13

DDR_DQ37
DDR_DQ33

DDR_DM4
DDR_DQ39

DDR_DQ34
DDR_DQ44

DDR_DQ41

DDR_DQS#5

DDR_DQS5
DDR_DQ42DDR_DQ46

DDR_DQ47
DDR_DQ53

DDR_DQ49DDR_DQ48
DDR_CLK0

DDR_CLK0#

DDR_DM6

DDR_DQ51
DDR_DQ60DDR_DQ56

DDR_DQ57

DDR_DQS7
DDR_DQ63

DDR_DQ59

ATI recommendation

+3VS

Trace=20mil

DDR_CLK1 7
DDR_CLK1# 7

DDR_SCKE1 7

DDR_SRAS# 7,10
DDR_SCS#0 7

DDR_ODT0 7

DDR_CLK0 7
DDR_CLK0# 7

DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]

DDR_SMA[0..17]

DDR_DQ[0..63] 7,10
DDR_DQS[0..7] 7,10
DDR_DQS#[0..7] 7,10
DDR_DM[0..7] 7,10

DDR_SMA[0..17] 7,10

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

E

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

DDRII-SODIMM2

Size Documen t N u mb er Re v

HAZ00/BL10E (LA2861) 1.0

C

Monday, August 08, 2005

Date: Sheet of

G

942

H

A

DDR_DQ[0..63]7,9
DDR_DQS[0..7]7, 9

DDR_DQS#[0..7]7,9

1 1

2 2

3 3

DDR_DM[0..7]7,9

DDR_SMA[0..17]7,9

DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]

DDR_SCKE27,9

DDR_SWE#7,9

DDR_SCAS#7,9
DDR_SCS#37,9

DDR_ODT37,9

SB_SMDATA9,11,15
SB_SMCLK9,11,15

B

+3VS

DDR_DQ10
DDR_DQ14

DDR_DQS#1
DDR_DQS1

DDR_DQ9
DDR_DQ13

DDR_DQ1
DDR_DQ0

DDR_DQS#0
DDR_DQS0

DDR_DQ3
DDR_DQ2

DDR_DQ16
DDR_DQ20

DDR_DQS#2
DDR_DQS2

DDR_DQ23
DDR_DQ19

DDR_DQ25
DDR_DM3

DDR_DQ26
DDR_DQ27

DDR_SCKE2

DDR_SMA17
DDR_SMA12

DDR_SMA9
DDR_SMA8

DDR_SMA5
DDR_SMA3
DDR_SMA1

DDR_SMA10
DDR_SMA15
DDR_SWE#

DDR_SCAS#
DDR_SCS#3

DDR_ODT3
DDR_DQ32

DDR_DQ36
DDR_DQS#4

DDR_DQS4
DDR_DQ38

DDR_DQ35
DDR_DQ45

DDR_DQ40
DDR_DM5
DDR_DQ46

DDR_DQ43
DDR_DQ52

DDR_DQ48

DDR_DQS#6
DDR_DQS6

DDR_DQ50
DDR_DQ54

DDR_DQ56
DDR_DQ61

DDR_DM7
DDR_DQ62

DDR_DQ58

0.1U_0402_16V4Z

+1.8V +1.8V

DDR_VREF2

Trace=20mil

JP15

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DIMMB
Reverse

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

1

2

2.2U_0805_10V6K

C186

1

2

C184

21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

PTI_A5652D-A0G16- P

CK0#

CK1#

C

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS

NC
DM2
VSS

VSS

VSS

VSS

VSS
VDD

VDD

A11

A7
A6

VDD

A4
A2

A0
VDD
BA1

S0#

VDD

VDD

NC

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

DDR_DQ15

4

DDR_DQ12

6
8

DDR_DM1

10
12

DDR_DQ8

14

DDR_DQ11

16
18

DDR_DQ4

20

DDR_DQ5

22
24

DDR_DM0

26
28

DDR_CLK4

30

DDR_CLK4#

32
34

DDR_DQ6

36

DDR_DQ7

38
40

42

DDR_DQ17

44

DDR_DQ21

46
48
50

DDR_DM2

52
54

DDR_DQ22

56

DDR_DQ18

58
60

DDR_DQ29DDR_DQ28

62

DDR_DQ24

64
66

DDR_DQS#3

68

DDR_DQS3

70
72

DDR_DQ30

74

DDR_DQ31

76
78

DDR_SCKE3

80
82
84

DDR_SMA14

86
88

DDR_SMA11

90

DDR_SMA7

92

DDR_SMA6

94
96

DDR_SMA4

98

DDR_SMA2

100

DDR_SMA0

102
104

DDR_SMA16

106

DDR_SRAS#

108

DDR_SCS#2

110
112

DDR_ODT1

114

DDR_SMA13

116
118
120
122

DDR_DQ37

124

DDR_DQ33

126
128

DDR_DM4

130
132

DDR_DQ39

134

DDR_DQ34

136
138

DDR_DQ44

140

DDR_DQ41

142
144

DDR_DQS#5

146

DDR_DQS5

148
150

DDR_DQ42

152

DDR_DQ47

154
156

DDR_DQ53

158

DDR_DQ49

160
162

DDR_CLK3

164

DDR_CLK3#

166
168

DDR_DM6

170
172

DDR_DQ55

174

DDR_DQ51

176
178

DDR_DQ60

180

DDR_DQ57

182
184

DDR_DQS#7

186

DDR_DQS7

188
190

DDR_DQ63

192

DDR_DQ59

194
196
198
200

DDR_CLK4 7

DDR_CLK4# 7

DDR_SCKE3 7,9

DDR_SRAS# 7,9
DDR_SCS#2 7,9

DDR_ODT1 7,9

DDR_CLK3 7

DDR_CLK3# 7

+3VS

C52

470U_D2_2.5VM

+1.8V

C112 0.1U_0402_16V4Z

1

1

+

2

2

C97 0.1U_0402_16V4Z

1

2

D

Layout Note:
Place near JDIM1

C165 0.1U_0402_16V4Z

1

1

2

2

C157 0.1U_0402_16V4Z

1

2

C125 0.1U_0402_16V4Z

C98 0.1U_0402_16V4Z

1

2

DDR_VREF2

C155 0.1U_0402_16V4Z

1

2

C142 0.1U_0402_16V4Z

1

2

12

1K_0402_5%

12

1K_0402_5%

C109 0.1U_0402_16V4Z

1

2

+1.8V

R15

R16

C164 0.1U_0402_16V4Z

1

2

1

C21

0.1U_0402_16V4Z

2

1

C20

0.1U_0402_16V4Z

2

E

C645 0.1U_0402_16V4Z

1

2

C646 0.1U_0402_16V4Z

1

2

C647 0.1U_0402_16V4Z

1

2

4 4

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

DDR-II SODIMM1

Size Documen t N u mb er Re v

HAZ00/BL10E (LA2861) 1.0

C

Monday, August 08, 2005

Date: Sheet

E

of

10 42

A

Clock Generator

1 1

1 2

+3VS

KC FBM-L11-201209-221LMAT_0805

L14

1 2

+3VS

CHB1608U301_0603

L33

1 2

+3VS

CHB1608U301_0603

2 2

+CLK_VDD1

10K_0402_5%

CLK_OK15,16

+CLK_VDD1

L16

C497

4.7U_0805_10V4Z

R281

1 2

1

C221

10U_0805_10V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C203

10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

2

13

D

Q40

2

G

S

2N7002_SOT23

0.1U_0402_16V4Z

1

C188

2

1

C189

2

1

C484

2

0.1U_0402_16V4Z

1

1

C458

C486

2

2

0.1U_0402_16V4Z

1

C190

0.1U_0402_16V4Z

2

22P_0402_50V8J

22P_0402_50V8J

+CLK_VDD1
CPU_STP#4,14,40

1

C485

2

C500

B

0.1U_0402_16V4Z

1

C456

2

+3VS

1 2

C501

12

Y3

1 2

XTALOUT_CLK

14.31818MHZ_20P_6X1430004201

SB_SMCLK9,10,15

SB_SMDATA9 , 10,15

1 2

L13 CHB1608U301_0603

2

2

XTALIN_CLK

C457

10U_0805_10V4Z

12

R269 4.7K_0402_5%@
R255 0_0402_5%

R277
1M_0402_5%@

C182

1

1

12
12

C

1- PLACE ALL THE SERIES TERMINATION
RESISTORS AS CLOSE TO CLOCK GEN AS POSSIBLE

2- ROUTE ALL CPUCLK/#, NBCLK/#, ITPCLK/#
AND SCR/# ,AS DIFFERENT PAIR RULE

3- PUT DECOUPLING CAPS CLOSE TO CLOCK GEN
POWER PIN

U23

45

R260

0.1U_0402_16V4Z

12

VDDCPU

51

VDDPCI

32

VDDATI

35

VDDSRC

14

VDDSRC

21

VDDSRC

3

VDD48

56

VDDREF

39

VDDA

44

GNDCPU

49

GNDPCI

31

GNDATI

36

GNDSRC

26

GNDSRC

20

GNDSRC

15

GNDSRC

5

GND

55

GND

38

GNDA

1

XIN

2

XOUT

6

VTT_PWRGD#/PD

48

CPU_STOP#

7

SCLK

8

SDATA

37

IREF

ICS951413CGLFT_TSSOP56

CPUCLKT0

CPUCLKC0

CPUCLKT1

CPUCLKC1

CPUCLKT2_ITP

CPUCLKC2_ITP

SRCCLKT0

SRCCLKC0
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1

SRCCLKT3
SRCCLKC3

SRCCLKT4
SRCCLKC4

SRCCLKT5
SRCCLKC5

SRCCLKT6
SRCCLKC6

SRCCLKT7
SRCCLKC7

CLKREQA#
CLKREQB#

CK410#/PCICLK0

USB_48MHZ

FS_B/REF1
FS_A/REF0

TEST_SEL/REF2

ICS951413

475_0402_1%

FS_C

47
46
43
42
41
40

34
33
30
29
27
28
24
25
22
23
18
19
16
17
12
13

10
11

50
4

9
53
54
52

CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1

SRCCLKT0
SRCCLKC0

SRCCLKT3
SRCCLKC3

10K_0402_5%

FS_C
FS_B/REF1
FS_A/REF0
TEST_SEL/REF2

D

R270 33_0402_5%

1 2

R271 33_0402_5%

1 2

R272 33_0402_5%

1 2

R273 33_0402_5%

1 2

R261 33_0402_5%

1 2

R263 33_0402_5%

1 2

R285 33_0402_5%

1 2

R278 33_0402_5%

1 2

R283

12

R284

12

10K_0402_5%

R254 4.7K_0402_5%

1 2
1 2

R268 4.7K_0402_5%@

R266 33_0402_5%

1 2

R252 33_0402_5%

1 2

R267 33_0402_5%

1 2

R265 33_0402_5%

1 2

R256

R257

R258

1 2

1 2

49.9_0402_1%

+CLK_VDD1
+CLK_VDD1

+CLK_VDD1

1 2
1 2
1 2

1 2

12

R279

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

R282 4.7K_0402_5%
R253 4.7K_0402_5%
R251 4.7K_0402_5%

R259

1 2

12

R286

49.9_0402_1%

49.9_0402_1%

R264

12

49.9_0402_1%

R262

E

CLK_NB_BCLK 7
CLK_NB_BCLK# 7
CLK_BCLK 4
CLK_BCLK# 4

12

49.9_0402_1%

CPU_BSEL0 5,7
CPU_BSEL1 5

+CLK_VDD1

CLK_SB_14M 15

CLK_14M_SIO 29

CLK_NB_14M 7

CLK_AUDIO_14M 24

CLK_SB_ALINK 14
CLK_SB_ALINK# 14

CLK_NB_ALINK 6
CLK_NB_ALINK# 6

3 3

FS_C FS_B FS_A

10
0

0

CPU SRC PCI REF USB
1
1

100.00

133.33

100.00

100.00

33.33

33.33

14.318

14.318

48.000

48.000

111 --- --- --- --- ---

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

ClockGen ICS 951411

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

B

Monday, August 08, 2005

D

Date: Sheet

E

11 42

of

A

B

C

D

E

TV-OUT CONNECTOR

Reduce LUMA_1 and CRMA_1 length
As short as possible

1

1

C223

82P_0402_50V8J

2

D8

2

DAN217_SC59@

LUMA_2
CRMA_2

3

1

C200

2

1 1

22P_0402_50V8J

C204

1 2

NB_LUMA7

NB_CRMA7

R57

75_0603_1%

2 2

12

R59

12

75_0603_1%

NB_LUMA

NB_CRMA

82P_0402_50V8J

+3VS

BKOFF#28

C202

1

C213

2

1 2

R209 10K_0402_5%

D19 CH751H-40_SC76

1 2

L15 CHB1608B121_0603

22P_0402_50V8J

C224

1 2

1 2

L17 CHB1608B121_0603

1

82P_0402_50V8J

2

DISPOFF#

21

220P_0402_50V7K

C410

1 2

D7

2

DAN217_SC59@

82P_0402_50V8J

1

3

1. Y ground

2. C ground

3. Y (luminance+sync)

4. C (crominance)

+3VS

JP18

ALLTO_C10877-104A1-L_4P

1

1

2

5

2

5

3

6

3

6

4

4

JUMP_43X118@

1

1

2

2

PANEL +LCDVDD CTRL CKT

+3VALW

S

Q2

G

2

SI2301BDS_SOT23

D

R9

1 3
12

R7
100_0402_5%

12

R8

1

C13

100K_0402_5%

2

Q34

G

2

+3VS

80mil

S

SI2301BDS_SOT23

D

1 3

80mil

1

C404

4.7U_0805_10V4Z

2

1

2

+LCDVDD

1

2

C411

4.7U_0805_10V4Z

C405

0.1U_0402_16V4Z

+LCDVDD

12

13

D

S

NB_ENVDD

2

G

2N7002_SOT23

12

100K_0402_5%

NB_ENVDD7

R10

2

J1

J4

2

JUMP_43X118@

1

1

470_0402_5%

Q3

+LCDVDD Width: 40mils

0.047U_0402_16V7K

LCD/PANEL BD. Conn.

1

C406

0.1U_0402_16V4Z@

+3VS

+LCDVDD

3 3

0.1U_0402_16V4Z@

4 4

A

C407

1

2

L40 FBM-L11-201209-221LMA30T_0805

1 2

2

1 2

L38 FBM-L11-201209-221LMA30T_0805

NB_EDID_CLK7
NB_EDID_DATA7

DAC_BRIG28
INVT_PWM28

1 2

B+

FBM-L11-201209-221LMA30T_0805

B

NB_EDID_CLK
NB_EDID_DATA
DAC_BRIG
INVT_PWM
DISPOFF# NB_TXOUT1+

L39

NB_EDID_CLK

NB_EDID_DATA

JP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88242-3000

1 2

C408 47P_0402_50V8J

1 2

C409 47P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NB_TXCLK­NB_TXCLK+

NB_TXOUT0­NB_TXOUT0+

NB_TXOUT2­NB_TXOUT2+

NB_TXOUT1-

C

NB_TXCLK- 7
NB_TXCLK+ 7

NB_TXOUT0- 7
NB_TXOUT0+ 7

NB_TXOUT2- 7
NB_TXOUT2+ 7

NB_TXOUT1- 7
NB_TXOUT1+ 7

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

TV-OUT, LVDS CONNECTOR

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

B

Monday, August 08, 2005

D

Date: Sheet

E

12 42

of

5

4

3

2

1

CRT CONNECTOR

D D

1

D2

DAN217_SC59@

2

3

L1

NB_CRT_R7

NB_CRT_G7

NB_CRT_B7

1

1

12

75_0603_1%

+CRT_VCC

U3

12

R3

6P_0402_50V8K

75_0603_1%

1

5

P

OE#

A2Y

G

3

C10

2

6P_0402_50V8K

+CRT_VCC

4

1 2

C11

0.1U_0402_16V4Z

C8

2

A2Y

C C

NB_CRT_HSYNC7

NB_CRT_VSYNC7

B B

75_0603_1%

12

R1

R2

C12

1 2

0.1U_0402_16V4Z

SN74AHCT1G125GW_SOT353-5

1 2

FCM2012C-800_0805

L2

1 2

FCM2012C-800_0805

L3

1 2

FCM2012C-800_0805

1

C5
6P_0402_50V8K

2

R4

1K_0402_5%

1 2

1

5

P

4

OE#

U2

G

SN74AHCT1G125GW_SOT353-5

3

1

C4

2

6P_0402_50V8K@

L29

1 2

CHB1608B121_0603

L30

1 2

CHB1608B121_0603

1

D1

DAN217_SC59@

2

3

1

C6
6P_0402_50V8K@

2

1

C401

68P_0402_50V8K@

2

1

D3

DAN217_SC59@

2

1

C7

2

6P_0402_50V8K@

1

C403
68P_0402_50V8K@

2

+3VS

3

DVI_HSYNC

DVI_VSYNC

+5VS +R_CRT_VCC

D4

2 1

CH491D_SC59

1A_6VDC_MINISMDC110

0.1U_0402_16V4Z

DVI_R

DVI_G

DVI_B

1

C402

2

220P_0402_50V7K

C398

68P_0402_50V8K

F1

21

1

2

+CRT_VCC

1

C400

2

1

C9

2

68P_0402_50V8K

CRT Conn.

JP14

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

TYCO_1470801-1

R204

1 2

4.7K_0402_5%

R207

1 2

4.7K_0402_5%

Q32

2N7002_SOT23

2N7002_SOT23

1 2

2.2K_0402_5%

2

1 3

D

Q33

R205

G

S

1 3

D

10K_0402_5%

2

G

S

1 2

R206

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

R208

1 2

10K_0402_5%

NB_DDC_DATA 7

NB_DDC_CLK 7

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CRT CONNECTOR

Size Document Number Rev

HAZ00/BL10E (LA2861) 1.0

B

Thursday, A ugus t 04, 2005

2

Date: Sheet

1

13 42

of