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Liverpool 10AR
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Toshiba Satellite L500D, Compal LA-4971P KSWAE, Liverpool 10AR, Liverpool 10ARG Schematic

A
1 1
B
C
D
E
Compal confidential
2 2
Liverpool 10AR/10ARG
KSWAE LA-4971P Schematics Document
Mobile AMD S1G2 S1G3/ RS780MN & RS780MC & RX781 & RS880 /
3 3
SB700 & SB710
2009-04-22 Rev. 1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Cover Sheet
Cover Sheet
Cover Sheet
LA-4971P
LA-4971P
LA-4971P
E
1.0
1.0
1 45Wednesday, April 22, 2009
1 45Wednesday, April 22, 2009
1 45Wednesday, April 22, 2009
1.0
A
Compal Confidential
M o d e l N a m e : K S W A E / K T W A E
M o d e l N a m e : K S W A E / K T W A E
M o d e l N a m e : K S W A E / K T W A EM o d e l N a m e : K S W A E / K T W A E
F i l e N a m e : L A - 4 9 7 1 P
F i l e N a m e : L A - 4 9 7 1 P
F i l e N a m e : L A - 4 9 7 1 PF i l e N a m e : L A - 4 9 7 1 P
G r i f f i n P l a t f o r m
G r i f f i n P l a t f o r m
G r i f f i n P l a t f o r mG r i f f i n P l a t f o r m
1 1
H D M I C E C C o n t r o l l e r
H D M I C E C C o n t r o l l e r
H D M I C E C C o n t r o l l e rH D M I C E C C o n t r o l l e r
EC SMBUS
2 2
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 MR T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
PCIe port 3
3 3
C l o c k G e n e r a t o r
C l o c k G e n e r a t o r
C l o c k G e n e r a t o rC l o c k G e n e r a t o r
SLG8SP626VTR
R T C C K T .
R T C C K T .
R T C C K T .R T C C K T .
P o w e r O n / O f f C K T .
P o w e r O n / O f f C K T .
P o w e r O n / O f f C K T .P o w e r O n / O f f C K T .
D C / D C I n t e r f a c e C K T .
D C / D C I n t e r f a c e C K T .
D C / D C I n t e r f a c e C K T .D C / D C I n t e r f a c e C K T .
P o w e r C i r c u i t D C / D C
P o w e r C i r c u i t D C / D C
P o w e r C i r c u i t D C / D CP o w e r C i r c u i t D C / D C
page 37,38,39,40 41,42,43,44
4 4
R J 4 5
R J 4 5
R J 4 5R J 4 5
page 26
page 15
page 37
page 35
page 36
R5F211A4SP
page 26
page 32
page 35
page 35
U S B / B
U S B / B
U S B / BU S B / B
P o w e r / B
P o w e r / B
P o w e r / BP o w e r / B
S W / B
S W / B
S W / BS W / B
page 18
P C I e M i n i C a r d W L A N
P C I e M i n i C a r d W L A N
P C I e M i n i C a r d W L A NP C I e M i n i C a r d W L A N
PCIe Port 2
page 27
B
A T I M 9 2
A T I M 9 2
A T I M 9 2A T I M 9 2
with VRAM
V G A M X M C o n n
V G A M X M C o n n
V G A M X M C o n nV G A M X M C o n n
C R T
C R T
C R T C R T
page 16
L C D C o n n .
L C D C o n n .
L C D C o n n .L C D C o n n .
page 17
H D M I C o n n .
H D M I C o n n .
H D M I C o n n .H D M I C o n n .
page 18
PCIe 4x
N E W C a r d
N E W C a r d
N E W C a r dN E W C a r d
USB port 11
PCIe port 0
USB port 2
SATA port 2
C a r d B u s C o n t r o l l e r
C a r d B u s C o n t r o l l e r
C a r d B u s C o n t r o l l e rC a r d B u s C o n t r o l l e r
OZ601
D e b u g P o r t
D e b u g P o r t
D e b u g P o r tD e b u g P o r t
page 33
G s e n s o r
G s e n s o r
G s e n s o rG s e n s o r
page 35
Page 19
1.5V 2.5GHz(250MB/s)
page 27
e S A T A
e S A T A
e S A T Ae S A T A
page 25
page 28
E N E K B 9 2 6 D 3
E N E K B 9 2 6 D 3
E N E K B 9 2 6 D 3E N E K B 9 2 6 D 3
T o u c h P a d
T o u c h P a d
T o u c h P a dT o u c h P a d
page 35
H y p e r T r a n s p o r t L i n k 2 . 6 G H z
H y p e r T r a n s p o r t L i n k 2 . 6 G H z
H y p e r T r a n s p o r t L i n k 2 . 6 G H zH y p e r T r a n s p o r t L i n k 2 . 6 G H z
A - L i n k E x p r e s s I I
A - L i n k E x p r e s s I I
A - L i n k E x p r e s s I IA - L i n k E x p r e s s I I 4 X P C I - E
4 X P C I - E
4 X P C I - E4 X P C I - E
5V 480MHzUSB
SATA 5V 1.5GHz(150MB/s)
5V 480MHzUSB
PCI BUS
3.3V 33 MHz
LPC BUS
3.3V 33 MHz
page 34
I n t . K B D
I n t . K B D
I n t . K B DI n t . K B D
page 33
C
A M D S 1 G 2 C P U
A M D S 1 G 2 C P U
A M D S 1 G 2 C P UA M D S 1 G 2 C P U
uFCPGA-638 Package
1 6 X 1 6
1 6 X 1 6
1 6 X 1 61 6 X 1 6
A T I
A T I
A T IA T I
RS780MN
RS780MC
RX781
RS880
page 10,11,12,13,14
A T I
A T I
A T IA T I
SB700 SB710
page 20,21,22,23,24
S P I R O M
S P I R O M
S P I R O MS P I R O M
page 33
page 4,5,6,7
HD Audio
ADM1032ARMZ
R i g h t U S B C o n n
R i g h t U S B C o n n
R i g h t U S B C o n nR i g h t U S B C o n n
USB Port 0,1
USB 5x
5V 480MHz
USBPort 8
SATA
5V 1.5GHz(150MB/s)
SATA
5V 1.5GHz(150MB/s)
3.3V 24.576MHz/48Mhz
M D C 1 . 5
M D C 1 . 5
M D C 1 . 5 M D C 1 . 5
page 33
R J 1 1
R J 1 1
R J 1 1R J 1 1
page 33
D
T h e r m a l S e n s o r
T h e r m a l S e n s o r F a n C o n t r o l
T h e r m a l S e n s o rT h e r m a l S e n s o r
page 6
2 0 0 p i n D D R I I - S O - D I M M X 2
2 0 0 p i n D D R I I - S O - D I M M X 2
2 0 0 p i n D D R I I - S O - D I M M X 22 0 0 p i n D D R I I - S O - D I M M X 2
BANK 0, 1, 2, 3
M e m o r y B U S ( D D R I I )
M e m o r y B U S ( D D R I I )
M e m o r y B U S ( D D R I I )M e m o r y B U S ( D D R I I ) D u a l C h a n n e l
D u a l C h a n n e l
D u a l C h a n n e lD u a l C h a n n e l 1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
I n t . C a m e r a
I n t . C a m e r a
I n t . C a m e r aI n t . C a m e r a
page 32
USBPort 9
W L A N
W L A N
W L A NW L A N
A M P L I F I E R
A M P L I F I E R
A M P L I F I E RA M P L I F I E R
TPA6017
S P K C O N N
S P K C O N N
S P K C O N NS P K C O N N
page 27
page 31
page 31
USBPort 7
S A T A H D D 1
S A T A H D D 1
S A T A H D D 1S A T A H D D 1
SATA port 0
S A T A O D D
S A T A O D D
S A T A O D DS A T A O D D
SATA port 3
H D A C o d e c
H D A C o d e c
H D A C o d e cH D A C o d e c
ALC272
M I C C O N N
M I C C O N N
M I C C O N NM I C C O N N
F i n g e r P r i n t e r
F i n g e r P r i n t e r
F i n g e r P r i n t e rF i n g e r P r i n t e r
page 31
APL5607KI-TRG
page 8,9
page 32
page 27
page 25
page 25
page 30
F a n C o n t r o l
F a n C o n t r o lF a n C o n t r o l
I n t . M I C
I n t . M I C
I n t . M I C I n t . M I C
page 31
USBPort 6
R T S 5 1 5 9 E
R T S 5 1 5 9 E
R T S 5 1 5 9 ER T S 5 1 5 9 E
USBPort 4
page 4
B l u e t o o t h
B l u e t o o t h
B l u e t o o t hB l u e t o o t h
H P C O N N
H P C O N N
H P C O N NH P C O N N
page 31
page 32
3IN1
page 29
E
3IN1
page 29
V o l u m e C o n t r o l
V o l u m e C o n t r o l
V o l u m e C o n t r o lV o l u m e C o n t r o l
page 31
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
LA-4971P
LA-4971P
LA-4971P
E
1.0
1.0
2 45Wednesday, April 22, 2009
2 45Wednesday, April 22, 2009
2 45Wednesday, April 22, 2009
1.0
A
Voltage Rails
O : ON
X : OFF
+5VS
1 1
2 2
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
State
S0
S1
S3
S5 S4/AC
power plane
+B
+3VL
+5VL
+RTCVCC
O
O
O
O
O
X
+3VALW
+1.2VALW
+3V_LAN
O
O
O
O
X
X X X
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.1VS
+1.8V+5VALW
+VGA_CORE
+0.9V
+1.2V_HT
+0.9V
+CPU_CORE_NB
+CPU_CORE_0
+CPU_CORE_1
O
X X
X
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
3 3
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
EC SM Bus1 address
Device Address
Smart Battery
HDMI-CEC 34H
EC KB926D2
HEX
16H
0001 011X b
0011 010X b
B
Symbol Note :
@ : just reserve , no build
DEBUG@ : reserve for debug.
Layout Notes
L
UMA@: means for RS780M.
: Digital Ground
: Analog Ground
C
Platform
PUMA@
Platform
TIGRIS@
D
NB
GM@
GM@
PM@+GPM@
PM@+PM1@ SB700
GM@
GM@
PM@+GPM@
PM@+PM1@ SB710
S1G2
RS780MC NA
S1G2
RS780MN
S1G2
S1G2
RX781
Item CPU SB
S1G3
RS880MC NA
S1G3
RS880M
S1G3
S1G3
RX881
VGA
NA
MXMRS780MN
MXM
NB
VGA
NA
MXMRS880M
MXM
SB700
SB700
SB700
SB710
SB710
SB710
E
CommentItem CPU SB
Comment
BTO (Build-To-Order) Option Table
( B )
BT@
AMD(UMA)
IHDMI@
SOURCE
KB926
KB926
RS780M
RS780M
RS780M
SB700
SB700
SB700
SB700
RJ11
( R )
MDC@
SSD
( S )
SSD@
HDMI
(Y)
ATI VGA/B
HDMI@
SATA ODD
16" 17"
16inch@
COMMON
H@
BATTINVERTER
VVV
17inch@
LVDS wireset
Cost down
LVDSSET@
HDMI CEC
( H )
Half - size
WLAN@ WIMAX@
16inch_45@ 17inch_45@
CPU
THERMAL
SENSOR
WiFi
SODIMM
I / II
First Second
G@ + G_1st@ G@ + G_2nd@
DC-IN
CLK
WLAN
GEN
VV
G- sensor
CHIPSET
PUMA@ TIGRIS@
LCD DDC ROM
V
V
HDMI DDC ROM
V
3 in 1 card reader
NEW CARD
V
RTS5159
CARD@
MXM Thermal Sensor
V
Function
Description
Explain
OO
OO
X
BTO
Function
Description
Explain
BTO
X
Express card / PCMCIA
( E / A )
EXPCARD@ / PCMCIA@
FP@
CAMERA & MIC
( F )
CAMERA MIC
CAM@ MIC@
FingerPrinter
SMBUS Control Table
BLUE TOOTH
(X)
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
I2C_CLK
I2C_DATA
DDC_CLK0
DDC_DATA0
DDC_CLK1
DDC_DATA1
SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
4 4
EC SM Bus2 address
Device
ADI1032-1 CPU
ADI1032-2 VGA
EC KB926D2
Ext. VGA/B
CS/B
HEX Address
1001 100X b
98H
1001 101X b
9AH
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Notes List
Notes List
Notes List
LA-4971P
LA-4971P
LA-4971P
E
1.0
1.0
3 45Wednesday, April 22, 2009
3 45Wednesday, April 22, 2009
3 45Wednesday, April 22, 2009
1.0
A
B
C
D
E
< C1, C2 and C7 must be replaced to 10-uF for Caspian compatibility >
+1.2V_HT
250 mil
1
PUMA@
PUMA@
C1
C1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1 1
TIGRIS@
TIGRIS@
C1
C1 10U_0805_10V6K
10U_0805_10V6K
1
PUMA@
PUMA@
C2
C2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
TIGRIS@
TIGRIS@
C2
C2 10U_0805_10V6K
10U_0805_10V6K
Near CPU SocketVLDT CAP.
1
2
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C5
C5
180P_0402_50V8J
180P_0402_50V8J
2
1
C6
C6
180P_0402_50V8J
180P_0402_50V8J
2
H_CADIP[0..15]10
2 2
3 3
H_CADIP[0..15]
H_CADIN[0..15]
VLDT=500mA
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
H_CLKIP010 H_CLKIN010 H_CLKIP110 H_CLKIN110
H_CTLIP010 H_CTLIN010 H_CTLIP110 H_CTLIN110
+1.2V_HT
JCPUA
JCPUA
D1
HT LINK
HT LINK
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
FOX_PZ63823-284S-41F_638P@
FOX_PZ63823-284S-41F_638P@
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9
L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1
1A
+FAN1
1
C192
C192
10U_0805_10V4Z
10U_0805_10V4Z
2
< From EC >
4 4
EN_DFAN134
A
10U_0805_10V4Z
10U_0805_10V4Z
U6
U6
1
EN
2
VIN
3
VOUT
4
VSET
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
C183
C183
8
GND
7
GND
6
GND
5
GND
B
H_CADOP[0..15]
H_CADON[0..15]
+VLDT_B
AE2 AE3 AE4 AE5
H_CADOP0
AD1
H_CADON0
AC1
H_CADOP1
AC2
H_CADON1
AC3
H_CADOP2
AB1
H_CADON2
AA1
H_CADOP3
AA2
H_CADON3
AA3
H_CADOP4
W2
H_CADON4
W3
H_CADOP5
V1
H_CADON5
U1
H_CADOP6
U2
H_CADON6
U3
H_CADOP7
T1
H_CADON7
R1
H_CADOP8
AD4
H_CADON8
AD3
H_CADOP9
AD5
H_CADON9
AC5
H_CADOP10
AB4
H_CADON10
AB3
H_CADOP11
AB5
H_CADON11
AA5
H_CADOP12
Y5
H_CADON12
W5
H_CADOP13
V4
H_CADON13
V3
H_CADOP14
V5
H_CADON14
U5
H_CADOP15
T4
H_CADON15
T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
12
D1
D1
@
@
2
1
@
@
1SS355_SOD323-2
1SS355_SOD323-2
12
D2
D2
BAS16_SOT23-3
BAS16_SOT23-3
< To NB >< From NB >
H_CLKOP0 10 H_CLKON0 10 H_CLKOP1 10 H_CLKON1 10
H_CTLOP0 10 H_CTLON0 10 H_CTLOP1 10 H_CTLON1 10
@
@
H_CADOP[0..15] 10
H_CADON[0..15] 10H_CADIN[0..15]10
PUMA@
PUMA@
C7
C7
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1 2
TIGRIS@
TIGRIS@
C7
C7 10U_0805_10V6K
10U_0805_10V6K
2
C9
C9
1000P_0402_25V8J
1000P_0402_25V8J
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
JFAN
JFAN
+FAN1
1
1
2
2
3
3
4
GND
5
GND
ACES_85204-0300N_3P@
ACES_85204-0300N_3P@
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
+3VS
12
R12
R12
10K_0402_5%
10K_0402_5%
2
C8
C8
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
FAN_SPEED1 34
D
< To EC >
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-4971P
LA-4971P
LA-4971P
E
4 45Wednesday, April 22, 2009
4 45Wednesday, April 22, 2009
4 45Wednesday, April 22, 2009
1.0
1.0
1.0
A
< DDR2 VREF is 0.5 ratio >
+1.8V
R1
1K_0402_1%R11K_0402_1%
1 2
R2
1 1
1K_0402_1%R21K_0402_1%
1 2
2 2
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
3 3
< To SO_DIMMA >
< To SO_DIMMA >
+MCH_REF
1
C12
C12
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C13
C13
1000P_0402_25V8J
1000P_0402_25V8J
2
Place them close to CPU within 1"
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
R3 39.2_0402_1%R3 39.2_0402_1%
1 2
+1.8V
T2 PADT2 PAD
DDR_A_ODT09 DDR_A_ODT19
DDR_CS0_DIMMA#9 DDR_CS1_DIMMA#9 DDR_CS0_DIMMB# 8
DDR_CKE0_DIMMA9 DDR_CKE1_DIMMA9
DDR_A_CLK09 DDR_A_CLK#09 DDR_A_CLK19 DDR_A_CLK#19
DDR_A_MA[15..0]9
DDR_A_BS#09 DDR_A_BS#19 DDR_A_BS#29
DDR_A_RAS#9 DDR_A_CAS#9 DDR_A_WE#9
< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH >
DDR_A_CLK0
1
C10
C10
1.5P_0402_50V9C
1.5P_0402_50V9C
2
DDR_A_CLK#0
DDR_A_CLK1
1
C11
C11
1.5P_0402_50V9C
1.5P_0402_50V9C
2
DDR_A_CLK#1
JCPUB
JCPUB
D10
VTT1
C10
VTT2
B10
VTT3
AD10
MEM_P MEM_N VTT_SENSE
DDR_A_ODT0 DDR_A_ODT1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
VTT4
AF10
MEMZP
AE10
MEMZN
H16
RSVD_M1
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H0
N20
MA_CLK_L0
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H2
AA16
MA_CLK_L2
P19
MA_CLK_H3
P20
MA_CLK_L3
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
@ FOX_PZ63823-284S-41F_638P
@ FOX_PZ63823-284S-41F_638P
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
VTT_SENSE
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3
B
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
MEMVREF
RSVD_M2
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB_CKE0 MB_CKE1
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
C
D
E
< Processor DDR2 Memory Interface >
1
C14
C14
1.5P_0402_50V9C
1.5P_0402_50V9C
2
1
C15
C15
1.5P_0402_50V9C
1.5P_0402_50V9C
2
+0.9V+0.9V
W10
VTT5
AC10
VTT6
AB10
VTT7
AA10
VTT8
A10
VTT9
Y10
+MCH_REF
W17
B18
DDR_B_ODT0
W26
DDR_B_ODT1
W23 Y26
V26
DDR_CS1_DIMMB#
W25 U22
DDR_CKE0_DIMMB
J25
DDR_CKE1_DIMMB
H26
P22 R22
DDR_B_CLK0
A17
DDR_B_CLK#0
A18
DDR_B_CLK1
AF18
DDR_B_CLK#1DDR_A_CLK#1
AF17 R26 R25
DDR_B_MA0
P24
DDR_B_MA1
N24
DDR_B_MA2
P26
DDR_B_MA3
N23
DDR_B_MA4
N26
DDR_B_MA5
L23
DDR_B_MA6
N25
DDR_B_MA7
L24
DDR_B_MA8
M26
DDR_B_MA9
K26
DDR_B_MA10
T26
DDR_B_MA11
L26
DDR_B_MA12
L25
DDR_B_MA13
W24
DDR_B_MA14
J23
DDR_B_MA15
J24
DDR_B_BS#0
R24
DDR_B_BS#1
U26
DDR_B_BS#2
J26
DDR_B_RAS#
U25
DDR_B_CAS#
U24
DDR_B_WE#
U23
T1PAD T1PAD
T3PAD T3PAD
DDR_B_ODT0 8 DDR_B_ODT1 8
DDR_CS1_DIMMB# 8
DDR_CKE0_DIMMB 8 DDR_CKE1_DIMMB 8
DDR_B_CLK0 8 DDR_B_CLK#0 8 DDR_B_CLK1 8 DDR_B_CLK#1 8
DDR_B_MA[15..0] 8
DDR_B_BS#0 8 DDR_B_BS#1 8 DDR_B_BS#2 8
DDR_B_RAS# 8 DDR_B_CAS# 8 DDR_B_WE# 8
< VTT regulator voltage >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
DDR_B_D[63..0]8
< From/To SO_DIMMB >
DDR_B_DM[7..0]8 DDR_A_DM[7..0] 9
< To SO_DIMMB > < To SO_DIMMA >
DDR_B_DQS08 DDR_B_DQS#08 DDR_B_DQS18 DDR_B_DQS#18 DDR_B_DQS28 DDR_B_DQS#28 DDR_B_DQS38 DDR_B_DQS#38 DDR_B_DQS48 DDR_B_DQS#48 DDR_B_DQS58 DDR_B_DQS#58 DDR_B_DQS68 DDR_B_DQS#68 DDR_B_DQS78 DDR_B_DQS#78
< From/To SO_DIMMB > < From/To SO_DIMMA >
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
JCPUC
JCPUC
MEM:DATA
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
FOX_PZ63823-284S-41F_638P@
FOX_PZ63823-284S-41F_638P@
MEM:DATA
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23
G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
Y11 AE14 AF14 AF11 AD11
A12
B16
A22
E25 AB26 AE22 AC16 AD12
C12
B12
D16
C16
A24
A23
F26
E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9
DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0] 9
< From/To SO_DIMMA >
DDR_A_DQS0 9 DDR_A_DQS#0 9 DDR_A_DQS1 9 DDR_A_DQS#1 9 DDR_A_DQS2 9 DDR_A_DQS#2 9 DDR_A_DQS3 9 DDR_A_DQS#3 9 DDR_A_DQS4 9 DDR_A_DQS#4 9 DDR_A_DQS5 9 DDR_A_DQS#5 9 DDR_A_DQS6 9 DDR_A_DQS#6 9 DDR_A_DQS7 9 DDR_A_DQS#7 9
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
LA-4971P
LA-4971P
LA-4971P
E
5 45Wednesday, April 22, 2009
5 45Wednesday, April 22, 2009
5 45Wednesday, April 22, 2009
1.0
1.0
1.0
A
+CPU_CORE_0
+CPU_CORE_1
1 1
< Close to CPU >
R487
R487 10_0402_5%
10_0402_5%
1 2
R486
R486 10_0402_5%
10_0402_5%
1 2
Un-Mount R489 For Caspian
R489
R489 10_0402_5%PUMA@
10_0402_5%PUMA@
1 2
R488
R488 10_0402_5%PUMA@
10_0402_5%PUMA@
1 2
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L
Change R488 to 10K For Caspian
< 200-MHz PLL Reference Clock >
CLK_CPU_BCLK15
CLK_CPU_BCLK#15
C20
C20 3900P_0402_50V7K
3900P_0402_50V7K
1 2
C21
C21 3900P_0402_50V7K
3900P_0402_50V7K
1 2
Address:100_1100 Place close to CPU wihtin 1.5"
12
R8
169_0402_1%R8169_0402_1%
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
< Filtered PLL Supply Voltage >
2 2
L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805
1 2
1
@+C16
@
2
+
C16
100U_D2_6.3VM
100U_D2_6.3VM
1
C17
C17
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
2
VDDA=300mA
C18
C18
3300P_0402_50V7K
3300P_0402_50V7K
+2.5VDDA+2.5VS
1
2
+2.5VDDA
C19
C19
0.22U_0603_16V4Z
0.22U_0603_16V4Z
B
< Differential feedback for VDDNB >
+VDDNB
< Sideband-Temperature Sensor Interface Clock & Data>
< Sideband-Temperature Sensor Interface interrupt >
< Compensation Resistor to VSS >
< Compensation Resistor to VLDT >
R484
R484 10_0402_5%
10_0402_5%
12
R485
R485 10_0402_5%
10_0402_5%
12
Close to CPU
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
+1.2V_HT
R13 44.2_0402_1%R13 44.2_0402_1%
1 2
R14 44.2_0402_1%R14 44.2_0402_1%
1 2
CPU_VDD0_RUN_FB_H43 CPU_VDD0_RUN_FB_L43
CPU_VDD1_RUN_FB_H43 CPU_VDD1_RUN_FB_L43
< Debug ready >
< JTAG debug port >
T9 PADT9 PAD T10 PADT10 PAD T11 PADT11 PAD T12 PADT12 PAD T19 PADT19 PAD
C
+2.5VDDA
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ_R#
CPU_HTREF0 CPU_HTREF1
CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L
CPU_TEST23_TSTUPD
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1
1 2
R25
R25 0_0402_5%
0_0402_5%
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC THERMDA
VDDIO_FB_H VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
DBREQ_L
TEST28_H
TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
D
M11
KEY1
W18
KEY2
A6
SVC
A4
SVD
AF6 AC7 AA8
W7 W8
W9 Y9
H6 G6
E10
AE9
TDO
J7 H8
D7 E7 F7 C7
C3 K8
C4
C9 C8
H18 H19 AA7 D5 C5
CPU_SVC CPU_SVD
CPU_THERMTRIP#_R CPU_PROCHOT#_1.8
R42
R42
12
300_0402_5%
300_0402_5%
THERMDC_CPU THERMDA_CPU
+1.8V sense no support
CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L
CPU_DBREQ#
CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N
CPU_TEST17_BP3 CPU_TEST16_BP2
CPU_TEST10_ANALOGOUT
CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N
CPU_SVC 43 CPU_SVD 43
+1.8V
T22PAD T22PAD T21PAD T21PAD
CPU_VDDNB_RUN_FB_H 43 CPU_VDDNB_RUN_FB_L 43
T20PAD T20PAD
T5PAD T5PAD T6PAD T6PAD
T7PAD T7PAD T8PAD T8PAD
R32
@R32
@
300_0402_5%
300_0402_5%
12
Add R32 at PVT
T13PAD T13PAD T14PAD T14PAD
JCPUD
JCPUD
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
FOX_PZ63823-284S-41F_638P@
FOX_PZ63823-284S-41F_638P@
E
< Serial VID Interface clock & data >
< Thermal Sensor Trip output > < HTC-active state indication or command >
< Thermal diode cathode & anode >
< Differential feedback for VDDIO > < VDDIO : DDR SDRAM I/O ring power supply> < Differential feedback for VDDNB > < Northbridge power supply >
< Debug request >
route as differential as short as possible testpoint under package
+1.2V_HT
< Serial VID Interface clock & data >
+1.8VS
3 3
LDT_RST#20
H_PWRGD20,43
4 4
CPU_LDT_REQ#11,20
0718 AMD --> 1K ohm
R22
R22 1K_0402_5%
1K_0402_5%
12
R23
R23 1K_0402_5%
1K_0402_5%
12
+1.8VS
R15
R15
300_0402_5%
300_0402_5%
1 2
1
C22
C22
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+1.8VS +1.8VS
R21
R21
300_0402_5%
300_0402_5%
1 2
H_PWRGD LDT_STOP#
1
C23
C23
0.1U_0402_16V7K
0.1U_0402_16V7K
2
300_0402_5%
300_0402_5%
CPU_LDT_REQ#
0.01U_0402_25V7K
0.01U_0402_25V7K
LDT_RST#
A
CPU_SVC
CPU_SVD
LDT_STOP#11,20
+1.8VS
R30
R30
1 2
1 2
1
C24
C24
@
@
2
R36
R36
300_0402_5%
300_0402_5%
1 2
1
C25
C25
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
PUMA@
PUMA@
R27
R27
CPU_LDT_REQ_R#
0_0402_5%
0_0402_5%
Un-Mount R27 For Caspian
Add R497 and R498 at PVT
1 2
1 2
R10
R10 10K_0402_5%
10K_0402_5%
1 2
+1.8V
+1.8V
CPU_PROCHOT#_1.8
Add R29 and R31 at PVT
1 2
1 2
B
1 2
CPU_THERMTRIP#_R
R9 300_0402_5%R9300_0402_5%
1 2
TIGRIS@
TIGRIS@
R31
R31 300_0402_5%
300_0402_5%
12
TIGRIS@
TIGRIS@
R29
R29 300_0402_5%
300_0402_5%
R26
R26 300_0402_5%
300_0402_5%
12
R28
R28 300_0402_5%
300_0402_5%
R5 300_0402_5%R5300_0402_5%
R497
R497
CPU_TEST25_H_BYPASSCLK_H
510_0402_5%TIGRIS@
510_0402_5%TIGRIS@
R499
R499
CPU_TEST25_L_BYPASSCLK_L
510_0402_5%@
510_0402_5%@
B
B
2
Q3
Q3
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
@ R11
@
1 2
CPU_TEST20_SCANCLK2
CPU_TEST23_TSTUPD
CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1
+1.8V
R498
R498 510_0402_5%@
510_0402_5%@
1 2
R500
R500 510_0402_5%TIGRIS@
510_0402_5%TIGRIS@
1 2
D12
@D12
@
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
21
D20
@D20
@
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
21
D16
D16 CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
21
R11 0_0402_5%
0_0402_5%
< To SB700 CPU block>
H_PROCHOT# 20
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
< To power circuitry>
ENTRIP2 38,40
< To power circuitry>
EN0 37,40
< To SB700 ACPI block>
H_THERMTRIP# 21
0.1U_0402_16V7K
0.1U_0402_16V7K
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+1.8V
T23 PADT23 PAD
+1.8V
T24 PADT24 PAD
+3VS
1
C26
C26
2
< R41 Close to CPU >
CPU_DBREQ#
R41 300_0402_5%R41 300_0402_5%
1 2
R40 220_0402_5%@ R40 220_0402_5%@
1 2
R39 220_0402_5%@ R39 220_0402_5%@
1 2
R38 220_0402_5%@ R38 220_0402_5%@
1 2
R37 220_0402_5%@ R37 220_0402_5%@
1 2
THERMDA_CPU
THERMDC_CPU
C27
C27
1 2
2200P_0402_50V7K
2200P_0402_50V7K
< noise filter cap >
D
< HDT Connector >
JP3
< R494 Close to CPU >
1 2
+1.8V
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
< Thermal Sensor >
U2
U2
1
VDD
SCLK
2
D+
SDATA
3
ALERT#
D-
THERM#4GND
ADM1032ARM-1 ZREEL_MSOP8
ADM1032ARM-1 ZREEL_MSOP8
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R494
R494 0_0402_5%@
0_0402_5%@
8
7
6
5
EC_SMB_CK2
EC_SMB_DA2
JP3
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
@ SAMTEC_ASP-68200-07
@
LA-4971P
LA-4971P
LA-4971P
E
< From EC >
EC_SMB_CK2 19,34,35
EC_SMB_DA2 19,34,35
6 45Wednesday, April 22, 2009
6 45Wednesday, April 22, 2009
6 45Wednesday, April 22, 2009
LDT_RST#
1.0
1.0
1.0
A
VDD decoupling : +CPU_CORE
+CPU_CORE_0
1
+
+
C30
C30
330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
1 1
+CPU_CORE_1 +CPU_CORE_1 +CPU_CORE_1
1
+
+
C31
C31
330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power
+1.8V
1
C46
C46
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+1.8V
2 2
1
C55
C55
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Between CPU Socket and DIMM
+1.8V
1
C60
C60
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Between CPU Socket and DIMM
+1.8V
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
C62
C62
180P_0402_50V8J
180P_0402_50V8J
2
Between CPU Socket and DIMM
+1.8V
3 3
1
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Between CPU Socket and DIMM
+0.9V
VTT decoupling.
1
C66
C66
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side
+0.9V
1
C79
C79
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Left side
4 4
+VDDNB decoupling : Northbridge power
+VDDNB
1
C52
C52
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
2
1
2
1
C47
C47
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C56
C56
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C63
C63
180P_0402_50V8J
180P_0402_50V8J
2
1
C75
C75
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C67
C67
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C80
C80
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C53
C53
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+CPU_CORE_0 +CPU_CORE_0
+
+
C28
C28
330U_X_2VM_R6M
330U_X_2VM_R6M
+
+
C29
C29
330U_X_2VM_R6M
330U_X_2VM_R6M
A
1
2
Under CPU Socket Under CPU Socket
1
2
Under CPU Socket Under CPU Socket
1
C48
C48
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C57
C57
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C61
C61
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C64
C64
180P_0402_50V8J
180P_0402_50V8J
2
1
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C68
C68
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C81
C81
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
TIGRIS@
TIGRIS@
1
C54
C54
22U_0805_6.3V6M
22U_0805_6.3V6M
2
C32
C32
22U_0805_6.3V6M
22U_0805_6.3V6M
C36
C36
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
1
2
1
2
1
2
1
C69
C69
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C82
C82
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C33
C33
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C37
C37
22U_0805_6.3V6M
22U_0805_6.3V6M
2
C49
C49
0.22U_0603_16V4Z
0.22U_0603_16V4Z
C58
C58
0.22U_0603_16V4Z
0.22U_0603_16V4Z
C65
C65
180P_0402_50V8J
180P_0402_50V8J
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C34
C34
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C38
C38
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C50
C50
180P_0402_50V8J
180P_0402_50V8J
2
Change to B2 size
1
+
C78
@+C78
@
220U_B2_4VM_R45M
220U_B2_4VM_R45M
2
1
C70
C70
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C83
C83 1000P_0402_25V8J
1000P_0402_25V8J
2
B
1
C51
C51
180P_0402_50V8J
180P_0402_50V8J
2
1
C71
C71
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C84
C84 1000P_0402_25V8J
1000P_0402_25V8J
2
B
1
C35
C35
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C39
C39
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C72
C72
180P_0402_50V8J
180P_0402_50V8J
2
1
C85
C85 180P_0402_50V8J
180P_0402_50V8J
2
1
C40
C40
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C43
C43
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
C
+0.9V
1. Near Power Supply
1
2. Change to B2 size
+
+
C59
C59 220U_B2_4VM_R45M
220U_B2_4VM_R45M
2
C
1
C42
C42
180P_0402_50V8J
180P_0402_50V8J
2
1
C45
C45
180P_0402_50V8J
180P_0402_50V8J
2
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+VDDNB
+1.8V
1
C41
C41
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C44
C44
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C73
C73
180P_0402_50V8J
180P_0402_50V8J
2
1
C86
C86 180P_0402_50V8J
180P_0402_50V8J
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
+CPU_CORE_0
AA11 AA13 AA15 AA17 AA19
AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21
AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23
D
LA-4971P
LA-4971P
LA-4971P
E
1.0
1.0
7 45Wednesday, April 22, 2009
7 45Wednesday, April 22, 2009
7 45Wednesday, April 22, 2009
E
1.0
JCPUE
JCPUE
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
FOX_PZ63823-284S-41F_638P@
FOX_PZ63823-284S-41F_638P@
JCPUF
JCPUF
AA4
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17
AD6
VSS18
AD8
VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ63823-284S-41F_638P@
FOX_PZ63823-284S-41F_638P@
+CPU_CORE_1
P8
VDD1_1
P10
VDD1_2
R4
VDD1_3
R7
VDD1_4
R9
VDD1_5
R11
VDD1_6
T2
VDD1_7
T6
VDD1_8
T8
VDD1_9
T10
VDD1_10
T12
VDD1_11
T14
VDD1_12
U7
VDD1_13
U9
VDD1_14
U11
VDD1_15
U13
VDD1_16
U15
VDD1_17
V6
VDD1_18
V8
VDD1_19
V10
VDD1_20
V12
VDD1_21
V14
VDD1_22
W4
VDD1_23
Y2
VDD1_24
AC4
VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
+1.8V
AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
Athlon 64 S1 Processor Socket
J6
VSS66
J8
VSS67
J10
VSS68
J12
VSS69
J14
VSS70
J16
VSS71
J18
VSS72
K2
VSS73
K7
VSS74
K9
VSS75
K11
VSS76
K13
VSS77
K15
VSS78
K17
VSS79
L6
VSS80
L8
VSS81
L10
VSS82
L12
VSS83
L14
VSS84
L16
VSS85
L18
VSS86
M7
VSS87
M9
VSS88
AC6
VSS89
M17
VSS90
N4
VSS91
N8
VSS92
N10
VSS93
N16
VSS94
N18
VSS95
P2
VSS96
P7
VSS97
P9
VSS98
P11
VSS99
P17
VSS100
R8
VSS101
R10
VSS102
R16
VSS103
R18
VSS104
T7
VSS105
T9
VSS106
T11
VSS107
T13
VSS108
T15
VSS109
T17
VSS110
U4
VSS111
U6
VSS112
U8
VSS113
U10
VSS114
U12
VSS115
U14
VSS116
U16
VSS117
U18
VSS118
V2
VSS119
V7
VSS120
V9
VSS121
V11
VSS122
V13
VSS123
V15
VSS124
V17
VSS125
W6
VSS126
Y21
VSS127
Y23
VSS128
N6
VSS129
Athlon 64 S1 Processor Socket
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
C1600.1U_0402_16V7K C1600.1U_0402_16V7K
1 2
+V_DDR_MCH_REF9
1 1
2 2
3 3
4 4
A
1
C104
C104 1000P_0402_25V8J
1000P_0402_25V8J
2
DDR_CKE0_DIMMB5
DDR_B_BS#25
DDR_B_BS#05 DDR_B_WE#5
DDR_B_CAS#5 DDR_CS1_DIMMB#5
DDR_B_ODT15
SMB_CK_DAT09,15,21,27
SMB_CK_CLK09,15,21,27
DDR_B_D0 DDR_B_D1
DDR_B_DQS#0 DDR_B_DQS0
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D22 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12 DDR_B_MA9
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_B_ODT0 DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_DM5
DDR_B_D42 DDR_B_D43 DDR_B_D47
DDR_B_D48 DDR_B_D49 DDR_B_D53
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51 DDR_B_D55
DDR_B_D56 DDR_B_D57
DDR_B_DM7
DDR_B_D58 DDR_B_D59
+3VS
1
C119
C119
0.1U_0402_16V7K
0.1U_0402_16V7K
2
DIMM0 STD H:9.2mm (Bot)
B
+1.8V+1.8V
< EMI require >< EMI require >
C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K
JDDRH
JDDRH
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
VSS
FOX_AS0A426-N8RN-7F_200P@
FOX_AS0A426-N8RN-7F_200P@
2
VSS
4
DQ4
6
DQ5
8
VSS
10
DM0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
VSS
30
CK0
32
CK0#
34
VSS
36
DQ14
38
DQ15
40
VSS
42
VSS
44
DQ20
46
DQ21
48
VSS
50
NC
52
DM2
54
VSS
56
DQ22
58
DQ23
60
VSS
62
DQ28
64
DQ29
66
VSS
68
DQS3#
70
DQS3
72
VSS
74
DQ30
76
DQ31
78
VSS
80
NC/CKE1
82
VDD
84
NC/A15
86
NC/A14
88
VDD
90
A11
92
A7
94
A6
96
VDD
98
A4
100
A2
102
A0
104
VDD
106
BA1
108
RAS#
110
S0#
112
VDD
114
ODT0
116
NC/A13
118
VDD
120
NC
122
VSS
124
DQ36
126
DQ37
128
VSS
130
DM4
132
VSS
134
DQ38
136
DQ39
138
VSS
140
DQ44
142
DQ45
144
VSS
146
DQS5#
148
DQS5
150
VSS
152
DQ46
154
DQ47
156
VSS
158
DQ52
160
DQ53
162
VSS
164
CK1
166
CK1#
168
VSS
170
DM6
172
VSS
174
DQ54
176
DQ55
178
VSS
180
DQ60
182
DQ61
184
VSS
186
DQS7#
188
DQS7
190
VSS
192
DQ62
194
DQ63
196
VSS
198
SAO
200
SA1
202
VSS
B
12
DDR_B_D4 DDR_B_D5
DDR_B_DM0
DDR_B_D6 DDR_B_D7
DDR_B_D12 DDR_B_D13
DDR_B_DM1
DDR_B_D14 DDR_B_D15
DDR_B_D20 DDR_B_D21
DDR_B_DM2
DDR_B_D23
DDR_B_D28 DDR_B_D29
DDR_B_DQS#3 DDR_B_DQS3
DDR_B_D30 DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15 DDR_B_MA14
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6DDR_B_MA8
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#
DDR_B_MA13
DDR_B_D36 DDR_B_D37
DDR_B_DM4
DDR_B_D38 DDR_B_D39
DDR_B_D44 DDR_B_D45
DDR_B_DQS#5 DDR_B_DQS5
DDR_B_D46
DDR_B_D52
DDR_B_DM6
DDR_B_D54
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
DDR_B_CLK0 5 DDR_B_CLK#0 5
DDR_CKE1_DIMMB 5
DDR_B_BS#1 5 DDR_B_RAS# 5 DDR_CS0_DIMMB# 5
DDR_B_ODT0 5
DDR_B_CLK1 5 DDR_B_CLK#1 5
+3VS
Security Classification
Security Classification
Security Classification
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
C
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_RAS#
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA15 DDR_CKE1_DIMMB
DDR_B_MA3 DDR_B_MA8 DDR_B_MA12 DDR_B_MA9
DDR_B_BS#0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA5
DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_CAS# DDR_B_WE#
DDR_B_BS#1 DDR_CS0_DIMMB# DDR_B_MA13 DDR_B_ODT0
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
RP8
RP8
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP9
RP9
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP10
RP10
47_0804_8P4R_5%
47_0804_8P4R_5%
RP11
RP11
47_0804_8P4R_5%
47_0804_8P4R_5%
RP12
RP12
47_0804_8P4R_5%
47_0804_8P4R_5%
RP13
RP13
47_0804_8P4R_5%
47_0804_8P4R_5%
RP14
RP14
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
D
+0.9V
C105 0.1U_0402_16V7KC105 0.1U_0402_16V7K
C106 0.1U_0402_16V7KC106 0.1U_0402_16V7K
C108 0.1U_0402_16V7KC108 0.1U_0402_16V7K
C107 0.1U_0402_16V7KC107 0.1U_0402_16V7K
C109 0.1U_0402_16V7KC109 0.1U_0402_16V7K
18 27
C110 0.1U_0402_16V7KC110 0.1U_0402_16V7K
36 45
C111 0.1U_0402_16V7KC111 0.1U_0402_16V7K
18 27
C112 0.1U_0402_16V7KC112 0.1U_0402_16V7K
36 45
C114 0.1U_0402_16V7KC114 0.1U_0402_16V7K
18 27
C113 0.1U_0402_16V7KC113 0.1U_0402_16V7K
36 45
C116 0.1U_0402_16V7KC116 0.1U_0402_16V7K
18 27
C115 0.1U_0402_16V7KC115 0.1U_0402_16V7K
36 45
C118 0.1U_0402_16V7KC118 0.1U_0402_16V7K
C117 0.1U_0402_16V7KC117 0.1U_0402_16V7K
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
D
E
+1.8V
12
12
12
12
12
12
12
12
12
12
12
12
12
12
DDR_B_D[0..63] 5
DDR_B_DM[0..7] 5
DDR_B_DQS[0..7] 5
DDR_B_MA[0..15] 5
DDR_B_DQS#[0..7] 5
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDRII SO-DIMM 0
DDRII SO-DIMM 0
DDRII SO-DIMM 0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-4971P
LA-4971P
LA-4971P
E
1.0
1.0
8 45Wednesday, April 22, 2009
8 45Wednesday, April 22, 2009
8 45Wednesday, April 22, 2009
1.0
A
+1.8V
R43
R43 1K_0402_1%
1K_0402_1%
+V_DDR_MCH_REF8
1 1
2 2
3 3
4 4
1 2
R44
R44 1K_0402_1%
1K_0402_1%
1 2
A
1
C96
C96
0.1U_0402_16V7K
0.1U_0402_16V7K
2
DDR_CKE0_DIMMA5
DDR_A_BS#25
DDR_A_BS#05 DDR_A_WE#5
DDR_A_CAS#5 DDR_CS1_DIMMA#5
DDR_A_ODT15
SMB_CK_DAT08,15,21,27
SMB_CK_CLK08,15,21,27
+V_DDR_MCH_REF
1
C95
C95 1000P_0402_25V8J
1000P_0402_25V8J
2
DDR_A_D0 DDR_A_D1
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D20 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12 DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA0
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0 DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_DM5
DDR_A_D42 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7
DDR_A_D58 DDR_A_D59
+3VS
B
JDDRL
JDDRL
C1930.1U_0402_16V7K C1930.1U_0402_16V7K
1 2
1
C103
C103
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
203
VSS
DIMM0 STD H:5.2mm (Bot)
B
C
+1.8V+1.8V
< EMI require >< EMI require >
C161 0.1U_0402_16V7KC161 0.1U_0402_16V7K
2
VSS
4
DQ4
6
DQ5
8
VSS
10
DM0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
VSS
30
CK0
32
CK0#
34
VSS
36
DQ14
38
DQ15
40
VSS
42
VSS
44
DQ20
46
DQ21
48
VSS
50
NC
52
DM2
54
VSS
56
DQ22
58
DQ23
60
VSS
62
DQ28
64
DQ29
66
VSS
68
DQS3#
70
DQS3
72
VSS
74
DQ30
76
DQ31
78
VSS
80
NC/CKE1
82
VDD
84
NC/A15
86
NC/A14
88
VDD
90
A11
92
A7
94
A6
96
VDD
98
A4
100
A2
102
A0
104
VDD
106
BA1
108
RAS#
110
S0#
112
VDD
114
ODT0
116
NC/A13
118
VDD
120
NC
122
VSS
124
DQ36
126
DQ37
128
VSS
130
DM4
132
VSS
134
DQ38
136
DQ39
138
VSS
140
DQ44
142
DQ45
144
VSS
146
DQS5#
148
DQS5
150
VSS
152
DQ46
154
DQ47
156
VSS
158
DQ52
160
DQ53
162
VSS
164
CK1
166
CK1#
168
VSS
170
DM6
172
VSS
174
DQ54
176
DQ55
178
VSS
180
DQ60
182
DQ61
184
VSS
186
DQS7#
188
DQS7
190
VSS
192
DQ62
194
DQ63
196
VSS
198
SAO
200
SA1
204
VSS
FOX_AS0A426-M4R-TR_200P@
FOX_AS0A426-M4R-TR_200P@
12
DDR_A_D4 DDR_A_D5
DDR_A_DM0
DDR_A_D6 DDR_A_D7
DDR_A_D12 DDR_A_D13
DDR_A_DM1
DDR_A_D14 DDR_A_D15
DDR_A_D21
DDR_A_DM2
DDR_A_D22 DDR_A_D23
DDR_A_D28 DDR_A_D29
DDR_A_DQS#3 DDR_A_DQS3
DDR_A_D30 DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15 DDR_A_MA14
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6
DDR_A_MA4 DDR_A_MA2
DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#
DDR_A_MA13
DDR_A_D36 DDR_A_D37
DDR_A_DM4
DDR_A_D38 DDR_A_D39
DDR_A_D44 DDR_A_D45
DDR_A_DQS#5 DDR_A_DQS5
DDR_A_D46 DDR_A_D47
DDR_A_D52 DDR_A_D53
DDR_A_DM6
DDR_A_D54 DDR_A_D55
DDR_A_D60 DDR_A_D61
DDR_A_DQS#7 DDR_A_DQS7
DDR_A_D62 DDR_A_D63
DDR_A_CLK0 5 DDR_A_CLK#0 5
DDR_CKE1_DIMMA 5
DDR_A_BS#1 5 DDR_A_RAS# 5 DDR_CS0_DIMMA# 5
DDR_A_ODT0 5
DDR_A_CLK1 5 DDR_A_CLK#1 5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_MA6 DDR_A_MA14 DDR_A_MA7 DDR_A_MA11
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_BS#1 DDR_A_MA2 DDR_A_MA0 DDR_A_MA4
DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12
DDR_A_BS#0 DDR_A_MA10 DDR_A_MA3 DDR_A_MA1
DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE#
DDR_A_MA13 DDR_A_ODT0 DDR_A_RAS# DDR_CS0_DIMMA#
D
D
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_D[0..63] 5
DDR_A_DM[0..7] 5
DDR_A_DQS[0..7] 5
DDR_A_MA[0..15] 5
DDR_A_DQS#[0..7] 5
+0.9V
RP1
RP1
1 8 2 7 3 6 4 5
RP2
RP2
18 27 36 45
RP3
RP3
1 8 2 7 3 6 4 5
RP4
RP4
18 27 36 45
RP5
RP5
18 27 36 45
RP6
RP6
18 27 36 45
RP7
RP7
1 8 2 7 3 6 4 5
E
C87 0.1U_0402_16V7KC87 0.1U_0402_16V7K
1 2
C88 0.1U_0402_16V7KC88 0.1U_0402_16V7K
1 2
C90 0.1U_0402_16V7KC90 0.1U_0402_16V7K
1 2
C89 0.1U_0402_16V7KC89 0.1U_0402_16V7K
1 2
C91 0.1U_0402_16V7KC91 0.1U_0402_16V7K
1 2
C92 0.1U_0402_16V7KC92 0.1U_0402_16V7K
1 2
C93 0.1U_0402_16V7KC93 0.1U_0402_16V7K
1 2
C94 0.1U_0402_16V7KC94 0.1U_0402_16V7K
1 2
C98 0.1U_0402_16V7KC98 0.1U_0402_16V7K
1 2
C97 0.1U_0402_16V7KC97 0.1U_0402_16V7K
1 2
C100 0.1U_0402_16V7KC100 0.1U_0402_16V7K
1 2
C99 0.1U_0402_16V7KC99 0.1U_0402_16V7K
1 2
C102 0.1U_0402_16V7KC102 0.1U_0402_16V7K
1 2
C101 0.1U_0402_16V7KC101 0.1U_0402_16V7K
1 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.8V
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRII SO-DIMM 1
DDRII SO-DIMM 1
DDRII SO-DIMM 1
LA-4971P
LA-4971P
LA-4971P
9 45Wednesday, April 22, 2009
9 45Wednesday, April 22, 2009
9 45Wednesday, April 22, 2009
E
1.0
1.0
1.0
A
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
1 1
PCIE_GTX_C_MRX_P[0..15] 19
PCIE_GTX_C_MRX_N[0..15] 19
< To New Card >
< To WLAN >
< To LAN >
2 2
H_CADON[0..15]
3 3
4 4
< From S1G2 CPU : x16 HT> < To S1G2 CPU : x16 HT>
H_CADOP[0..15] 4
H_CADON[0..15] 4
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
PCIE_PTX_C_IRX_P027 PCIE_PTX_C_IRX_N027
PCIE_PTX_C_IRX_P227 PCIE_PTX_C_IRX_N227 PCIE_PTX_C_IRX_P326 PCIE_PTX_C_IRX_N326
SB_RX0P20 SB_RX0N20 SB_RX1P20 SB_RX1N20 SB_RX2P20 SB_RX2N20 SB_RX3P20 SB_RX3N20
0718 Place within 1" layout 1:2
H_CLKOP04
H_CLKON04
H_CLKOP14
H_CLKON14
H_CTLOP04 H_CTLON04
H_CTLON14
1 2
B
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15
RS780MCR3@
RS780MCR3@
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7
H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
HT_RXCALP
R57301_0402_1% R57301_0402_1%
HT_RXCALN
U3B
U3B
GM : RS780MN & RS780MC, PM : RX781
D4
GFX_RX0P
C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6
M8
L8 P7
M7
P5
M5
R8 P8 R6 R5 P4 P3 T4 T3
AE3 AD4 AE2 AD3 AD1 AD2
V5
W6
U5 U6 U8 U7
AA8
Y8
AA7
Y7 AA5 AA6
W5
Y5
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
AC24 AC25 AB25 AB24 AA24 AA25
Y22
Y23 W21 W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23 AA22
M22 M23
R21
R20
C23
A24
PART 2 OF 6
PART 2 OF 6
GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N
GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P
PCIE I/F GPP
PCIE I/F GPP
GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N
SB_RX0P SB_RX0N SB_RX1P SB_RX1N
PCIE I/F SB
PCIE I/F SB
SB_RX2P SB_RX2N SB_RX3P SB_RX3N
RS780M_FCBGA528
RS780M_FCBGA528
U3A
U3A
HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
NEED CHECK R57 & R58 WITH AMD
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)
PART 1 OF 6
PART 1 OF 6
C
PCIE_MTX_GRX_P0
A5
GFX_TX0P
PCIE_MTX_GRX_N0
B5
GFX_TX0N
PCIE_MTX_GRX_P1
A4
GFX_TX1P
PCIE_MTX_GRX_N1
B4
GFX_TX1N
PCIE_MTX_GRX_P2
C3
GFX_TX2P
PCIE_MTX_GRX_N2
B2
GFX_TX2N
PCIE_MTX_GRX_P3
D1
GFX_TX3P
D2
GFX_TX3N
PCIE_MTX_GRX_P4
E2
GFX_TX4P
PCIE_MTX_GRX_N4
E1
GFX_TX4N
PCIE_MTX_GRX_P5
F4
GFX_TX5P
F3
GFX_TX5N
PCIE_MTX_GRX_P6
F1
GFX_TX6P
PCIE_MTX_GRX_N6
F2
GFX_TX6N
PCIE_MTX_GRX_P7
H4
GFX_TX7P
PCIE_MTX_GRX_N7
H3
GFX_TX7N
PCIE_MTX_GRX_P8
H1
GFX_TX8P
H2
GFX_TX8N
PCIE_MTX_GRX_P9
J2
GFX_TX9P
PCIE_MTX_GRX_N9
J1
GFX_TX9N
K4
GFX_TX10P
PCIE_MTX_GRX_N10
K3
GFX_TX10N
PCIE_MTX_GRX_P11
K1
GFX_TX11P
PCIE_MTX_GRX_N11
K2
GFX_TX11N
PCIE_MTX_GRX_P12
M4
GFX_TX12P
PCIE_MTX_GRX_N12
M3
GFX_TX12N
PCIE_MTX_GRX_P13
M1
GFX_TX13P
M2
GFX_TX13N
PCIE_MTX_GRX_P14
N2
GFX_TX14P
PCIE_MTX_GRX_N14
N1
GFX_TX14N
PCIE_MTX_GRX_P15
P1
GFX_TX15P
P2
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
HT_TXCALN
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
HT_TXCALP
PCIE_ITX_PRX_P0
AC1
PCIE_ITX_PRX_N0
AC2 AB4 AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
PCIE_ITX_PRX_P3
Y1
PCIE_ITX_PRX_N3
Y2 Y4 Y3 V1 V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5
PCIE_CALRP
AC8
PCIE_CALRN
AB8
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18
H24 H25 L21 L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
HT_TXCALP
B24
HT_TXCALN
B25
0718 Place within 1" layout 1:2
C120 0.1U_0402_16V7KPM@ C120 0.1U_0402_16V7KPM@
1 2
C121 0.1U_0402_16V7KPM@ C121 0.1U_0402_16V7KPM@
1 2
C122 0.1U_0402_16V7KPM@ C122 0.1U_0402_16V7KPM@
1 2
C123 0.1U_0402_16V7KPM@ C123 0.1U_0402_16V7KPM@
1 2
C124 0.1U_0402_16V7KPM@ C124 0.1U_0402_16V7KPM@
1 2
C125 0.1U_0402_16V7KPM@ C125 0.1U_0402_16V7KPM@
1 2
C126 0.1U_0402_16V7KPM@ C126 0.1U_0402_16V7KPM@
1 2
C127 0.1U_0402_16V7KPM@ C127 0.1U_0402_16V7KPM@
1 2
C128 0.1U_0402_16V7KPM@ C128 0.1U_0402_16V7KPM@
1 2
C129 0.1U_0402_16V7KPM@ C129 0.1U_0402_16V7KPM@
1 2
C130 0.1U_0402_16V7KPM@ C130 0.1U_0402_16V7KPM@
1 2
C131 0.1U_0402_16V7KPM@ C131 0.1U_0402_16V7KPM@
1 2
C132 0.1U_0402_16V7KPM@ C132 0.1U_0402_16V7KPM@
1 2
C133 0.1U_0402_16V7KPM@ C133 0.1U_0402_16V7KPM@
1 2
C134 0.1U_0402_16V7KPM@ C134 0.1U_0402_16V7KPM@
1 2
C135 0.1U_0402_16V7KPM@ C135 0.1U_0402_16V7KPM@
1 2
C136 0.1U_0402_16V7KPM@ C136 0.1U_0402_16V7KPM@
1 2
C137 0.1U_0402_16V7KPM@ C137 0.1U_0402_16V7KPM@
1 2
C138 0.1U_0402_16V7KPM@ C138 0.1U_0402_16V7KPM@
1 2
C139 0.1U_0402_16V7KPM@ C139 0.1U_0402_16V7KPM@
1 2
C140 0.1U_0402_16V7KPM@ C140 0.1U_0402_16V7KPM@
1 2
C141 0.1U_0402_16V7KPM@ C141 0.1U_0402_16V7KPM@
1 2
C142 0.1U_0402_16V7KPM@ C142 0.1U_0402_16V7KPM@
1 2
C143 0.1U_0402_16V7KPM@ C143 0.1U_0402_16V7KPM@
1 2
C144 0.1U_0402_16V7KPM@ C144 0.1U_0402_16V7KPM@
1 2
C145 0.1U_0402_16V7KPM@ C145 0.1U_0402_16V7KPM@
1 2
C146 0.1U_0402_16V7KPM@ C146 0.1U_0402_16V7KPM@
1 2
C147 0.1U_0402_16V7KPM@ C147 0.1U_0402_16V7KPM@
1 2
C148 0.1U_0402_16V7KPM@ C148 0.1U_0402_16V7KPM@
1 2
C149 0.1U_0402_16V7KPM@ C149 0.1U_0402_16V7KPM@
1 2
C150 0.1U_0402_16V7KPM@ C150 0.1U_0402_16V7KPM@
1 2
C151 0.1U_0402_16V7KPM@ C151 0.1U_0402_16V7KPM@
1 2
C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K
1 2
C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K
1 2
C156 0.1U_0402_16V7KWLAN@ C156 0.1U_0402_16V7KWLAN@
1 2
C157 0.1U_0402_16V7KWLAN@ C157 0.1U_0402_16V7KWLAN@
1 2
C158 0.1U_0402_16V7KC158 0.1U_0402_16V7K
1 2
C159 0.1U_0402_16V7KC159 0.1U_0402_16V7K
1 2
C162 0.1U_0402_16V7KC162 0.1U_0402_16V7K
1 2
C163 0.1U_0402_16V7KC163 0.1U_0402_16V7K
1 2
C164 0.1U_0402_16V7KC164 0.1U_0402_16V7K
1 2
C165 0.1U_0402_16V7KC165 0.1U_0402_16V7K
1 2
C166 0.1U_0402_16V7KC166 0.1U_0402_16V7K
1 2
C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K
1 2
C169 0.1U_0402_16V7KC169 0.1U_0402_16V7K
1 2
C167 0.1U_0402_16V7KC167 0.1U_0402_16V7K
1 2
R55 1.27K_0402_1%R55 1.27K_0402_1%
1 2
R56 2K_0402_1%R56 2K_0402_1%
1 2
H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]
H_CLKIP0 4
H_CLKIN0 4
H_CLKIP1 4
H_CLKIN1 4
H_CTLIP0 4 H_CTLIN0 4 H_CTLIP1 4H_CTLOP14 H_CTLIN1 4
R58 301_0402_1%R58 301_0402_1%
1 2
H_CADIP[0..15] 4
H_CADIN[0..15] 4
< Transmitter Calibration Resistor to HT_TXCALN >
D
PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3PCIE_MTX_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15PCIE_MTX_GRX_N15
Polarity inversion
Polarity inversion
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
Polarity inversion
< To MXM VGA board >< From MXM VGA board >
Polarity inversion
Polarity inversion
PCIE_ITX_C_PRX_P0 27 PCIE_ITX_C_PRX_N0 27
PCIE_ITX_C_PRX_P2 27 PCIE_ITX_C_PRX_N2 27 PCIE_ITX_C_PRX_P3 26 PCIE_ITX_C_PRX_N3 26
SB_TX0P 20 SB_TX0N 20 SB_TX1P 20 SB_TX1N 20 SB_TX2P 20 SB_TX2N 20 SB_TX3P 20 SB_TX3N 20
+1.1VS
RS780M Display Port Support (muxed on GFX)
< To New Card >
< To WLAN >
< To LAN >
< To SB700 : x4 PCEI A-link>< From SB700 : x4 PCIE A-link >
< TX Impedance Calibration. Connect to GND > < RX Impedance Calibration. Connect to VDDPCIE >
DP0
GFX_TX0,TX1,TX2 and TX3
DP1
GFX_TX4,TX5,TX6 and TX7
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3
R74 0_0402_5%IHDMI@ R74 0_0402_5%IHDMI@ R75 0_0402_5%IHDMI@ R75 0_0402_5%IHDMI@ R76 0_0402_5%IHDMI@ R76 0_0402_5%IHDMI@ R81 0_0402_5%IHDMI@ R81 0_0402_5%IHDMI@
R82 0_0402_5%IHDMI@ R82 0_0402_5%IHDMI@ R83 0_0402_5%IHDMI@ R83 0_0402_5%IHDMI@ R84 0_0402_5%IHDMI@ R84 0_0402_5%IHDMI@ R85 0_0402_5%IHDMI@ R85 0_0402_5%IHDMI@
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
E
PCIE_MTX_C_GRX_P[0..15] 19
PCIE_MTX_C_GRX_N[0..15] 19
AUX0 and HPD0
AUX1 and HPD1
HDMI_TXD2+ 18,19 HDMI_TXD2- 18,19 HDMI_TXD1+ 18,19 HDMI_TXD1- 18,19
HDMI_TXD0+ 18,19 HDMI_TXD0- 18,19 HDMI_CLK0+ 18,19 HDMI_CLK0- 18,19
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
LA-4971P
LA-4971P
LA-4971P
10 45Wednesday, April 22, 2009
10 45Wednesday, April 22, 2009
10 45Wednesday, April 22, 2009
E
1.0Custom
1.0Custom
1.0Custom
A
UMA_CRT_R16
1 1
< DAC internal reference to set full scale DAC current >
+1.1VS
R71
R71
4.7K_0402_5%
4.7K_0402_5%
1 2
12
2 2
R72
R72
4.7K_0402_5%
4.7K_0402_5%
UMA_CRT_G16
UMA_CRT_B16
UMA_CRT_HSYNC14,16 UMA_CRT_VSYNC14,16 UMA_CRT_CLK16 UMA_CRT_DATA16
PLT_RST#14,19,20,26,27,33,34
NB_PWRGD21 LDT_STOP#6,20 CPU_LDT_REQ#6,20
NB_OSC_14.318M15
NBGFX_CLK15 NBGFX_CLK#15
CLK_SBLINK_BCLK15 CLK_SBLINK_BCLK#15
UMA_LCD_DDC_CLK17
UMA_LCD_DDC_DAT17
HDMIDAT_UMA18 HDMICLK_UMA18
Strap pin
< Dedicated power for the DAC which can affect display quality > < Dedicated power for the DAC which can affect display quality >
GPM@
GPM@
+3VS +1.8VS
3 3
< DAC Bandgap Reference Voltage >
+1.8VS
< IO power for HyperTransport PLL >
+1.8VS +VDDA18HTPLL
4 4
A
< 1.8V IO power for PCI-E PLLs >
+1.8VS
1 2
GPM@
GPM@
1 2
L10 BLM18PG121SN1D_0603L10 BLM18PG121SN1D_0603
1 2
L11 BLM18PG121SN1D_0603L11 BLM18PG121SN1D_0603
1 2
+NB_PLLVDD
+NB_HTPVDD
+VDDA18HTPLL
+VDDA18PCIEPLL
CLK_NBHT15 CLK_NBHT#15
AUX_CAL14
L2
L2 0_0603_5%
0_0603_5%
L2
L2 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
L6
L6 0_0603_5%
0_0603_5%
L6
L6 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
B
+AVDD1
+AVDD2
+AVDDQ
UMA_CRT_R
UMA_CRT_G
UMA_CRT_B
R67 0_0402_5%R67 0_0402_5%
1 2
+3VS
1
2
1
2
B
R65 715_0402_1%GPM@ R65 715_0402_1%GPM@ R65 715_0402_1%GM@ R65 715_0402_1%GM@
1 2
R88 10K_0402_5%@ R88 10K_0402_5%@
PM1@ C170
PM1@
1
GM@
GM@
2
PM1@ C175
PM1@
1
GM@
GM@
2
C179
C179
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+VDDA18PCIEPLL
C180
C180
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
AVDD=100mA
UMA_CRT_HSYNC UMA_CRT_VSYNC
12
C170 0_0603_5%
0_0603_5%
C170
C170
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C175 0_0603_5%
0_0603_5%
C175
C175
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
+NB_PLLVDD +NB_HTPVDD
NB_RESET# NB_PWRGD
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780MCR3@
RS780MCR3@
RS780M_FCBGA528
RS780M_FCBGA528
+AVDD1 +AVDD2
+AVDDQ
/
/
/
Security Classification
Security Classification
Security Classification
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
GPM@ L4
GPM@
< 1.8V power for system PLLs >
GPM@
GPM@
+1.8VS
< 1.1V Power for system PLLs >
GPM@
GPM@
+1.1VS
Issued Date
Issued Date
Issued Date
C
A22
TXOUT_L0P(NC)
PART 3 OF 6
PART 3 OF 6
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PL L PWR
CLOCKs PL L PWR
MIS.
MIS.
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P THERMALDIODE_N
PM1@ C172
PM1@
L4 0_0603_5%
0_0603_5%
L4 0_0603_5%GM@L40_0603_5%GM@
GM@
GM@
L7
L7 0_0603_5%
0_0603_5%
L7
L7 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
1 2
L9
L9 0_0603_5%
0_0603_5%
L9
L9 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
1 2
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L3P(NC)
TXOUT_U0P(NC) TXOUT_U0N(NC)
TXOUT_U2P(NC) TXOUT_U2N(NC)
TXOUT_U3N(NC)
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
TESTMODE
C172 0_0603_5%
0_0603_5%
1
C172
C172
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
A13 B13
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
D9 D10
D12
AE8 AD8
D13
PM1@ C198
PM1@
GM@
GM@
C176
PM1@ C176
PM1@
0_0603_5%
0_0603_5%
1
C176
C176
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
C178
PM1@ C178
PM1@
0_0603_5%
0_0603_5%
1
C178
C178
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
Deciphered Date
Deciphered Date
Deciphered Date
T17PAD T17PAD
R80 1.8K_0402_5%R80 1.8K_0402_5%
1
C198
C198
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+VDDLTP18
+VDDLT18
R79 0_0402_5%GM@ R79 0_0402_5%GM@
1 2
R78 0_0402_5%GPM@ R78 0_0402_5%GPM@ R78 0_0402_5%GM@ R78 0_0402_5%GM@
1 2
1 2
C198 0_0402_5%
0_0402_5%
D
R73 100K_0402_5%GPM@ R73 100K_0402_5%GPM@ R73 100K_0402_5%GM@ R73 100K_0402_5%GM@
12
< Power for integrated DVI/HDMI PLL macro >
+1.8VS
+NB_HTPVDD
< 1.8V IO power for the integrated DVI/HDMI interface >
+1.8VS
+NB_PLLVDD
D
UMA_LCD_TXOUT0_A0+ 17 UMA_LCD_TXOUT0_A0- 17 UMA_LCD_TXOUT0_A1+ 17 UMA_LCD_TXOUT0_A1- 17 UMA_LCD_TXOUT0_A2+ 17 UMA_LCD_TXOUT0_A2- 17
UMA_LCD_TZOUT0_B0+ 17 UMA_LCD_TZOUT0_B0- 17 UMA_LCD_TZOUT0_B1+ 17 UMA_LCD_TZOUT0_B1- 17 UMA_LCD_TZOUT0_B2+ 17 UMA_LCD_TZOUT0_B2- 17
UMA_LCD_TXCLK_ACLK+ 17 UMA_LCD_TXCLK_ACLK- 17 UMA_LCD_TZCLK_BCLK+ 17 UMA_LCD_TZCLK_BCLK- 17
UMA_ENVDD 17 UMA_ENBKL 34
HPD 18,19,21
+1.8VS
SUS_STAT# 14,21
R371 300_0402_5%R371 300_0402_5%
1 2
< LVDS dual channel : channel 1 >
< LVDS dual channel : channel 2 >
< LVDS digital power enable >
< LVDS backlight enable >
< HDMI hot-plug detection >
< Strap option pin or gate side-port memory IO >
NB_PWRGD
RS780 use 140 ohm, check RS880 use what value
R62 140_0402_1%GM@ R62 140_0402_1%GM@
1 2
R63 150_0402_1%GM@ R63 150_0402_1%GM@
1 2
R64 150_0402_1%GM@ R64 150_0402_1%GM@
1 2
GPM@
GPM@
GPM@ L5
GPM@
GM@ L5
GM@
L3
L3 0_0603_5%
0_0603_5%
L3
L3 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
12
L5 0_0603_5%
0_0603_5%
L5 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
12
GM@
GM@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
UMA_CRT_R
UMA_CRT_G
UMA_CRT_B
PM1@ C171
PM1@
GM@
GM@
1
C174
C174
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
LA-4971P
LA-4971P
LA-4971P
E
1
C171
C171
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
PM1@ C173
PM1@
GM@
GM@
E
C171 0_0603_5%
0_0603_5%
1
2
+VDDLTP18
C173 0_0402_5%
0_0402_5%
+VDDLT18
C173
C173
0.1U_0402_16V7K
0.1U_0402_16V7K
11 45Wednesday, April 22, 2009
11 45Wednesday, April 22, 2009
11 45Wednesday, April 22, 2009
1.0
1.0
1.0
2
B B
U3D
U3D
PAR 4 OF 6
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)
MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
MEM_DQ4(NC)
MEM_DQ12(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM0(NC)
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23
+1.8VS
AE24
+1.1VS
AD23
AE18
AB12 AE16
V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
Y14
AD16 AE17 AD17
W12
Y12 AD18 AB13 AB18
V14
V15
W14
AE12 AD12
1
A A
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
LA-4971P
LA-4971P
LA-4971P
1.0
1.0
12 45Wednesday, April 22, 2009
12 45Wednesday, April 22, 2009
12 45Wednesday, April 22, 2009
1.0
A
2A
L16 0_0805_5%L16 0_0805_5%
+1.1VS
1 1
+1.2V_HT
+1.8VS
2 2
+1.8VS
3 3
4 4
12
1
C209
C209
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < IO power for HyperTransport receive interface >
L18 0_0805_5%L18 0_0805_5%
12
C215
C215
10U_0805_10V4Z
10U_0805_10V4Z
2A < IO power for HyperTransport transmit interface >
L19 0_0805_5%L19 0_0805_5%
12
1
C225
C225
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
L22 0_0805_5%L22 0_0805_5%
12
1
C235
C235
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C251
C251
+1.8VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C206
C206
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C214
C214
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C226
C226
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C246
C246
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
L89 0_0603_5%GM@ L89 0_0603_5%GM@
1 2
L89 0_0603_5%GPM@ L89 0_0603_5%GPM@
A
< Digital IO power for HyperTransport interface >
1
C207
C207
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C216
C216
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C227
C227
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C236
C236
0.1U_0402_16V7K
0.1U_0402_16V7K
2
< 1.8V IO transform power >
< 1.8V power for side-port memory interface >
GM@
GM@
PM1@ C252
PM1@
1
C208
C208
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C217
C217
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C228
C228
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C237
C237
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C252
C252
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
C252 0_0402_5%
0_0402_5%
B
B
1
C210
C210
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C218
C218
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C229
C229
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C238
C238
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C239
C239
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C
U3E
U3E
+VDDHT
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_6
T16
+VDDHTRX
+VDDHTTX
+VDDA18PCIE
VDDHT_7
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_4
D22
VDDHTRX_5
B23
VDDHTRX_6
A23
VDDHTRX_7
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y20
VDDHTTX_6
W19
VDDHTTX_7
V18
VDDHTTX_8
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_12
M17
VDDHTTX_13
J10
VDDA18PCIE_1
P10
VDDA18PCIE_2
K10
VDDA18PCIE_3
M10
VDDA18PCIE_4
L10
VDDA18PCIE_5
W9
VDDA18PCIE_6
H9
VDDA18PCIE_7
T10
VDDA18PCIE_8
R10
VDDA18PCIE_9
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_13
AE9
VDDA18PCIE_14
U10
VDDA18PCIE_15
F9
VDD18_1
G9
VDD18_2
AE11
VDD18_MEM1(NC)
AD11
VDD18_MEM2(NC)
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
U3F
U3F
A25
VSSAHT1
D23
VSSAHT2
E22
VSSAHT3
G22
VSSAHT4
G24
VSSAHT5
G25
VSSAHT6
H19
VSSAHT7
J22
VSSAHT8
L17
VSSAHT9
L22
VSSAHT10
L24
VSSAHT11
L25
VSSAHT12
M20
VSSAHT13
N22
VSSAHT14
P20
VSSAHT15
R19
VSSAHT16
R22
VSSAHT17
R24
VSSAHT18
R25
VSSAHT19
H20
VSSAHT20
U22
VSSAHT21
V19
VSSAHT22
W22
VSSAHT23
W24
VSSAHT24
W25
VSSAHT25
Y21
VSSAHT26
AD25
VSSAHT27
L12
VSS11
M14
VSS12
N13
VSS13
P12
VSS14
P15
VSS15
R11
VSS16
R14
VSS17
T12
VSS18
U14
VSS19
U11
VSS20
U15
VSS21
V12
VSS22
W11
VSS23
W15
VSS24
AC12
VSS25
AA14
VSS26
Y18
VSS27
AB11
VSS28
AB15
VSS29
AB17
VSS30
AB19
VSS31
AE20
VSS32
AB21
VSS33
K11
VSS34
RS780M_FCBGA528
RS780M_FCBGA528
RS780MCR3@
RS780MCR3@
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
VDDPCIE_1
PART 5/6
PART 5/6
VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
POWER
POWER
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
VSSAPCIE1
PART 6/6
PART 6/6
VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30
GROUND
GROUND
VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
+VDDA11PCIE
A6 B6 C6
VDDA_12=2.5A
D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12
VDDC_1
J14
VDDC_2
U16
VDDC_3
J11
VDDC_4
K15
VDDC_5
M12
VDDC_6
L14
VDDC_7
L11
VDDC_8
M13
VDDC_9
M15
VDDC_10
N12
VDDC_11
N14
VDDC_12
P11
VDDC_13
P13
VDDC_14
P14
VDDC_15
R12
VDDC_16
R15
VDDC_17
T11
VDDC_18
T15
VDDC_19
U12
VDDC_20
T14
VDDC_21
J16
VDDC_22
AE10 AA11
< Isolated power for side-port memory interface >
Y11 AD10 AB10 AC10
< 3.3V IO power >
H11 H12
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14
VSS1
D11
VSS2
G8
VSS3
E14
VSS4
E15
VSS5
J15
VSS6
J12
VSS7
K14
VSS8
M11
VSS9
L15
VSS10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
D
GM@
GM@
C2191U_0402_6.3V4Z C2191U_0402_6.3V4Z
C2201U_0402_6.3V4Z C2201U_0402_6.3V4Z
1
1
2
2
C2400.1U_0402_16V7K C2400.1U_0402_16V7K
C2470.1U_0402_16V7K C2470.1U_0402_16V7K
2
2
1
1
1
C250
C250
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2221U_0402_6.3V4Z C2221U_0402_6.3V4Z
C2211U_0402_6.3V4Z C2211U_0402_6.3V4Z
1
1
2
2
C21210U_0805_10V4Z C21210U_0805_10V4Z
C2240.1U_0402_16V7K C2240.1U_0402_16V7K
2
2
1
1
+NB_CORE
C21110U_0805_10V4Z C21110U_0805_10V4Z
C2230.1U_0402_16V7K C2230.1U_0402_16V7K
VDD_CORE:GM=5A/PM=10A< Core power >
C2420.1U_0402_16V7K C2420.1U_0402_16V7K
C2410.1U_0402_16V7K C2410.1U_0402_16V7K
2
2
1
1
C2320.1U_0402_16V7K C2320.1U_0402_16V7K
C2300.1U_0402_16V7K C2300.1U_0402_16V7K
C2430.1U_0402_16V7K C2430.1U_0402_16V7K
C2310.1U_0402_16V7K C2310.1U_0402_16V7K
C2440.1U_0402_16V7K C2440.1U_0402_16V7K
2
2
2
2
2
1
1
1
1
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1
1
C24510U_0805_10V4Z C24510U_0805_10V4Z
C23310U_0805_10V4Z C23310U_0805_10V4Z
2
2
2
1
GM@
GM@
2
LA-4971P
LA-4971P
LA-4971P
E
1 2
PJP9
PJP9
PAD-OPEN 4x4m
PAD-OPEN 4x4m
+
+
C234
C234 470U_D2E_2.5VM_R9M
470U_D2E_2.5VM_R9M
DVT change to B size
C253
C253
0.1U_0402_16V4Z
0.1U_0402_16V4Z
13 45Wednesday, April 22, 2009
13 45Wednesday, April 22, 2009
13 45Wednesday, April 22, 2009
E
L17FBMA-L11-201209-221LMA30T_0805 L17FBMA-L11-201209-221LMA30T_0805
+1.1VS
12
+1.1VS
+3VS
1.0Custom
1.0Custom
1.0Custom
A
B
C
D
E
< RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K >
SI2: Change to 3K pull high
R101
R101 3K_0402_5%
3K_0402_5%
UMA_CRT_VSYNC11,16
1 1
12
R102
R102 3K_0402_5%@
3K_0402_5%@
12
< RS780 use register to control PCI-E configure >
< RS780 DFT_GPIO1 >
R104
R104 150_0402_1%@
150_0402_1%@
D4
D4 CH751H-40PT_SOD323-2@
CH751H-40PT_SOD323-2@
1 2
PLT_RST# 11,19,20,26,27,33,34
2 2
AUX_CAL11
SUS_STAT#11,21
2 1
< RS780 use HSYNC to enable SIDE PORT (internal pull high) >
R125
R125 3K_0402_5%
3K_0402_5%
UMA_CRT_HSYNC11,16
12
< DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb >
Enables the Test Debug Bus using GPIO.
1 : Enable (RX780, RS780)
+3VS
0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010 010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011
< DFT_GPIO1 : LOAD_EEPROM_STRAPS >
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
< DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb >
RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
+3VS
0 : Enable
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780) 0 : Enable (RS780)
3 3
4 4
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
LA-4971P
LA-4971P
LA-4971P
14 45Wednesday, April 22, 2009
14 45Wednesday, April 22, 2009
14 45Wednesday, April 22, 2009
E
1.0Custom
1.0Custom
1.0Custom
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