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A500
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Toshiba a500, l500 Schematics

0.1
0.1
0.1
1 45Wednesday, February 25, 2009
1 45Wednesday, February 25, 2009
1 45Wednesday, February 25, 2009
E
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
D
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
E
LA-4971P
LA-4971P
LA-4971P
Cover Sheet
Cover Sheet
Cover Sheet
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
C
Security Classification
Security Classification
Security Classification
B
Liverpool 10AR/10ARG
Mobile AMD S1G2 S1G3/
RS780MN & RS780MC & RX781 & RS880 /
SB700 & SB710
2009-02-09 Rev. 0.3
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
KSWAE LA-4971P Schematics Document
Compal confidential
A
1 1
2 2
3 3
4 4
A
0.1
0.1
0.1
2 45Wednesday, February 25, 2009
2 45Wednesday, February 25, 2009
2 45Wednesday, February 25, 2009
E
LA-4971P
LA-4971P
LA-4971P
Block Diagram
Block Diagram
Block Diagram
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
V o l u m e C o n t r o l
V o l u m e C o n t r o l
V o l u m e C o n t r o lV o l u m e C o n t r o l
page 31
page 29
3IN1
E
3IN1
page 32
page 4
F a n C o n t r o lF a n C o n t r o l
F a n C o n t r o l
1 6 X 1 6
1 6 X 1 6
1 6 X 1 61 6 X 1 6
2 0 0 p i n D D R I I - S O - D I M M X 2
2 0 0 p i n D D R I I - S O - D I M M X 22 0 0 p i n D D R I I - S O - D I M M X 2
2 0 0 p i n D D R I I - S O - D I M M X 2
A T I
A T IA T I
A T I
page 8,9
1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
D u a l C h a n n e l
M e m o r y B U S ( D D R I I )
D u a l C h a n n e lD u a l C h a n n e l
M e m o r y B U S ( D D R I I )M e m o r y B U S ( D D R I I )
1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
M e m o r y B U S ( D D R I I )
D u a l C h a n n e l
1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
BANK 0, 1, 2, 3
RS780MN
RS780MC
RX781
RS880
APL5607KI-TRG
page 6
D
T h e r m a l S e n s o r
T h e r m a l S e n s o r F a n C o n t r o l
T h e r m a l S e n s o rT h e r m a l S e n s o r
ADM1032ARMZ
page 4,5,6,7
A M D S 1 G 2 C P U
A M D S 1 G 2 C P U
A M D S 1 G 2 C P UA M D S 1 G 2 C P U
C
uFCPGA-638 Package
B l u e t o o t h
B l u e t o o t hB l u e t o o t h
B l u e t o o t h
USBPort 6
page 32
I n t . C a m e r a
I n t . C a m e r aI n t . C a m e r a
I n t . C a m e r a
USBPort 9
page 32
R i g h t U S B C o n n
R i g h t U S B C o n n
R i g h t U S B C o n nR i g h t U S B C o n n
USB Port 0,1
A T I
A T IA T I
A T I
page 10,11,12,13,14
USB 5x
SB700
SB710
R T S 5 1 5 9 E
R T S 5 1 5 9 E
R T S 5 1 5 9 ER T S 5 1 5 9 E
F i n g e r P r i n t e r
F i n g e r P r i n t e rF i n g e r P r i n t e r
F i n g e r P r i n t e r
W L A N
W L A N
W L A NW L A N
5V 480MHz
page 29
USBPort 4
page 27
USBPort 7
S A T A H D D 1
S A T A H D D 1S A T A H D D 1
S A T A H D D 1
page 27
USBPort 8
page 25
page 25
S A T A O D D
S A T A O D DS A T A O D D
S A T A O D D
SATA port 3
SATA port 0
SATA
SATA
5V 1.5GHz(150MB/s)
page 20,21,22,23,24
H D A C o d e c
H D A C o d e cH D A C o d e c
H D A C o d e c
5V 1.5GHz(150MB/s)
3.3V 24.576MHz/48Mhz
M D C 1 . 5
M D C 1 . 5 M D C 1 . 5
M D C 1 . 5
HD Audio
page 30
ALC272
page 33
S P I R O M
S P I R O M
S P I R O MS P I R O M
page 31
H P C O N N
H P C O N NH P C O N N
H P C O N N
page 31
I n t . M I C
I n t . M I C
I n t . M I C I n t . M I C
page 31
M I C C O N N
M I C C O N N
M I C C O N NM I C C O N N
A M P L I F I E R
A M P L I F I E R
A M P L I F I E RA M P L I F I E R
TPA6017
R J 1 1
R J 1 1R J 1 1
R J 1 1
page 33
page 33
page 31
S P K C O N N
S P K C O N NS P K C O N N
S P K C O N N
page 31
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Secret Data
Compal Secret Data
Compal Secret Data
A - L i n k E x p r e s s I I
4 X P C I - E
A - L i n k E x p r e s s I IA - L i n k E x p r e s s I I
4 X P C I - E
A - L i n k E x p r e s s I I
4 X P C I - E4 X P C I - E
I n t . K B D
I n t . K B DI n t . K B D
I n t . K B D
T o u c h P a d
T o u c h P a d
T o u c h P a dT o u c h P a d
G s e n s o r
G s e n s o r
G s e n s o rG s e n s o r
page 35
page 35
page 33
page 35
page 35
page 36
C a r d B u s C o n t r o l l e r
C a r d B u s C o n t r o l l e rC a r d B u s C o n t r o l l e r
C a r d B u s C o n t r o l l e r
3.3V 33 MHz
LPC BUS
page 28
OZ601
U S B / B
U S B / BU S B / B
U S B / B
page 32
page 15
P o w e r / B
P o w e r / BP o w e r / B
P o w e r / B
page 34
E N E K B 9 2 6 D 2
E N E K B 9 2 6 D 2E N E K B 9 2 6 D 2
E N E K B 9 2 6 D 2
page 33
D e b u g P o r t
D e b u g P o r tD e b u g P o r t
D e b u g P o r t
S W / B
S W / B
S W / BS W / B
page 35
page 37
5V 480MHzUSB
H y p e r T r a n s p o r t L i n k 2 . 6 G H z
H y p e r T r a n s p o r t L i n k 2 . 6 G H zH y p e r T r a n s p o r t L i n k 2 . 6 G H z
H y p e r T r a n s p o r t L i n k 2 . 6 G H z
N E W C a r d
N E W C a r dN E W C a r d
N E W C a r d
P C I e M i n i C a r d W L A N
P C I e M i n i C a r d W L A N
P C I e M i n i C a r d W L A NP C I e M i n i C a r d W L A N
page 27
USB port 11
PCIe port 0
page 27
PCIe Port 2
page 26
Page 19
A T I M 9 2 / 9 6
A T I M 9 2 / 9 6A T I M 9 2 / 9 6
A T I M 9 2 / 9 6
with VRAM
V G A M X M C o n n
V G A M X M C o n n
B
A
V G A M X M C o n nV G A M X M C o n n
C R T
C R T
C R T C R T
page 16
L C D C o n n .
L C D C o n n .
L C D C o n n .L C D C o n n .
page 17
H D M I C o n n .
H D M I C o n n .H D M I C o n n .
H D M I C o n n .
H D M I C E C C o n t r o l l e r
H D M I C E C C o n t r o l l e rH D M I C E C C o n t r o l l e r
H D M I C E C C o n t r o l l e r
1.5V 2.5GHz(250MB/s)
page 18
PCIe 4x
page 18
R5F211A4SP
5V 480MHzUSB
3.3V 33 MHz
page 25
USB port 2
SATA port 2
page 26
PCI BUS
SATA 5V 1.5GHz(150MB/s)
e S A T A
e S A T A
e S A T Ae S A T A
R J 4 5
R J 4 5R J 4 5
R J 4 5
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
A
M o d e l N a m e : K S W A E
F i l e N a m e : L A - 4 9 7 1 P
G r i f f i n P l a t f o r m
M o d e l N a m e : K S W A E
M o d e l N a m e : K S W A EM o d e l N a m e : K S W A E
F i l e N a m e : L A - 4 9 7 1 PF i l e N a m e : L A - 4 9 7 1 P
F i l e N a m e : L A - 4 9 7 1 P
G r i f f i n P l a t f o r m
Compal Confidential
G r i f f i n P l a t f o r mG r i f f i n P l a t f o r m
1 1
EC SMBUS
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 MR T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
PCIe port 3
2 2
3 3
C l o c k G e n e r a t o r
C l o c k G e n e r a t o rC l o c k G e n e r a t o r
C l o c k G e n e r a t o r
SLG8SP626VTR
P o w e r O n / O f f C K T .
R T C C K T .
R T C C K T .
R T C C K T .R T C C K T .
P o w e r O n / O f f C K T .P o w e r O n / O f f C K T .
P o w e r O n / O f f C K T .
D C / D C I n t e r f a c e C K T .
D C / D C I n t e r f a c e C K T .D C / D C I n t e r f a c e C K T .
D C / D C I n t e r f a c e C K T .
page 37,38,39,40
41,42,43,44
P o w e r C i r c u i t D C / D C
P o w e r C i r c u i t D C / D CP o w e r C i r c u i t D C / D C
P o w e r C i r c u i t D C / D C
4 4
0.1
0.1
0.1
3 45Wednesday, February 25, 2009
3 45Wednesday, February 25, 2009
Notes List
Notes List
Notes List
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-4971P
LA-4971P
LA-4971P
3 45Wednesday, February 25, 2009
E
Date: Sheet of
Date: Sheet of
Date: Sheet of
CARD@
RTS5159
First Second
G@ + G_1st@ G@ + G_2nd@
CHIPSET
PUMA@ TIGRIS@
MXM
Thermal
NEW
HDMI
DDC
LCD
DDC
WLAN
CLK
Sensor
CARD
ROM
ROM
GEN
V
V
V
Compal Electronics, Inc.
Compal Electronics, Inc.
V
Compal Electronics, Inc.
V
VV
MXM
RX781
S1G2
Comment
SB710
SB710
VGA
NA
NB
RS880M
RS880MC NA
S1G3
S1G3
SB710
MXM
MXMRS880M
RX881
S1G3
S1G3
3 in 1 card reader
G- sensor
CommentItem CPU SB
E
VGA
NB
SB700
SB700
NA
RS780MN
RS780MC NA
S1G2
S1G2
SB700
MXMRS780MN
S1G2
D
Platform
C
: Digital Ground
Symbol Note :
B
GM@
PM@+GPM@
GM@
PUMA@
: Analog Ground
Item CPU SB
GM@
PM@+PM1@ SB700
@ : just reserve , no build
GM@
Platform
PM@+GPM@
TIGRIS@
Layout Notes
L
DEBUG@ : reserve for debug.
DC-IN
WiFi
PM@+PM1@ SB710
UMA@: means for RS780M.
( H )
Half - size
WLAN@ WIMAX@
LVDS wireset
17inch@
SATA ODD
16" 17"
16inch@
SSD
RJ11
BLUE TOOTH
Express card / PCMCIA
Function
BTO (Build-To-Order) Option Table
SSD@
( S )
( R )
MDC@
( B )
BT@
( E / A )
EXPCARD@ / PCMCIA@
Description
BTO
Explain
HDMI
CAMERA & MIC
FingerPrinter
Function
Cost down
COMMON
(Y)
ATI VGA/B
AMD(UMA)
(X)
CAMERA MIC
( F )
Explain
Description
16inch_45@ 17inch_45@
LVDSSET@
H@
HDMI@
IHDMI@
CAM@ MIC@
FP@
BTO
I / II
SODIMM
V
SENSOR
CPU
THERMAL
CEC
EC_SMB_CK1
V
V
KB926
KB926
EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
RS780M
I2C_DATA
I2C_CLK
HDMI
BATTINVERTER
SOURCE
SMBUS Control Table
RS780M
RS780M
DDC_DATA0
DDC_CLK0
DDC_CLK1
SB700
SDA0
SCL0
DDC_DATA1
SCL1
SB700
SDA1
SB700
SCL2
SDA2
SB700
SCL3
SDA3
D
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
A
Voltage Rails
O : ON
X : OFF
+5VS
+3VS
1 1
+2.5VS+B+1.5VS
+1.8VS
power
plane
+VGA_CORE
+1.1VS
+1.8V+5VALW
+0.9V
+3VALW
+3VL
+1.2V_HT
+CPU_CORE_NB
+CPU_CORE_0
+0.9V
+3V_LAN
+1.2VALW
+5VL
+RTCVCC
State
+CPU_CORE_1
OO
O
O
O
O
O
O
O
S3
S1
S0
2 2
X
X X
X
X
O
O
S5 S4/AC
X X X
O
X
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1 0 1 0 0 1 0
1 0 1 0 0 1 0 0A4
1 0 1 0 0 0 0 0
ADDRESS
HEX
I2C / SMBUS ADDRESSING
DEVICE
D2
A0
CLOCK GENERATOR (EXT.)
DDR SO-DIMM 1
DDR SO-DIMM 0
3 3
HEX
EC SM Bus1 address
Device Address
0001 011X b
0011 010X b
16H
Smart Battery
HDMI-CEC 34H
EC KB926D2
1001 100X b
1001 101X b
HEX Address
98H
9AH
EC SM Bus2 address
Device
ADI1032-1 CPU
ADI1032-2 VGA
4 4
Ext. VGA/B
CS/B
EC KB926D2
A
X
OO
0.1
0.1
0.1
4 45Wednesday, February 25, 2009
4 45Wednesday, February 25, 2009
4 45Wednesday, February 25, 2009
E
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
E
LA-4971P
LA-4971P
LA-4971P
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
< To EC >
D
FAN_SPEED1 34
C8
0.01U_0402_25V7K
C8
10K_0402_5%
10K_0402_5%
2
ACES_85204-0300N
ACES_85204-0300N
5
0.01U_0402_25V7K
1
@
@
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
12
+3VS
112233GND4GND
JFAN
JFAN
R12
R12
Deciphered Date
Deciphered Date
Deciphered Date
D
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
C
C6
180P_0402_50V8J
C6
180P_0402_50V8J
1
2
+FAN1
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
C7
4.7U_0805_10V4Z
PUMA@C74.7U_0805_10V4Z
PUMA@
C7
10U_0805_10V6K
TIGRIS@ C7
10U_0805_10V6K
C5
180P_0402_50V8J
C5
180P_0402_50V8J
1
2
C4
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
1
2
C3
0.22U_0603_16V4Z
C3
0.22U_0603_16V4Z
1
B
2
H_CADON[0..15] 10H_CADIN[0..15]10
H_CADOP[0..15] 10
H_CADOP[0..15]
H_CADON[0..15]
Near CPU SocketVLDT CAP.
C2
10U_0805_10V6K
TIGRIS@ C2
10U_0805_10V6K
TIGRIS@
C2
4.7U_0805_10V4Z
PUMA@C24.7U_0805_10V4Z
PUMA@
1
2
C1
10U_0805_10V6K
TIGRIS@ C1
10U_0805_10V6K
A
TIGRIS@
H_CADIN[0..15]
H_CADIP[0..15]
H_CADIP[0..15]10
1 2
+VLDT_B
AE4
AE3
AE2
VLDT_B1
VLDT_B0
HT LINK
HT LINK
VLDT_A1
VLDT_A0
JCPUA
JCPUA
D3
D2
D1
+1.2V_HT
VLDT=500mA
TIGRIS@
AE5
VLDT_B3
VLDT_B2
VLDT_A3
VLDT_A2
D4
H_CADON0
H_CADOP1
H_CADOP2
H_CADON1
H_CADOP0
AB1
AC2
AC3
AD1
AC1
L0_CADOUT_L1
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_H0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
F1
E1
E3
E2
G3
H_CADIN1
H_CADIN0
H_CADIP2
H_CADIP1
H_CADIP0
H_CADON2
H_CADON3
H_CADOP4
H_CADON4
H_CADOP3
W2
W3
AA2
AA3
AA1
L0_CADOUT_L4
L0_CADOUT_L3
L0_CADOUT_L2
L0_CADOUT_H4
L0_CADOUT_H3
L0_CADOUT_H2
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
J1
K1
H1
G1
G2
H_CADIP3
H_CADIN2
H_CADIN3
H_CADIP4
H_CADIN4
H_CADON6
H_CADOP6
H_CADOP5
H_CADON5
H_CADOP7
T1
U2
U3
V1
U1
L0_CADOUT_L6
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_H5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L1
L3
L2
N3
M1
H_CADIN5
H_CADIP5
H_CADIN6
H_CADIP6
H_CADIP7
< To NB >< From NB >
H_CADON9
H_CADOP8
H_CADON7
H_CADON8
H_CADOP9
AD5
AC5
AD4
AD3
R1
L0_CADOUT_L9
L0_CADOUT_L8
L0_CADOUT_L7
L0_CADOUT_H9
L0_CADOUT_H8
L0_CADOUT_H7
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
F3
F4
F5
E5
N2
H_CADIN8
H_CADIN7
H_CADIN9
H_CADIP8
H_CADIP9
H_CADOP11
H_CADON12
H_CADON10
H_CADOP12
H_CADOP10
H_CADON11
Y5
AB5
AA5
AB4
AB3
L0_CADOUT_L11
L0_CADOUT_L10
L0_CADOUT_H12
L0_CADOUT_H11
L0_CADOUT_H10
L0_CADIN_H12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
K3
H3
H4
H5
G5
H_CADIN10
H_CADIP10
H_CADIN11
H_CADIP11
H_CADIN12
H_CADIP12
H_CADOP13
H_CADON13
H_CADOP15
H_CADOP14
H_CADON14
V5
U5
V4
V3
W5
L0_CADOUT_L14
L0_CADOUT_L13
L0_CADOUT_L12
L0_CADOUT_H14
L0_CADOUT_H13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_L12
L5
K4
M3
M4
M5
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIP13
H_CLKOP0 10
H_CLKON0 10
H_CLKOP1 10
H_CADON15
T4
T3
Y4
Y1
W1
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_H0
L0_CADOUT_L15
L0_CADOUT_H15
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H1
L0_CLKIN_H0
L0_CLKIN_L0J2L0_CTLIN_H1
J5
J3
P5
N5
H_CADIN15
H_CLKIN010
H_CLKIP110
H_CLKIP010
H_CLKON1 10
H_CTLOP0 10
H_CTLON0 10
H_CTLOP1 10
Y3
T5
R2
R3
L0_CTLOUT_L0
L0_CLKOUT_L1
L0_CTLOUT_H1
L0_CTLOUT_H0
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
K5
P3
P1
N1
H_CLKIN110
H_CTLIP110
H_CTLIN010
H_CTLIP010
H_CTLON1 10
R5
L0_CTLOUT_L1
L0_CTLIN_L1
6090022100G_B@
6090022100G_B@
P4
H_CTLIN110
C9
1000P_0402_25V8J
C9
1000P_0402_25V8J
1
2
@
@
D1
1SS355_SOD323-2
D1
1SS355_SOD323-2
D2
BAS16_SOT23-3
D2
12
@
@
2
C183
C183
1A
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
+FAN1
12
@
@
1
10U_0805_10V4Z
10U_0805_10V4Z
U6
U6
C192
10U_0805_10V4Z
C192
10U_0805_10V4Z
1
2
BAS16_SOT23-3
5
GND8GND7GND6GND
EN1VIN2VOUT3VSET
4
EN_DFAN134
Security Classification
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
A
250 mil
C1
4.7U_0805_10V4Z
PUMA@C14.7U_0805_10V4Z
PUMA@
1
+1.2V_HT
2
< C1, C2 and C7 must be replaced to 10-uF for Caspian compatibility >
1 1
2 2
< From EC >
3 3
4 4
0.1
0.1
0.1
DDR_A_D[63..0] 9
< From/To SO_DIMMA >
E
DDR_A_D12
DDR_A_D11
DDR_A_D4
DDR_A_D5
DDR_A_D6
C13
H12
H11
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
E11
D12
G11
DDR_B_D5
DDR_B_D4
DDR_B_D6
DDR_A_D9
DDR_A_D8
DDR_A_D7
E15
H15
E13
MA_DATA9
MA_DATA8
MA_DATA7
MB_DATA9
MB_DATA8
MB_DATA7
A16
A15
A13
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_A_D10
E14
H17
E17
MA_DATA11
MA_DATA10
MB_DATA11
MB_DATA10
A20
A19
C14
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_A_D3
DDR_A_D0
DDR_A_D1
DDR_A_D2
G14
H14
F12
G12
MA_DATA2
MA_DATA1
MA_DATA0
MEM:DATA
MEM:DATA
MB_DATA2
MB_DATA1
MB_DATA0
JCPUC
JCPUC
B14
A14
A11
< Processor DDR2 Memory Interface >
D
C11
DDR_B_D0
DDR_B_D3
DDR_B_D1
DDR_B_D2
DDR_B_D[63..0]8
< From/To SO_DIMMB >
DDR_A_D13
DDR_A_D15
DDR_A_D14
DDR_A_D16
G17
C17
F14
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
D18
C18
D14
DDR_B_D16
DDR_B_D14
DDR_B_D15
DDR_B_D13
DDR_A_D19
DDR_A_D17
DDR_A_D18
E20
D22
C19
G18
MA_DATA18
MA_DATA17
MA_DATA16
MB_DATA18
MB_DATA17
MB_DATA16
A21
C25
D24
D20
DDR_B_D19
DDR_B_D17
DDR_B_D18
DDR_A_D20
DDR_A_D23
DDR_A_D22
DDR_A_D21
C23
B22
F18
E18
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
B24
B20
C24
C20
DDR_B_D22
DDR_B_D20
DDR_B_D21
DDR_B_D23
DDR_A_D24
DDR_A_D26
DDR_A_D25
DDR_A_D27
H24
F22
F20
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
E24
E23
G25
DDR_B_D26
DDR_B_D27
DDR_B_D24
DDR_B_D25
DDR_A_D29
DDR_A_D28
DDR_A_D30
H20
E22
E21
J19
MA_DATA29
MA_DATA28
MA_DATA27
MB_DATA29
MB_DATA28
MB_DATA27
D26
C26
G23
G26
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_A_D34
DDR_A_D33
DDR_A_D31
DDR_A_D32
AB24
Y24
H22
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
G24
AA23
AA24
DDR_B_D32
DDR_B_D33
DDR_B_D31
DDR_B_D34
DDR_A_D36
DDR_A_D37
DDR_A_D35
W21
W22
AA21
AB22
MA_DATA36
MA_DATA35
MA_DATA34
MB_DATA36
MB_DATA35
MB_DATA34
AA25
AA26
AE24
AD24
DDR_B_D35
DDR_B_D37
DDR_B_D36
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D41
AA20
Y20
AA22
Y22
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
AE25
AD22
AC22
AD26
DDR_B_D41
DDR_B_D38
DDR_B_D40
DDR_B_D39
DDR_A_D43
DDR_A_D42
DDR_A_D44
DDR_A_D45
AB21
AB18
AA18
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
AF24
AF20
AE20
DDR_B_D44
DDR_B_D45
DDR_B_D42
DDR_B_D43
DDR_A_D47
DDR_A_D46
DDR_A_D48
Y18
AD19
AD21
MA_DATA47
MA_DATA46
MA_DATA45
MB_DATA47
MB_DATA46
MB_DATA45
AF23
AD20
AC20
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_A_D51
DDR_A_D50
DDR_A_D49
Y14
W14
W16
AD17
MA_DATA50
MA_DATA49
MA_DATA48
MB_DATA50
MB_DATA49
MB_DATA48
AE18
AD14
AC14
AD18
DDR_B_D50
DDR_B_D51
DDR_B_D49
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D52
AB15
AB17
Y17
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
AF16
AF19
AC18
DDR_B_D52
DDR_B_D53
DDR_B_D55
DDR_B_D54
DDR_A_D56
DDR_A_D57
DDR_A_D58
Y12
AD13
AB13
AD15
MA_DATA57
MA_DATA56
MA_DATA55
MB_DATA57
MB_DATA56
MB_DATA55
AF13
AF15
AB11
AC12
DDR_B_D56
DDR_B_D58
DDR_B_D57
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
AA14
AB14
W11
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
Y11
AF14
AE14
DDR_B_D59
DDR_B_D62
DDR_B_D60
DDR_B_D61
DDR_A_D63
DDR_A_DM0
AA12
AB12
E12
MA_DATA63
MA_DATA62
MB_DATA63
MB_DATA62
A12
AF11
AD11
DDR_B_D63
DDR_B_DM0
DDR_B_DM[7..0]8 DDR_A_DM[7..0] 9
MA_DM0
MB_DM0
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM7
Y13
AB16
Y19
AC24
F24
E19
C15
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
E25
A22
B16
AE22
AB26
AD12
AC16
DDR_B_DM6
DDR_B_DM4
DDR_B_DM2
DDR_B_DM5
DDR_B_DM3
DDR_B_DM1
DDR_B_DM7
< To SO_DIMMB > < To SO_DIMMA >
DDR_A_DQS0 9
DDR_A_DQS#0 9
DDR_A_DQS1 9
DDR_A_DQS#1 9
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS2
DDR_A_DQS1
DDR_A_DQS#1
C22
G16
G15
G13
H13
MA_DQS_L1
MA_DQS_L0
MA_DQS_H1
MA_DQS_H0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
A24
B12
D16
C16
C12
DDR_B_DQS2
DDR_B_DQS1
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS#0
DDR_B_DQS18
DDR_B_DQS08
DDR_B_DQS#18
DDR_B_DQS#08
DDR_A_DQS2 9
DDR_A_DQS#2 9
DDR_A_DQS3 9
DDR_A_DQS#3 9
DDR_A_DQS4 9
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS#2
DDR_A_DQS4
AD23
G22
G21
C21
MA_DQS_L3
MA_DQS_L2
MA_DQS_H4
MA_DQS_H3
MA_DQS_H2
MB_DQS_H4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
F26
E26
A23
AC25
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS48
DDR_B_DQS38
DDR_B_DQS28
DDR_B_DQS#38
DDR_B_DQS#28
DDR_A_DQS#4 9
DDR_A_DQS5 9
DDR_A_DQS#5 9
DDR_A_DQS6 9
DDR_A_DQS#6 9
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
Y15
W15
AB19
AB20
AC23
MA_DQS_L6
MA_DQS_L5
MA_DQS_L4
MA_DQS_H6
MA_DQS_H5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_L4
AF21
AF22
AE16
AD16
AC26
DDR_B_DQS6
DDR_B_DQS5
DDR_B_DQS#6
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS68
DDR_B_DQS58
DDR_B_DQS#68
DDR_B_DQS#58
DDR_B_DQS#48
DDR_A_DQS7 9
DDR_A_DQS#7 9
DDR_A_DQS#7
DDR_A_DQS7
W12
W13
MA_DQS_L7
MA_DQS_H7
MB_DQS_H7
MB_DQS_L7
6090022100G_B@
6090022100G_B@
AF12
AE12
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS78
DDR_B_DQS#78
< From/To SO_DIMMB > < From/To SO_DIMMA >
5 45Wednesday, February 25, 2009
5 45Wednesday, February 25, 2009
5 45Wednesday, February 25, 2009
E
LA-4971P
LA-4971P
LA-4971P
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
C
C14
1.5P_0402_50V9C
C14
1.5P_0402_50V9C
1
B
DDR_B_CLK0
C10
1.5P_0402_50V9C
C10
1.5P_0402_50V9C
1
DDR_A_CLK0
< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH >
2
DDR_B_CLK#0
2
DDR_A_CLK#0
C15
1.5P_0402_50V9C
C15
1.5P_0402_50V9C
1
DDR_B_CLK1
C11
1.5P_0402_50V9C
C11
1.5P_0402_50V9C
1
DDR_A_CLK1
2
DDR_B_CLK#1
2
DDR_A_CLK#1
< VTT regulator voltage >
+0.9V+0.9V
W10
AC10
AB10
AA10
VTT5
VTT6
VTT7
VTT8
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
VTT1
VTT2
VTT3
VTT4
JCPUB
JCPUB
B10
D10
C10
AD10
A10
Y10
VTT9
MEMZP
AF10
AE10
MEM_P
MEM_N VTT_SENSE
T1PAD T1PAD
+MCH_REF
W17
MEMVREF
VTT_SENSE
MEMZN
RSVD_M1
H16
< To SO_DIMMB >
T3PAD T3PAD
DDR_B_ODT0 8
DDR_B_ODT1 8
DDR_B_ODT0
DDR_B_ODT1
Y26
W23
W26
B18
RSVD_M2
MB0_ODT1
MB0_ODT0
MA1_ODT1
MA1_ODT0
MA0_ODT1
MA0_ODT0
T19
V19
V22
U21
DDR_A_ODT1
DDR_A_ODT0
< To SO_DIMMB >
DDR_CS1_DIMMB# 8
DDR_CKE0_DIMMB 8
DDR_CKE0_DIMMB
DDR_CS1_DIMMB#
U22
W25
V26
J25
MB_CKE0
MB1_ODT0
MB1_CS_L0
MB0_CS_L1
MB0_CS_L0
MA0_CS_L1
MA1_CS_L1
MA1_CS_L0
MA0_CS_L0
MA_CKE0
J22
T20
V20
U19
U20
DDR_CKE0_DIMMA
DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CS0_DIMMA#
< To SO_DIMMB >
< To SO_DIMMB >
DDR_CKE1_DIMMB 8
DDR_B_CLK0 8
DDR_B_CLK#0 8
DDR_B_CLK1 8
DDR_CKE1_DIMMB
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CLK#1DDR_A_CLK#1
AF18
AF17
A17
A18
P22
R22
H26
MB_CKE1
MB_CLK_L1
MB_CLK_L0
MB_CLK_H2
MB_CLK_H1
MB_CLK_H0
MA_CLK_H2
MA_CLK_H1
MA_CLK_L1
MA_CLK_H0
MA_CLK_L0
MA_CKE1
J20
Y16
F16
E16
N19
N20
AA16
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK1
DDR_CKE1_DIMMA
< To SO_DIMMB >
DDR_B_CLK#1 8
DDR_B_MA[15..0] 8
DDR_B_MA1
DDR_B_MA0
R26
R25
N24
P24
MB_ADD0
MB_CLK_L3
MB_CLK_L2
MB_CLK_H3
MA_ADD0
MA_CLK_H3
MA_CLK_L3
MA_CLK_L2
P19
P20
N21
M20
DDR_A_MA1
DDR_A_MA0
DDR_B_MA3
DDR_B_MA2
DDR_B_MA4
N26
N23
P26
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
N22
M22
M19
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA8
M26
L24
N25
L23
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
L19
L21
L20
M24
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_B_MA10
DDR_B_MA12
DDR_B_MA11
DDR_B_MA9
L25
L26
T26
K26
MB_ADD9
MB_ADD12
MB_ADD11
MB_ADD10
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
L22
K20
K22
R21
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_B_MA15
DDR_B_MA13
DDR_B_BS#0
DDR_B_MA14
J24
J23
W24
MB_ADD15
MB_ADD14
MB_ADD13
MA_ADD15
MA_ADD14
MA_ADD13
K19
K24
V24
DDR_A_BS#0
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
< To SO_DIMMB >
< To SO_DIMMB >
DDR_B_BS#0 8
DDR_B_BS#1 8
DDR_B_BS#2 8
DDR_B_RAS# 8
DDR_B_CAS# 8
DDR_B_WE# 8
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_BS#1
DDR_B_BS#2
J26
U26
R24
U25
U24
U23
MB_WE_L
MB_RAS_L
MB_CAS_L
MB_BANK2
MB_BANK1
MB_BANK0
MA_BANK2
MA_BANK1
MA_BANK0
MA_RAS_L
MA_CAS_L
MA_WE_L
J21
T22
T24
R23
R20
R19
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS#2
DDR_A_BS#1
@ 6090022100G_B
@ 6090022100G_B
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
A
< DDR2 VREF is 0.5 ratio >
R1
R1
+1.8V
+MCH_REF
1K_0402_1%
1K_0402_1%
1 2
C13
1000P_0402_25V8J
C13
1000P_0402_25V8J
1
2
C12
0.1U_0402_16V7K
C12
0.1U_0402_16V7K
1
2
R2
1K_0402_1%
R2
1K_0402_1%
1 1
T2 PADT2 PAD
1 2
1 2
R4 39.2_0402_1%R4 39.2_0402_1%
R3 39.2_0402_1%R3 39.2_0402_1%
Place them close to CPU within 1"
+1.8V
1 2
2 2
DDR_CS0_DIMMA#9
DDR_CS1_DIMMA#9 DDR_CS0_DIMMB# 8
DDR_A_ODT09
DDR_A_ODT19
< To SO_DIMMA >
< To SO_DIMMA >
DDR_CKE0_DIMMA9
DDR_CKE1_DIMMA9
DDR_A_CLK09
DDR_A_CLK#09
DDR_A_CLK19
< To SO_DIMMA >
< To SO_DIMMA >
DDR_A_MA[15..0]9
DDR_A_CLK#19
< To SO_DIMMA >
DDR_A_RAS#9
DDR_A_CAS#9
DDR_A_WE#9
DDR_A_BS#09
DDR_A_BS#19
DDR_A_BS#29
< To SO_DIMMA >
< To SO_DIMMA >
3 3
4 4
A
E
W18
M11
D
KEY2
KEY1
JCPUD
JCPUD
VDDA1F8VDDA2F9RESET_LB7PWROKA7LDTSTOP_L
< Serial VID Interface clock & data >
< Thermal Sensor Trip output >
< HTC-active state indication or command >
CPU_SVD 43
CPU_SVC 43
CPU_SVC
SVCA6SVD
CLKIN_HA9CLKIN_L
CPU_SVD
A4
A8
+1.8V
R42
300_0402_5%
R42
300_0402_5%
12
CPU_THERMTRIP#_R
THERMDC_CPU
CPU_PROCHOT#_1.8
AF6
AC7
W7
AA8
THERMDC
MEMHOT_L
PROCHOT_L
THERMTRIP_L
SIC
SID
LDTREQ_L
ALERT_L
C6
F10
AF4
AF5
AE6
< Thermal diode cathode & anode >
< Debug request >
< Differential feedback for VDDIO >
< VDDIO : DDR SDRAM I/O ring power supply>
< Differential feedback for VDDNB >
< Northbridge power supply >
T21PAD T21PAD
T22PAD T22PAD
CPU_VDDNB_RUN_FB_H 43
CPU_VDDNB_RUN_FB_L 43
+1.8V sense no support
THERMDA_CPU
W9
W8
THERMDA
HT_REF1
HT_REF0R6VDD0_FB_HF6VDD0_FB_L
P6
CPU_DBREQ#
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
Y9
E10
H6
G6
VDDIO_FB_L
VDDIO_FB_H
VDDNB_FB_L
VDDNB_FB_H
DBRDY
VDD1_FB_HY6VDD1_FB_L
E6
G10
AA9
AB6
DBREQ_L
TMS
route as differential
as short as possible
testpoint under package
T6PAD T6PAD
T5PAD T5PAD
T20PAD T20PAD
CPU_TEST17_BP3
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST28_H_PLLCHRZ_P
AE9
J7
H8
TDO
TEST28_L
TEST28_H
TCK
TRST_L
TDI
TEST23
AF9
H10
AC9
AD9
AD7
+1.2V_HT
T7PAD T7PAD
T8PAD T8PAD
R32
300_0402_5%
300_0402_5%
@R32
@
12
CPU_TEST16_BP2
CPU_TEST10_ANALOGOUT
C7
C3
K8
TEST7
TEST17D7TEST16E7TEST15F7TEST14
TEST25_HE9TEST25_L
TEST19G9TEST18
TEST21
E8
AF7
AB8
T14PAD T14PAD
T13PAD T13PAD
Add R32 at PVT
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST29_H_FBCLKOUT_P
C9
C8
C4
TEST8
TEST10
TEST29_L
TEST29_H
TEST9
TEST12
TEST6
TEST24
TEST22
TEST20
TEST27
C2
AF8
AA6
AE7
AE8
AC8
H18
H19
RSVD10
RSVD1
A5
A3
AA7
D5
RSVD8
RSVD7
RSVD9
RSVD2
RSVD4
RSVD3B3RSVD5
B5
C5
RSVD6
C1
0.1
0.1
0.1
LDT_RST#
EC_SMB_DA2 19,34,35
246
8
10121416182022
JP3
JP3
< HDT Connector >
R494
0_0402_5%@
R494
0_0402_5%@
1 2
2423
26
21191715131197531
+1.8V
EC_SMB_CK2 19,34,35
< From EC >
SAMTEC_ASP-68200-07
@ SAMTEC_ASP-68200-07
@
EC_SMB_CK2
EC_SMB_DA2
6
5
8
7
GND
Compal Electronics, Inc.
Compal Electronics, Inc.
SCLK
SDATA
ALERT#
VDD
D+2D-
< Thermal Sensor >
U2
U2
1
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
3
Compal Electronics, Inc.
THERM#
ADM1032ARM-1 ZREEL_MSOP8
ADM1032ARM-1 ZREEL_MSOP8
4
6 45Wednesday, February 25, 2009
6 45Wednesday, February 25, 2009
6 45Wednesday, February 25, 2009
E
LA-4971P
LA-4971P
LA-4971P
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
< R494 Close to CPU >
THERMDA_CPU
+3VS
THERMDC_CPU
C27
C27
1 2
1
C26
C26
0.1U_0402_16V7K
0.1U_0402_16V7K
2200P_0402_50V7K
2200P_0402_50V7K
< noise filter cap >
2
D
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
1 2
1 2
1 2
1 2
R40 220_0402_5%@ R40 220_0402_5%@
R39 220_0402_5%@ R39 220_0402_5%@
R37 220_0402_5%@ R37 220_0402_5%@
R38 220_0402_5%@ R38 220_0402_5%@
1 2
R41 300_0402_5%R41 300_0402_5%
CPU_DBREQ#
< R41 Close to CPU >
+1.8V
+1.8V
T23 PADT23 PAD
T24 PADT24 PAD
6090022100G_B@
6090022100G_B@
+1.8V
LDT_STOP#
CPU_LDT_REQ_R#
H_PWRGD
LDT_RST#
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
+2.5VDDA
C
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
Close to CPU
R485
10_0402_5%
R485
10_0402_5%
R484
10_0402_5%
R484
10_0402_5%
12
12
B
< Differential feedback for VDDNB >
+VDDNB
CPU_VDD0_RUN_FB_L
CPU_VDD0_RUN_FB_H
R487
10_0402_5%
R487
10_0402_5%
R486
10_0402_5%
R486
10_0402_5%
A
< Close to CPU >
1 2
1 2
+CPU_CORE_0
CPU_HTREF0
CPU_HTREF1
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L
T10 PADT10 PAD
T9 PADT9 PAD
T11 PADT11 PAD
CPU_VDD0_RUN_FB_H43
CPU_VDD0_RUN_FB_L43
CPU_VDD1_RUN_FB_H43
CPU_VDD1_RUN_FB_L43
< JTAG debug port >
1 2
1 2
R13 44.2_0402_1%R13 44.2_0402_1%
R14 44.2_0402_1%R14 44.2_0402_1%
+1.2V_HT
< Sideband-Temperature Sensor Interface Clock & Data>
< Sideband-Temperature Sensor Interface interrupt >
< Compensation Resistor to VLDT >
< Compensation Resistor to VSS >
CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L
Un-Mount R489 For Caspian
R488
10_0402_5%PUMA@
R488
10_0402_5%PUMA@
R489
10_0402_5%PUMA@
R489
10_0402_5%PUMA@
1 2
1 2
+CPU_CORE_1
1 1
< Debug ready >
CPU_CLKIN_SC_P
Change R488 to 10K For Caspian
C20
3900P_0402_50V7K
C20
3900P_0402_50V7K
1 2
< 200-MHz PLL Reference Clock >
CPU_TEST23_TSTUPD
T12 PADT12 PAD
T19 PADT19 PAD
R8
169_0402_1%
R8
169_0402_1%
12
CLK_CPU_BCLK15
R25
0_0402_5%
R25
0_0402_5%
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1
CPU_TEST20_SCANCLK2
1 2
+2.5VDDA
C19
0.22U_0603_16V4Z
C19
+2.5VDDA+2.5VS
VDDA=300mA
0.22U_0603_16V4Z
1
2
C18
3300P_0402_50V7K
C18
3300P_0402_50V7K
1
2
C17
4.7U_0805_10V4Z
C17
4.7U_0805_10V4Z
1
2
CPU_CLKIN_SC_N
C21
3900P_0402_50V7K
C21
3900P_0402_50V7K
1 2
Address:100_1100 Place close to CPU wihtin 1.5"
1 2
CLK_CPU_BCLK#15
L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805
C16
100U_D2_10VM
C16
100U_D2_10VM
+
+
1
< Filtered PLL Supply Voltage >
2 2
2
@
@
R500
510_0402_5%TIGRIS@
R500
510_0402_5%TIGRIS@
R498
510_0402_5%@
R498
510_0402_5%@
1 2
1 2
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST25_H_BYPASSCLK_H
R499
510_0402_5%@
R499
510_0402_5%@
R497
510_0402_5%TIGRIS@
R497
510_0402_5%TIGRIS@
1 2
1 2
Add R497 and R498 at PVT
CPU_SVC
CPU_SVD
0718 AMD --> 1K ohm
R23
1K_0402_5%
R23
1K_0402_5%
R22
1K_0402_5%
R22
1K_0402_5%
12
12
+1.8VS
< Serial VID Interface clock & data >
ENTRIP2 38,40
< To power circuitry>
D12
CH751H-40PT_SOD323-2
D12
CH751H-40PT_SOD323-2
21
R10
10K_0402_5%
R10
10K_0402_5%
1 2
+1.8V
R15
R15
+1.8VS
3 3
H_THERMTRIP# 21
< To SB700 ACPI block>
D16
CH751H-40PT_SOD323-2
D16
CH751H-40PT_SOD323-2
21
C
C
Q3
Q3
2
B
B
E
E
3 1
R5
300_0402_5%
R5
300_0402_5%
1 2
CPU_THERMTRIP#_R
LDT_RST#
C22
C22
300_0402_5%
300_0402_5%
1
1 2
LDT_RST#20
< To SB700 CPU block>
R11
@ R11
@
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
R9
300_0402_5%
R9
300_0402_5%
1 2
+1.8V
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+1.8VS +1.8VS
@
@
H_PROCHOT# 20
0_0402_5%
0_0402_5%
1 2
CPU_PROCHOT#_1.8
C25
C25
R36
300_0402_5%
R36
300_0402_5%
1
1 2
LDT_STOP#11,20
H_PWRGD LDT_STOP#
C23
C23
R21
300_0402_5%
R21
300_0402_5%
1
1 2
H_PWRGD20,43
CPU_TEST21_SCANEN
CPU_TEST23_TSTUPD
CPU_TEST20_SCANCLK2
R31
300_0402_5%
TIGRIS@
R31
300_0402_5%
TIGRIS@
R29
300_0402_5%
TIGRIS@
R29
300_0402_5%
TIGRIS@
R26
300_0402_5%
R26
4 4
1 2
PUMA@
PUMA@
R30
R30
300_0402_5%
300_0402_5%
300_0402_5%
12
CPU_LDT_REQ_R#
R27
0_0402_5%
R27
0_0402_5%
1 2
1
1 2
CPU_LDT_REQ#
CPU_LDT_REQ#11,20
12
Add R29 and R31 at PVT
0.01U_0402_25V7K
0.01U_0402_25V7K
2
@
@
+1.8VS
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CPU_TEST24_SCANCLK1
R28
300_0402_5%
R28
300_0402_5%
B
1 2
Un-Mount R27 For Caspian
@
@
2
C24
C24
A
0.01U_0402_25V7K
0.01U_0402_25V7K
0.1
0.1
0.1
7 45Wednesday, February 25, 2009
7 45Wednesday, February 25, 2009
7 45Wednesday, February 25, 2009
E
+CPU_CORE_1
JCPUE
JCPUE
D
+CPU_CORE_0
C
P10
R11
VDD1_1P8VDD1_2
VDD1_3R4VDD1_4R7VDD1_5R9VDD1_6
VDD0_1G4VDD0_2H2VDD0_3J9VDD0_4
VDD0_5
J11
J13
J15
T8
VDD1_7T2VDD1_8T6VDD1_9
VDD0_7K6VDD0_8
VDD0_6
K10
K12
C42
180P_0402_50V8J
C42
180P_0402_50V8J
1
T10
T12
T14
VDD1_10
VDD1_11
VDD0_9
VDD0_10
VDD0_11L4VDD0_12L7VDD0_13L9VDD0_14
K14
2
U11
VDD1_12
VDD1_13U7VDD1_14U9VDD1_15
VDD0_15
L11
L13
U13
U15
VDD1_16
VDD1_18V6VDD1_19V8VDD1_20
VDD1_17
VDD0_17M2VDD0_18M6VDD0_19M8VDD0_20
VDD0_16
L15
1
V10
V12
V14
VDD1_21
VDD1_22
VDD1_23W4VDD1_24
VDD0_21N7VDD0_22N9VDD0_23
N11
M10
+VDDNB
C45
180P_0402_50V8J
C45
180P_0402_50V8J
2
AC4
Y2
K16
+1.8V
AD2
VDD1_25
VDD1_26
VDDNB_1
VDDNB_2
VDDNB_3
P16
M16
V25
Y25
VDDIO26
VDDIO27
VDDNB_4
VDDNB_5
T16
V16
+1.8V
V21
V23
VDDIO24
VDDIO25
VDDIO1
H25
U17
V18
VDDIO22
VDDIO23
VDDIO2
VDDIO3
J17
K18
T23
T25
VDDIO20
VDDIO21
VDDIO4
VDDIO5
K21
K23
T18
T21
VDDIO18
VDDIO19
VDDIO6
VDDIO7
L17
K25
P25
R17
VDDIO16
VDDIO17
VDDIO8
VDDIO9
M18
M21
P18
P21
P23
VSS66J6VSS67J8VSS68
Athlon 64 S1 Processor Socket
VDDIO13
VDDIO14
VDDIO15
VDDIO10
VDDIO11
VDDIO12
N17
M23
M25
VSS1
6090022100G_B@
6090022100G_B@
JCPUF
JCPUF
AA4
AA11
VSS2
J10
VSS3
AA13
J12
VSS69
VSS4
AA15
J14
VSS70
VSS5
AA17
J16
VSS71
VSS6
AA19
J18
VSS72
VSS7
AB2
K11
VSS73K2VSS74K7VSS75K9VSS76
VSS8
VSS9
VSS10
VSS11
AB7
AB9
AB23
AB25
K13
VSS77
VSS12
AC11
K15
VSS78
VSS13
AC13
K17
VSS79
VSS80L6VSS81L8VSS82
VSS14
VSS15
AC15
AC17
VSS16
AC19
L10
VSS17
AC21
L12
VSS83
VSS18
AD6
L14
VSS84
VSS19
AD8
L16
VSS85
VSS20
AD25
L18
VSS86
VSS87M7VSS88M9VSS89
VSS21
VSS22
AE11
AE13
VSS23
AE15
AC6
VSS24
AE17
M17
VSS90
VSS25
AE19
AE21
VSS91N4VSS92N8VSS93
VSS26
N10
N16
N18
VSS94
VSS95
VSS27
VSS28B4VSS29B6VSS30B8VSS31B9VSS32
AE23
P11
P17
VSS96P2VSS97P7VSS98P9VSS99
VSS100
VSS33
VSS34
VSS35
B11
B13
B15
B17
R10
R16
VSS101R8VSS102
VSS103
VSS36
VSS37
VSS38
B19
B21
B23
R18
VSS104
VSS105T7VSS106T9VSS107
VSS39
VSS40D6VSS41D8VSS42D9VSS43
B25
T11
T13
T15
VSS108
D11
D13
T17
VSS109
VSS110
VSS44
VSS45
D15
D17
U10
U12
U14
U16
VSS111U4VSS112U6VSS113U8VSS114
VSS115
VSS116
VSS117
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51E4VSS52F2VSS53
D19
D21
D23
D25
1. Near Power Supply
2. Change to B2 size
C59
C59
+
+
1
+0.9V
U18
V11
V13
V15
V17
VSS118
VSS119V2VSS120V7VSS121V9VSS122
VSS123
VSS124
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
F11
F13
F15
F17
F19
F21
F23
F25
220U_B2_4VM_R45M
220U_B2_4VM_R45M
2
Y21
VSS125
VSS126W6VSS127
VSS60
VSS61H7VSS62H9VSS63
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
Y23
VSS128
H21
N6
H23
Title
Title
Title
VSS129
Athlon 64 S1 Processor Socket
VSS64
VSS65
6090022100G_B@
6090022100G_B@
J4
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
LA-4971P
LA-4971P
LA-4971P
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
E
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
C
C41
0.01U_0402_25V7K
C41
0.01U_0402_25V7K
1
2
C40
0.22U_0603_16V4Z
C40
0.22U_0603_16V4Z
1
2
C35
22U_0805_6.3V6M
C35
22U_0805_6.3V6M
1
2
B
C34
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
1
2
C33
22U_0805_6.3V6M
C33
22U_0805_6.3V6M
1
2
C32
22U_0805_6.3V6M
C32
22U_0805_6.3V6M
1
2
Under CPU Socket Under CPU Socket
+CPU_CORE_0 +CPU_CORE_0
330U_X_2VM_R6M
330U_X_2VM_R6M
C28
A
C28
+
+
1
2
C44
0.01U_0402_25V7K
C44
0.01U_0402_25V7K
1
2
C43
0.22U_0603_16V4Z
C43
0.22U_0603_16V4Z
1
2
C39
22U_0805_6.3V6M
C39
22U_0805_6.3V6M
1
2
C38
22U_0805_6.3V6M
C38
22U_0805_6.3V6M
1
2
C37
22U_0805_6.3V6M
C37
22U_0805_6.3V6M
1
2
C36
22U_0805_6.3V6M
C36
22U_0805_6.3V6M
1
2
C29
C29
+
+
1
Under CPU Socket Under CPU Socket
330U_X_2VM_R6M
330U_X_2VM_R6M
2
C51
180P_0402_50V8J
C51
180P_0402_50V8J
1
2
C50
180P_0402_50V8J
C50
180P_0402_50V8J
1
2
C49
0.22U_0603_16V4Z
C49
0.22U_0603_16V4Z
1
2
C48
0.22U_0603_16V4Z
C48
0.22U_0603_16V4Z
1
2
C47
22U_0805_6.3V6M
C47
22U_0805_6.3V6M
1
2
C58
0.22U_0603_16V4Z
C58
0.22U_0603_16V4Z
1
2
C57
0.22U_0603_16V4Z
C57
0.22U_0603_16V4Z
1
2
C56
0.22U_0603_16V4Z
C56
0.22U_0603_16V4Z
1
2
C61
0.01U_0402_25V7K
C61
0.01U_0402_25V7K
1
2
C65
180P_0402_50V8J
C65
180P_0402_50V8J
1
C64
180P_0402_50V8J
C64
180P_0402_50V8J
1
C63
180P_0402_50V8J
C63
180P_0402_50V8J
1
2
2
2
C78
220U_B2_4VM_R45M
C78
220U_B2_4VM_R45M
+
+
1
2
@
@
Change to B2 size
C77
4.7U_0805_10V4Z
C77
4.7U_0805_10V4Z
1
2
C76
4.7U_0805_10V4Z
C76
4.7U_0805_10V4Z
1
2
C75
4.7U_0805_10V4Z
C75
4.7U_0805_10V4Z
1
2
C73
180P_0402_50V8J
C73
180P_0402_50V8J
1
2
C72
180P_0402_50V8J
C72
180P_0402_50V8J
1
2
C71
1000P_0402_25V8J
C71
1000P_0402_25V8J
1
2
C70
1000P_0402_25V8J
C70
1000P_0402_25V8J
1
2
C69
0.22U_0603_16V4Z
C69
0.22U_0603_16V4Z
1
2
C68
0.22U_0603_16V4Z
C68
0.22U_0603_16V4Z
1
2
C67
4.7U_0805_10V4Z
C67
4.7U_0805_10V4Z
1
2
C86
180P_0402_50V8J
C86
180P_0402_50V8J
1
2
C85
180P_0402_50V8J
C85
180P_0402_50V8J
1
2
C84
1000P_0402_25V8J
C84
1000P_0402_25V8J
1
2
C83
1000P_0402_25V8J
C83
1000P_0402_25V8J
1
2
C82
0.22U_0603_16V4Z
C82
0.22U_0603_16V4Z
1
2
C81
0.22U_0603_16V4Z
C81
0.22U_0603_16V4Z
1
2
C80
4.7U_0805_10V4Z
C80
4.7U_0805_10V4Z
1
2
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
TIGRIS@
TIGRIS@
1
1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
C54
22U_0805_6.3V6M
C54
22U_0805_6.3V6M
2
A
C53
22U_0805_6.3V6M
C53
22U_0805_6.3V6M
2
330U_X_2VM_R6M
330U_X_2VM_R6M
C30
C30
+
+
1
2
VDD decoupling : +CPU_CORE
+CPU_CORE_0
Near CPU Socket
1 1
1
+CPU_CORE_1 +CPU_CORE_1 +CPU_CORE_1
C31
C31
+
+
330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
C46
22U_0805_6.3V6M
C46
22U_0805_6.3V6M
1
+1.8V
2
Under CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power
+1.8V
C55
0.22U_0603_16V4Z
C55
0.22U_0603_16V4Z
1
2
Between CPU Socket and DIMM
2 2
+1.8V
C60
0.01U_0402_25V7K
C60
0.01U_0402_25V7K
1
2
Between CPU Socket and DIMM
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
C62
180P_0402_50V8J
C62
+1.8V
180P_0402_50V8J
1
2
Between CPU Socket and DIMM
+1.8V
3 3
C74
4.7U_0805_10V4Z
C74
4.7U_0805_10V4Z
1
2
VTT decoupling.
Between CPU Socket and DIMM
+0.9V
C66
4.7U_0805_10V4Z
C66
4.7U_0805_10V4Z
1
2
Near CPU Socket Right side
+0.9V
C79
4.7U_0805_10V4Z
C79
4.7U_0805_10V4Z
1
2
Near CPU Socket Left side
C52
22U_0805_6.3V6M
C52
22U_0805_6.3V6M
+VDDNB
1
2
+VDDNB decoupling : Northbridge power
4 4
0.1
0.1
0.1
8 45Wednesday, February 25, 2009
8 45Wednesday, February 25, 2009
8 45Wednesday, February 25, 2009
E
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDR_B_DQS#[0..7] 5
DDR_B_MA[0..15] 5
DDR_B_DQS[0..7] 5
DDR_B_D[0..63] 5
DDR_B_DM[0..7] 5
+1.8V
12
12
12
C105 0.1U_0402_16V7KC105 0.1U_0402_16V7K
C106 0.1U_0402_16V7KC106 0.1U_0402_16V7K
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_B_MA0
DDR_B_RAS#
C108 0.1U_0402_16V7KC108 0.1U_0402_16V7K
RP9
RP9
1 8
2 7
DDR_B_MA14
DDR_B_MA11
D
+0.9V
RP8
RP8
DDR_B_MA4
1 8
2 7
DDR_B_MA2
12
C107 0.1U_0402_16V7KC107 0.1U_0402_16V7K
RP10
RP10
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_B_MA7
DDR_B_MA6
12
12
C109 0.1U_0402_16V7KC109 0.1U_0402_16V7K
C110 0.1U_0402_16V7KC110 0.1U_0402_16V7K
182736
45
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_BS#2
12
12
C111 0.1U_0402_16V7KC111 0.1U_0402_16V7K
C112 0.1U_0402_16V7KC112 0.1U_0402_16V7K
182736
45
RP11
RP11
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
DDR_B_MA3
12
12
C113 0.1U_0402_16V7KC113 0.1U_0402_16V7K
C114 0.1U_0402_16V7KC114 0.1U_0402_16V7K
182736
45
RP12
RP12
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_B_MA10
DDR_B_BS#0
DDR_B_MA5
DDR_B_MA1
12
12
C116 0.1U_0402_16V7KC116 0.1U_0402_16V7K
C115 0.1U_0402_16V7KC115 0.1U_0402_16V7K
182736
45
RP13
RP13
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_B_WE#
DDR_B_CAS#
DDR_B_ODT1
DDR_CS1_DIMMB#
12
12
C117 0.1U_0402_16V7KC117 0.1U_0402_16V7K
C118 0.1U_0402_16V7KC118 0.1U_0402_16V7K
RP14
RP14
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_B_BS#1
DDR_CS0_DIMMB#
DDR_B_MA13
DDR_B_ODT0
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
Title
Title
Title
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
E
LA-4971P
LA-4971P
LA-4971P
DDRII SO-DIMM 0
DDRII SO-DIMM 0
DDRII SO-DIMM 0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
C
Security Classification
Security Classification
198
197
+3VS
200
SAO
SCL
199
202
SA1
VDDSPD
201
Security Classification
VSS
VSS
P-TWO_A5692B-A0G16-P@
P-TWO_A5692B-A0G16-P@
DDR_B_CLK1 5
154
153
156
DQ47
DQ43
155
VSS
VSS
DDR_B_D52
158
160
162
164
VSS
DQ52
DQ53
DQ48
DQ49
VSS
157
159
161
163
DDR_B_CLK#1 5
166
168
CK1
VSS
CK1#
NC,TEST
VSS
DQS6#
165
167
DDR_B_D54
DDR_B_DM6
170
172
174
176
VSS
DM6
DQ54
DQ55
DQS6
VSS
DQ50
DQ51
169
171
173
175
DDR_B_D61
DDR_B_D60
178
180
182
VSS
DQ60
DQ61
VSS
DQ56
DQ57
177
179
181
DDR_B_DQS7
DDR_B_DQS#7
184
186
188
190
VSS
VSS
DQS7
DQS7#
VSS
DM7
VSS
DQ58
183
185
187
189
DDR_B_D63
DDR_B_D62
192
194
196
VSS
DQ62
DQ63
DQ59
VSS
SDA
191
193
195
DDR_B_ODT0 5
DDR_B_RAS# 5
DDR_B_D30
DDR_B_DQS3
68
70
72
VSS
DQS3
DQS3#
DDR_CKE1_DIMMB 5
DDR_B_D31
DDR_CKE1_DIMMB
76
78
80
82
VSS
VDD
DQ3074DQ31
NC/CKE1
DDR_B_MA11
DDR_B_MA7
DDR_B_MA15
DDR_B_MA14
86
88
90A792A694
A11
VDD
NC/A1584NC/A14
DDR_B_CLK0 5
DDR_B_CLK#0 5
12
< EMI require >< EMI require >
C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K
+1.8V+1.8V
B
JDDRH
JDDRH
DDR_B_D6
DDR_B_D7
DDR_B_D5
DDR_B_D4
2
6
8
VSS
DQ44DQ5
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1
DDR_B_DM0
10
12
VSS
VSS
DQ614DQ7
DM0
16
18
VSS
DDR_B_D13
DDR_B_D12
22
DQ1220DQ13
DDR_B_DM1
24
26
28
30
VSS
VSS
DM1
32
CK0
CK0#
DDR_B_D14
DDR_B_D15
34
38
VSS
DQ1436DQ15
42
VSS40VSS
DDR_B_D20
DDR_B_D21
46
48NC50
VSS
DQ2044DQ21
DDR_B_D23
DDR_B_DM2
52
54
58
VSS
DM2
DQ2256DQ23
DDR_B_D29
DDR_B_D28
60
64
VSS
DQ2862DQ29
DDR_B_DQS#3
66
VSS
DDR_B_MA4
DDR_B_MA6DDR_B_MA8
DDR_B_MA2
96A498A2100A0102
VDD
DDR_B_BS#1 5
DDR_B_BS#1
DDR_B_MA0
DDR_B_RAS#
104
106
108
BA1
VDD
VDD
A10/AP
101
103
105
107
DDR_CS0_DIMMB# 5
DDR_B_MA13
DDR_CS0_DIMMB#
110
112
114
116
118NC120
S0#
VDD
VDD
RAS#
ODT0
NC/A13
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
109
111
113
115
117
119
DDR_B_D36
DDR_B_D37
122
124
126
VSS
DQ36
DQ37
VSS
DQ32
DQ33
121
123
125
DDR_B_D38
DDR_B_DM4
128
130
132
VSS
VSS
DM4
VSS
DQS4#
DQS4
127
129
131
DDR_B_D39
134
136
138
VSS
DQ38
DQ39
VSS
DQ34
DQ35
133
135
137
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
140
142
144
146
VSS
DQ44
DQ45
VSS
DQ40
DQ41
139
141
143
145
DDR_B_D46
DDR_B_DQS5
148
150
152
VSS
DQ46
DQS5
DQS5#
VSS
DM5
VSS
DQ42
147
149
151
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
DIMM0 STD H:9.2mm (Bot)
C1600.1U_0402_16V7K C1600.1U_0402_16V7K
C119
0.1U_0402_16V7K
C119
0.1U_0402_16V7K
1
1 2
DDR_B_D0
DDR_B_D1
DDR_B_D3
DDR_B_D2
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D8
DDR_B_D9
DDR_B_D11
DDR_B_D10
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_D18 DDR_B_D22
DDR_B_D19
DDR_B_DQS2
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_BS#0
DDR_B_MA10
DDR_B_WE#
DDR_B_CAS# DDR_B_ODT0
DDR_B_D33
DDR_B_D32
DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_D34
DDR_B_D35
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_D41
DDR_B_D40
DDR_B_DM5
DDR_B_D42
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_D51 DDR_B_D55
DDR_B_D50
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D59
DDR_B_D58
2
+3VS
SMB_CK_DAT09,15,21,27
C104
1000P_0402_25V8J
C104
1000P_0402_25V8J
1
2
A
+V_DDR_MCH_REF9
1 1
2 2
DDR_CKE0_DIMMB5
DDR_B_BS#25
DDR_B_BS#05
DDR_B_WE#5
DDR_B_CAS#5
DDR_CS1_DIMMB#5
DDR_B_ODT15
3 3
SMB_CK_CLK09,15,21,27
A
4 4
0.1
0.1
0.1
9 45Wednesday, February 25, 2009
9 45Wednesday, February 25, 2009
9 45Wednesday, February 25, 2009
E
+1.8V
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1 2
1 2
C88 0.1U_0402_16V7KC88 0.1U_0402_16V7K
C87 0.1U_0402_16V7KC87 0.1U_0402_16V7K
+0.9V
RP1
DDR_A_DQS[0..7] 5
DDR_A_D[0..63] 5
DDR_A_DM[0..7] 5
DDR_A_DQS#[0..7] 5
DDR_A_MA[0..15] 5
D
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
RP1
1 8
2 7
DDR_A_MA6
DDR_A_MA14
3 6
DDR_A_MA7
C90 0.1U_0402_16V7KC90 0.1U_0402_16V7K
RP2
RP2
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_MA11
DDR_CKE0_DIMMA
1 2
1 2
C89 0.1U_0402_16V7KC89 0.1U_0402_16V7K
182736
DDR_A_BS#2
DDR_CKE1_DIMMA
1 2
C91 0.1U_0402_16V7KC91 0.1U_0402_16V7K
45
RP3
RP3
1 8
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_MA15
DDR_A_BS#1
1 2
C92 0.1U_0402_16V7KC92 0.1U_0402_16V7K
2 7
3 6
DDR_A_MA0
DDR_A_MA2
1 2
C93 0.1U_0402_16V7KC93 0.1U_0402_16V7K
182736
RP4
RP4
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_MA5
DDR_A_MA4
1 2
C94 0.1U_0402_16V7KC94 0.1U_0402_16V7K
45
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
1 2
1 2
C97 0.1U_0402_16V7KC97 0.1U_0402_16V7K
C98 0.1U_0402_16V7KC98 0.1U_0402_16V7K
182736
45
RP5
RP5
DDR_A_BS#0
DDR_A_MA10
DDR_A_MA3
DDR_A_MA1
1 2
1 2
C99 0.1U_0402_16V7KC99 0.1U_0402_16V7K
C100 0.1U_0402_16V7KC100 0.1U_0402_16V7K
182736
45
RP6
RP6
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_WE#
1 2
1 2
C102 0.1U_0402_16V7KC102 0.1U_0402_16V7K
C101 0.1U_0402_16V7KC101 0.1U_0402_16V7K
RP7
RP7
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_MA13
DDR_A_ODT0
47_0804_8P4R_5%
47_0804_8P4R_5%
Title
Title
Title
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
E
LA-4971P
LA-4971P
LA-4971P
DDRII SO-DIMM 1
DDRII SO-DIMM 1
DDRII SO-DIMM 1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
C
12
DDR_A_CLK0 5
DDR_A_CLK#0 5
DDR_CKE1_DIMMA 5
DDR_CS0_DIMMA# 5
DDR_A_ODT0 5
DDR_A_RAS# 5
DDR_A_BS#1 5
< EMI require >< EMI require >
DDR_A_D4
DDR_A_D6
DDR_A_D7
DDR_A_D5
C161 0.1U_0402_16V7KC161 0.1U_0402_16V7K
+1.8V+1.8V
2
6
VSS
DQ44DQ5
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1
JDDRL
JDDRL
B
C1930.1U_0402_16V7K C1930.1U_0402_16V7K
1 2
DDR_A_D0
+V_DDR_MCH_REF
C95
1000P_0402_25V8J
C95
1000P_0402_25V8J
1
2
C96
0.1U_0402_16V7K
C96
0.1U_0402_16V7K
1
2
DDR_A_DM0
8
10
12
VSS
VSS
DM0
DDR_A_D1
DDR_A_DQS#0
DDR_A_D12
DDR_A_D13
16
18
VSS
DQ614DQ7
DQ1220DQ13
DDR_A_D3
DDR_A_D2
DDR_A_DQS0
22
DDR_A_DM1
24
26
28
VSS
VSS
DM1
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_D14
30
32
34
CK0
VSS
CK0#
DDR_A_D10
DDR_A_DQS1
DDR_A_D15
38
VSS40VSS
DQ1436DQ15
DDR_A_D11
DDR_A_D21
42
46
DQ2044DQ21
DDR_A_D16 DDR_A_D20
DDR_A_D17
48NC50
VSS
DDR_A_DQS#2
DDR_A_D23
DDR_A_D22
DDR_A_DM2
52
54
58
VSS
DM2
DQ2256DQ23
DDR_A_D19
DDR_A_D18
DDR_A_DQS2
DDR_A_D29
DDR_A_D28
60
64
VSS
DQ2862DQ29
DDR_A_D24
DDR_A_D25
66
DDR_A_D30
DDR_A_DQS3
DDR_A_DQS#3
68
70
72
VSS
VSS
DQ3074DQ31
DQS3
DQS3#
DDR_A_D26
DDR_A_DM3
DDR_CKE1_DIMMA
DDR_A_D31
DDR_A_MA15
76
78
80
82
VSS
VDD
NC/CKE1
DDR_CKE0_DIMMA
DDR_A_D27
DDR_CKE0_DIMMA5
DDR_A_MA11
DDR_A_MA14
DDR_A_MA7
86
88
90A792A694
A11
VDD
NC/A1584NC/A14
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_BS#25
DDR_A_MA6
DDR_A_MA8
DDR_A_MA4
DDR_A_MA2
96A498A2100A0102
VDD
DDR_A_MA1 DDR_A_MA0
DDR_A_MA3
DDR_A_MA5
DDR_A_BS#1
104
106
BA1
VDD
VDD
A10/AP
101
103
105
DDR_A_MA10
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_MA13
108
110
112
114
116
118NC120
S0#
VDD
RAS#
ODT0
NC/A13
BA0
WE#
VDD
CAS#
NC/S1#
107
109
111
113
115
117
DDR_CS1_DIMMA#
DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0
DDR_A_BS#0
DDR_A_BS#05
DDR_A_WE#5
DDR_A_CAS#5
DDR_CS1_DIMMA#5
DDR_A_D36
DDR_A_D37
122
124
126
VSS
VDD
DQ36
VDD
NC/ODT1
VSS
DQ32
119
121
123
125
DDR_A_ODT1
DDR_A_D33
DDR_A_D32
DDR_A_ODT15
DDR_A_DM4
128
130
132
VSS
VSS
DM4
DQ37
DQ33
VSS
DQS4#
DQS4
127
129
131
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_D38
DDR_A_D44
DDR_A_D39
134
136
138
140
VSS
DQ38
DQ39
VSS
DQ34
DQ35
133
135
137
139
DDR_A_D35
DDR_A_D34
DDR_A_D45
DDR_A_DQS#5
142
144
146
VSS
DQ44
DQ45
VSS
DQ40
DQ41
141
143
145
DDR_A_D41
DDR_A_D40
DDR_A_DQS5
148
150
VSS
DQS5
DQS5#
VSS
DM5
VSS
147
149
DDR_A_DM5
DDR_A_D46
DDR_A_D47
DDR_A_D52
152
154
156
158
VSS
DQ46
DQ47
DQ42
DQ43
VSS
151
153
155
157
DDR_A_D43
DDR_A_D48
DDR_A_D42
DDR_A_D53
160
162
164
VSS
DQ52
DQ53
DQ48
DQ49
VSS
159
161
163
DDR_A_D49
DDR_A_CLK1 5
DDR_A_CLK#1 5
DDR_A_DM6
166
168
170
CK1
VSS
DM6
CK1#
NC,TEST
VSS
DQS6#
DQS6
165
167
169
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_D55
DDR_A_D54
172
174
176
VSS
DQ54
VSS
DQ50
171
173
175
DDR_A_D50
DDR_A_D51
DDR_A_D60
178
180
VSS
DQ55
DQ60
DQ51
VSS
DQ56
177
179
DDR_A_D56
DDR_A_D61
DDR_A_DQS7
DDR_A_DQS#7
182
184
186
188
VSS
DQ61
DQS7#
DQ57
VSS
DM7
181
183
185
187
DDR_A_D57
DDR_A_DM7
DDR_A_D63
DDR_A_D62
190
192
194
VSS
DQ62
DQ63
DQS7
VSS
DQ58
DQ59
VSS
189
191
193
DDR_A_D59
DDR_A_D58
196
195
Security Classification
Security Classification
Security Classification
198
200
204
SA1
VSS
SAO
SDA
SCL
VDDSPD
197
199
203
+3VS
SMB_CK_DAT08,15,21,27
SMB_CK_CLK08,15,21,27
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VSS
PTI_A5652D-A0G16-P@
PTI_A5652D-A0G16-P@
VSS
DIMM0 STD H:5.2mm (Bot)
B
C103
0.1U_0402_16V7K
C103
0.1U_0402_16V7K
1
2
R43
1K_0402_1%
R43
1K_0402_1%
R44
1K_0402_1%
R44
A
+1.8V
1K_0402_1%
1 2
1 2
+V_DDR_MCH_REF8
1 1
2 2
3 3
4 4
A
PCIE_MTX_C_GRX_P[0..15] 19
E
PCIE_MTX_C_GRX_P[0..15]
Polarity inversion
PCIE_MTX_C_GRX_N[0..15] 19
PCIE_MTX_C_GRX_N[0..15]
Polarity inversion
Polarity inversion
< To MXM VGA board >< From MXM VGA board >
Polarity inversion
Polarity inversion
< To LAN >
< To WLAN >
< To New Card >
PCIE_ITX_C_PRX_P2 27
PCIE_ITX_C_PRX_N2 27
PCIE_ITX_C_PRX_P3 26
PCIE_ITX_C_PRX_P0 27
PCIE_ITX_C_PRX_N3 26
PCIE_ITX_C_PRX_N0 27
AUX0 and HPD0
< To SB700 : x4 PCEI A-link>< From SB700 : x4 PCIE A-link >
< TX Impedance Calibration. Connect to GND >
< RX Impedance Calibration. Connect to VDDPCIE >
DP0 GFX_TX0,TX1,TX2 and TX3
RS780M Display Port Support (muxed on GFX)
SB_TX0P 20
SB_TX1N 20
SB_TX0N 20
SB_TX1P 20
+1.1VS
SB_TX2P 20
SB_TX2N 20
SB_TX3N 20
SB_TX3P 20
HDMI_TXD2+ 18,19
HDMI_TXD2- 18,19
AUX1 and HPD1
1 2
1 2
1 2
R76 0_0402_5%IHDMI@ R76 0_0402_5%IHDMI@
R74 0_0402_5%IHDMI@ R74 0_0402_5%IHDMI@
R75 0_0402_5%IHDMI@ R75 0_0402_5%IHDMI@
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P0
DP1 GFX_TX4,TX5,TX6 and TX7
PCIE_MTX_GRX_P1
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
HDMI_CLK0+ 18,19
HDMI_CLK0- 18,19
HDMI_TXD1+ 18,19
HDMI_TXD1- 18,19
HDMI_TXD0+ 18,19
HDMI_TXD0- 18,19
1 2
1 2
1 2
1 2
1 2
R82 0_0402_5%IHDMI@ R82 0_0402_5%IHDMI@
R84 0_0402_5%IHDMI@ R84 0_0402_5%IHDMI@
R81 0_0402_5%IHDMI@ R81 0_0402_5%IHDMI@
R85 0_0402_5%IHDMI@ R85 0_0402_5%IHDMI@
R83 0_0402_5%IHDMI@ R83 0_0402_5%IHDMI@
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
0.1Custom
0.1Custom
0.1Custom
10 45Wednesday, February 25, 2009
10 45Wednesday, February 25, 2009
10 45Wednesday, February 25, 2009
E
LA-4971P
LA-4971P
LA-4971P
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8PCIE_MTX_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10PCIE_MTX_GRX_P10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N0
C
PCIE_MTX_GRX_P0
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3PCIE_MTX_GRX_N3
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C125 0.1U_0402_16V7KPM@ C125 0.1U_0402_16V7KPM@
C121 0.1U_0402_16V7KPM@ C121 0.1U_0402_16V7KPM@
C123 0.1U_0402_16V7KPM@ C123 0.1U_0402_16V7KPM@
C120 0.1U_0402_16V7KPM@ C120 0.1U_0402_16V7KPM@
C122 0.1U_0402_16V7KPM@ C122 0.1U_0402_16V7KPM@
C126 0.1U_0402_16V7KPM@ C126 0.1U_0402_16V7KPM@
C127 0.1U_0402_16V7KPM@ C127 0.1U_0402_16V7KPM@
C124 0.1U_0402_16V7KPM@ C124 0.1U_0402_16V7KPM@
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
A5
B5
A4
B4
C3
B2
D1
GFX_TX0P
GFX_TX1P
GFX_TX2P
GFX_TX3P
GFX_TX0N
GFX_TX1N
GFX_TX2N
PART 2 OF 6
PART 2 OF 6
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5PCIE_MTX_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C133 0.1U_0402_16V7KPM@ C133 0.1U_0402_16V7KPM@
C134 0.1U_0402_16V7KPM@ C134 0.1U_0402_16V7KPM@
C128 0.1U_0402_16V7KPM@ C128 0.1U_0402_16V7KPM@
C131 0.1U_0402_16V7KPM@ C131 0.1U_0402_16V7KPM@
C129 0.1U_0402_16V7KPM@ C129 0.1U_0402_16V7KPM@
C130 0.1U_0402_16V7KPM@ C130 0.1U_0402_16V7KPM@
C132 0.1U_0402_16V7KPM@ C132 0.1U_0402_16V7KPM@
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
D2
E2
E1
F4
F3
F1
F2
GFX_TX4P
GFX_TX5P
GFX_TX6P
GFX_TX3N
GFX_TX4N
GFX_TX5N
GFX_TX6N
PCIE_MTX_C_GRX_N7
1 2
1 2
1 2
1 2
1 2
C138 0.1U_0402_16V7KPM@ C138 0.1U_0402_16V7KPM@
C136 0.1U_0402_16V7KPM@ C136 0.1U_0402_16V7KPM@
C137 0.1U_0402_16V7KPM@ C137 0.1U_0402_16V7KPM@
C135 0.1U_0402_16V7KPM@ C135 0.1U_0402_16V7KPM@
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N7
H4
H3
H1
H2
J2
GFX_TX7P
GFX_TX8P
GFX_TX7N
GFX_TX8N
PCIE_MTX_C_GRX_P12
1 2
1 2
1 2
1 2
1 2
1 2
C139 0.1U_0402_16V7KPM@ C139 0.1U_0402_16V7KPM@
C145 0.1U_0402_16V7KPM@ C145 0.1U_0402_16V7KPM@
C140 0.1U_0402_16V7KPM@ C140 0.1U_0402_16V7KPM@
C141 0.1U_0402_16V7KPM@ C141 0.1U_0402_16V7KPM@
C142 0.1U_0402_16V7KPM@ C142 0.1U_0402_16V7KPM@
C144 0.1U_0402_16V7KPM@ C144 0.1U_0402_16V7KPM@
C143 0.1U_0402_16V7KPM@ C143 0.1U_0402_16V7KPM@
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
J1
K4
K3
K1
K2
M4
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX11P
GFX_TX12P
GFX_TX10N
GFX_TX11N
1 2
M3
GFX_TX12N
GM : RS780MN & RS780MC, PM : RX781
GFX_RX0PD4GFX_RX0NC4GFX_RX1PA3GFX_RX1NB3GFX_RX2PC2GFX_RX2NC1GFX_RX3PE5GFX_RX3NF5GFX_RX4PG5GFX_RX4NG6GFX_RX5PH5GFX_RX5NH6GFX_RX6PJ6GFX_RX6NJ5GFX_RX7PJ7GFX_RX7NJ8GFX_RX8PL5GFX_RX8NL6GFX_RX9PM8GFX_RX9NL8GFX_RX10PP7GFX_RX10NM7GFX_RX11PP5GFX_RX11NM5GFX_RX12PR8GFX_RX12NP8GFX_RX13PR6GFX_RX13NR5GFX_RX14PP4GFX_RX14NP3GFX_RX15PT4GFX_RX15N
U3B
U3B
B
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13PCIE_MTX_GRX_N13
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15PCIE_MTX_GRX_N15
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
1 2
1 2
1 2
C146 0.1U_0402_16V7KPM@ C146 0.1U_0402_16V7KPM@
PCIE_MTX_GRX_P13
M1
PCIE_GTX_C_MRX_N13
1 2
1 2
1 2
1 2
1 2
C148 0.1U_0402_16V7KPM@ C148 0.1U_0402_16V7KPM@
C150 0.1U_0402_16V7KPM@ C150 0.1U_0402_16V7KPM@
C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K
C147 0.1U_0402_16V7KPM@ C147 0.1U_0402_16V7KPM@
C149 0.1U_0402_16V7KPM@ C149 0.1U_0402_16V7KPM@
C151 0.1U_0402_16V7KPM@ C151 0.1U_0402_16V7KPM@
C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
AC1
M2
GFX_TX13P
GFX_TX13N
PCIE_GTX_C_MRX_P13
AC2
N2
N1
P1
P2
GPP_TX0P
GFX_TX14P
GFX_TX15P
GFX_TX14N
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
GPP_RX0P
T3
AE3
AD4
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
1 2
1 2
C157 0.1U_0402_16V7KWLAN@ C157 0.1U_0402_16V7KWLAN@
C156 0.1U_0402_16V7KWLAN@ C156 0.1U_0402_16V7KWLAN@
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
AA2
AA1
AB4
AB3
GPP_TX2P
GPP_TX1P
GPP_TX0N
GPP_TX1N
PCIE I/F GPP
PCIE I/F GPP
GPP_RX2P
GPP_RX0N
GPP_RX1P
GPP_RX1N
AE2
AD1
AD2
AD3
1 2
1 2
C158 0.1U_0402_16V7KC158 0.1U_0402_16V7K
C159 0.1U_0402_16V7KC159 0.1U_0402_16V7K
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
Y1
Y2
Y4
Y3
V1
V2
GPP_TX3P
GPP_TX4P
GPP_TX5P
GPP_TX2N
GPP_TX3N
GPP_TX4N
GPP_RX2N
GPP_RX3PV5GPP_RX3N
GPP_RX4PU5GPP_RX4NU6GPP_RX5PU8GPP_RX5N
U7
W6
1 2
1 2
1 2
C165 0.1U_0402_16V7KC165 0.1U_0402_16V7K
C164 0.1U_0402_16V7KC164 0.1U_0402_16V7K
C163 0.1U_0402_16V7KC163 0.1U_0402_16V7K
C162 0.1U_0402_16V7KC162 0.1U_0402_16V7K
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
AD7
AE7
AE6
SB_TX0P
SB_TX1P
SB_TX0N
GPP_TX5N
SB_RX0P
SB_RX0NY8SB_RX1P
AA8
AA7
1 2
1 2
1 2
1 2
1 2
C167 0.1U_0402_16V7KC167 0.1U_0402_16V7K
C166 0.1U_0402_16V7KC166 0.1U_0402_16V7K
C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K
C169 0.1U_0402_16V7KC169 0.1U_0402_16V7K
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
AD5
AE5
AD6
AC6
AB6
SB_TX3P
SB_TX2P
SB_TX3N
SB_TX1N
SB_TX2N
PCIE I/F SB
PCIE I/F SB
SB_RX3PW5SB_RX3N
SB_RX1N
SB_RX2P
SB_RX2N
Y5
Y7
AA5
AA6
H_CADIP[0..15] 4
H_CADIN[0..15] 4
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
1 2
1 2
R56 2K_0402_1%R56 2K_0402_1%
R55 1.27K_0402_1%R55 1.27K_0402_1%
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP0
PCIE_CALRP
PCIE_CALRN
E24
E25
D24
AC8
D25
AB8
HT_TXCAD1P
HT_TXCAD0P
HT_TXCAD0N
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
PART 1 OF 6
PART 1 OF 6
HT_RXCAD1P
HT_RXCAD0P
HT_RXCAD0N
U3A
U3A
RS780M_FCBGA528
RS780M_FCBGA528
Y25
Y24
V22
V23
RS780MCR3@
RS780MCR3@
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADIN2
H_CADIP2
H_CADIN3
H_CADIP3
F23
F22
F24
F25
HT_TXCAD3P
HT_TXCAD2P
HT_TXCAD3N
HT_TXCAD2N
HT_TXCAD1N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1N
V25
V24
U24
U25
H_CADON2
H_CADOP2
H_CADOP3
H_CADON3
H_CADIN4
H_CADIP4
H_CADIN5
H_CADIP5
J25
J24
H23
H22
HT_TXCAD5P
HT_TXCAD4P
HT_TXCAD5N
HT_TXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
T25
T24
P22
P23
H_CADON4
H_CADOP4
H_CADOP5
H_CADON5
H_CADIN6
H_CADIP6
H_CADIN7
H_CADIP7
K23
K22
K24
K25
HT_TXCAD7P
HT_TXCAD6P
HT_TXCAD7N
HT_TXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
P25
P24
N24
N25
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADIN8
H_CADIP8
H_CADIN9
H_CADIP9
G20
H21
F21
G21
HT_TXCAD9P
HT_TXCAD8P
HT_TXCAD9N
HT_TXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N
AB25
AB24
AC24
AC25
H_CADON9
H_CADOP9
H_CADOP8
H_CADON8
H_CADIN10
H_CADIP10
H_CADIP11
H_CADIN11
H_CADIP12
J18
K17
J20
J21
HT_TXCAD11P
HT_TXCAD10P
HT_TXCAD11N
HT_TXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
Y22
Y23
AA24
AA25
H_CADOP12
H_CADOP11
H_CADON11
H_CADON10
H_CADOP10
H_CADIN12
H_CADIN13
H_CADIP13
H_CADIP14
M21
M19
L18
L19
J19
HT_TXCAD13P
HT_TXCAD12P
HT_TXCAD13N
HT_TXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
V21
V20
U20
W21
W20
H_CADOP14
H_CADOP13
H_CADON13
H_CADON12
H_CADIN14
H_CADIN15
H_CADIP15
P18
M18
P21
HT_TXCAD15P
HT_TXCAD14P
HT_TXCAD15N
HT_TXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
U19
U18
U21
H_CADOP15
H_CADON15
H_CADON14
H_CLKIP0 4
H_CLKIP1 4
H_CLKIN0 4
H_CLKIN1 4
L21
L20
H24
H25
HT_TXCLK1P
HT_TXCLK0P
HT_TXCLK1N
HT_TXCLK0N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_RXCLK1P
HT_RXCLK1N
HT_RXCLK0P
HT_RXCLK0N
T22
T23
AB23
AA22
< Transmitter Calibration Resistor to HT_TXCALN >
1 2
H_CTLIP0 4
H_CTLIP1 4H_CTLOP14
H_CTLIN0 4
H_CTLIN1 4
R58 301_0402_1%R58 301_0402_1%
HT_TXCALP
HT_TXCALN
H_CTLIN0
H_CTLIP0
H_CTLIP1
H_CTLIN1
0718 Place within 1"
layout 1:2
M24
M25
P19
R18
B24
B25
HT_TXCALP
HT_TXCALN
HT_TXCTL0P
HT_TXCTL1P
HT_TXCTL0N
HT_TXCTL1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
NEED CHECK R57 & R58 WITH AMD
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
A24
R21
R20
C23
M22
M23
HT_RXCALP
HT_RXCALN
H_CTLON0
H_CTLOP0
H_CTLOP1
H_CTLON1
R57301_0402_1% R57301_0402_1%
D
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
/
/
/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
Polarity inversion
A
PCIE_GTX_C_MRX_P[0..15] 19
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
Polarity inversion
Polarity inversion
Polarity inversion
PCIE_GTX_C_MRX_N[0..15] 19
Polarity inversion
Polarity inversion
Polarity inversion
1 1
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
PCIE_PTX_C_IRX_P027
PCIE_PTX_C_IRX_N027
PCIE_PTX_C_IRX_P326
PCIE_PTX_C_IRX_N326
PCIE_PTX_C_IRX_P227
PCIE_PTX_C_IRX_N227
< To LAN >
< To WLAN >
< To New Card >
1 2
H_CTLOP04
H_CLKOP04
H_CLKOP14
H_CTLON04
SB_RX1P20
SB_RX1N20
SB_RX0P20
SB_RX0N20
SB_RX3P20
SB_RX3N20
SB_RX2P20
SB_RX2N20
H_CADOP[0..15] 4
H_CADON[0..15] 4
H_CADON[0..15]
2 2
< From S1G2 CPU : x16 HT> < To S1G2 CPU : x16 HT>
3 3
H_CLKON04
H_CTLON14
H_CLKON14
0718 Place within 1"
layout 1:2
A
4 4
0.1
0.1
0.1
E
D
C
U3C
U3C
AVDD=100mA
+AVDD1
B
UMA_LCD_TXOUT0_A0- 17
UMA_LCD_TXOUT0_A0+ 17
A22
B22
TXOUT_L0P(NC)
TXOUT_L0N(NC)
PART 3 OF 6
PART 3 OF 6
AVDD1(NC)
AVDD2(NC)
F12
E12
+AVDD2
< LVDS dual channel : channel 1 >
UMA_LCD_TXOUT0_A2- 17
UMA_LCD_TXOUT0_A1- 17
UMA_LCD_TXOUT0_A2+ 17
UMA_LCD_TXOUT0_A1+ 17
A21
B21
B20
A20
TXOUT_L1P(NC)
TXOUT_L2P(NC)
TXOUT_L1N(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
F14
H15
H14
G15
+AVDDQ
< LVDS dual channel : channel 2 >
UMA_LCD_TZOUT0_B0+ 17
UMA_LCD_TZOUT0_B1+ 17
UMA_LCD_TZOUT0_B0- 17
UMA_LCD_TZOUT0_B1- 17
A19
B18
B19
A18
A17
B17
TXOUT_L3P(NC)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
RED(DFT_GPIO0)
E17
F17
F15
REDb(NC)
G18
G17
UMA_CRT_R
UMA_CRT_R16
AVSSQ(NC)
UMA_LCD_TXCLK_ACLK- 17
UMA_LCD_TXCLK_ACLK+ 17
UMA_LCD_TZOUT0_B2+ 17
UMA_LCD_TZOUT0_B2- 17
D20
D21
TXOUT_U2P(NC)
GREEN(DFT_GPIO1)
F18
E18
UMA_CRT_G
UMA_CRT_G16
UMA_LCD_TZCLK_BCLK- 17
UMA_LCD_TZCLK_BCLK+ 17
D18
D19
B16
A16
D16
D17
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
BLUE(DFT_GPIO3)
DAC_VSYNC(PWM_GPIO6)
DAC_HSYNC(PWM_GPIO4)
GREENb(NC)
BLUEb(NC)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
F8
E8
F19
E19
B11
A11
G14
UMA_CRT_VSYNC
UMA_CRT_HSYNC
R65 715_0402_1%GPM@ R65 715_0402_1%GPM@
UMA_CRT_B
UMA_CRT_B16
UMA_CRT_CLK16
UMA_CRT_DATA16
UMA_CRT_HSYNC14,16
UMA_CRT_VSYNC14,16
+VDDLTP18
+VDDLT18
A13
B13
B15
A14
B14
C14
A15
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT18_1(NC)
VDDA18HTPLL
PLLVDD18(NC)
PLLVSS(NC)
B12
H17
D14
+NB_HTPVDD
+VDDA18HTPLL
VSSLT1(VSS)
VDDLT33_2(NC)
LVTM
LVTM
VDDA18PCIEPLL1
VDDA18PCIEPLL2
E7
D7
+VDDA18PCIEPLL
VSSLTP18(NC)
VDDLTP18(NC)
PLLVDD(NC)
DAC_RSET(PWM_GPIO1)
A12
+NB_HTPVDD
+NB_PLLVDD
1 2
R65 715_0402_1%GM@ R65 715_0402_1%GM@
+NB_PLLVDD
D15
C16
C18
C20
E20
C22
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
SYSRESETbD8POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
A10
C10
C12
NB_RESET#
NB_PWRGD
1 2
R67 0_0402_5%R67 0_0402_5%
NB_PWRGD21
PLT_RST#14,19,20,26,27,33,34
LDT_STOP#6,20
CPU_LDT_REQ#6,20
< LVDS digital power enable >
UMA_ENVDD 17
R79 0_0402_5%GM@ R79 0_0402_5%GM@
E9
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
PM
PM
REFCLK_P/OSCIN(OSCIN)
HT_REFCLKN
HT_REFCLKP
REFCLK_N(PWM_GPIO3)
F11
E11
C24
C25
CLK_NBHT15
CLK_NBHT#15
NB_OSC_14.318M15
< LVDS backlight enable >
UMA_ENBKL 34
12
R73 100K_0402_5%GPM@ R73 100K_0402_5%GPM@
R73 100K_0402_5%GM@ R73 100K_0402_5%GM@
1 2
T17PAD T17PAD
F7
G12
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
CLOCKs PLL PWR
GFX_REFCLKP
GFX_REFCLKN
GPP_REFCLKP
GPP_REFCLKN
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
T2
T1
V4
V3
U1
U2
NBGFX_CLK15
NBGFX_CLK#15
CLK_SBLINK_BCLK15
CLK_SBLINK_BCLK#15
< Strap option pin or gate side-port memory IO >
< HDMI hot-plug detection >
SUS_STAT# 14,21
HPD 18,19,21
1 2
R78 0_0402_5%GM@ R78 0_0402_5%GM@
R78 0_0402_5%GPM@ R78 0_0402_5%GPM@
D10
D9
TMDS_HPD(NC)
MIS.
MIS.
I2C_CLKB9STRP_DATA
I2C_DATA
B8
A9
UMA_LCD_DDC_DAT17
UMA_LCD_DDC_CLK17
1 2
R80 1.8K_0402_5%R80 1.8K_0402_5%
AE8
AD8
D13
D12
HPD(NC)
DDC_DATA0/AUX0N(NC)
HDMIDAT_UMA18
TESTMODE
THERMALDIODE_P
THERMALDIODE_N
SUS_STAT#(PWM_GPIO5)
DDC_CLK0/AUX0P(NC)
DDC_DATA1/AUX1N(NC)
DDC_CLK1/AUX1P(NC)
RSVD
A8
A7
B7
B10
G11
12
R88 10K_0402_5%@ R88 10K_0402_5%@
+3VS
HDMICLK_UMA18
C8
AUX_CAL(NC)
AUX_CAL14
Strap pin
UMA_CRT_R
UMA_CRT_G
1 2
R62 140_0402_1%GM@ R62 140_0402_1%GM@
1 2
R63 150_0402_1%GM@ R63 150_0402_1%GM@
UMA_CRT_B
1 2
R64 150_0402_1%GM@ R64 150_0402_1%GM@
NB_PWRGD
1 2
R371 300_0402_5%R371 300_0402_5%
RS780 use 140 ohm, check RS880 use what value
+1.8VS
C198
0_0402_5%
C198
0_0402_5%
C198
0.1U_0402_16V7K
C198
L4
0_0603_5%GM@L40_0603_5%GM@
+AVDD1 +AVDD2
C170
0_0603_5%
C170
0_0603_5%
PM1@
PM1@
L2
BLM18PG121SN1D_0603GM@L2BLM18PG121SN1D_0603GM@
+3VS +1.8VS
1
C172
C172
1
C170
C170
1
1 2
0.1U_0402_16V7K
2
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
GM@
GM@
PM1@
PM1@
C172
0_0603_5%
C172
0_0603_5%
PM1@
PM1@
L4
0_0603_5%
L4
0_0603_5%
GPM@
GPM@
RS780M_FCBGA528
RS780M_FCBGA528
RS780MCR3@
RS780MCR3@
L2
0_0603_5%
L2
0_0603_5%
GPM@
GPM@
< Dedicated power for the DAC which can affect display quality > < Dedicated power for the DAC which can affect display quality >
+VDDLTP18
C171
0_0603_5%
C171
0_0603_5%
C171
2.2U_0603_6.3V4Z
C171
2.2U_0603_6.3V4Z
1
L3
BLM18PG121SN1D_0603GM@L3BLM18PG121SN1D_0603GM@
12
+NB_HTPVDD
1
L7
BLM18PG121SN1D_0603GM@L7BLM18PG121SN1D_0603GM@
1 2
+AVDDQ
C175
C175
1
BLM18PG121SN1D_0603GM@L6BLM18PG121SN1D_0603GM@
1 2
2
GM@
GM@
C176
2.2U_0603_6.3V4Z
C176
2.2U_0603_6.3V4Z
2
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
GM@
GM@
PM1@
PM1@
L3
0_0603_5%
L3
0_0603_5%
GPM@
GPM@
< Power for integrated DVI/HDMI PLL macro >
+1.8VS
C176
0_0603_5%
C176
0_0603_5%
PM1@
PM1@
L7
0_0603_5%
L7
0_0603_5%
GPM@
GPM@
< 1.8V power for system PLLs >
+1.8VS
C175
0_0603_5%
C175
0_0603_5%
PM1@
PM1@
L6
L6
0_0603_5%
L6
0_0603_5%
GPM@
GPM@
< DAC Bandgap Reference Voltage >
+1.8VS
+VDDLT18
C173
0_0402_5%
C173
0_0402_5%
C173
0.1U_0402_16V7K
C173
0.1U_0402_16V7K
1
PM1@
PM1@
L5
0_0603_5%
L5
0_0603_5%
GPM@
GPM@
< 1.8V IO power for the integrated DVI/HDMI interface >< 1.1V Power for system PLLs >
+1.8VS
C178
0_0603_5%
C178
0_0603_5%
PM1@
PM1@
L9
0_0603_5%
L9
0_0603_5%
GPM@
GPM@
+1.1VS
1 2
L10 BLM18PG121SN1D_0603L10 BLM18PG121SN1D_0603
< IO power for HyperTransport PLL >
+1.8VS +VDDA18HTPLL
2
GM@
GM@
C174
4.7U_0805_10V4Z
C174
4.7U_0805_10V4Z
1
2
GM@
GM@
L5
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
12
GM@ L5
GM@
+NB_PLLVDD
C178
2.2U_0603_6.3V4Z
C178
2.2U_0603_6.3V4Z
1
2
GM@
GM@
L9
BLM18PG121SN1D_0603GM@L9BLM18PG121SN1D_0603GM@
1 2
C179
2.2U_0603_6.3V4Z
C179
2.2U_0603_6.3V4Z
1
2
< 1.8V IO power for PCI-E PLLs >
+1.8VS
11 45Wednesday, February 25, 2009
11 45Wednesday, February 25, 2009
11 45Wednesday, February 25, 2009
E
LA-4971P
LA-4971P
LA-4971P
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
/
/
/
+VDDA18PCIEPLL
C180
C180
1
1 2
L11 BLM18PG121SN1D_0603L11 BLM18PG121SN1D_0603
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
B
A
< DAC internal reference to set full scale DAC current >
R72
4.7K_0402_5%
R72
1 2
4.7K_0402_5%
12
2 2
3 3
4 4
R71
4.7K_0402_5%
R71
4.7K_0402_5%
+1.1VS
1 1
A
0.1
0.1
0.1
12 45Wednesday, February 25, 2009
12 45Wednesday, February 25, 2009
12 45Wednesday, February 25, 2009
LA-4971P
LA-4971P
LA-4971P
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Custom
Custom
Custom
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
+1.8VS
+1.1VS
2008-09-25 2009-09-25
2008-09-25 2009-09-25
AA18
AA20
AA19
Y19
V17
AA17
MEM_DQ4(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
PAR 4 OF 6
PAR 4 OF 6
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
AB12
AE16
V11
AE15
AA12
MEM_A5(NC)
AB16
U3D
U3D
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
MEM_DQ12(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ13/DVO_D9(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
AD14
AD13
AD15
AC16
AE13
AC14
Y14
AB14
W17
AE19
Y17
W18
AD20
AE21
AD21
MEM_DM0(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_BA0(NC)
MEM_BA1(NC)
AE17
AD16
MEM_DM1/DVO_D8(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
Y12
W12
AB13
AB18
AD17
AD18
AE23
AD23
AE24
IOPLLVDD(NC)
IOPLLVDD18(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
MEM_ODT(NC)
MEM_CKP(NC)
MEM_CKN(NC)
V14
V15
W14
AE18
IOPLLVSS(NC)
MEM_VREF(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
AE12
AD12
2008-09-25 2009-09-25
Security Classification
Security Classification
Security Classification
/
/
/
1
Deciphered Date
Deciphered Date
Deciphered Date
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
B B
A A
2
+1.1VS
L17FBMA-L11-201209-221LMA30T_0805 L17FBMA-L11-201209-221LMA30T_0805
1 2
E
C21210U_0805_10V4Z C21210U_0805_10V 4Z
C21110U_0805_10V4Z C21110U_0805_10V 4Z
1
2
C2230.1U_0402_16V7K C2230.1U_0402_16V7K
1
2
C2240.1U_0402_16V7K C2240.1U_0402_16V7K
1
2
C2211U_0402_6.3V4Z C2211U_0402_6.3V4Z
1
2
C2221U_0402_6.3V4Z C2221U_0402_6.3V4Z
1
2
C2191U_0402_6.3V4Z C2191U_0402_6.3V4Z
1
2
C2201U_0402_6.3V4Z C2201U_0402_6.3V4Z
D
+VDDA11PCIE
VDDA_12=2.5A
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
J9
M9
K9
L9
VDDPCIE_1A6VDDPCIE_2B6VDDPCIE_3C6VDDPCIE_4D6VDDPCIE_5E6VDDPCIE_6F6VDDPCIE_7G7VDDPCIE_8H8VDDPCIE_9
PART 5/6
PART 5/6
VDDPCIE_11
VDDPCIE_10
R9
T9
V9
VDDPCIE_12
VDDPCIE_13P9VDDPCIE_14
VDDPCIE_15
K12
J14
U9
VDDC_1
VDDPCIE_16
VDDPCIE_17
VDDC_2
+1.1VS
12
PJP9
PJP9
+NB_CORE
VDD_CORE:GM=5A/PM=10A< Core power >
U16
J11
K15
M12
VDDC_3
VDDC_4
VDDC_5
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1
C2320.1U_0402_16V 7K C2320.1U_0402_16V7K
C2440.1U_0402_16V 7K C2440.1U_0402_16V7K
C2310.1U_0402_16V 7K C2310.1U_0402_16V7K
C2300.1U_0402_16V 7K C2300.1U_0402_16V7K
C2430.1U_0402_16V 7K C2430.1U_0402_16V7K
C2420.1U_0402_16V 7K C2420.1U_0402_16V7K
C2410.1U_0402_16V 7K C2410.1U_0402_16V7K
C2400.1U_0402_16V 7K C2400.1U_0402_16V7K
C2470.1U_0402_16V 7K C2470.1U_0402_16V7K
L14
L11
M13
M15
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
C234
C234
+
+
1
C24510U_0805_10V4Z C24510U_0805_10V4Z
1
C23310U_0805_10V4Z C23310U_0805_10V4Z
2
2
2
2
2
2
2
2
2
N12
N14
VDDC_11
VDDC_12
P11
VDDC_13
POWER
POWER
330U_D2E_2.5VM
330U_D2E_2.5VM
2
2
2
1
1
1
1
1
1
1
1
1
P13
VDDC_14
DVT change to B size
P14
R12
R15
T11
T15
U12
T14
J16
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
+3VS
C253
0.1U_0402_16V4Z
C253
0.1U_0402_16V4Z
1
2
GM@
GM@
C250
0.1U_0402_16V4Z
C250
0.1U_0402_16V4Z
1
2
GM@
GM@
< Isolated power for side-port memory interface >
< 3.3V IO power >
H11
Y11
AD10
AC10
AB10
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM6(NC)
VDD_MEM5(NC)
H12
VDD33_1(NC)
VDD33_2(NC)
VSSAPCIE1A2VSSAPCIE2B1VSSAPCIE3D3VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6G1VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9
PART 6/6
PART 6/6
AE10
AA11
VDD_MEM1(NC)
H7
J4
R7
VSSAPCIE10
L1
L2
L4
L7
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
M6
N4
P6
R1
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
R2
R4
V7
U4
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
V8
V6
W1
W2
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
W4
W7
Y6
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30W8VSSAPCIE31
AA4
AB5
AB1
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
GROUND
GROUND
AB7
AC3
AC4
AE1
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
AE4
AB2
VSSAPCIE39
VSSAPCIE40
AE14
VSS1
D11
VSS2
E14
VSS3G8VSS4
E15
J15
VSS5
J12
VSS6
K14
VSS7
M11
VSS8
VSS9
L15
VSS10
0.1Custom
0.1Custom
0.1Custom
13 45Wednesday, February 25, 2009
13 45Wednesday, February 25, 2009
13 45Wednesday, February 25, 2009
E
LA-4971P
LA-4971P
LA-4971P
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
C
U3E
U3E
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
J17
L16
T16
P16
R16
H18
G19
+VDDHTRX
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
F20
E21
C218
0.1U_0402_16V7K
C218
0.1U_0402_16V7K
C217
0.1U_0402_16V7K
C217
0.1U_0402_16V7K
K16
M16
+VDDHT
C210
C210
1
B
C208
C208
1
< Digital IO power for HyperTransport interface >
C207
0.1U_0402_16V7K
C207
0.1U_0402_16V7K
C216
0.1U_0402_16V7K
C216
1
C206
0.1U_0402_16V7K
C206
0.1U_0402_16V7K
1
2
2
0.1U_0402_16V7K
1
C214
0.1U_0402_16V7K
C214
0.1U_0402_16V7K
1
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
B23
A23
D22
2
2
2
2
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
AE25
AD24
AC23
+VDDHTTX
C229
C229
1
C228
C228
1
C227
C227
1
C226
C226
1
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
Y20
V18
U17
W19
AB22
AA21
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
T17
P17
R17
M17
VDDA18PCIE_1
VDDA18PCIE_2
VDDHTTX_13
J10
P10
K10
+VDDA18PCIE
C239
C239
1
C238
C238
1
C237
C237
1
C236
C236
1
C246
C246
1
VDDA18PCIE_3
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_4
VDDA18PCIE_5
H9
W9
L10
T10
M10
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_8
VDDA18PCIE_9
Y9
R10
AA9
AB9
AD9
VDD18_1F9VDD18_2G9VDD18_MEM1(NC)
VDDA18PCIE_13
VDD18_MEM2(NC)
VDDA18PCIE_14
VDDA18PCIE_15
U10
AE9
AE11
AD11
C252
C252
1
< 1.8V IO transform power >
< 1.8V power for side-port memory interface >
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
U3F
U3F
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
GM@
GM@
VSSAHT1
VSSAHT2
A25
E22
D23
C252
0_0402_5%
C252
0_0402_5%
PM1@
PM1@
VSSAHT3
VSSAHT4
G22
1 2
L89 0_0603_5%GPM@ L89 0_0603_5%GPM@
L89 0_0603_5%GM@ L89 0_0603_5%GM@
VSSAHT5
VSSAHT6
G24
G25
VSSAHT7
VSSAHT8
J22
H19
VSSAHT9
VSSAHT10
L17
L22
VSSAHT11
VSSAHT12
VSSAHT13
L24
L25
M20
VSSAHT14
VSSAHT15
VSSAHT16
P20
N22
R19
VSSAHT17
VSSAHT18
VSSAHT19
R22
R24
R25
VSSAHT21
VSSAHT22
VSSAHT20
V19
U22
H20
VSSAHT23
VSSAHT24
VSSAHT25
W22
W24
W25
VSSAHT26
VSSAHT27
Y21
AD25
VSS11
L12
VSS12
M14
N13
VSS13
VSS14
P12
VSS15
P15
VSS16
R11
VSS17
R14
VSS18
T12
U14
VSS19
VSS20
U11
VSS21
U15
VSS22
V12
VSS23
W11
VSS24
W15
VSS25
AC12
VSS26
AA14
VSS27
Y18
VSS28
AB11
VSS29
AB15
VSS30
AB17
AB19
VSS31
VSS32
AE20
VSS34
VSS33
RS780M_FCBGA528
RS780M_FCBGA528
K11
AB21
RS780MCR3@
RS780MCR3@
Security Classification
Security Classification
Security Classification
/
/
/
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
A
L16 0_0805_5%L16 0_0805_5%
C209
C209
1
12
2A
+1.1VS
C215
C215
L18 0_0805_5%L18 0_0805_5%
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
12
2A < IO power for HyperTransport receive interface >
1 1
C225
4.7U_0805_10V4Z
C225
10U_0805_10V4Z
10U_0805_10V4Z
4.7U_0805_10V4Z
L19 0_0805_5%L19 0_0805_5%
1
2
12
2A < IO power for HyperTransport transmit interface >
+1.2V_HT
C235
C235
L22 0_0805_5%L22 0_0805_5%
1
12
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
+1.8VS
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+1.8VS
C251
1U_0402_6.3V4Z
C251
1U_0402_6.3V4Z
1
2
+1.8VS
2 2
3 3
4 4
A
0.1Custom
0.1Custom
0.1Custom
14 45Wednesday, February 25, 2009
14 45Wednesday, February 25, 2009
14 45Wednesday, February 25, 2009
E
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
D
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
E
LA-4971P
LA-4971P
LA-4971P
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
Deciphered Date
Deciphered Date
Deciphered Date
C
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
< DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb >
Enables the Test Debug Bus using GPIO.
1 : Enable (RX780, RS780)
0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
+3VS
B
R101
3K_0402_5%
R101
3K_0402_5%
12
R102
R102
3K_0402_5%@
3K_0402_5%@
12
These pin straps are used to configure PCI-E GPP mode.
SI2: Change to 3K pull high
000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011
< DFT_GPIO1 : LOAD_EEPROM_STRAPS >
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
< DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb >
RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780)
0 : Enable (RS780)
+3VS
PLT_RST# 11,19,20,26,27,33,34
R104
150_0402_1%@
R104
150_0402_1%@
1 2
D4
CH751H-40PT_SOD323-2@D4CH751H-40PT_SOD323-2@
2 1
R125
3K_0402_5%
R125
3K_0402_5%
12
C
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
/
/
/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
A
< RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K >
UMA_CRT_VSYNC11,16
< RS780 use register to control PCI-E configure >
1 1
SUS_STAT#11,21
AUX_CAL11
< RS780 DFT_GPIO1 >
2 2
UMA_CRT_HSYNC11,16
< RS780 use HSYNC to enable SIDE PORT (internal pull high) >
3 3
A
4 4
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