TOPSTAR S42G Schematics

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Topstar Digital technologies Co.,LTD

D D

Board name: MotherBoard Schematic
Project name: C49
Version: VerA
Initial Date: 2010-04-01

02. System block & Index

03. PWR Block & Description

04. Notes & Annotations

05. Schematic Modify and History

06. CLOCK Distribution

Topstar Confidential

C C

Hardware drawing by:

Power drawing by:

Hardware check by: EMI Check by:

Power check by:

Manager Sign by:

B B

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Joseph
Title

Title

Title

C49

C49

C49

1

A

A

A

of

of

of

159Friday, May 07, 2010

159Friday, May 07, 2010

159Friday, May 07, 2010

5

4

Page Name

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Size

Size

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Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

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2

the expressed written consent of TOPSTAR

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Topstar Confidential

ShenZhen Topstar Industry Co.,LTD

D D

Backlight
Connector

+VDC

TFT

+V3.3S

C C

B B

LVDS switch

PCIE mini Card

VGA

+V5S

PCIE mini Card

C49 SYSTEM BLOCK Ver:A

Only for PM

64M*16Bit*4 DDRIII

+V1.5GDDR

Memory

Nvidia
NB11M

LVDS
HDMI

R/G/B

interface

+VGA_CORE,
+V1.05GPU
+V1.8GDDR,
+V3.3GPU
+V1.5GPU

PCIE 1X

USB PORT(3)

+V5AL

HDMI
CONN

SIM Card

Blue Tooth

+V3.3AL

LVDS

R/G/B
TMDS

USB1.1/2.0

Camera

1.3M ODULE
+V3.3S

PEGX16 /eDP

BIOS

8Mbit

+V3.3AL

Arrandule/clarsfield

989rPGA

+VCC_CORE,+VccGFX
+V1.5S, +V1.8S,
+V1.1S_VTT

FDI

SPI

Ibex_peak

1071 BGA

+V3.3A,+V3.3S,+V1.5S,
+V1.05S,+V1.8S,
+V5A,+V5S

LPC

KB Controller/EC

ENE 3926

+V3.3AL,+V3.3S,+V5AL

DMI*4 100MHz

CK505M
Clocking

SLG8SP585

+V3.3S

DDR3 800/1066

DDR3 800/1066

PCIE 1X

USB1.1/2.0

AZALIA

TCM

(Reserve)

DDR3 SODIMM0
800/1066

+V0.75S,+V1.5,+V3.3S

DDR3 SODIMM1
800/1066

+V0.75S,+V1.5,+V3.3S

RTL8102E/8111D

+V3.3S,+V3.3AL

SATA ODD

S-ATA

2.5" HDD

+V5S

+V5S

Card Reader

ITE 1337

+V3.3AL

L

R

AZALIA

ALC662

+V5S,+V3.3S

RJ45

.

.

SD/MMC/MS CARD

MiC In

Line Out

LED/TouchPAD/Button/
Switch Board

DAUGHTER BOARD

KB Matrix

A A

5

4

3

LID Switch

DAUGHTER BOARD

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TOPSTAR TECHNOLOGY

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Joseph
Sys block

Sys block

Sys block

C49

C49

C49

1

A

A

A

of

of

of

259Friday, May 07, 2010

259Friday, May 07, 2010

259Friday, May 07, 2010

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736

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736

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C46 POWER BLOCK Ver:A

D D

9,1

⊼ᛣ

㰮㒓㸼⼎⬉⑤⬉ֵোDŽ

9B

9B

95B21

VCC_SENCE
VSS_SENCE

IMON

95B77
9FFBFRUH

9,'>@
36,
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C C

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96

9*38

96B977

MOSFET

+V3.3GPU

9$/
9$/

MOSFET

9'&

MOSFET

+V1.5GPU

9
96

9&&B&25(

+V1.5S

+V1.8S

KIA1117

96
96

MOSFET

MOSFET

+V1.8GPU

&/.B(1$%/(

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A A

TOPSTAR TECHNOLOG

TOPSTAR TECHNOLOG

TOPSTAR TECHNOLOG

Joseph

Joseph

Joseph

PWR Block

PWR Block

PWR Block

C49

C49

C49

1

A

A

359Friday, May 07, 2010

359Friday, May 07, 2010

359Friday, May 07, 2010

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Page Name
Size

Size

Size

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Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

5

6670

6/3B6

6/3B6

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66RIW2II

6/3B6

6)XOO2Q

9

667'

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Voltage Rails

+VDC

D D

+VCC_CORE

+V1.1S_VTT

+V1.05S
+V0.75S
+V1.5

+V3.3AL

+V3.3S
+V5AL
+V5S
+VGA_CORE

+V1.5S

+V1.8S

+V3.3GPU

+V1.05GPU

C C

+V1.8GPU 1.8V for external GPU

+V1.5GPU 1.5V for external GPU

Primary DC system power supply(9V-19V)
Core voltage for processor

1.1V for CPU

1.05V for PCH core

0.75V DDR3 Termination voltage

1.5V power rail for DDR3

3.3V always on power rail

3.3V main power rail
5V for USB Device
5V main power rail

0.8--1.03V for GPU NB8M core voltage

1.5S for PCIE Device

1.8V for display votage

3.3V for external GPU

1.05V for external GPU

I2C SMB Address

Device

Clock Generator
SO-DIMM0
SO-DIMM1
NEW CARD
PCIE Mini CARD

Smart Battery

Touch sensor IC

0001 011x 16 I2C ENE3926
1000 110x 8C SMB1_PCH ENE3926

Address

1101 001x
1010 000x
1010 010x

Variable Variable SMB1_PCHPCH

BusHex

SMB_PCH

D2

SMB_PCH

A0

SMB_PCH

A4

SMB_PCH

VariableVariable

SMB_PCH

VariableVariable

Master

PCH
PCH
PCH
PCH
PCH

ENE3926

Power States/AC mode

Board stack up description

PCB Layers

TOP

GND

IN1

IN2

VCC

IN3

B B

GND

Bottom

Trace Impedence:50ohm +/-15%(Default)

+,*+

/2:

/2: 2))

/2:

+,*+

+,*+ 21 2))

/2:

/2:

+,*+

+,*+

+,*+

/2:

21

21

21

21 21

21

2))

2))

2))

2))

21

2))

2))

Wake up Events

USB Table

USB Port#

A A

Function Description

0

Express Card

1

minicard1

reserved

2

3

camera

4

USB port1

5

Bluetooth

6

Reserved

7

Reserved

8

CARD Reader

9

minicard2

10

USB port2

11

USB port3

5

4

3

LID switch from EC
Power switch from EC

TOPSTAR TECHNOLOG

TOPSTAR TECHNOLOG

TOPSTAR TECHNOLOG

Joseph

Joseph

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Size

Size

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Project Name Rev

Project Name Rev

Project Name Rev

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C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Notes

Notes

Notes

C49

C49

C49

Joseph

A

A

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459Friday, May 07, 2010

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C48 VerB to VerC change

1:GPURST#



GPURST#ϢPLATRST#

Փ⫼Ϣ䮼᥻ࠊ˄

䖭ḋخⱘ಴ህᰃབᵰྟ㒜⬅
಴Ў೼⛁ࡼⱘ䖛⿟Ё
᳝ৃ㛑Ӯᡧϡࠄ

D D

2

˖⅏䫕⬉䆱䆒䅵ব᳈ˈ⬉䏃ᬍবᦣ䗄བϟ˖

PLTRST#

I GU1 ,NI GR1

ৠℹˈ⬅

EC_GPURST#

PLTRST#

PLTRST#

㹿ᢝϟᴹⱘᯊ䯈෎ᴀϞህ೼

˅ˈ⬅

PLTRST#ϢEC_GPURST#

᥻ࠊˈخᰒߛᤶⱘᯊ׭⬅

䗮䖛պ⌟

PLTRST#

ᴹ᥻ࠊ

5ms

݅ৠ᥻ࠊˈℷᐌⱘᓔ݇ᴎⱘᯊ׭

EC_GPURST#

GPURST#

ˈ

Ꮊেˈ㗠ECⱘᠿᦣᳳህᰃ

ϔϾব࣪ⱘ䖛⿟㗠ֱᣕϔⳈЎ催ˈӮ䗴៤ᰒ偅ࡼⱘ϶༅ㄝᓖᐌ⦄䈵DŽ

᥻ࠊ

GPURST#

ˈ

5ms,

EC_GPURST#

ྟ㒜Ў催⬉ᑇˈ

NI Q31,PZ8,change PR187 from 100 ohm to 2K ohm,change PR24 from 51k to 15K

ব᳈಴བϟ˖
᠔᳝

GPU

⬉䛑Ӯᥝϟᴹˈ᠔ҹ

䗮䖛

BIOS

䇏প✊ৢথ䗕㒭
ህㅫ᳝⅏䫕ֵোথߎᴹˈ಴Ў
থ⦄〇ㅵ䱣ⴔ⏽ᑺব࣪ⓣ⬉⌕Ӯ๲໻ˈৃ㛑Ӯᇐ㟈ᓖᐌ⅏䫕ˈৠᯊ಴Ў
ᬙএᥝ

PZ8

Q31

ᰃᰒ

EC

ϡӮᇍ㒓䏃᳝ᕅડDŽ

GPU_OVT#

᥻ࠊ⅏䫕⬉䏃ⱘ䗮䘧ˈ಴Ў㋏㒳ϟ㽕خᰒߛᤶˈᔧҢ⣀ᰒߛࠄ䲚ᰒⱘᯊ׭ˈ

GPU_OVT#

ˈ⬅EC᥻ࠊDŽ

51K100ohm

гӮᥝϟᴹˈӮᇐ㟈ᓖᐌ⅏䫕ˈ᠔ҹϡ㛑䖭ḋ᥻ࠊˈ⦄೼

PR187

ᤶ៤

2K,PR24

ᤶ៤

15K

ⱘ಴ᰃ಴ЎПࠡⱘ㒘ড়ϡ㛑⅏䫕ˈ

ߚˈߚߎᴹⱘ⬉ϡ㛑㓈ᣕ⅏䫕⬉䏃ˈৠᯊএᥝ

3.3AL

㢃⠛ݙ䚼᳝䖛ֱᡸࡳ㛑ˈ

GPU

PZ8

ᰃ಴ЎПࠡ

⏽ᑺպ⌟ᰃ

3˖TP_CON2

Пࠡⱘ㒓䏃Ϟা᳝ϔϾ

4˖PWRLED#

C C

ᇐ㟈䖭ϸϾ

5˖Audio Jack
SPK CONN

6˖USB conn

7

˖㔥

⬅Пࠡⱘ

ֵোৠᯊ᥻ࠊ

PWR

6Pin

ᤶ៤

7pin,

ব᳈ⱘ಴ᰃЏᵓ㽕ݐᆍ

EC GPIO

ˈᬙ䳔㽕๲ࡴ

POWER1ϢPWRLED1

♃ϡ㛑ৠℹˈϡ⒵䎇䆒䅵㽕∖DŽ

⠽᭭ব᳈ˈ⬅Пࠡⱘ

SMD

᭭ߛᤶࠄ

⠽᭭಴Ў៤ᴀ಴㋴ˈг᳝ব᳈Ў᱂䗮Փ⫼ⱘ

⠽᭭ব᳈ˈ಴ЎПࠡⱘ

CO-lay

ܚ

Option for C49,

USB conn

݋ԧ㒓䏃೒ব᳈䇋খ㗗㒓䏃೒DŽ

C49

ˈ㗠

C49

1pin

DŽ

ˈПࠡ㒓䏃䆒䅵

DIP

᭭ˈⳌⱘܗӊ

CONN

PWRLED#

ˈϢ

RTC CONN

Ϟ䳔㽕ϸϾ

া᥻ࠊ

POWER1,㗠PWRLED1

Symbol

г᳝ব᳈DŽৠᯊ

ϔ㟈ˈϡ⍝ঞ㒓䏃೒ব᳈DŽ

ECⱘGPIO

ᰃডⱘˈӮ㒭⫼᠋Փ⫼䗴៤ೄᡄˈ㒓䏃೒ব᳈খ㗗㒓䏃೒

᥻ࠊϸϾᓔ݇ˈ

ᰃՓ⫼݊Ҫ

Audio

ᇣᵓϞⱘ

ECⱘGPIO

᥻ࠊˈ

C48 VerC to C49 VerA change

1˖PROCHOT#
2

˖

B B

PCH GPIO33
3˖MCH_HDMI_HPD
4

˖䖲᥹ᰒⱘ

5

˖ߴ䰸㪱⠭ЏᵓϞⱘ

6

˖

GPU_OVT#
7˖ESATA USB CONN

˖ߴ䰸

8

˖䇗ᭈ

9
10

˖䇗ᭈ

11˖PWR_LAN

˖এᥝ

12
13

˖᳈ᬍ⅏䫕⬉䏃䆒䅵

A A

⬅ⳌবঠⳌˈ

䖲᥹ࠄ

EC pin 104(EC

EC

Ⳉ᥹

SMBUSϢECⱘSMBUS

CONN

ˈᇚ㪱⠭ֵো䖲᥹ࠄ

䖲᥹ࠄECⱘ

Pin88(EC

ব᳈ЎϾⱘ

E-CARD Function
RSMRST#Ϣ+V3.3AL

ᥝ⬉ᯊᑣˈ

C49_switch2ࠄ110pin(EC

ϢЏᵓ䖲᥹㒓⬅

+V1.05S

㒓䏃ˈ݅⫼

5

30pin
+V1.1S_VTT

԰Ў᥻ࠊֵো䕧ߎ

䕧ߎ)ˈ԰Ў

ˈՓECⳈ᥹䇏পᰒ⏽ᑺ

LCD CONN

䕧ֵܹো

)

USB CONN

ALW_PWROK ҢPin110

䕧ܹ

)

⬉ᄤ㒓ব᳈Ў1Ͼ

ˈЁ䯈Փ⫼

4

EC_ME_LOCK#

ব᳈ࠄ

8pin

ⱘ⬉ᄤ㒓˄

Open

⚍Ϣ⬉䰏䖲᥹

᥻ࠊֵো

Pin95(EC

For

䕧ܹ&Ёᮁ

⬉⑤˅ϢϔϾ

3

pin)

20pin FFC conn(For

Page Name

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Custom

Custom

Custom

Date: Sheet of

Date: Sheet

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

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㔥

)

TOPSTAR TECHNOLOG

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Joseph

Joseph

history

history

history

C49

C49

C49

A

A

A

of

of

559Friday, May 07, 2010

559Friday, May 07, 2010

559Friday, May 07, 2010

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+V3.3S {8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V3.3AL {22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}

3

2

1

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C7

C7

C3

C3

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

+V3.3S

R573

R573
10K

10K

R0402

R0402

C8

C8

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

+V3.3S

R10

R10
10K

10K

R0402

R0402

ns

ns

+V3.3S_CK_VDD

C4

C4

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

+VDDIO_CLK

C9

C9

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

C5

C5

C0402

C0402

Layout Note:
Cap Close to CK505 PWR pin

C10

C10

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

CLK_BUF_REF14

C13 10PF/50V,NPOnsC0402C13 10PF/50V,NPOnsC0402

+V3.3S_CK_VDD

+VDDIO_CLK

C11 27pF/50V,NPO

C11 27pF/50V,NPO

C0402

C0402

C12 27pF/50V,NPO

C12 27pF/50V,NPO

C0402

C0402

No more than 500 mil

12

Y1

Y1

14.31818MHz

14.31818MHz

XS2_3D3

XS2_3D3

XTAL_IN

XTAL_OUT

1

5
17
29

24
18
15

G1
G2
G3
G4

28
27

G5

2

8

9
12
21
26

U1

U1

VDD_DOT
VDD_27
VDD_SRC
VDD_REF

VDD_CPU
VDD_CPU_IO
VDD_SRC_IO
GND1
GND2
GND3
GND4
XTAL_IN

XTAL_OUT
GND5

VSS_DOT
VSS_27
VSS_SATA
VSS_SRC
VSS_CPU
VSS_REF

CK505QFN32

CK505QFN32

SMB_DATA

SMB_CLK

CPU_STOP#

CPU0

CPU0#

CPU1

CPU1#
DOT96

DOT96#

SRC0/SATA

SRC0#/SATA

SRC1

SRC1#

27M_NSS

27M_SS

REF/FS

CK_PWRGD/PWRDWN#

SMBUS ADD:1101 001X

31
32

16
23

22
20

19
3

4
10

11
13

14
6

7
30

25

R955 0 R0402R955 0 R0402

R956 0 R0402R956 0 R0402

CPU_STOP#
BCLK

R1 0 R0402R1 0 R0402

BCLK#

R2 0 R0402R2 0 R0402

Integrated resistors on differentail clk

DOT96

R3 0 R0402R3 0 R0402

DOT96#

R4 0 R0402R4 0 R0402

R5 0 R0402R5 0 R0402

R6 0 R0402R6 0 R0402

R7 0 R0402R7 0 R0402

R8 0 R0402R8 0 R0402

BCLK_FS

R9 33 R0402R9 33 R0402

CLK_PWRGD

SMB_DATA_S {14,15,24,37}
SMB_CLK_S {14,15,24,37}

CLK_BUF_BCLK_P {24}
CLK_BUF_BCLK_N {24}

CLK_BUF_DOT96_P {24}
CLK_BUF_DOT96_N {24}

CLK_BUF_SATA_P {24}
CLK_BUF_SATA_N {24}

CLK_BUF_EXP_P {24}
CLK_BUF_EXP_N {24}

27M_nonSSC {20}

27M_SSC {20}

CLK_BUF_REF14 {24}

FB1 100ohm@100MHz,3A

FB1 100ohm@100MHz,3A

D D

C C

B B

+V3.3S

+V3.3S

12

FB0805

FB0805

C1

C1

10UF/6.3V,X5R

10UF/6.3V,X5R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0805

C0805

CPU_STOP#

FB2 100ohm@100MHz,3A

FB2 100ohm@100MHz,3A

1 2

FB0805

FB0805

C6

C6

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

C0805

Frequence Select
High:100Mhz
Low:133Mhz(Default)

C2

C2

C0402

C0402

C0805

C0805

BCLK_FS

+V3.3S

R896

R896
10K

10K

R897

R897

R0402

R0402

10K

10K

R0402

R0402

ns

ns

3

PQ85

PQ85
2N7002

2N7002

SOT23

R898 1K

A A

5

CK505_CLK_EN#{53}

R898 1K

R0402

R0402

C535

C535

C0402

C0402

0.1UF/25V,Y5V

0.1UF/25V,Y5V

ns

ns

SOT23

1

2

C536

C536

C0402

C0402

0.1UF/25V,Y5V

0.1UF/25V,Y5V

4

+V3.3AL

VCC

VCC

1
2

GND

GND

R895 0 nsR895 0 ns

53

4
SOT23_5

SOT23_5

SN74AHC1G08DBV

SN74AHC1G08DBV
U30

U30

C534

C534

0.1UF/10V,X7R

0.1UF/10V,X7R

CLK_PWRGD

TOPSTAR TECHNOLOG

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

CK505M

CK505M

CK505M

C49

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1

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659Friday, May 07, 2010

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3

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1

U2A

U2A

D D

C C

B B

A A

5

DMI_TXN0{25}
DMI_TXN1{25}
DMI_TXN2{25}
DMI_TXN3{25}

DMI_TXP0{25}
DMI_TXP1{25}
DMI_TXP2{25}
DMI_TXP3{25}

DMI_RXN0{25}
DMI_RXN1{25}
DMI_RXN2{25}
DMI_RXN3{25}

DMI_RXP0{25}
DMI_RXP1{25}
DMI_RXP2{25}
DMI_RXP3{25}

FDI_TXN[7:0]{25}

FDI_TXP[7:0]{25}

FDI_FSYNC0{25}
FDI_FSYNC1{25}

FDI_INT{25}

FDI_LSYNC0{25}
FDI_LSYNC1{25}

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0

DMI_RXP1

DMI_RXP2

DMI_RXP3

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

DMI Intel(R) FDI

DMI Intel(R) FDI

4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_IRCOMP_R

EXP_RBIAS

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

GC2190.1UF/10V,X7RPMGC2190.1UF/10V,X7R
GC2210.1UF/10V,X7RPMGC2210.1UF/10V,X7R

GC2230.1UF/10V,X7RPMGC2230.1UF/10V,X7R
GC2220.1UF/10V,X7RPMGC2220.1UF/10V,X7R
GC2240.1UF/10V,X7RPMGC2240.1UF/10V,X7R
GC2250.1UF/10V,X7RPMGC2250.1UF/10V,X7R
GC2270.1UF/10V,X7RPMGC2270.1UF/10V,X7R

GC2260.1UF/10V,X7RPMGC2260.1UF/10V,X7R
GC2280.1UF/10V,X7RPMGC2280.1UF/10V,X7R
GC2290.1UF/10V,X7RPMGC2290.1UF/10V,X7R

GC2310.1UF/10V,X7RPMGC2310.1UF/10V,X7R

GC2370.1UF/10V,X7R

GC2370.1UF/10V,X7R

GC2400.1UF/10V,X7R

GC2400.1UF/10V,X7R

GC2420.1UF/10V,X7R

GC2420.1UF/10V,X7R

GC2410.1UF/10V,X7R

GC2410.1UF/10V,X7R

GC2380.1UF/10V,X7R

GC2380.1UF/10V,X7R

GC2430.1UF/10V,X7R

GC2430.1UF/10V,X7R

GC2390.1UF/10V,X7R

GC2390.1UF/10V,X7R

GC2440.1UF/10V,X7R

GC2440.1UF/10V,X7R

GC2450.1UF/10V,X7R

GC2450.1UF/10V,X7R

GC2470.1UF/10V,X7R

GC2470.1UF/10V,X7R

GC2460.1UF/10V,X7R

GC2460.1UF/10V,X7R

GC2480.1UF/10V,X7R

GC2480.1UF/10V,X7R

GC2350.1UF/10V,X7R

GC2350.1UF/10V,X7R

GC2330.1UF/10V,X7R

GC2330.1UF/10V,X7R

GC2360.1UF/10V,X7R

GC2360.1UF/10V,X7R

GC2340.1UF/10V,X7R

GC2340.1UF/10V,X7R

GC2170.1UF/10V,X7RPMGC2170.1UF/10V,X7R
GC2180.1UF/10V,X7RPMGC2180.1UF/10V,X7R

GC2200.1UF/10V,X7RPMGC2200.1UF/10V,X7R

GC2300.1UF/10V,X7RPMGC2300.1UF/10V,X7R
GC2320.1UF/10V,X7RPMGC2320.1UF/10V,X7R

R11 49.9,1%

R11 49.9,1%

R12 750 OHM

R12 750 OHM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

PM

3

R0402

R0402

R0402

R0402

PEG_TXN[15..0] {17}

PEG_TXP[15..0] {17}

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_RXN[15..0] {17}

PEG_RXP[15..0] {17}

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Page Name

Page Name

Page Name
Size

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Project Name Rev

Project Name Rev

Project Name Rev

B

B

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Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

1

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D D

U2B

H_COMP3
H_COMP2
H_COMP1

S_Top

S_Top

S_Top

S_Top

S_Top

S_Top

S_Top

S_Top

S_Top

S_Top

VR_PROCHOT#

VCCPWRGOOD_1_R

VCCPWRGD_0_R

PLT_RST#_R

H_COMP0

H_CATERR#

H_PECI_R

H_CPURST#_R

H_PM_SYNC_R

+V1.1S_VTT

R21 49.9,1% R0402

R21 49.9,1% R0402

R23 0 R0402

R23 0 R0402

S_Top

S_Top

R26 68 R0402 ns

R26 68 R0402 ns

S_Top

S_Top

R27 0 R0402

R27 0 R0402

R487 0 R0402

R487 0 R0402

R488 0 R0402

R488 0 R0402

PM_DRAM_PWRGD

CPU_VTT_PWG

H_PWRGD_XDP_R

R29 1.5K,1% R0402

R29 1.5K,1% R0402

S_Top

S_Top

R33

R33
750 OHM

750 OHM

R0402

R0402
S_Top

S_Top

+V1.1S_VTT

H_PM_SYNC{25}

VCCPWRGD_0{28}

PM_DRAM_PWRGD{25}

BUF_PLT_RST#{17,27,34,35,37,41,42}

H_PECI{28}

R25 68 R0402 ns

R25 68 R0402 ns

THERMTRIP#{28,34}

+V1.1S_VTT

C C

+V1.1S_VTT

R413

R413
1K,1%

1K,1%

R0402

R0402

ns

ns

S_Top

S_Top

B B

U2B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

S_Bot

S_Bot

R34

R34

49.9,1%

49.9,1%

R0402

R0402
S_Top

S_Top

4

MISC THERMAL

MISC THERMAL

CLOCKS

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

Processor Compensation
Signals

H_COMP1
H_COMP0

R36

R35

R35

49.9,1%

49.9,1%

R0402

R0402
S_Top

S_Top

R36

20,1%

20,1%

r0402

r0402

S_Bot

S_Bot

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H_COMP3
H_COMP2

R37

R37
20,1%

20,1%

r0402

r0402
S_Bot

S_Bot

3

PM_EXT_TS#0

R30

R30
1K

1K

R0402ns

R0402ns
S_Top

S_Top

+V1.1S_VTT

R15

R15
10K

10K

R0402

R0402
S_Top

S_Top

+V1.1S_VTT

R22

R22
10K

10K

R0402

R0402
S_Top

S_Top

Layout Note:
Place close to CPU

BCLK_CPU_P_R

A16

BCLK_CPU_N_R

B16

BCLK_ITP_P

AR30

BCLK_ITP_N

AT30

CLK_EXP_P_R

E16

CLK_EXP_N_R

D16

CLK_DP_P_R

A18

CLK_DP_N_R

A17

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1
AN15

PM_EXT_TS#1

AP15

AT28
AP27

AN28

TCK

AP28

TMS

AT27
AT29

TDI

AR27

TDO

TDI_M

AR29

TDO_M

AP29
AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

XDP_REQ
TCK

TMS

TDI
TDO

R13 0 R0402

R13 0 R0402
R14 0 R0402

R14 0 R0402

R17 0 R0402

R17 0 R0402
R18 0 R0402

R18 0 R0402
R19 0 R0402 ns

R19 0 R0402 ns
R20 0 R0402 ns

R20 0 R0402 ns

TRST#

R562

R562

49.9,1%

49.9,1%

R0402

R0402
S_Bot

S_Bot

T48

T48

T20

T20
T42

T42
T43

T43
T44

T44
T46

T46
T45

T45
T47

T47
T37

T37

TDI_M

TDO_M

SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0

100,1%

100,1%

R0402

R0402

S_Bot

S_Bot

S_Bot

S_Bot
S_Bot

S_Bot

ns

ns

T24

T24

ns

ns

T36

T36

S_Bot

S_Bot

S_Bot

S_Bot

S_Bot

S_Bot

S_Bot

S_Bot

S_Bot

S_Bot
S_Bot

S_Bot

DDR3_DRAMRST# {14,15}

TDO

TMS

ns

ns

TCK

TDI

ns

ns

S_Top

S_Top

ns

ns
ns

ns

XDP_REQ

ns

ns

S_Top

S_Top

ns

ns

S_Top

S_Top

ns

ns

S_Top

S_Top

ns

ns

S_Top

S_Top

ns

ns

S_Top

S_Top
S_Top

S_Top
S_Top

S_Top

R265

R265

S_Top

S_Top

0

0

R0402

R0402

ns

ns

S_Top

S_Top

DDR3 Compensation Signals

R38

R38

R39

R39

24.9,1%

24.9,1%

R0402

R0402
S_Bot

S_Bot

BCLK_CPU_P {28}
BCLK_CPU_N {28}

CLK_EXP_P {24}
CLK_EXP_N {24}

R566 49.9,1% R0402

R566 49.9,1% R0402

ns

ns

S_Bot

S_Bot

R253 49.9,1% R0402

R253 49.9,1% R0402

ns

ns

S_Bot

S_Bot

R267 49.9,1% R0402

R267 49.9,1% R0402

ns

ns

S_Bot

S_Bot

R296 49.9,1% R0402

R296 49.9,1% R0402

ns

ns

S_Bot

S_Bot

R325 49.9,1% R0402

R325 49.9,1% R0402

ns

ns

S_Bot

S_Bot

R40

R40
130,1%

130,1%

R0402

R0402
S_Bot

S_Bot

PM_EXT_TS#1PM_EXT_TS#0

+V1.1S_VTT

1

R28

R28
10K

10K

R0402

R0402
S_Top

S_Top

+V3.3S

+V1.1S_VTT

R154

R154
1K

1K

R0402

R0402
ns

ns
S_Top

S_Top

Q28

Q28

Q1

Q1
MMBT3904-F

MMBT3904-F

SOT23

SOT23

ns

ns

2 3

S_Top

S_Top

2

+V1.1S_VTT {10,11,48,49,53}
+V3.3S {6,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.5 {11,14,15,47,54,55,56}

+V1.1S_VTT

R59

R59
1K

1K

R0402

R0402
ns

ns
S_Top

S_Top

Q27

Q27

1

MMBT3904-FSOT23

MMBT3904-FSOT23

S_Top

S_Top

1

ns

ns

23

MMBT3904-FSOT23

MMBT3904-FSOT23

S_Top

S_Top

ns

ns

23

R51

R51
10K

10K

R0402

R0402
ns

ns
S_Top

S_Top

R24

R24
10K

10K

R0402

R0402
ns

ns
S_Top

S_Top

+V3.3S

+V3.3S

Voltage Level?

DIM_EXTTS#0 {14}

Voltage Level?

DIM_EXTTS#1 {15}

Ⳃࠡ៥Ӏ⫼ⱘݙᄬッ≵᳝خ䖛⏽ⱘࡳ㛑DŽ

+V1.1S_VTT

R31

R31
1K

1K

R0402

R0402
S_Top

S_Top

Q2

Q2
MMBT3904-F

MMBT3904-F

23

SOT23

SOT23
S_Top

S_Top

VR_PROCHOT#

EC_PROCHOT# {42}

R32

R32
1K

1K

R0402

R0402
S_Top

S_Top

1

+V1.1S_VTT+V1.1S_VTT

VR_PROCHOT# {53}

1

+V1.5

R215

R215

1.21K,1%

1.21K,1%

S_Top

S_Top

R234

R234

3.3K

3.3K

S_Top

S_Top

CPU_VTT_PWG{42}

R899

R899
750 OHM

750 OHM

S_Bot

S_Bot

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

4

3

2

the expressed written consent of TOPSTAR

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

1

A

A

A

of

of

of

859Friday, May 07, 2010

859Friday, May 07, 2010

859Friday, May 07, 2010

A A

5

PM_DRAM_PWRGD

5

http://hobi-elektronika.net

U2C

U2C

D D

MA_DATA[63:0]{14}

C C

MA_A_BS0{14}
MA_A_BS1{14}

B B

MA_A_BS2{14}

MA_A_CAS#{14}
MA_A_RAS#{14}

MA_A_WE#{14}

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

AM10

AM12
AM13

AJ10
AL10

AK12

AK11

AR11
AL11

AT11
AP12

AN12
AT14

AT12
AL13
AR14
AP14

A10

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39]
SA_DQ[40]

AJ9

SA_DQ[41]
SA_DQ[42]
SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45]
SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

4

AA6

SA_CK[0]

AA7

SA_CK#[0]

P7

SA_CKE[0]

Y6

SA_CK[1]

Y5

SA_CK#[1]

P6

SA_CKE[1]

AE2

SA_CS#[0]

AE8

SA_CS#[1]

AD8

SA_ODT[0]

AF9

SA_ODT[1]

MA_DM0

B9

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

MA_DM1

D7

MA_DM2

H7

MA_DM3

M7

MA_DM4

AG6

MA_DM5

AM7

MA_DM6

AN10

MA_DM7

AN13

MA_DQS#0

C9

MA_DQS#1

F8

MA_DQS#2

J9

MA_DQS#3

N9

MA_DQS#4

AH7

MA_DQS#5

AK9

MA_DQS#6

AP11

MA_DQS#7

AT13

MA_DQS0

C8

MA_DQS1

F9

MA_DQS2

H9

MA_DQS3

M9

MA_DQS4

AH8

MA_DQS5

AK10

MA_DQS6

AN11

MA_DQS7

AR13

MA_A_A0

Y3

MA_A_A1

W1

MA_A_A2

AA8

MA_A_A3

AA3

MA_A_A4

V1

MA_A_A5

AA9

MA_A_A6

V8

MA_A_A7

T1

MA_A_A8

Y9

MA_A_A9

U6

MA_A_A10

AD4

MA_A_A11

T2

MA_A_A12

U3

MA_A_A13

AG8

MA_A_A14

T3

MA_A_A15 MB_B_A14

V9

M_CLK_DDR0 {14}

M_CLK_DDR#0 {14}
M_CKE0 {14}

M_CLK_DDR1 {14}

M_CLK_DDR#1 {14}
M_CKE1 {14}

M_CS#0 {14}
M_CS#1 {14}

M_ODT0 {14}
M_ODT1 {14}

MA_DM[7:0] {14}

MA_DQS#[7:0] {14}

MA_A_A[15:0] {14}

MA_DQS[7:0] {14}

3

U2D

U2D

MB_DATA[63:0]{15}

MB_B_BS0{15}
MB_B_BS1{15}
MB_B_BS2{15}

MB_B_CAS#{15}
MB_B_RAS#{15}

MB_B_WE#{15}

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

AR10
AT10

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

2

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

MB_DM0

D4

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

MB_DM1

E1

MB_DM2

H3

MB_DM3

K1

MB_DM4

AH1

MB_DM5

AL2

MB_DM6

AR4

MB_DM7

AT8

MB_DQS#0

D5

MB_DQS#1

F4

MB_DQS#2

J4

MB_DQS#3

L4

MB_DQS#4

AH2

MB_DQS#5

AL4

MB_DQS#6

AR5

MB_DQS#7

AR8

MB_DQS0

C5

MB_DQS1

E3

MB_DQS2

H4

MB_DQS3

M5

MB_DQS4

AG2

MB_DQS5

AL5

MB_DQS6

AP5

MB_DQS7

AR7

MB_B_A0

U5

MB_B_A1

V2

MB_B_A2

T5

MB_B_A3

V3

MB_B_A4

R1

MB_B_A5

T8

MB_B_A6

R2

MB_B_A7

R6

MB_B_A8

R4

MB_B_A9

R5

MB_B_A10

AB5

MB_B_A11

P3

MB_B_A12

R3

MB_B_A13

AF7
P5

MB_B_A15

N1

M_CLK_DDR2 {15}

M_CLK_DDR#2 {15}
M_CKE2 {15}

M_CLK_DDR3 {15}

M_CLK_DDR#3 {15}
M_CKE3 {15}

M_CS#2 {15}
M_CS#3 {15}

M_ODT2 {15}
M_ODT3 {15}

MB_DM[7:0] {15}

MB_DQS#[7:0] {15}

MB_DQS[7:0] {15}

MB_B_A[15:0] {15}

1

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

A A

5

4

3

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

1

A

A

A

of

of

of

959Friday, May 07, 2010

959Friday, May 07, 2010

959Friday, May 07, 2010

5

http://hobi-elektronika.net

U2F

U2F

+VCC_CORE +V1.1S_VTT

4

Clarksfield 1.1v

3

2

+VCC_CORE {53}
+V1.1S_VTT {8,11,48,49,53}

1

Arrandale 1.05v

D D

C C

B B

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

PSI#

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

VTT_SELECT_R

G15

Vcore_IMON_R

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15
A15

C14

C14
10uF/6.3V,X5R

10uF/6.3V,X5R

C20

C20
10uF/6.3V,X5R

10uF/6.3V,X5R

C26

C26
10uF/6.3V,X5R

10uF/6.3V,X5R

R41 0R0402R41 0R0402

R42 0

R42 0

R0402

R0402

R44 0R0402R44 0R0402
R45 0R0402R45 0R0402

C15

C15
10uF/6.3V,X5R

10uF/6.3V,X5R

C21

C21
10uF/6.3V,X5R

10uF/6.3V,X5R

C27

C27
10uF/6.3V,X5R

10uF/6.3V,X5R

Vcore_IMON {53}

ns

ns

ICTP

ICTP

T3

T3

ns

ns

ICTP

ICTP

T1

T1

C16

C16
10uF/6.3V,X5R

10uF/6.3V,X5R

C22

C22
10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.1S_VTT

PM_PSI# {53}

H_VID0 {53}
H_VID1 {53}
H_VID2 {53}
H_VID3 {53}
H_VID4 {53}
H_VID5 {53}
H_VID6 {53}
PM_DPRSLPVR {53}

VTT_SELECT {48}

+VCC_CORE

R43

R43
100,1%

100,1%

R0402

R0402

R46

R46
100,1%

100,1%

R0402

R0402

C17

C17

10uF/6.3V,X5R

10uF/6.3V,X5R

C23

C23

10uF/6.3V,X5R

10uF/6.3V,X5R

VCCSENSE {53}
VSSSENSE {53}

C18

C18

10uF/6.3V,X5R

10uF/6.3V,X5R

C24

C24

0.22uF/10V,X7R

0.22uF/10V,X7R

C39

C39

10uF/6.3V,X5R

10uF/6.3V,X5R

C51

C51

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C19

C19
10uF/6.3V,X5R

10uF/6.3V,X5R

C25

C25

0.01uF/25V,X7R

0.01uF/25V,X7R

C28

C28
10uF/6.3V,X5R

10uF/6.3V,X5R

C40

C40
10uF/6.3V,X5R

10uF/6.3V,X5R

C52

C52
10uF/6.3V,X5R

10uF/6.3V,X5R

C29

C29
10uF/6.3V,X5R

10uF/6.3V,X5R

C41

C41
10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C53

C53
10uF/6.3V,X5R

10uF/6.3V,X5R

PM_PSI# PM_DPRSLPVR

C31

C31

C30

C30

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C42

C42
10uF/6.3V,X5R

10uF/6.3V,X5R

C54

C54
10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.1S_VTT +V1.1S_VTT

R58

R58
1K

1K

R0402

R0402

ns

ns

R155

R155
1K

1K

R0402

R0402

C32

C32
10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C43

C43
10uF/6.3V,X5R

10uF/6.3V,X5R

C55

C55
10uF/6.3V,X5R

10uF/6.3V,X5R

C44

C44
10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C56

C56
1uF/10V,X7R

1uF/10V,X7R

C33

C33
10uF/6.3V,X5R

10uF/6.3V,X5R

C45

C45
10uF/6.3V,X5R

10uF/6.3V,X5R

C34

C34
10uF/6.3V,X5R

10uF/6.3V,X5R

C57

C57
1uF/10V,X7R

1uF/10V,X7R

C46

C46
10uF/6.3V,X5R

10uF/6.3V,X5R

C35

C35
10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C58

C58

0.22uF/10V,X7R

0.22uF/10V,X7R

C47

C47
10uF/6.3V,X5R

10uF/6.3V,X5R

C59

C59

0.22uF/10V,X7R

0.22uF/10V,X7R

R156

R156
1K

1K

R0402

R0402

R157

R157
1K

1K

R0402

R0402

ns

ns

C36

C36
10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C48

C48
10uF/6.3V,X5R

10uF/6.3V,X5R

C37

C37
10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C49

C49
10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C60

C60

0.01uF/25V,X7R

0.01uF/25V,X7R

+VCC_CORE

C38

C38
10uF/6.3V,X5R

10uF/6.3V,X5R

C50

C50

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C61

C61

0.01uF/25V,X7R

0.01uF/25V,X7R

C62

C62
10uF/6.3V,X5R

10uF/6.3V,X5R

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

1

A

A

A

of

of

of

10 59Friday, May 07, 2010

10 59Friday, May 07, 2010

10 59Friday, May 07, 2010

5

4

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

5

http://hobi-elektronika.net

D D

4

3

2

+VGFX {49}

+V1.1S_VTT {8,10,48,49,53}

+V1.5 {8,14,15,47,54,55,56}

+V1.8S {16,27,29,30,47,54,55}

1

+VGFX

C64

C64
10uF/6.3V,X5R

10uF/6.3V,X5R

C C

C67

C67

0.22uF/10V,X7R

0.22uF/10V,X7R

+V1.1S_VTT

+V1.1S_VTT

B B

C68

C68

0.01uF/25V,X7R

0.01uF/25V,X7R

C81

C81
10uF/6.3V,X5R

10uF/6.3V,X5R

C65

C65

10uF/6.3V,X5R

10uF/6.3V,X5R

C77

C77
10uF/6.3V,X5R

10uF/6.3V,X5R

C82
10uF/6.3V,X5R

10uF/6.3V,X5R

C82

C66

C66
10uF/6.3V,X5R

10uF/6.3V,X5R

C69

C69
10uF/6.3V,X5R

10uF/6.3V,X5R

C78

C78
10uF/6.3V,X5R

10uF/6.3V,X5R

C70

C70
10uF/6.3V,X5R

10uF/6.3V,X5R

C83

C83
10uF/6.3V,X5R

10uF/6.3V,X5R

C63

C63
10uF/6.3V,X5R

10uF/6.3V,X5R

C84

C84
10uF/6.3V,X5R

10uF/6.3V,X5R

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16

AK21
AK19
AK18
AK16

AH21
AH19
AH18
AH16

AL21
AL19
AL18
AL16

AJ21
AJ19
AJ18
AJ16

U2G

U2G

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

GRAPHICS

GRAPHICS

FDI PEG & DMI

FDI PEG & DMI

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_DPRSLPVR

GRAPHICS VIDs

GRAPHICS VIDs

POWER

POWER

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

VAXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

VGFXVCCSEN {49}
VGFXVSSSEN {49}

GFXVR_VID_0 {49}
GFXVR_VID_1 {49}
GFXVR_VID_2 {49}
GFXVR_VID_3 {49}
GFXVR_VID_4 {49}
GFXVR_VID_5 {49}
GFXVR_VID_6 {49}

GFXVR_DPRSLPVR {49}
VGFX_IMON {49}

C72

C72

C71

C71

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

C79

C79
10uF/6.3V,X5R

10uF/6.3V,X5R

VCCPLL

C73

C73
1uF/10V,X7R

1uF/10V,X7R

C80

C80
10uF/6.3V,X5R

10uF/6.3V,X5R

C74

C74
1uF/10V,X7R

1uF/10V,X7R

C85

C85
10uF/6.3V,X5R

10uF/6.3V,X5R

GFXVR_EN {49}

R705

R705
470

470

R0402

R0402

C75

C75
1uF/10V,X7R

1uF/10V,X7R

+V1.1S_VTT

+V1.1S_VTT

C86

C86
10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.5

C76

C76
1uF/10V,X7R

1uF/10V,X7R

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

+V1.8S

VCCPLL

C87

C87
1uF/10V,X7R

1uF/10V,X7R

A A

5

4

C88

C88
1uF/10V,X7R

1uF/10V,X7R

C89

C89
1uF/10V,X7R

1uF/10V,X7R

3

FB3

1 2

300ohm@100MHz,1.5A

300ohm@100MHz,1.5A

C90

C90
10uF/6.3V,X5R

10uF/6.3V,X5R

FB0805FB3

FB0805

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

1

A

A

A

of

of

of

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11 59Friday, May 07, 2010

11 59Friday, May 07, 2010

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U2H

U2H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

A A

VSS8

AR17

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

5

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

4

4

3

U2I

U2I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

3

VSS

VSS

NCTF

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

2

Page Name

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Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

1

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

12 59Friday, May 07, 2010

12 59Friday, May 07, 2010

12 59Friday, May 07, 2010

1

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A

A

of

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of

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U2E

U2E

AP25
AL25
AL24
AL22

CFG0

CFG3
CFG4

AJ33

AG9
M27

L28
J17

H17
G25
G17

E31

E30

AM30
AM28

AP31
AL32

AL30
AM31
AN29
AM32

AK32

AK31

AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30

AK30

H16

B19
A19

A20
B20

U9

T9

AC9
AB9

C1
A3

J29
J28

A34
A33

C35
B35

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

D D

VREFA_DDR3{14}

VREFB_DDR3{15}

C C

B B

A A

R496 0 nsR0402R496 0 nsR0402
R497 0 nsR0402R497 0 nsR0402

R47 3.01K,1% R0402 nsR47 3.01K,1% R0402 ns

R49 3.01K,1% R0402R49 3.01K,1% R0402
R48 3.01K,1% R0402 nsR48 3.01K,1% R0402 ns

5

4

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD26
RSVD27

RSVD_NCTF_28
RSVD_NCTF_29

RSVD_NCTF_30
RSVD_NCTF_31

4

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD_NCTF_37

RSVD38
RSVD39

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD58

RSVD_TP_59
RSVD_TP_60

RESERVED

RESERVED

RSVD62

RSVD63

RSVD64

RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

KEY

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

3

BRACKET

BRACKET

CPU_BRACKET

CPU_BRACKET

R50 0 R0402R50 0 R0402

3

H11

H11

CPU_HOLE

11223344556677889

CPU_HOLE

2

H13

H12

H12

CPU_HOLE

ns

ns

9

CPU_HOLE

11223344556677889

ns

ns

9

2

H13

CPU_HOLE

CPU_HOLE

ns

11223344556677889

BRACKET1_Mylar

BRACKET1_Mylar

Mylar

Mylar

Page Name

Page Name

Page Name
Size

Size

Size

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

ns

9

Project Name Rev

Project Name Rev

Project Name Rev

1

H14

H14

CPU_HOLE

CPU_HOLE

ns

11223344556677889

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

ns

9

13 59Friday, May 07, 2010

13 59Friday, May 07, 2010

13 59Friday, May 07, 2010

1

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D D

C C

+V3.3S

close to DDR pin

0.1UF/25V,Y5V

0.1UF/25V,Y5V
C379

C379

C0402

C0402

B B

C380

C380

2.2UF/10V,X7R

2.2UF/10V,X7R

C0805

C0805

DDR3_DRAMRST#{8,15}

DIM_EXTTS#0{8}

MA_DM[7:0]{9}

M_CLK_DDR0{9}
M_CLK_DDR#0{9}
M_CLK_DDR1{9}
M_CLK_DDR#1{9}

MA_DQS[7:0]{9}

SMB_DATA_S{6,15,24,37}
SMB_CLK_S{6,15,24,37}

VREFA_DDR3

MA_A_A[15:0]{9}

MA_A_BS0{9}
MA_A_BS1{9}
MA_A_BS2{9}

M_CS#0{9}
M_CS#1{9}

MA_A_WE#{9}
MA_A_CAS#{9}
MA_A_RAS#{9}

M_CKE0{9}

M_CKE1{9}

M_ODT0{9}
M_ODT1{9}

R416 0R416 0

C381

C381

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

close to DDR pin

MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3
MA_DQS4
MA_DQS5
MA_DQS6
MA_DQS7

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.5 {8,11,15,47,54,55,56}
+V0.75S {15,47,54}

MA_A_A0

98

MA_A_A1

97

MA_A_A2

96

MA_A_A3

95

MA_A_A4

92

MA_A_A5

91

MA_A_A6

90

MA_A_A7

86

MA_A_A8

89

MA_A_A9

85

MA_A_A10

107

MA_A_A11

84

MA_A_A12

83

MA_A_A13

119

MA_A_A14

80

MA_A_A15

78

109
108

79

114
121

MA_DM0

11

MA_DM1

28

MA_DM2

46

MA_DM3

63

MA_DM4

136

MA_DM5

153

MA_DM6

170

MA_DM7

187
113

115
110

73
74

101
103
102
104

116
120

12
29
47

64
137
154
171
188

200

R415 10K R0402R415 10K R0402
R414 10K R0402R414 10K R0402

C382

C382

2.2UF/10V,X7R

2.2UF/10V,X7R

C0805

C0805

202
197

201
199

1

126
198

30

77
122
125

DDR3_SODIMM204_0

DDR3_SODIMM204_0

4

+V1.5+V0.75S

99

100

105

106

111

112

VDD10

VDD11

VDD12

VDD13

117

VDD14

203

204

VTT1

VTT2

VDD175VDD276VDD381VDD482VDD587VDD688VDD793VDD894VDD9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2

CS0
CS1

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7

WE
CAS
RAS

CKE0
CKE1

CK0
CK0
CK1
CK1

ODT0
ODT1

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

SDA
SCL

SA0
SA1

VDDSPD
VREF_DQ

VREF_CA
EVENT#

RESET#
NC1

NC2
NCTEST

VSS23VSS38VSS49VSS513VSS614VSS719VSS820VSS925VSS1026VSS1131VSS1232VSS1337VSS1438VSS1543VSS1644VSS1748VSS1849VSS1954VSS2055VSS2160VSS2261VSS2365VSS2466VSS2571VSS2672VSS27

VSS1

2

VDD15

3

+V1.5

12

C91

118

123

124

151

145

150

155

156

161

162

167

168

172

173

178

179

184

185

189

190

195

196

DIMM1

VDD16

VDD17

VDD18

DIMM1

MA_DATA0

VSS36

VSS34

VSS35

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

VSS29

VSS30

VSS28

127

133

134

128

5

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

D0

MA_DATA1

7

D1

MA_DATA2

15

D2

MA_DATA3

17

D3

MA_DATA4

4

D4

MA_DATA5

6

D5

MA_DATA6

16

D6

MA_DATA7

18

D7

MA_DATA8

21

D8

MA_DATA9

23

D9

MA_DATA10

33

D10

MA_DATA11

35

D11

MA_DATA12

22

D12

MA_DATA13

24

D13

MA_DATA14

34

D14

MA_DATA15

36

D15

MA_DATA16

39

D16

MA_DATA17

41

D17

MA_DATA18

51

D18

MA_DATA19

53

D19

MA_DATA20

40

D20

MA_DATA21

42

D21

MA_DATA22

50

D22

MA_DATA23

52

D23

MA_DATA24

57

D24

MA_DATA25

59

D25

MA_DATA26

67

D26

MA_DATA27

69

D27

MA_DATA28

56

D28

MA_DATA29

58

D29

MA_DATA30

68

D30

MA_DATA31

70

D31

MA_DATA32

129

D32

MA_DATA33

131

D33

MA_DATA34

141

D34

MA_DATA35

143

D35

MA_DATA36

130

D36

MA_DATA37

132

D37

MA_DATA38

140

D38

MA_DATA39

142

D39

MA_DATA40

147

D40

MA_DATA41

149

D41

MA_DATA42

157

D42

MA_DATA43

159

D43

MA_DATA44

146

D44

MA_DATA45

148

D45

MA_DATA46

158

D46

MA_DATA47

160

D47

MA_DATA48

163

D48

MA_DATA49

165

D49

MA_DATA50

175

D50

MA_DATA51

177

D51

MA_DATA52

164

D52

MA_DATA53

166

D53

MA_DATA54

174

D54

MA_DATA55

176

D55

MA_DATA56

181

D56

MA_DATA57

183

D57

MA_DATA58

191

D58

MA_DATA59

193

D59

MA_DATA60

180

D60

MA_DATA61

182

D61

MA_DATA62

192

D62

MA_DATA63

194

D63

MA_DQS#0

10

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

VSS31

VSS32

VSS33

GND1

138

139

144

205

206

GND2

MA_DQS#1VREFB_CA

27

MA_DQS#2

45

MA_DQS#3

62

MA_DQS#4

135

MA_DQS#5

152

MA_DQS#6

169

MA_DQS#7

186

MA_DATA[63:0] {9}

MA_DQS#[7:0] {9}

C91

1

1

ns

ns

+

+

CT7343_19

CT7343_19

220UF/2.5V,POSCAP

220UF/2.5V,POSCAP

+V1.5

C105

C105
10uF/6.3V,X5R

10uF/6.3V,X5R

Layout note:

+V0.75S

C99

C99
1uF/10V,X7R

1uF/10V,X7R

C92

C92

C0402

C0402

0.1UF/25V,Y5V

0.1UF/25V,Y5V

2.2UF/10V,X7R

2.2UF/10V,X7R

C100

C100

C0402

C0402

0.1UF/25V,Y5V

0.1UF/25V,Y5V

2

C93

C93

C94

C94

ns

ns

C0805

C0805

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C101

C101

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

⬉ᆍ䴴䖥

DDR slot VDD PIN

C102

C102
1uF/10V,X7R

1uF/10V,X7R

C95

C95

C0402

C0402

2.2UF/10V,X7R

2.2UF/10V,X7R

C106

C106
10uF/6.3V,X5R

10uF/6.3V,X5R

2.2UF/10V,X7R

2.2UF/10V,X7R

C107

C107
1uF/10V,X7R

1uF/10V,X7R

C96

C96

C0805

C0805

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C103

C103

C0805

C0805

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C98

C98

C97

C97

ns

ns

ns

ns

C0805

C0805

C0402

C0402

2.2UF/10V,X7R

2.2UF/10V,X7R

1, A minimum of 9 high frequency
capacitors are recommended to be
placed near each SO-DIMM of DDR2.
2, 2.2ȝF*5 per DIMM,0.1ȝF*4 per
DIMM,330ȝF*1 per DIMM

C104

C104

C0402

C0402

C108

C108
1uF/10V,X7R

1uF/10V,X7R

1

+V1.5

R492

R492
1K,1%

1K,1%

R0402

R0402

R493

R493
1K,1%

1K,1%

R0402

R0402

A A

5

VREFA_DDR3 VREFB_CA

VREFA_DDR3 {13}

+V1.5

R900

R900
1K,1%

1K,1%

R0402

R0402

R901

R901
1K,1%

1K,1%

R0402

R0402

C537

C537

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

4

C538

C538

2.2UF/10V,X7R

2.2UF/10V,X7R

C0805

C0805

close to DDR pin

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

Joseph
DDR3 SODIMM0

DDR3 SODIMM0

DDR3 SODIMM0

C49

C49

C49

1

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A

A

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of

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14 59Friday, May 07, 2010

14 59Friday, May 07, 2010

14 59Friday, May 07, 2010

5

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4

3

2

+V3.3S {6,8,14,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.5 {8,11,14,47,54,55,56}
+V0.75S {14,47,54}

1

203

204

VTT1

VTT2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

CS0

121

CS1

11

DQM0

28

DQM1

46

DQM2

63

DQM3

136

DQM4

153

DQM5

170

DQM6

187

DQM7

113

WE

115

CAS

110

RAS

73

CKE0

74

CKE1

101

CK0

103

CK0

102

CK1

104

CK1

116

ODT0

120

ODT1

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

200

SDA

202

SCL

197

SA0

201

SA1

199

VDDSPD

1

VREF_DQ

126

VREF_CA

198

EVENT#

30

RESET#

77

NC1

122

NC2

125

NCTEST

DDR3_SODIMM204_0

DDR3_SODIMM204_0

+V1.5+V0.75S

99

100

105

106

111

112

117

118

123

124

VDD175VDD276VDD381VDD482VDD587VDD688VDD793VDD894VDD9

VSS1

2

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

VSS23VSS38VSS49VSS513VSS614VSS719VSS820VSS925VSS1026VSS1131VSS1232VSS1337VSS1438VSS1543VSS1644VSS1748VSS1849VSS1954VSS2055VSS2160VSS2261VSS2365VSS2466VSS2571VSS2672VSS27

151

145

150

155

156

161

162

167

168

172

173

178

179

184

185

189

190

195

196

DIMM2

DIMM2

MB_DATA0

VSS36

VSS34

VSS35

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

VSS29

VSS30

VSS28

127

133

134

128

5

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

D0

MB_DATA1

7

D1

MB_DATA2

15

D2

MB_DATA3

17

D3

MB_DATA4

4

D4

MB_DATA5

6

D5

MB_DATA6

16

D6

MB_DATA7

18

D7

MB_DATA8

21

D8

MB_DATA9

23

D9

MB_DATA10

33

D10

MB_DATA11

35

D11

MB_DATA12

22

D12

MB_DATA13

24

D13

MB_DATA14

34

D14

MB_DATA15

36

D15

MB_DATA16

39

D16

MB_DATA17

41

D17

MB_DATA18

51

D18

MB_DATA19

53

D19

MB_DATA20

40

D20

MB_DATA21

42

D21

MB_DATA22

50

D22

MB_DATA23

52

D23

MB_DATA24

57

D24

MB_DATA25

59

D25

MB_DATA26

67

D26

MB_DATA27

69

D27

MB_DATA28

56

D28

MB_DATA29

58

D29

MB_DATA30

68

D30

MB_DATA31

70

D31

MB_DATA32

129

D32

MB_DATA33

131

D33

MB_DATA34

141

D34

MB_DATA35

143

D35

MB_DATA36

130

D36

MB_DATA37

132

D37

MB_DATA38

140

D38

MB_DATA39

142

D39

MB_DATA40

147

D40

MB_DATA41

149

D41

MB_DATA42

157

D42

MB_DATA43

159

D43

MB_DATA44

146

D44

MB_DATA45

148

D45

MB_DATA46

158

D46

MB_DATA47

160

D47

MB_DATA48

163

D48

MB_DATA49

165

D49

MB_DATA50

175

D50

MB_DATA51

177

D51

MB_DATA52

164

D52

MB_DATA53

166

D53

MB_DATA54

174

D54

MB_DATA55

176

D55

MB_DATA56

181

D56

MB_DATA57

183

D57

MB_DATA58

191

D58

MB_DATA59

193

D59

MB_DATA60

180

D60

MB_DATA61

182

D61

MB_DATA62

192

D62

MB_DATA63

194

D63

MB_DQS#0

10

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

VSS31

VSS32

VSS33

GND1

138

139

144

205

MB_DQS#1

27

MB_DQS#2

45

MB_DQS#3

62

MB_DQS#4

135

MB_DQS#5

152

MB_DQS#6

169

MB_DQS#7

186

GND2

206

MB_DATA[63:0] {9}

MB_DQS#[7:0] {9}

D D

MB_B_A[15:0]{9}

+V1.5

C117

C110

C110

C109

C109

C0805

C0805

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

10UF/6.3V,X5R

10UF/6.3V,X5R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C C

+V0.75S

B B

+V1.5

C121

C121

C120

C120

C0805

C0805

C0402

C0402

2.2UF/10V,X7R

2.2UF/10V,X7R

Layout note:

C383

C383
1uF/10V,X7R

1uF/10V,X7R

ns

ns

䖭޴Ͼ⬉ᆍᣓᥝњ

C46

0.1UF/25V,Y5V

0.1UF/25V,Y5V

ns

ns

C111

C111

ns

ns

C0402

C0402

2.2UF/10V,X7R

2.2UF/10V,X7R

+V1.5

C118

C118
10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C122

C122

C0402

C0402

2.2UF/10V,X7R

2.2UF/10V,X7R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

⬉ᆍ䴴䖥

C384

C384

1uF/10V,X7R

1uF/10V,X7R

ns

ns

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C112

C112

C113

C113

C0805

C0805

C0805

C0805

0.1UF/25V,Y5V

0.1UF/25V,Y5V

2.2UF/10V,X7R

2.2UF/10V,X7R

C119

C119
10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C123

C123

C124

C124

C0805

C0805

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

DDR SLOT VDD PIN

C385

C385
1uF/10V,X7R

1uF/10V,X7R

ns

ns

+V3.3S

close to DDR pin

C129

C129

C0402

C0402

C114

C114

C115

C115

ns

ns

C0402

C0402

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

C125

C125

ns

ns

ns

ns

C0402

C0402

0.1UF/25V,Y5V

0.1UF/25V,Y5V

2.2UF/10V,X7R

2.2UF/10V,X7R

C386

C386
1uF/10V,X7R

1uF/10V,X7R

ns

ns

Note:
SO-DIMM1 SPD Address is 0xA4
SO-DIMM1 TS Address is 0x34

C130

C130

2.2UF/10V,X7R

2.2UF/10V,X7R

C0805

C0805

C116

C116

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C126

C126

ns

ns

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

C117

C0402

C0402

C127

C127

C0805

C0805

VREFB_DDR3

C128

C128

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

close to DDR pin

DDR3_DRAMRST#{8,14}

MB_B_BS0{9}
MB_B_BS1{9}
MB_B_BS2{9}

MB_DM[7:0]{9}

MB_B_WE#{9}
MB_B_CAS#{9}
MB_B_RAS#{9}

M_CKE2{9}
M_CKE3{9}

M_CLK_DDR2{9}
M_CLK_DDR#2{9}
M_CLK_DDR3{9}
M_CLK_DDR#3{9}

M_ODT2{9}
M_ODT3{9}

MB_DQS[7:0]{9}

SMB_DATA_S{6,14,24,37}
SMB_CLK_S{6,14,24,37}

R54 10K R0402R54 10K R0402
R55 10K R0402R55 10K R0402

DIM_EXTTS#1{8}

M_CS#2{9}
M_CS#3{9}

C131

C131

2.2UF/10V,X7R

2.2UF/10V,X7R

C0805

C0805

VREFA_CA

MB_B_A0
MB_B_A1
MB_B_A2
MB_B_A3
MB_B_A4
MB_B_A5
MB_B_A6
MB_B_A7
MB_B_A8
MB_B_A9
MB_B_A10
MB_B_A11
MB_B_A12
MB_B_A13
MB_B_A14
MB_B_A15

MB_DQS0
MB_DQS1
MB_DQS2
MB_DQS3
MB_DQS4
MB_DQS5
MB_DQS6
MB_DQS7

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

+V1.5

R494

R494
1K,1%

1K,1%

R0402

R0402

VREFB_DDR3

R495

R495
1K,1%

1K,1%

R0402

A A

R0402

VREFB_DDR3 {13}

+V1.5

R902

R902
1K,1%

1K,1%

R0402

R0402

R903

R903
1K,1%

1K,1%

R0402

R0402

C539

C539

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C0402

C0402

VREFA_CAVREFA_CA

C540

C540

2.2UF/10V,X7R

2.2UF/10V,X7R

C0805

C0805

close to DDR pin

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Joseph
DDR3 SODIMM1

DDR3 SODIMM1

DDR3 SODIMM1

C49

C49

C49

1

A

A

A

of

of

of

15 59Friday, May 07, 2010

15 59Friday, May 07, 2010

15 59Friday, May 07, 2010

5

4

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

5

http://hobi-elektronika.net

D D

4

+V1.8S +V1.8S

U26

U26

1

VSS

2

VDD

10
11
12
13
14
15
16
17
18
19
20
21

3
4
5
6
7
8
9

TS3DV421

TS3DV421

PM

PM

TMDS2+
TMDS2­VSS1
TMDS1+
TMDS1­VDD1
SEL
VSS2
TMDS0+
TMDS0­VSS3
TMDSCLK+
TMDSCLK­VDD2
VSS4
VDD3
VSS5
VDD4
VSS6

ATMDS2+

ATMDS2-

ATMDS1+

ATMDS1-

ATMDS0+

ATMDS0-

ATMDSCLK+

ATMDSCLK-

BTMDS2+

BTMDS2-

BTMDS1+

BTMDS1-

BTMDS0+

BTMDS0-

BTMDSCLK+

BTMDSCLK-

LVDS_CLKAP{22}
LVDS_CLKAM{22}

LVDS_YAP2{22}

LVDS_YAM2{22}
LVDS_SEL{27}

LVDS_YAP1{22}

LVDS_YAM1{22}

LVDS_YAP0{22}

LVDS_YAM0{22}

VDD7

VSS8

VDD6

VSS7

VDD5

3

+V3.3S {6,8,14,15,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.8S {11,27,29,30,47,54,55}

43

GND

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

PCH_LVDS_CLKAP {26}
PCH_LVDS_CLKAM {26}
PCH_LVDS_YAP2 {26}
PCH_LVDS_YAM2 {26}
PCH_LVDS_YAP1 {26}
PCH_LVDS_YAM1 {26}
PCH_LVDS_YAP0 {26}
PCH_LVDS_YAM0 {26}

GPU_LVDS_CLKAP {20}
GPU_LVDS_CLKAM {20}
GPU_LVDS_YAP2 {20}
GPU_LVDS_YAM2 {20}
GPU_LVDS_YAP1 {20}
GPU_LVDS_YAM1 {20}
GPU_LVDS_YAP0 {20}
GPU_LVDS_YAM0 {20}

2

1

C C

LVDS_DDC_SEL{27}
G_SMB_CLK{21}

G_SMB_DATA{21} LVDS_BKLTEN {22}

B B

PCH_LVDS_CLKAP{26}
PCH_LVDS_CLKAM{26}
PCH_LVDS_YAP2{26}
PCH_LVDS_YAM2{26}
PCH_LVDS_YAP1{26}
PCH_LVDS_YAM1{26}

PCH_LVDS_YAP0{26}

PCH_LVDS_YAM0{26}

PCH_LVDS_BKLTEN{26}

PCH_LVDS_VDDEN{26}

PCH_DDC_CLK{26}

A A

PCH_DDC_DATA{26}

1
2
3
4
5

TS5A23157

TS5A23157

PM

PM

RN4 0

RN4 0

RA0402_4 GM

RA0402_4 GM

RN5 0

RN5 0

RA0402_4 GM

RA0402_4 GM

RN6 0

RN6 0

RA0402_4 GM

RA0402_4 GM

RN7 0

RN7 0

RA0402_4 GM

RA0402_4 GM

R893 0 R0402GMR893 0 R0402GM

R894 0 R0402GMR894 0 R0402GM

U27

U27

IN1
NO1
GND
NO2
IN2

R891 0 R0402GMR891 0 R0402GM

R892 0 R0402GMR892 0 R0402GM

COM1

NC1

V+

NC2

COM2

1 2
3 4
1 2
3 4
1 2
3 4
1 2
3 4

10
9
8
7
6

+V3.3S

EDID_CLK {22}
PCH_DDC_CLK {26}

PCH_DDC_DATA {26}

EDID_DATA {22}

LVDS_CLKAP {22}
LVDS_CLKAM {22}
LVDS_YAP2 {22}
LVDS_YAM2 {22}
LVDS_YAP1 {22}
LVDS_YAM1 {22}
LVDS_YAP0 {22}
LVDS_YAM0 {22}

LVDS_BKLTEN {22}

LVDS_VDDEN {22}

EDID_CLK {22}

EDID_DATA {22}

GPU_LVDS_BKLTEN_R{21}

PCH_LVDS_BKLTEN{26}

GPU_LVDS_VDDEN{21}

PCH_LVDS_VDDEN{26}

1
2
3

ts5a3157

ts5a3157

PM

PM

1
2
3

U28

U28

NO
GND
NC

ts5a3157

ts5a3157

PM

PM

+V3.3S

6

IN

5

V+

4

COM

U29

U29

6

NO

IN

5

GND

V+

4

NC

COM

LVDS_BLT_SEL {27}

+V3.3S

LVDS_SEL_PCH {27}

LVDS_VDDEN {22}

5

4

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

Joseph
DDR3 Decoupling

DDR3 Decoupling

DDR3 Decoupling

C49

C49

C49

1

A

A

A

of

of

of

16 59Friday, May 07, 2010

16 59Friday, May 07, 2010

16 59Friday, May 07, 2010

5

http://hobi-elektronika.net

4

3

+V3.3GPU {20,21,36,38,55}
+VGA_CORE {50}
+V1.05GPU {18,19,20,55}

2

1

D D

EC_GPU_RST#{42}

BUF_PLT_RST#{8,27,34,35,37,41,42}

PEG_RXP[15..0]{7}
PEG_RXN[15..0]{7}
PEG_TXP[15..0]{7}
PEG_TXN[15..0]{7}

+V3.3GPU

+V3.3GPU

GR53

GR53

GR4

GR4

10K

10K

10K

S_Bot

S_Bot

EC_GPU_RST#

10K

PM

PM

PCIE_CLKREQ

PM

PM

C C

B B

EC_GPU_RST#

PCIE_CLKREQ{24}
CLK_PCIE_N11M{24}

CLK_PCIE_N11M#{24}

PEG_RXP[15..0]
PEG_RXN[15..0]
PEG_TXP[15..0]
PEG_TXN[15..0]

GR1 0 nsGR1 0 ns

+V3.3GPU

53

GU1

GU1

VCC

VCC

1
2

GND

GND

SN74AHC1G08DBV

SN74AHC1G08DBV

SOT23_5

SOT23_5

PM

PM

PEG_TXP15
PEG_TXN15

PEG_RXP15
PEG_RXN15

PEG_TXP14
PEG_TXN14

PEG_RXP14
PEG_RXN14

PEG_TXP13
PEG_TXN13

PEG_RXP13
PEG_RXN13

PEG_TXP12
PEG_TXN12

PEG_RXP12
PEG_RXN12

PEG_TXP11
PEG_TXN11

PEG_RXP11
PEG_RXN11

PEG_TXP10
PEG_TXN10

PEG_RXP10
PEG_RXN10

PEG_TXP9
PEG_TXN9

PEG_RXP9
PEG_RXN9

PEG_TXP8
PEG_TXN8

PEG_RXP8
PEG_RXN8

PEG_TXP7
PEG_TXN7

PEG_RXP7
PEG_RXN7

PEG_TXP6
PEG_TXN6

PEG_RXP6
PEG_RXN6

PEG_TXP5
PEG_TXN5

PEG_RXP5
PEG_RXN5

PEG_TXP4
PEG_TXN4

PEG_RXP4
PEG_RXN4

PEG_TXP3
PEG_TXN3

PEG_RXP3
PEG_RXN3

PEG_TXP2
PEG_TXN2

PEG_RXP2
PEG_RXN2

PEG_TXP1
PEG_TXN1

PEG_RXP1
PEG_RXN1

PEG_TXP0
PEG_TXN0

PEG_RXP0
PEG_RXN0

4

GC1

GC1

0.1uF/10V,X7R

0.1uF/10V,X7R

ns

ns

GPU_RST#

GR2

GR2
100K

100K

PM

PM

GC14 0.1UF/10V,X7R

GC14 0.1UF/10V,X7R

GC17 0.1UF/10V,X7R

GC17 0.1UF/10V,X7R

GC21 0.1UF/10V,X7R

GC21 0.1UF/10V,X7R

GC10 0.1UF/10V,X7R

GC10 0.1UF/10V,X7R

GC22 0.1UF/10V,X7R

GC22 0.1UF/10V,X7R

GC23 0.1UF/10V,X7R

GC23 0.1UF/10V,X7R

GC11 0.1UF/10V,X7R

GC11 0.1UF/10V,X7R

GC26 0.1UF/10V,X7R

GC26 0.1UF/10V,X7R

GC30 0.1UF/10V,X7R

GC30 0.1UF/10V,X7R

GC31 0.1UF/10V,X7R

GC31 0.1UF/10V,X7R

GC37 0.1UF/10V,X7R

GC37 0.1UF/10V,X7R

GC38 0.1UF/10V,X7R

GC38 0.1UF/10V,X7R

GC39 0.1UF/10V,X7R

GC39 0.1UF/10V,X7R

GC42 0.1UF/10V,X7R

GC42 0.1UF/10V,X7R

GC46 0.1UF/10V,X7R

GC46 0.1UF/10V,X7R

GC47 0.1UF/10V,X7R

GC47 0.1UF/10V,X7R

GC51 0.1UF/10V,X7R

GC51 0.1UF/10V,X7R

GC52 0.1UF/10V,X7R

GC52 0.1UF/10V,X7R

GC53 0.1UF/10V,X7R

GC53 0.1UF/10V,X7R

GC54 0.1UF/10V,X7R

GC54 0.1UF/10V,X7R

GC58 0.1UF/10V,X7R

GC58 0.1UF/10V,X7R

GC59 0.1UF/10V,X7R

GC59 0.1UF/10V,X7R

GC60 0.1UF/10V,X7R

GC60 0.1UF/10V,X7R

GC61 0.1UF/10V,X7R

GC61 0.1UF/10V,X7R

GC67 0.1UF/10V,X7R

GC67 0.1UF/10V,X7R

GC68 0.1UF/10V,X7R

GC68 0.1UF/10V,X7R

GC69 0.1UF/10V,X7R

GC69 0.1UF/10V,X7R

GC70 0.1UF/10V,X7R

GC70 0.1UF/10V,X7R

GC74 0.1UF/10V,X7R

GC74 0.1UF/10V,X7R

GC75 0.1UF/10V,X7R

GC75 0.1UF/10V,X7R

GC76 0.1UF/10V,X7R

GC76 0.1UF/10V,X7R

GC77 0.1UF/10V,X7R

GC77 0.1UF/10V,X7R

GR2 is used for test only, so it
can be unstuff for cost saving.

AM16

PCIE_CLKREQ

AR13

GR3 200,1% R0402

GR3 200,1% R0402

AJ17

ns

ns

AJ18
AR16

AR17

AL17
AM17

PM

PM

PM

PM

AP17
AN17

AM18
AM19

PM

PM

AN19

PM

PM

AP19
AL19

AK19

PM

PM

AR19

PM

PM

AR20
AL20

AM20

PM

PM

PM

PM

AP20
AN20

AM21
AM22

PM

PM

PM

PM

AN22
AP22

AL22
AK22

PM

PM

PM

PM

AR22
AR23

AL23
AM23

PM

PM

AP23

PM

PM

AN23
AM24

AM25

PM

PM

AN25

PM

PM

AP25
AL25

AK25

PM

PM

PM

PM

AR25
AR26

AL26
AM26

PM

PM

PM

PM

AP26
AN26

AM27
AM28

PM

PM

PM

PM

AN28
AP28

AL28
AK28

PM

PM

AR28

PM

PM

AR29
AK29

AL29

PM

PM

AP29

PM

PM

AN29
AM29

AM30

PM

PM

PM

PM

AN31
AP31

AM31
AM32

PM

PM

PM

PM

AR31
AR32

AN32
AP32

PM

PM

PM

PM

AR34

CLOSE
TO N11

AP34

U3A

U3A

PEX_RST#
PEX_CLKREQ

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

PEX_REFCLK
PEX_REFCLK#

PEX_TX0
PEX_TX0#

PEX_RX0
PEX_RX0#

PEX_TX1
PEX_TX1#

PEX_RX1
PEX_RX1#

PEX_TX2
PEX_TX2#

PEX_RX2
PEX_RX2#

PEX_TX3
PEX_TX3#

PEX_RX3
PEX_RX3#

PEX_TX4
PEX_TX4#

PEX_RX4
PEX_RX4#

PEX_TX5
PEX_TX5#

PEX_RX5
PEX_RX5#

PEX_TX6
PEX_TX6#

PEX_RX6
PEX_RX6#

PEX_TX7
PEX_TX7#

PEX_RX7
PEX_RX7#

PEX_TX8
PEX_TX8#

PEX_RX8
PEX_RX8#

PEX_TX9
PEX_TX9#

PEX_RX9
PEX_RX9#

PEX_TX10
PEX_TX10#

PEX_RX10
PEX_RX10#

PEX_TX11
PEX_TX11#

PEX_RX11
PEX_RX11#

PEX_TX12
PEX_TX12#

PEX_RX12
PEX_RX12#

PEX_TX13
PEX_TX13#

PEX_RX13
PEX_RX13#

PEX_TX14
PEX_TX14#

PEX_RX14
PEX_RX14#

PEX_TX15
PEX_TX15#

PEX_RX15
PEX_RX15#

NB10_G128

NB10_G128

PM

PM

PCI_EXPRESS

PCI_EXPRESS

PEX_IOVDD_01
PEX_IOVDD_02
PEX_IOVDD_03
PEX_IOVDD_04
PEX_IOVDD_05

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10

PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24
PEX_IOVDDQ_25

PEX_SVDD_3V3_1
PEX_SVDD_3V3_2

VDD_SENSE1
VDD_SENSE2
VDD_SENSE3
GND_SENSE1
GND_SENSE2
GND_SENSE3

PEX_CAL_PU_GND/NC

NC_10
NC_11
NC_14
NC_16
NC_17
NC_18
NC_21
NC_22
NC_23

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5

PEX_PLLVDD

PEX_TERMP

TESTMODE

AK16
AK17
AK21
AK24
AK27

PEX_IOVDD+PEX_IOVDDQ:MAX:2200mA

AG11
AG12
AG13
AG15

0.1uF/10V,X7R

0.1uF/10V,X7R

AG16
AG17
AG18

PM

PM

AG22
AG23
AG24

AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

A2

NC_1

AA4

NC_2

AB4

NC_3

AB7

NC_4

AC5

NC_5

AD6

NC_6

AF6

NC_7

AG6

NC_8

AJ5

NC_9

AK15
AL7
E7
H32
M7
P6
U7
V6
Y4

MAX:120mA

F7
AG19

J10
J11
J12
J13
J9

D35
P7
AD20
AD19

R57 0 R0402PMR57 0 R0402

R7
E35

PM

MAX:120mA

AG14

T2 nsT2 ns

AG20

GR5 2.49K,1% R0402 PMGR5 2.49K,1% R0402 PM

AG21

GR6 10K R0402nsGR6 10K R0402

AP35

GR7 10K R0402PMGR7 10K R0402

PM

S46 VerA:Add reserved pull up resistor
on TESTMODE follewed nvidia suggest

Under GPU Near GPU

GC3

GC3

GC4

GC4

0.1uF/10V,X7R

0.1uF/10V,X7R

C0402

C0402

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

PM

PM

PM

PM

Under GPU Near GPU

GC18

GC18

GC16

GC16

GC15

GC15

C0402

C0402

0.1uF/10V,X7R

0.1uF/10V,X7R
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

PM

PM

PM

PM

PM

PM

MAX:19.6A

GC12

GC12

GC24

GC24

0.047uF/16V,X7R

0.047uF/16V,X7R

PM

PM

GC32

GC32

0.047uF/16V,X7R

0.047uF/16V,X7R

PM

PM

GC40

GC40

C0402

C0402

0.01uF/25V,X7R

0.01uF/25V,X7R

PM

PM

GC48

GC48

C0402

C0402

0.01uF/25V,X7R

0.01uF/25V,X7R

PM

PM

MAX:180mA

NVVDD_SENSE {50}

ns

0.047uF/16V,X7R

0.047uF/16V,X7R

0.022uF/16V,X7R

0.022uF/16V,X7R

0.01uF/25V,X7R

0.01uF/25V,X7R

4700pF/25V,X7R

4700pF/25V,X7R

0.1uF/10V,X7R

0.1uF/10V,X7R

PM

PM

+V3.3GPU

PM

PM

PM

PM

PM

PM

PM

PM

GC63

GC63

C0402

C0402

GC33

GC33

C0402

C0402

GC41

GC41

GC49

GC49

0.22uF/10V,X7R

0.22uF/10V,X7R

0.01uF/25V,X7R

0.01uF/25V,X7R

0.1uF/10V,X7R

0.1uF/10V,X7R

PM

PM

0.1uF/10V,X7R

0.1uF/10V,X7R

PM

PM

Near GPU

1uF/10V,X7R

1uF/10V,X7R

GC25

GC25

PM

PM

PM

PM

GC43

GC43

C0402

C0402

PM

PM

GC50

GC50

C0402

C0402

4700pF/25V,X7R

4700pF/25V,X7R

PM

PM

GC55

GC55

GC64

GC64

GC71

GC71

C0603

C0603

PM

PM

+V1.05GPU

GC8

GC5

GC5

C0402

C0402

PM

PM

GC13

GC13

C0402

C0402

Under GPU

0.22uF/10V,X7R

0.22uF/10V,X7R

GC45

GC45

C0402

C0402

0.022uF/16V,X7R

0.022uF/16V,X7R

0.01uF/25V,X7R

0.01uF/25V,X7R

PM

PM

PM

PM

GC6

GC6

C0805

C0805

4.7uF/10V,X5R

4.7uF/10V,X5R

PM

PM

GC9

GC9

C0805

C0805

4.7uF/10V,X5R

4.7uF/10V,X5R

PM

PM

GC27

GC27

C0603

C0603

PM

PM

GC35

GC35

C0402

C0402

0.022uF/16V,X7R

0.022uF/16V,X7R

PM

PM

GC44

GC44

PM

PM

Near GPUUnder GPU

GC56

GC56

C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

GC72

GC72

C0805

C0805

4.7uF/10V,X5R

4.7uF/10V,X5R

GFB1

GFB1

1 2

GC8

C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

PM

PM

+V1.05GPU

GC20

GC20

GC19

GC19

C0805

C0805

C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

4.7uF/10V,X5R

4.7uF/10V,X5R

PM

PM

PM

PM

+VGA_CORE

Near GPU

GC29

GC29

GC28

GC28

C0805

C0805

4.7uF/10V,X5R

4.7uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

PM

PM

PM

PM

GC36

GC36

0.022uF/16V,X7R

0.022uF/16V,X7R

PM

PM

+V3.3GPU

GC57

GC57

C0805

C0805

4.7uF/10V,X5R

4.7uF/10V,X5R

PM

PM

S46 VerA:Delete some caps
followed N10M DG 090327

+V1.05GPU

FB0603

FB0603

120ohm@100MHz,500mA

120ohm@100MHz,500mA

GC73

GC73

C0805

C0805

PM

PM

4.7uF/10V,X5R

4.7uF/10V,X5R

PM

PM

Layout Notice

Under GPU:
The total trace length measured from GPU ball to cap is no more than 150 mil
Near GPU:
The total trace length measured from GPU ball to cap is no more than 750 mil

U3F

U3F

+VGA_CORE +VGA_CORE

AB11

VDD_001

AB13

VDD_002

AB15

VDD_003

AB17

VDD_004

AB19

VDD_005

AB21

VDD_006

AB23

VDD_007

AB25

VDD_008

AC11

VDD_009

AC12

VDD_010

AC13

VDD_011

AC14

VDD_012

AC15

VDD_013

AC16

VDD_014

AC17

VDD_015

AC18

VDD_016

AC19

VDD_017

AC20

VDD_018

AC21

VDD_019

AC22

VDD_020

AC23

VDD_021

AC24

VDD_022

AC25

VDD_023

AD12

VDD_024

AD14

VDD_025

AD16

VDD_026

AD18

VDD_027

AD22

VDD_028

AD24

VDD_029

L11

VDD_030

L12

VDD_031

L13

VDD_032

L14

VDD_033

L15

VDD_034

L16

VDD_035

L17

VDD_036

L18

VDD_037

L19

VDD_038

L20

VDD_039

L21

VDD_040

L22

VDD_041

L23

VDD_042

L24

VDD_043

L25

VDD_044

M12

VDD_045

M14

VDD_046

M16

VDD_047

M18

VDD_048

M20

VDD_049

M22

VDD_050

M24

VDD_051

P11

VDD_052

P13

VDD_053

P15

VDD_054

P17

VDD_055

P19

VDD_056

NB10_G128

NB10_G128

PM

PM

U3G

NVVDD

NVVDD

P21

VDD_057

P23

VDD_058

P25

VDD_059

R11

VDD_060

R12

VDD_061

R13

VDD_062

R14

VDD_063

R15

VDD_064

R16

VDD_065

R17

VDD_066

R18

VDD_067

R19

VDD_068

R20

VDD_069

R21

VDD_070

R22

VDD_071

R23

VDD_072

R24

VDD_073

R25

VDD_074

T12

VDD_075

T14

VDD_076

T16

VDD_077

T18

VDD_078

T20

VDD_079

T22

VDD_080

T24

VDD_081

V11

VDD_082

V13

VDD_083

V15

VDD_084

V17

VDD_085

V19

VDD_086

V21

VDD_087

V23

VDD_088

V25

VDD_089

W11

VDD_090

W12

VDD_091

W13

VDD_092

W14

VDD_093

W15

VDD_094

W16

VDD_095

W17

VDD_096

W18

VDD_097

W19

VDD_098

W20

VDD_099

W21

VDD_100

W22

VDD_101

W23

VDD_102

W24

VDD_103

W25

VDD_104

Y12

VDD_105

Y14

VDD_106

Y16

VDD_107

Y18

VDD_108

Y20

VDD_109

Y22

VDD_110

Y24

VDD_111

U3G

GND

GND

E15

GND_096

E18

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095

NB10_G128

NB10_G128

PM

PM

GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191

E24
E27
E30
E6
E9
F2
F31
F34
F5
J2
J31
J34
J5
L9
M11
M13
M15
M17
M19
M2
M21
M23
M25
M31
M34
M5
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R31
R34
R5
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V12
V14
V16
V18
V2
V20
V22
V24
V31
V5
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25

AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19

AA2
AA20
AA21
AA22
AA23
AA24
AA25
AA34

AA5
AB12
AB14
AB16
AB18
AB20
AB22
AB24

AC9
AD11
AD13
AD15
AD17

AD2
AD21
AD23
AD25
AD31
AD34

AD5
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25

AG2

AG31
AG34

AG5

AK2
AK31
AK34

AK5
AL12
AL15
AL18
AL21
AL24
AL27
AL30

AL6

AL9

AN2
AN34
AP12
AP15
AP18
AP21
AP24
AP27

AP3
AP30
AP33

AP6

AP9

B12

B15

B21

B24

B27

B3
B30
B33

B6

B9

C2
C34
E12

VerA: all PCIE singala lane reversal llh0523

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

D

D

D

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

1

Joseph
N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

N11M PCIE&PWR&GND

C49

C49

C49

of

of

of

17 59Friday, May 07, 2010

17 59Friday, May 07, 2010

17 59Friday, May 07, 2010

A

A

A

5

http://hobi-elektronika.net

U3B

U3B

FBAD_0

L32

FBA_D0

FBAD_1
FBAD_2
FBAD_3
FBAD_4
FBAD_5
FBAD_6
FBAD_7
FBAD_8
FBAD_9
FBAD_10
FBAD_11
FBAD_12

+V1.5GPU

GR21

GR21
1K,1%

1K,1%

ns

ns

GR22

GR22

2.49K,1%

2.49K,1%

ns

ns

FBAD_13
FBAD_14
FBAD_15
FBAD_16
FBAD_17
FBAD_18
FBAD_19
FBAD_20
FBAD_21
FBAD_22
FBAD_23
FBAD_24
FBAD_25
FBAD_26
FBAD_27
FBAD_28
FBAD_29
FBAD_30
FBAD_31
FBAD_32
FBAD_33
FBAD_34
FBAD_35
FBAD_36
FBAD_37
FBAD_38
FBAD_39
FBAD_40
FBAD_41
FBAD_42
FBAD_43
FBAD_44
FBAD_45
FBAD_46
FBAD_47
FBAD_48
FBAD_49
FBAD_50
FBAD_51
FBAD_52
FBAD_53
FBAD_54
FBAD_55
FBAD_56
FBAD_57
FBAD_58
FBAD_59
FBAD_60
FBAD_61
FBAD_62
FBAD_63

FBADQM_0
FBADQM_1
FBADQM_2
FBADQM_3
FBADQM_4
FBADQM_5
FBADQM_6
FBADQM_7

FBADQS_0
FBADQS_1
FBADQS_2
FBADQS_3
FBADQS_4
FBADQS_5
FBADQS_6
FBADQS_7

FBADQS_0#
FBADQS_1#
FBADQS_2#
FBADQS_3#
FBADQS_4#
FBADQS_5#
FBADQS_6#
FBADQS_7#

GC92

GC92

0.01uF/16V,X7R

0.01uF/16V,X7R

ns

ns

+V1.5GPU

+V1.5GPU

1000pF/25V,X7R

1000pF/25V,X7R

GC101

GC101

1000pF/25V,X7R

1000pF/25V,X7R

PM

PM

GC108

GC108

PM

PM

D D

C C

B B

AM33
AL33
AK30
AK32

AH30
AH33
AH35
AH34
AH32

AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35

AF32
AL32
AL34
AF35

AE31

AC33

AD32

AC34

AG29
AH29
AD29
AE29

N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32

R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31

AJ30

AJ33

P32

H34

J30

P30

L34

H35

J32

N31
AJ32

AJ34

L35

G35

H31

N32
AJ31

AJ35

P29

R29

L29

M29

J27

FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_WDS0/NC
FBA_WDS0#/NC
FBA_WDS1/NC
FBA_WDS1#/NC
FBA_WDS2/NC
FBA_WDS2#/NC
FBA_WDS3/NC
FBA_WDS3#/NC

FB_VREF

NB10_G128

NB10_G128

PM

PM

GC102

GC102
1000pF/25V,X7R

1000pF/25V,X7R

PM

PM

GC109

GC109
1000pF/25V,X7R

1000pF/25V,X7R

PM

PM

FPA

FPA

PM

PM

GC103

GC103

0.01uF/16V,X7R

0.01uF/16V,X7R

PM

PM

GC110

GC110

0.01uF/16V,X7R

0.01uF/16V,X7R

FBVDDQ0
FBVDDQ1
FBVDDQ2
FBVDDQ3
FBVDDQ4
FBVDDQ5
FBVDDQ6
FBVDDQ7
FBVDDQ8

FBVDDQ9
FBVDDQ10
FBVDDQ11
FBVDDQ12
FBVDDQ13
FBVDDQ14
FBVDDQ15
FBVDDQ16
FBVDDQ17
FBVDDQ18
FBVDDQ19
FBVDDQ20
FBVDDQ21
FBVDDQ22
FBVDDQ23
FBVDDQ24
FBVDDQ25
FBVDDQ26

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9

FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27

FBA_CMD28
FBA_CMD29/NC
FBA_CMD30/NC

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

FBA_DEBUG

FB_DLLAVDD0

FB_PLLAVDD0

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22

V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29

T32
T31
AC31
AC30

T30

AG27
AF27

GC104

GC104

0.1uF/10V,X7R

0.1uF/10V,X7R

PM

PM

GC111

GC111

0.1uF/10V,X7R

0.1uF/10V,X7R

PM

PM

MAX:5700mA

FBA_A4
FBA_RAS#
FBA_A5
FBA_BA1

FBB_A2
FBB_A4
FBB_A3

FBB_CS#
FBA_A11
FBA_CAS#

FBA_WE#
FBA_BA0
FBB_A5
FBA_A12
FBA_RST
FBA_A7
FBA_A10
FBA_CKE
FBA_A0
FBA_A9
FBA_A6
FBA_A2
FBA_A8
FBA_A3
FBA_A1
FBA_A13
FBA_BA2

FBB_ODT0

FBA_CS0#

FBA_ODT0

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

GC105

GC105

1uF/10V,X7R

1uF/10V,X7R

PM

PM

GC112

GC112

1uF/10V,X7R

1uF/10V,X7R

PM

PM

FBB_CKE

T132 nsT132 ns

MAX:100mA

C0603

C0603

C0603

C0603

GC86

GC86

0.1uF/10V,X7R

0.1uF/10V,X7R

PM

PM

0.1uF/10V,X7R

0.1uF/10V,X7R

PM

PM

PM

PM

GC79

GC79

1uF/10V,X5R

1uF/10V,X5R

PM

PM

GC106

GC106

C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

PM

PM

GC113

GC113

C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

GC80

GC80

0.047uF/16V,X7R

0.047uF/16V,X7R

PM

PM

GC84

GC84

0.047uF/16V,X7R

0.047uF/16V,X7R

PM

PM

Near GPU

GC89

GC89

PM

PM

PM

PM

PM

PM

PM

PM

GC90

GC90

4.7uF/10V,X5R

4.7uF/10V,X5R

C0805

C0805

PM

PM

GC107

GC107

C0805

C0805

4.7uF/10V,X5R

4.7uF/10V,X5R

GC114

GC114

C0805

C0805

4.7uF/10V,X5R

4.7uF/10V,X5R

GC81

GC81

0.1uF/10V,X7R

0.1uF/10V,X7R

GC78

GC78

0.1uF/10V,X7R

0.1uF/10V,X7R

GFB2

GFB2

120ohm@100MHz,500mA

120ohm@100MHz,500mA

1 2

Near GPUUnder GPU

PM

PM

PM

PM

FB0603PM

FB0603PM

+V1.5GPU

GC82

GC82

4.7uF/10V,X5R

4.7uF/10V,X5R

GC85

GC85

4.7uF/10V,X5R

4.7uF/10V,X5R

+V1.05GPU

+V1.5GPU

4

FBB_VREF1

FBB_VREF3

FBAD_6
FBAD_1
FBAD_7
FBAD_4
FBAD_3
FBAD_0
FBAD_5
FBAD_2
FBADQS_0#
FBADQS_0

FBAD_60
FBAD_59
FBAD_61
FBAD_56
FBAD_63
FBAD_58
FBAD_62
FBAD_57

FBADQS_7

+V1.5GPU

+V1.5GPU

U21

U21

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

DDR3

PM

PM

U23

U23

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

DDR3

PM

PM

A15/BA3

RESET#

A15/BA3

RESET#

FBA_A0

N3

A0

FBA_A1

P7

A1

FBA_A2

P3

A2

FBA_A3

N2

A3

FBA_A4

P8

A4

FBA_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBA_ODT0

K1

ODT0

J1

ODT1

FBA_CS0#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_0

D3

DMU

FBADQM_3

E7

DML

FBA_CLK0

J7

CK

FBA_CLK0#

K7

CK#

FBA_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_25

E3

DQL0

FBAD_27

F7

DQL1

FBAD_28

F2

DQL2

FBAD_29

F8

DQL3

FBAD_26

H3

DQL4

FBAD_30

H8

DQL5

FBAD_24

G2

DQL6

FBAD_31

H7

DQL7

FBADQS_3#

G3

DQSL#

FBADQS_3

F3

DQSL

FBA_A0

N3

A0

FBA_A1

P7

A1

FBB_A2

P3

A2

FBB_A3

N2

A3

FBB_A4

P8

A4

FBB_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBB_ODT0

K1

ODT0

J1

ODT1

FBB_CS#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_7

D3

DMU

FBADQM_4

E7

DML

FBA_CLK1

J7

CK

FBA_CLK1#

K7

CK#

FBB_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_32

E3

DQL0

FBAD_36

F7

DQL1

FBAD_33

F2

DQL2

FBAD_37

F8

DQL3

FBAD_35

H3

DQL4

FBAD_39

H8

DQL5

FBAD_34

G2

DQL6

FBAD_38

H7

DQL7

FBADQS_4#FBADQS_7#

G3

DQSL#

FBADQS_4

F3

DQSL

3

FBB_CKE

FBA_CKE
FBA_RST

GR17

GR17
10K

10K

PM

PM

+V1.5GPU

GR61

GR61
243,1%

243,1%

PM

PM

ᕙ⹂ᅮ

+V1.5GPU +V1.5GPU

GR64

GR64
1K,1%

1K,1%

PM

PM

FBB_VREF3 FBB_VREF4

GR69

GR69
1K,1%

1K,1%

PM

PM

GR67

GR67
243,1%

243,1%

PM

PM

ᕙ⹂ᅮ

GR18

GR18
10K

10K

PM

PM

GR13

GR13
1K,1%

1K,1%

PM

PM

GR12

GR12
1K,1%

1K,1%

PM

PM

GC176

GC176

0.01uF/16V,X7R

0.01uF/16V,X7R

PM

PM

+V1.05GPU {17,19,20,55}
+V1.5GPU {19,55}

FBB_VREF1

GC88

GC88

0.01uF/16V,X7R

0.01uF/16V,X7R

PM

PM

2

+V1.5GPU

U22

U22

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

FBB_VREF2

FBAD_13
FBAD_11
FBAD_14
FBAD_8
FBAD_12
FBAD_10
FBAD_15
FBAD_9
FBADQS_1#
FBADQS_1

FBAD_48
FBAD_52
FBAD_50
FBAD_54
FBAD_51
FBAD_55
FBAD_49
FBAD_53
FBADQS_6#
FBADQS_6

+V1.5GPU

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

DDR3

PM

PM

U24

U24

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

DDR3

PM

PM

+V1.5GPU

GR16

GR16
1K,1%

1K,1%

PM

PM

GR19

GR19

FBB_VREF2

10K

10K

PM

PM

GC91

GC91

GR20

GR20

0.01uF/16V,X7R

0.01uF/16V,X7R

1K,1%

1K,1%

PM

PM

PM

PM

GR66

GR66
1K,1%

1K,1%

PM

PM

GC177

GC177

GR70

GR70

0.01uF/16V,X7R

0.01uF/16V,X7R

1K,1%

1K,1%

PM

PM

PM

PM

FBB_VREF4

A15/BA3

RESET#

A15/BA3

RESET#

FBA_A0

N3

A0

FBA_A1

P7

A1

FBA_A2

P3

A2

FBA_A3

N2

A3

FBA_A4

P8

A4

FBA_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBA_ODT0

K1

ODT0

J1

ODT1

FBA_CS0#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_1

D3

DMU

FBADQM_2

E7

DML

FBA_CLK0

J7

CK

FBA_CLK0#

K7

CK#

FBA_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_23

E3

DQL0

FBAD_19

F7

DQL1

FBAD_20

F2

DQL2

FBAD_16

F8

DQL3

FBAD_22

H3

DQL4

FBAD_17

H8

DQL5

FBAD_21

G2

DQL6

FBAD_18

H7

DQL7

FBADQS_2#

G3

DQSL#

FBADQS_2

F3

DQSL

FBA_A0

N3

A0

FBA_A1

P7

A1

FBB_A2

P3

A2

FBB_A3

N2

A3

FBB_A4

P8

A4

FBB_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBB_ODT0

K1

ODT0

J1

ODT1

FBB_CS#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_6

D3

DMU

FBADQM_5

E7

DML

FBA_CLK1

J7

CK

FBA_CLK1#

K7

CK#

FBB_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_47

E3

DQL0

FBAD_43

F7

DQL1

FBAD_46

F2

DQL2

FBAD_41

F8

DQL3

FBAD_45

H3

DQL4

FBAD_42

H8

DQL5

FBAD_44

G2

DQL6

FBAD_40

H7

DQL7

FBADQS_5#

G3

DQSL#

FBADQS_5

F3

DQSL

GR62

GR62
243,1%

243,1%

PM

PM

ᕙ⹂ᅮ

GR68

GR68
243,1%

243,1%

PM

PM

ᕙ⹂ᅮ

1

GC121

GC119

PM

PM

PM

PM

GC118

GC118

0.1uF/10V,X7R

0.1uF/10V,X7R

GC97

GC97

0.1uF/10V,X7R

0.1uF/10V,X7R

GC119
1uF/10V,X7R

1uF/10V,X7R

C0603

C0603

PM

PM

GC98

GC98
1uF/10V,X7R

1uF/10V,X7R

C0603

C0603

PM

PM

GC115

GC115
1000pF/25V,X7R

1000pF/25V,X7R

PM

FBA_ODT0

FBB_ODT0

GR14

GR14

GR15

GR15

10K

10K

10K

10K

PM

PM

PM

PM

A A

FBA_CLK0 FBA_CLK1

GR234

GR234
243,1%

243,1%

PM

FBA_CLK0# FBA_CLK1#

PM

5

GR235

GR235
243,1%

243,1%

PM

PM

PM

+V1.5GPU

GC93

GC93

GC94

GC94

150UF/2.5V

150UF/2.5V

+

+

1000pF/25V,X7R

1000pF/25V,X7R

CT7343_28

CT7343_28

ns

ns

PM

PM

PM

PM

4

PM

PM

GC95

GC95
1000pF/25V,X7R

1000pF/25V,X7R

GC116

GC116
1000pF/25V,X7R

1000pF/25V,X7R

PM

PM

PM

PM

GC96

GC96

0.01uF/16V,X7R

0.01uF/16V,X7R

GC117

GC117

0.01uF/16V,X7R

0.01uF/16V,X7R

GC121

GC120

GC120

4.7uF/10V,X5R

4.7uF/10V,X5R

1uF/10V,X7R

1uF/10V,X7R

C0805

C0805

C0603

C0603

PM

PM

PM

PM

GC99

GC99

GC100

GC100

1uF/10V,X7R

1uF/10V,X7R

4.7uF/10V,X5R

4.7uF/10V,X5R

C0603

C0603

C0805

C0805

PM

PM

PM

PM

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Joseph

Joseph

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

D

D

D

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

1

Joseph
N11M memory1

N11M memory1

N11M memory1

C49

C49

C49

of

of

of

18 59Friday, May 07, 2010

18 59Friday, May 07, 2010

18 59Friday, May 07, 2010

A

A

A