TOPSTAR N81 Schematics
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Topstar Digital technologies Co.,LTD
D D
Board name: Mother Board Schematic
Project name: N81
Version: Ver A
Initial Date:
1. System Block Diagram & Schematic page description;
2. Power Block Diagram & Discription;
3. Annotations & information;
4. Schematic modify Item and history;
New update: 5. Power on & off Sequence;
6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;
C C
9. Power Distribution;
Topstar Confidential
Hardware drawing by: Hardware check by: EMI Check by:
Power drawing by:
B B
许沐锌
Power check by:
Manager Sign by:
A A
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
the expressed written consent of TOPSTAR
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
Title
Title
Title
N81
N81
N81
1
A
A
139Wednesday, May 20, 2009
139Wednesday, May 20, 2009
139Wednesday, May 20, 2009
A
5
schematic-x.blogspot.com
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Topstar Confidential
ShenZhen Topstar Industry Co.,LTD
D D
N81 SYSTEM BLOCK Ver:A
1 Title
2 System Block & Sch Page
3 PWR Block & description
4 NOTE and Annotations
5 Sch Modify and history
CK505M
Clocking
ICS9LPRS365
+V3.3S
PG 6
Backlight
Connector
+VDC
PG 16
ATOM N330
FCBGA 437PIN
+VCC_CORE,+VCCP
+VCCA1.5
PG 7,8
FSB
533MHz
RTD2270L
18.5" CCFL
C C
+V5S
PG 16
LVDS
+V5S
PG 14
CH3708
PG 15
SDVO
VGALVDS
945GC
1202 FCBGA
+V3.3S,+V1.5S,
+V1.05S,+V1.8
+V2.5S
DDR2
400/533
DDR2 SODIMM1
400/533
+V0.9S,+V1.8,+V3.3S
PG 12,13
PG 9,10,11
DB
DB
DB
DB
PG 16
PCIE mini Card
PG 22
PCIE 1X
USB1.1/2.0
BIOS
8Mbit
+V3.3AL
PG 17
8Mbit
+V3.3AL
PG 26
ICH7
82801GBM 652 BGA
+V1.05S,+V3.3S
+V3.3AL,+V5AL
+V1.5S,+V5S
+V3.3A_RTC
PG 17,18,19,20
KB Controller/EC
KB3926
+V3.3AL
PG 26
BIOS
DMI
x2
PCIE X1
SATAO(R1.0)
HDA
LED
DB
S-ATA
2.5" HHD
+V5S
PG 21
10/100/1000M
LAN
RTL8102E/
RTL8111D
+V3.3AL,+V3.3S
PG 38
SATA-ODD
12.7mm ODD
+V5S
PG 21
AMP
TPA3101D2
+VDC
PG 25
AZALIA
ALC662
+V5S,+V3.3S
PG 25
RJ45
Speaker
L
R
MiC
Audio Jack
PG 25
PCIE mini Card
PG 23
B B
A A
USB PORT1
+V5AL
USB PORT2
+V5AL
USB PORT3
+V5AL
USB PORT4
+V5AL
CAMERA
+V5S
SD/MMC/MS/XD CARD
PG 39
5
4
3
2
6 CK-505M
7 Diamondvill (1of2)(Host BUS)
8 Diamondvill (2of2)(Power &GND)
09 MCH-LAKEPORT PART A
10 MCH-LAKEPORT PART B
11 MCH-LAKEPORT PART C
12 DDRII SODIMM0
13 DDR2 TERM and Decoupling
14 VGA to LVDS(RTD2270L)
15 SDVO to LVDS (CH7308)
16 LVDS Inverter CONN
17 ICH7_M(1 of 4)
18 ICH7_M(2 of 4)
19 ICH7_M(3 of 4)
20 ICH7_M(4 of 4
21 SATA HDD & ODD)
22 PCIE MINI SLOT 1
23 PCIE MINI SLOT 2
24 FAN& OTP
25 Audio (ALC662)
26 KBC(KB3926)
27 DB CONN/HOLE
28 ADAPTER IN
29 +V3.3V/+V5V ALWAYS
30 +0.9S Power
31 1.8V1.1V
32 +V1.5S/+V1.05S
33 Power Good Logic_OVP
34 3SYSTEM 2.5S
35 System Discharge
36 VCORE POWER
37 Power On Secquence & Reset M
38 Power ON/OFF
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
(Swain Xu)
System Block & Index
System Block & Index
System Block & Index
N81
N81
N81
1
A
A
239Wednesday, May 20, 2009
239Wednesday, May 20, 2009
239Wednesday, May 20, 2009
A
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N81 POWER BLOCK Ver:A
D D
Adapter
19V 3.42A
+VDC
Always
C C
power
ISL62382
+V3.3AL，3A
MOSFET
Switch
PU9
+V5AL，6A
MOSFET
Switch
+V5S，3A+V3.3S，2A
VCC_CORE
ISL6314
PU12
TPS51124
PU8
+V1.1S，4.5A
+V1.8 10A
APL5331
PU10
TPS51117
PU11
+V1.5S，15A
LDO
PQ30
+VCC_CORE
B B
LDO PU7
KIA1117
0.7V-1.5V
10A max
+V0.9S 2A
+V1.05S 1.5A
+V2.5S，0.5A
A A
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
the expressed written consent of TOPSTAR
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
PWR Block & description
PWR Block & description
PWR Block & description
N81
N81
N81
1
A
A
339Wednesday, May 20, 2009
339Wednesday, May 20, 2009
339Wednesday, May 20, 2009
A
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Voltage Rails
+VDC
D D
+VBATTERY
+VCC_CORE
+V1.05S
+V1.8
+V0.9S
+V3.3AL
+V5AL
+V3.3S
+V5S
+V2.5S 2.5V power rail for 945GMS
Primary DC system power supply (6V-9.5V)
Battery Power supply (6-8.4V)
Core Voltage for CPU
1.05V for Calistoga & ICH7M core / FSB VTT
1.8V power rail for DDR2
0.9V DDR2 Termination voltage
3.3V always on power rail
5V for ICH7-M's VCC5 Refsus
3.3V main power rail
5V main power rail
C C
Board stack up description
PCB Layers
Top(Signal1)
VCC 2
Signal 3
Signal4
Ground 5
Bottom(Signal6)
Trace Impedence:55ohm +/-15%
I2C SMB Address
Device
Clock Generator
SO-DIMM0
CPU Thermal Sensor
Smart Battery
PCIE Slot
Power States
Signal
S0(Full
On)
S3(STM)
S4(STD)
S5(SoftOff)
SLP_S3#
HIGH
LOW
LOW OFF
Wake up Events
LID switch from EC
Power switch from EC
Address Hex
1101 001x
1010 000x
1001 100x
0001 011x
TBD
SLP_S4#
D2
A0
98
16
TBD
HIGH
HIGH ON OFF
LOW
LOW
SLP_S5#
HIGH
HIGH
HIGH
LOW
Master
ICH7-M
ICH7-M
KBC
KBC
ICH7-M
+V*ALW
ON
ON
ON
+V*
ON ON
ON
OFFLOW
+V*S
OFF
OFF
OFF
Clock
ON
OFF
OFF
B B
USB Table
USB Port#
0
1
2
3
4
5
6
7
Function Description
Standard USB2.0 Port
Standard USB2.0 Port
Standard USB2.0 Port
MINICARD_USB
CAM_USB
MINICARD_USB
CR_USB
NC
PCB Footprints
3
SOT23
1 2
5 4
SOT23_5
3
21
ns: Component marked "ns" is not stuff
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
NOTE
NOTE
NOTE
N81
N81
N81
(Swain Xu)
439Wednesday, May 20, 2009
439Wednesday, May 20, 2009
439Wednesday, May 20, 2009
A
A
A
A
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Schematic modify Item and history:
D D
C C
B B
A A
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
the expressed written consent of TOPSTAR
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
Sch Modify and history
Sch Modify and history
Sch Modify and history
N81
N81
N81
1
A
A
539Wednesday, May 20, 2009
539Wednesday, May 20, 2009
539Wednesday, May 20, 2009
A
5
+V3.3S
FB28
FB28
100ohm@100MHz,3A
100ohm@100MHz,3A
FB0805
FB0805
1 2
C391
C390
C390
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C395
C395
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C399
C399
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C401
C401
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C405
C405
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
ns
ns
C0402
C392
C392
4.7UF/10V,Y5V
4.7UF/10V,Y5V
C0805
C0805
D D
C388
C388
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
+V3.3S
FB29
FB29
100ohm@100MHz,3A
100ohm@100MHz,3A
FB0805
FB0805
1 2
C394
C394
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C C
C391
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C393
C393
0.047uF/16V,X7R
0.047uF/16V,X7R
C0402
C0402
+VDDIO_CLK
C396
C396
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
+VDDIO_CLK
C400
C400
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C402
C402
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C406
C406
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C389
C389
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C398
C398
0.047uF/16V,X7R
0.047uF/16V,X7R
C0402
C0402
+VDDIO_CLK
C403
C403
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
+VDDIO_CLK
C404
C404
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C397
C397
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
27M_SEL
4
+V3.3S_CK_VDD
+V3.3S
R647
R647
10K
10K
R0402
R0402
ns
ns
R654
R654
10K
10K
R0402
R0402
C407
C407
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
C408
C408
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
3
U36
U36
ICS9LPRS365
ICS9LPRS365
TSSOP64_0D5_6D1
TSSOP64_0D5_6D1
2
+V3.3S_CK_VDD
+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK
TME
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
R631 22 R0402R631 22 R0402
R632 22 R0402R632 22 R0402
R635 22 R0402R635 22 R0402
R640 10K R0402R640 10K R0402
R644 22 R0402R644 22 R0402
R636 22 R0402R636 22 R0402
R637 2.2K R0402R637 2.2K R0402
R639 10K R0402R639 10K R0402
R638 22 R0402R638 22 R0402
27M_SEL
PCIF_ITP_EN
CLK_XTAL_IN
CLK_XTAL_OUT
No more than 500 mil
PCI_CLK_EC26
PCI_CLK_DEBUG22
PCI_CLK_ICH17
CR_USB4827 CLK_PCIE_LAN 21
CLK_USB4818
CLK_ICH1418
CLK_XTAL_IN
12
Y5
Y5
14.318180MHz
14.318180MHz
XS2_3D3
XS2_3D3
CLK_XTAL_OUT
VDD_PCI
9
VDD_48
16
VDD_PLL3
61
VDD_REF
39
VDD_SRC
55
VDD_CPU
12
VDD_IO
20
VDD_PLL3_IO
26
VDD_SRC_IO_1
36
VDD_SRC_IO_2
45
VDD_SRC_IO_3
49
VDD_CPU_IO
1
PCI0/OE#_0/2_A
3
PCI1/OE#_1/4_A
4
PCI2/TME
5
PCI3/FSD
6
PCI4/SRC5_SEL
7
PCIF5/ITP_EN
60
XTAL_IN
59
XTAL_OUT
10
USB_48/FSA
57
FSB/TEST_MODE
62
REF0/FSC/TEST_SEL
8
VSS_PCI
11
VSS_48
15
VSS_IO
19
VSS_PLL3
52
VSS_CPU
23
VSS_SRC_1
29
VSS_SRC_2
58
VSS_REF
42
VSS_SRC3
IO_VOUT
SMB_DATA
SMB_CLK
SRC5/PCI_STOP#
SRC5#/CPU_STOP#
SRC8/CPU2_ITP
SRC8#/CPU2#_ITP
SRC10#
SRC11/OE#_10
SRC11#/OE#_9
SRC7/OE#_8
SRC7#/OE#_6
SRC3/OE#_0/2_B
SRC3#/OE#_1/4_B
SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
CK_PWRGD/PWRDWN#
CPU0
CPU0#
CPU1
CPU1#
SRC10
SRC9
SRC9#
SRC6
SRC6#
SRC4
SRC4#
2
+V3.3S 7,8,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,31,32,33,35,36
+V1.1S 7,8,9,11,16,19,31,36
+V3.3AL 17,18,19,21,22,23,24,26,27,28,29,30,31,33,35
SMBUS ADD:1101 001X
48
63
64
38
37
54
53
51
50
47
46
34
35
33
32
30
31
44
43
41
40
27
28
24
25
21
22
17
18
13
14
56
R345 0 R0402R345 0 R0402
R347 0 R0402R347 0 R0402
CPU0
RN7 0,5%
RN7 0,5%
CPU#0
CPU1
RN8 0,5%
RN8 0,5%
CPU#1
RN18 0,5%
RN18 0,5%
RN10 0,5%
RN10 0,5%
MPCIE_CLKREQ
MCH_CLKREQ
RN11 0,5%
RN11 0,5%
RN12 0,5%
RN12 0,5%
RN15 0,5%
RN15 0,5%
RN13 0,5%
RN13 0,5%
RN14 0,5%
RN14 0,5%
VR_PWRGD_CLK_EN
1 2
3 4
1 2
3 4
1 2
3 4
3 4
1 2
R643 475,1% R0402 nsR643 475,1% R0402 ns
3 4
1 2
R658 475,1% R0402 nsR658 475,1% R0402 ns
1 2
3 4
3 4
1 2
3 4
1 2
3 4
1 2
R656 0 R0402R656 0 R0402
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
RA0402_4
SMB_DATA_S 12,18,22,23
SMB_CLK_S 12,18,22,23
PM_STP_PCI# 18
PM_STP_CPU# 18
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9
CLK_PCIE_EXPCARD2 23
CLK_PCIE_EXPCARD2# 23
CLK_PCIE_EXPCARD 22
CLK_PCIE_EXPCARD# 22
PCIE_CLKREQ1# 22
CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9
PCIE_CLKREQ2# 23
CLK_PCIE_LAN# 21
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
CLK_ICH_SATA 16
CLK_ICH_SATA# 16
DREFCLK 9
DREFCLK# 9
IMVP_PWRGD 18,26,36
1
+V3.3S
MCH_CLKREQ
MPCIE_CLKREQ
B B
TME
R675 10K R0402R675 10K R0402
R646 10K R0402R646 10K R0402
R648 10K R0402R648 10K R0402
0:Normal mode
1:No Overclocking
BUS FREQUENCE SELECT
+V1.1S
C409
R641
1K
1K
56
56
R0402
R0402
R0402
R0402
ns
ns
CPU_BSEL07
CPU_BSEL17
CPU_BSEL27
A A
R642 0 R0402 nsR642 0 R0402 ns
R651 0 R0402 nsR651 0 R0402 ns
R652 0 R0402 nsR652 0 R0402 ns
R645
R645
1K
1K
R0402
R0402
ns
ns
R653
R653
0
0
R0402
R0402
C0402
C0402
1K
1K
R0402
R0402
ns
ns
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
R655
R655
0
0
R0402
R0402
R670 1K R0402R670 1K R0402
R671 1K R0402R671 1K R0402
R672 1K R0402R672 1K R0402
MCH_BSEL0 9
MCH_BSEL1 9
MCH_BSEL2 9
FSC FSB FSA HOST Clock
BSEL2 BSEL1 BSEL0 frequency
0 0 1 133MHz
R279
R279
1K
1K
R0402
R0402
ns
IMVP_PWRGD18,26,36
ns
PC96
PC96
0.22uF/10V,X7R
0.22uF/10V,X7R
C0603
C0603
ns
ns
C409
0.1UF/25V,Y5V
0.1UF/25V,Y5V
R649
R649
R650
R650
R641
+V3.3AL
1
PR138
PR138
20K
20K
R278
R278
R0402
R0402
1K
1K
ns
ns
R0402
R0402
ns
ns
PQ42
PQ42
MMBT3904-F
MMBT3904-F
SOT23
SOT23
2 3
Add CLK_PWRGD SCH for pick noise issue
ns
ns
许沐锌
1 0 1 100MHz
5
4
3
1
090509
R259
R259
10K
10K
R0402
R0402
ns
ns
+V3.3S
3
2
Q24
Q24
2N7002
2N7002
SOT23
SOT23
ns
ns
VR_PWRGD_CLK_EN
C527
C527
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
ns
ns
2
CLK_ICH14
CR_USB48
CLK_USB48
PCI_CLK_DEBUG
PCI_CLK_EC
PCI_CLK_ICH
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
C410 10PF/50V,NPO ns
C410 10PF/50V,NPO ns
C0402
C0402
C421 10PF/50V,NPO ns
C421 10PF/50V,NPO ns
C0402
C0402
C411 10PF/50V,NPO ns
C411 10PF/50V,NPO ns
C0402
C0402
C412 10PF/50V,NPO ns
C412 10PF/50V,NPO ns
C0402
C0402
C413 10PF/50V,NPO ns
C413 10PF/50V,NPO ns
C0402
C0402
C414 10PF/50V,NPO ns
C414 10PF/50V,NPO ns
C0402
C0402
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
CK505M
CK505M
CK505M
N81
N81
N81
639Wednesday, May 20, 2009
639Wednesday, May 20, 2009
639Wednesday, May 20, 2009
1
A
A
A
5
4
3
2
1
+V3.3S
1
或高速线走线
3
H_D#[63:0]9
H_DSTBN#09
H_DSTBP#09
H_DINV#09
H_D#[63:0]9
H_DSTBN#19
H_DSTBP#19
H_DINV#19
GTLREF_EA
SMBCLK
VCC
SMBDATA
ALERT#
THERM#
GND
5
,
R737 0 R0402R737 0 R0402
CPU_BSEL06
CPU_BSEL16
CPU_BSEL26
U22A
H_A#[35:3]9
D D
H_ADSTB#09
H_REQ#[4:0]9
H_A#[35:3]9
C C
H_ADSTB#19
H_A20M#16
H_FERR#16
H_IGNNE#16
H_STPCLK#16
H_INTR16
H_NMI16
H_SMI#16
+V1.1S
B B
R758 51 R0402R758 51 R0402
R150 51 R0402R150 51 R0402
R86 51 R0402R86 51 R0402
R83 51 R0402 nsR83 51 R0402 ns
R105 51 R0402R105 51 R0402
R759 51 R0402R759 51 R0402
R757 51 R0402R757 51 R0402
R90 51 R0402 nsR90 51 R0402 ns
R92 51 R0402 nsR92 51 R0402 ns
R91 51 R0402 nsR91 51 R0402 ns
R99 1K,1% R0402R99 1K,1% R0402
R96 1K,1% R0402R96 1K,1% R0402
R95 1K,1% R0402R95 1K,1% R0402
A A
+V1.1S
R74
R74
1K,1%
1K,1%
R0402
R0402
R102
R102
1K
1K
R0402
R0402
ns
ns
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#9
H_A#10
H_A#11
H_A#13
H_A#14
H_A#15
H_A#16
T2 ICTPnsT2 ICTPns
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
T14 ICTPnsT14 ICTPns
ns
ns
+V1.1S
R2011K R0402R2011K R0402
5
R75
R75
1K,1%
1K,1%
R0402
R0402
ns
ns
R98
R98
10K
10K
R0402
R0402
ns
ns
1
U22A
P21
A[3]#
H20
A[4]#
N20
A[5]#
R20
A[6]#
J19
A[7]#
N19
A[8]#
G20
A[9]#
M19
A[10]#
H21
A[11]#
L20
A[12]#
M20
A[13]#
K19
A[14]#
J20
A[15]#
L21
A[16]#
K20
ADSTB[0]#
D17
AP0
N21
REQ[0]#
J21
REQ[1]#
G19
REQ[2]#
P20
REQ[3]#
R19
REQ[4]#
C19
A[17]#
F19
A[18]#
E21
A[19]#
A16
A[20]#
D19
A[21]#
C14
ADDR GROUP 1
ADDR GROUP 1
A[22]#
C18
A[23]#
C20
A[24]#
E20
A[25]#
D20
A[26]#
B18
A[27]#
C15
A[28]#
B16
A[29]#
B17
A[30]#
C16
A[31]#
A17
A[32]#
B14
A[33]#
B15
A[34]#
A14
A[35]#
B19
ADSTB[1]#
M18
AP1
U18
A20M#
T16
FERR#
J4
IGNNE#
R16
STPCLK#
T15
LINT0
R15
LINT1
U17
SMI#
Diamondville
Diamondville
H_FERR#
H_TDI
H_TDO
H_TMS
H_TRST#
H_TDX_M
H_BREQ#0
H_CPURST#
H_NMI
H_SMI#
H_INTR
H_DPSLP#
H_DPRSTP#
H_PWRGD
+V3.3S
Change R98 to 10k,R103 to 1K for CPU down frequency issue
许沐锌
081222
Q1
Q1
MMBT3904-F
MMBT3904-F
SOT23
SOT23
ns
ns
2 3
GROUP
0
GROUP
0
PROCHOT#
THERMTRIP#
THRMDA_2
THRMDC_2
THERM
THERM
H CLK
H CLK
NC
NC
R138 51 R0402R138 51 R0402
R88 51 R0402 nsR88 51 R0402 ns
R80 51 R0402R80 51 R0402
For defensive design
reservation only in this
initial release
+V1.1S
R103
R103
51
51
R0402
R0402
ADS#
BNR#
BPRI#
ADDR
ADDR
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
BPM[0]#_2
BPM[1]#_2
BPM[2]#_2
BPM[3]#_2
PRDY#
PREQ#
TCK
TDI
TDO
XDP/ITP SIGNALS
XDP/ITP SIGNALS
TMS
TRST#
BR1#
THRMDA
THRMDC
BCLK[0]
BCLK[1]
RSVD3
RSVD2
RSVD1
TDI_M
TDO_M
Q4
Q4
MMBT3904-F
MMBT3904-F
23
SOT23
SOT23
ns
ns
V19
Y19
U21
T21
T19
Y18
T20
F16
V16
W20
D15
W18
Y17
U20
W19
AA17
V20
H_BPM#0
K17
H_BPM#1
J18
H_BPM#2
H15
H_BPM#3
J15
H_BPM#4
G6
H_BPM#5
H6
H_BPM#6
K4
H_BPM#7
K5
K18
J16
H_TCK
M17
H_TDI
N16
H_TDO
M16
H_TMS
L17
H_TRST#
K16
H_DBR#
V15
G17
H17
G4
F4
H_THERMDA
E4
H_THERMDC
E5
V11
V12
C21
C1
A3
M15
L16
+V1.1S
R94
R94
1K,1%
1K,1%
R0402
R0402
R97
R97
1K,1%
1K,1%
R0402
R0402
ns
ns
R147
R147
1K
1K
R0402
R0402
1
ns
ns
VR_PROCHOT#
H_TDX_M
H_TRST#
H_TDI
H_TCK
UpdateH_TRST# from PU to PD
Update R150 from ns to stuff
Update R99 from ns to stuff
许沐锌
H_DPWR#
ICTP
ICTP
T1
T1
H_ADS# 9
ns
ns
H_BNR# 9
H_BPRI# 9
H_DEFER# 9
H_DRDY# 9
H_DBSY# 9
H_BREQ#0 9
H_IERR#
R65 1K,1% R0402R65 1K,1% R0402
H_LOCK# 9
ns
T3 ICTPnsT3 ICTP
H_CPURST# 9
H_RS#0 9
H_RS#1 9
H_RS#2 9
H_TRDY# 9
H_HIT# 9
H_HITM# 9
R113 1K,1% R0402R113 1K,1% R0402
R114 1K,1% R0402R114 1K,1% R0402
R115 1K,1% R0402R115 1K,1% R0402
R116 1K,1% R0402R116 1K,1% R0402
R117 1K,1% R0402R117 1K,1% R0402
R118 1K,1% R0402R118 1K,1% R0402
R119 1K,1% R0402R119 1K,1% R0402
R120 1K,1% R0402R120 1K,1% R0402
R121 1K,1% R0402R121 1K,1% R0402
R122 1K,1% R0402R122 1K,1% R0402
R674 0 R0402 nsR674 0 R0402 ns T12 ICTP
R104 22 R0402R104 22 R0402
PM_THRMTRIP# 16,24
H_THERMDA_2 8
H_THERMDC_2 8
CLK_CPU_BCLK 6
CLK_CPU_BCLK# 6
090509
EC_PROCHOT# 26
+V1.1S
R63
R63
1K,1%
1K,1%
R0402
R0402
Place testpoint on
H_IERR# with a GND
0.1" away
+V1.1S
PM_SYSRST# 18
VR_PROCHOT#
H_THERMDA
H_THERMDC
R64
R64
330
330
R0402
R0402
ns
ns
H_INIT# 16
+V1.1S
+V1.1S
C22
C22
2200pF/25V,X7R
2200pF/25V,X7R
C0402
C0402
Layout Note: Z=55ohm,
R66
R66
0.5" max for GTLREF
1.62K,1%
1.62K,1%
R0402
R0402
C19
C19
R71
R71
0.1uF/10V,X5R
0.1uF/10V,X5R
2.74K,1%
2.74K,1%
R0402
R0402
C0402
C0402
Layout Note: Z=55ohm,
0.5" max for GTLREF
R76
R76
1K,1%
1K,1%
R0402
R0402
R78
R78
C20
C20
2K,1%
2K,1%
0.1uF/10V,X5R
0.1uF/10V,X5R
R0402
R0402
C0402
C0402
EXTBGREF
2
3
DXP
DXN
G781
G781
ADM1032AR
ADM1032AR
LM86CIM
LM86CIM
MAX6657MSA
MAX6657MSA
SOIC-8
SOIC-8
U4
U4
F75393S
F75393S
SO8_50_150
SO8_50_150
NOTE
+V1.1S
1.H_THERMDA/C线宽10 MILS,
然后再包地处理
2.H_THERMDA/C
4
.
走线远离
并配对走线
19V及VGA
T4 ICTP
T4 ICTP
ns
ns
T12 ICTP
ns
ns
EXTBGREF
R89 150,1% R0402R89 150,1% R0402
C23
C23
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
8
7
6
THERM#
4
R100
R100
10K
10K
R0402
R0402
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6H_A#8
H_D#7
H_D#8
H_D#9
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
+V3.3S
U22B
U22B
Y11
W10
Y12
AA14
AA11
W12
AA16
Y10
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
AA5
W3
W7
W6
AA6
W2
AA8
W4
T17
M6
N15
P17
G5
+V3.3S
Y9
V9
Y8
U1
Y7
Y3
V3
U2
T3
V2
Y4
Y5
Y6
R4
D6
U5
V5
R6
N6
T6
J6
H5
Diamondville
Diamondville
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
GTLREF_EA
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
MISC
MISC
COMP[_0_2
COMP_2_1
COMP[_2_2
COMP_2_3
PWRGOOD
CORE_DET
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
DATA GRP 2
DATA GRP 2
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DP#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
DATA GRP 3
DATA GRP 3
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DP#3
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
SLP#
CMREF[1]
GTLREF
R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4
C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4
T1
T2
F20
F21
L5
N5
N4
P4
R18
R17
U4
V17
N18
A13
B7
A7
EC SMBUS ADD:1001 100X
C24
R101
R101
10K
10K
R0402
R0402
C24
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
C25
C25
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
2
+V3.3S 6,8,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,31,32,33,35,36
+V1.1S 6,8,9,11,16,19,31,36
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42H_A#12 H_D#10
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
ICTP
ICTP
H_D#48
ns
ns
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
COMP0_2
COMP2_1
COMP2_2VR_PROCHOT#
COMP2_3
H_DPRSTP#
H_DPSLP#
H_DPWR#
CPU_CMREF
H_D#[63:0] 9
H_DSTBN#/H_DSTBP# should route
as differential pair
H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2 9
T5
T5
H_D#[63:0] 9
H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9
ns
T13ICTPnsT13ICTP
R68 24.9,1%R0402R68 24.9,1%R0402
R70 49.9,1%R0402R70 49.9,1%R0402
R72 24.9,1%R0402R72 24.9,1%R0402
R73 49.9,1%R0402R73 49.9,1%R0402
R110 24.9,1%R0402R110 24.9,1%R0402
R108 49.9,1%R0402R108 49.9,1%R0402
R109 24.9,1%R0402R109 24.9,1%R0402
R111 49.9,1%R0402R111 49.9,1%R0402
H_PWRGD 16
H_CPUSLP# 16
T21ICTPnsT21ICTP
ns
I2C_CLK 26
I2C_DATA 26
OVT_SHUTDOWN# 8,24
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
Layout note:
Comp0,2 connec with Zo=27.4ohm,make
trace length shorter than 0.5"
Comp1,3 connec with Zo=55ohm,make
trace length shorter than 0.5"
+V1.1S
Layout Note: Zo=55ohm,
R77
R77
0.5" max for GTLREF
1.21K,1%
1.21K,1%
R0402
R0402
R85
R85
C21
C21
1.74K,1%
1.74K,1%
0.1uF/10V,X5R
0.1uF/10V,X5R
R0402
R0402
C0402
C0402
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
Diamondville (HOST)(1of2)
Diamondville (HOST)(1of2)
Diamondville (HOST)(1of2)
N81
N81
N81
1
CPU_CMREF
739Wednesday, May 20, 2009
739Wednesday, May 20, 2009
739Wednesday, May 20, 2009
A
A
A
5
U22D
U22D
A2
VSS1
A4
VSS2
A8
VSS4
A15
VSS5
A18
VSS6
A19
VSS7
A20
VSS8
B1
VSS9
B2
VSS10
B5
VSS11
D D
C C
B B
B13
B20
B21
C17
D14
D18
D21
E15
E16
E19
F17
F18
G13
G21
H13
H16
H18
H19
K13
K15
K21
L13
L15
L18
L19
M13
M21
B8
C8
D1
D5
D8
E3
E6
E7
E8
F5
F6
F7
G1
G7
G9
H3
H4
H7
H9
J5
J7
J9
J13
J17
K1
K6
K7
K9
L3
L4
L6
L7
L9
M1
M5
M7
M9
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS39
VSS41
VSS42
VSS45
VSS46
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
Diamondville
Diamondville
VSS161
VSS160
VSS159
VSS158
VSS157
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
N7
N9
N13
N17
P3
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
+V1.1S
+VCC_CORE
V10
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
A9
B9
U22C
U22C
VCCF
VCCQ1
VCCQ2
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
Diamondville
Diamondville
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VCCPC64
VCCPC63
VCCPC62
VCCPC61
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
4
+V1.1S
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
F14
F13
E14
E13
D7
F15
D16
E18
G15
G16
E17
G18
Place near PIN D7
H_VID0 36
H_VID1 36
H_VID2 36
H_VID3 36
H_VID4 36
H_VID5 36
H_VID6 36
C13
D13
Layout Note: VCCSENSE
and VSSSENSE lines
should be of equal
length
Route VCCSENSE and VSSSENSE
traces at 27.4 Ohms with 50
mil spacing
C26
C26
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C35
C35
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
VCCSENSE 36
VSSSENSE 36
C27
C27
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
+V1.5S
C36
C36
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
ns
ns
C28
C28
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
ns
ns
HCPU1
HCPU1
11223344556677889
H_THERMDA_27
H_THERMDC_27
3
C29
C29
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
CPU_HOLE
CPU_HOLE
ns
ns
C30
C30
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
ns
ns
HCPU2
HCPU2
11223344556677889
9
C69
C69
2200pF/25V,X7R
2200pF/25V,X7R
C0402
C0402
NOTE
1.H_THERMDA/C线宽10 MILS,
然后再包地处理
2.H_THERMDA/C
.
走线远离
C31
C31
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
CPU_HOLE
CPU_HOLE
ns
ns
9
C32
C32
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
2
DXP
3
DXN
G781
G781
ADM1032AR
ADM1032AR
LM86CIM
LM86CIM
MAX6657MSA
MAX6657MSA
SOIC-8
SOIC-8
U5
U5
F75393S
F75393S
SO8_50_150
SO8_50_150
并配对走线
19V及VGA
2
+VCC_CORE 33,36
+V1.5S 9,11,19,22,23,27,32,33,35
+V1.1S 6,7,9,11,16,19,31,36
+V3.3S 6,7,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,31,32,33,35,36
C33
C33
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
ns
ns
12
1
1
C34
C34
+
+
220uF/2.5V,POSCAP
220uF/2.5V,POSCAP
CT7343_19
CT7343_19
ns
ns
Install C34
Swain 080820
+V3.3S
R112 150,1% R0402R112 150,1% R0402
C70
C70
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
1
SMBCLK
VCC
SMBDATA
ALERT#
THERM#
GND
5
,
8
7
6
4
EC SMBUS ADD:1001 100X
R106
+V3.3S
R106
10K
10K
R0402
R0402
R107
R107
10K
10K
R0402
R0402
或高速线走线
C71
C71
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
C72
C72
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
1
I2C_CLK_2 26
I2C_DATA_2 26
OVT_SHUTDOWN# 7,24
+VCC_CORE
C46
C37
C37
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
A A
+VCC_CORE
C53
C53
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C38
C38
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C54
C54
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
5
C39
C39
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C55
C55
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C40
C40
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C56
C56
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C41
C41
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C57
C57
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C46
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C58
C58
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
4
C42
C42
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C59
C59
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C43
C43
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C60
C60
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C44
C44
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C61
C61
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C45
C45
1uF/10V,X5R
1uF/10V,X5R
C0402
C0402
C62
C62
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C51
C51
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C63
C63
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C47
C47
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C64
C64
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
3
C48
C48
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C49
C49
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C50
C50
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
C52
C52
0.1uF/10V,X5R
0.1uF/10V,X5R
C0402
C0402
2
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
Diamondville (PWR&GND)(2of2)
Diamondville (PWR&GND)(2of2)
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
Diamondville (PWR&GND)(2of2)
N81
N81
N81
839Wednesday, May 20, 2009
839Wednesday, May 20, 2009
839Wednesday, May 20, 2009
1
A
A
A
5
H_D#[63:0]7
U37B
H_A#[35:3]7
D D
C C
H_REQ#[4:0]7
H_ADSTB#07
H_ADSTB#17
H_DSTBP#07
H_DSTBN#07
H_DSTBP#17
H_DSTBN#17
H_DSTBP#27
H_DSTBN#27
H_DSTBP#37
H_DSTBN#37
B B
H_DEFER#7
H_BREQ#07
H_CPURST#7
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_DINV#07
H_DINV#17
H_DINV#27
H_DINV#37
H_ADS#7
H_TRDY#7
H_DRDY#7
H_HITM#7
H_HIT#7
H_LOCK#7
H_BNR#7
H_BPRI#7
H_DBSY#7
H_RS#07
H_RS#17
H_RS#27
T17nsT17
ns
T34nsT34
ns
K38
K35
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
AA37
V32
Y34
AA35
AA42
AA34
AA38
E41
D41
K36
G37
E42
M36
V35
K41
L43
K40
F35
G34
A38
M26
E29
E34
B37
B32
W42
W40
V41
P40
W41
U41
U40
AA41
U39
D42
U42
T40
Y43
T43
C30
F38
Y40
J39
J42
J37
J27
U37B
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
HDSTBP#0
HDSTBN#0
HDINV#0
HDSTBP#1
HDSTBN#1
HDINV#1
HDSTBP#2
HDSTBN#2
HDINV#2
HDSTBP#3
HDSTBN#3
HDINV#3
HADS#
HTRDY#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HRS#0
HRS#1
HRS#2
HCPURST#
HPCREQ#
HEDRDY#
LAKEPORT
LAKEPORT
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
HSWING
HSCOMP
HRCOMP
HDVREF
HACCVREF
HCLKP
HCLKN
P41
M39
P42
M42
N41
M40
L40
M41
K42
G39
J41
G42
G40
G41
F40
F43
F37
E37
J35
D39
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
D32
B30
D30
B27
C27
A28
D27
D28
M31
M29
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
MCH_SWING
MCH_SCOMP
MCH_GTLREF0
4
R749
R749
16.9,1%
16.9,1%
R0402
R0402
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
3
U37A
U37A
G12
EXP_RXP0
F12
EXP_RXN0
D11
EXP_RXP1
D12
EXP_RXN1
J13
EXP_RXP2
H13
EXP_RXN2
E10
EXP_RXP3
F10
EXP_RXN3
J9
EXP_RXP4
H10
EXP_RXN4
F7
EXP_RXP5
F9
EXP_RXN5
C4
EXP_RXP6
D3
EXP_RXN6
G6
EXP_RXP7
J6
EXP_RXN7
K9
EXP_RXP8
K8
EXP_RXN8
F4
EXP_RXP9
G4
EXP_RXN9
M6
EXP_RXP10
M7
EXP_RXN10
K2
EXP_RXP11
L1
EXP_RXN11
U11
EXP_RXP12
U10
EXP_RXN12
R8
EXP_RXP13
R7
EXP_RXN13
P4
EXP_RXP14
N3
EXP_RXN14
Y10
EXP_RXP15
Y11
EXP_RXN15
AA10
AC9
AC8
AA9
AA6
AA7
B14
B16
F15
E15
Y7
Y8
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
GCLKP
GCLKN
SDVO_CTRLDATA
SDVO_CTRLCLK
LAKEPORT
LAKEPORT
SDVO_DATA
SDVO_CLK
DMI_TXP017
DMI_TXN017
DMI_TXP117
DMI_TXN117
DMI_TXP217
DMI_TXN217
DMI_TXP317
DMI_TXN317
CLK_MCH_3GPLL6
CLK_MCH_3GPLL#6
SDVO_DATA
SDVO_CLK
EXP_TXP10
EXP_TXN10
EXP_TXP11
EXP_TXN11
EXP_TXP12
EXP_TXN12
EXP_TXP13
EXP_TXN13
EXP_TXP14
EXP_TXN14
EXP_TXP15
EXP_TXN15
EXP_COMPO
EXP_COMPI
R753 4.7KnsR753 4.7K ns
R754 4.7KnsR754 4.7K ns
EXP_TXP0
EXP_TXN0
EXP_TXP1
EXP_TXN1
EXP_TXP2
EXP_TXN2
EXP_TXP3
EXP_TXN3
EXP_TXP4
EXP_TXN4
EXP_TXP5
EXP_TXN5
EXP_TXP6
EXP_TXN6
EXP_TXP7
EXP_TXN7
EXP_TXP8
EXP_TXN8
EXP_TXP9
EXP_TXN9
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
D14
C13
A13
B12
A11
B10
C10
C9
A9
B7
D7
D6
A6
B5
E2
F1
G2
J1
J3
K4
L4
M4
M2
N1
P2
T1
T4
U4
U2
V1
V3
W4
W2
Y1
AA2
AB1
Y4
AA4
AB3
AC4
AC12
AC11
EXP_COMP
+V2.5S
DMI_RXP0 17
DMI_RXN0 17
DMI_RXP1 17
DMI_RXN1 17
DMI_RXP2 17
DMI_RXN2 17
DMI_RXP3 17
DMI_RXN3 17
R755 24.9,1%R755 24.9,1%
+V1.1S
+V1.5S
R801
R801
1K
1K
ns
ns
R0402
R0402
R802
R802
1K
1K
ns
ns
R0402
R0402
MCH_BSEL06
MCH_BSEL16
MCH_BSEL26
R762 1K nsR762 1K ns
R756 1K nsR756 1K ns
EXP_EN
2
EXP_EN
EXP_SLR
AW2
AW26
BC42
BC43
BB43
AV26
AV27
AL26
AL20
AK27
AK21
AJ29
AJ27
AJ26
AJ24
AJ23
AJ21
AG29
AG27
AG26
AG25
F21
H21
K18
H20
K21
F20
N21
A42
BA2
C42
B41
B42
B43
BC1
BC2
BB1
BB2
E35
R27
M15
L20
L18
L21
C2
B2
B3
L15
U37E
U37E
BSEL0
BSEL1
BSEL2
ALLZTEST
XORTEST
RSV_TP[5]
EXP_SLR
RSV_TP[4]
EXP_EN
RSV_TP[6]
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED25
LAKEPORT
LAKEPORT
RESERVED42
RESERVED43
RESERVED44
RESERVED26
RESERVED27
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
R137 150,1% R0402R137 150,1% R0402
R134 150,1% R0402R134 150,1% R0402
R136 150,1% R0402R136 150,1% R0402
150ohm
电阻到
走线阻抗
37.5ohm
150ohm
电阻到
走线阻抗
50ohm
PLACE 150 OHM
RESISTORS CLOSE TO
GMCH
+V2.5S 11,34,35
+V1.1S 6,7,8,11,16,19,31,36
+V1.5S 8,11,19,22,23,27,32,33,35
D17
HSYNC
C17
VSYNC
F17
RED
K17
GREEN
H18
BLUE
G17
RED#
J17
GREENB
J18
BLUE#
N18
DDC_DATA
N20
DDC_CLK
A20
IREF
J15
DREFCLKP
H15
DREFCLKN
R761 10KR761 10K
J20
EXTTS#
M11
V30
AJ12
RSTIN#
AJ9
PWROK
VCC
VSS
M18
A43
M17
L17
AL29
AA30
U27
U30
AF31
V31
Y30
Y33
AC30
AC34
AD30
AD31
BLUE
GREEN
RED
ICH_SYNC#
GMCH
VGA
口
1
HSYNC 14
VSYNC 14
RED 14
GREEN 14
BLUE 14
DDC_DATA 14,26
DDC_CLK 14,26
IREF
R760 255OHM,1%
R760 255OHM,1%
R0402
R0402
DREFCLK 6
DREFCLK# 6
+V2.5S
BUF_PLT_RST# 17,18,21,22,23,26
R348 0 R0402R348 0 R0402
MCH_ICH_SYNC# 17
+V1.5S
PM_ICH_PWROK 18
PLEASE
CLOSE TO
MCH
+V1.1S
R0402
R0402
R750
R750
301,1%
301,1%
R0603
A A
C639
C639
0.01uF/25V,X7R
0.01uF/25V,X7R
R0603
R748 62
R748 62
R751
R751
84.5,1%
84.5,1%
R0402
R0402
CAD NOTE :
HD_SWING Voltage
routed 10 mils / 7mils
TRACE
+V1.1S
R752 60.4,1%R752 60.4,1%
MCH_SCOMPMCH_SWING
C640
C640
3.3pF/50V,NPO
3.3pF/50V,NPO
ns
ns
PLEASE DRIVER
RESISTORS NEAR VTT
C642
C642
0.1uF/10V,X5R
0.1uF/10V,X5R
0.22 x VTT
5
4
3
+V1.1S
GTLREF VOLTAGE SHOULD BE 0.63 x VTT = 0.75V
R765
R765
124,1%
124,1%
MCH_GTLREF0
C641
C641
220pF/50V,X7R
220pF/50V,X7R
ns
ns
R778
R778
210,1%
210,1%
R0402
R0402
R764 10R764 10
Close to
pin D27
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
MCH LAKEPORT PART A
MCH LAKEPORT PART A
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
2
the expressed written consent of TOPSTAR
MCH LAKEPORT PART A
N81
N81
N81
1
A
A
939Wednesday, May 20, 2009
939Wednesday, May 20, 2009
939Wednesday, May 20, 2009
A
5
U37C
MA_A_A[13:0]12,13
D D
MA_A_CAS#12,13
MA_A_RAS#12,13
M_ODT012,13
M_ODT112,13
M_CLK_DDR012
M_CLK_DDR#012
C C
M_CLK_DDR112
M_CLK_DDR#112
MA_A_A0
BA32
MA_A_A1
AW32
MA_A_A2
BB30
MA_A_A3
BA30
MA_A_A4
AY30
MA_A_A5
BA27
MA_A_A6
BC28
MA_A_A7
AY27
MA_A_A8
AY28
MA_A_A9
BB27
MA_A_A10
AY33
MA_A_A11
AW27
MA_A_A12
BB26
MA_A_A13
BC38
MA_A_WE#12,13
MA_A_BS#012,13
MA_A_BS#112,13
MA_A_BS#212,13
M_CS#012,13
M_CS#112,13
T44 nsT44 ns
T43 nsT43 ns
M_CKE012,13
M_CKE112,13
T41 nsT41 ns
T38 nsT38 ns
T52 nsT52 ns
T51 nsT51 ns
T54 nsT54 ns
T53 nsT53 ns
T56 nsT56 ns
T55 nsT55 ns
T58 nsT58 ns
T57 nsT57 ns
T60 nsT60 ns
T59 nsT59 ns
BB35
BA37
BA34
BC33
AY34
BA26
BB37
BA39
BA35
AY38
BB25
AY25
BC24
BA25
AW37
AY39
AY37
BB40
BB32
AY32
AY5
BB5
AK42
AK41
BA31
BB31
AY6
BA5
AH40
AH43
BC16
AY14
AW17
AW18
AK40
MCH_VREF_A
B B
+V1.8
R766
R766
1K,1%
1K,1%
R767
R767
1K,1%
1K,1%
A A
T18 ICTPnsT18 ICTPns
T22 ICTPnsT22 ICTPns
PLACE
0.1UF CAP
CLOSE TO
MCH
MCH_VREF_A
C643
C643
0.1uF/10V,X5R
0.1uF/10V,X5R
CAD NOTES :
PLASE CLOSE TO MCH
5
C644
C644
0.1uF/10V,X5R
0.1uF/10V,X5R
RSV_TP1
RSV_TP0
AM4
AL17
AK17
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SWE_A#
SCAS_A#
SRAS_A#
SBS_A0
SBS_A1
SBS_A2
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SCLK_A0
SCLK_A#0
SCLK_A1
SCLK_A#1
SCLK_A2
SCLK_A#2
SCLK_A3
SCLK_A#3
SCLK_A4
SCLK_A#4
SCLK_A5
SCLK_A#5
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
SMVREF0
RSV_TP[1]
RSV_TP[0]
LAKEPORT
LAKEPORT
U37C
SDQS_A0
SDQS_A#0
SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQS_A1
SDQS_A#1
SDM_A1
SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQS_A2
SDQS_A#2
SDM_A2
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQS_A3
SDQS_A#3
SDM_A3
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQS_A4
SDQS_A#4
SDM_A4
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQS_A5
SDQS_A#5
SDM_A5
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQS_A6
SDQS_A#6
SDM_A6
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQS_A7
SDQS_A#7
SDM_A7
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
4
AU4
AR2
AR3
AP3
AP2
AU3
AV4
AN1
AP4
AU5
AU2
BA3
BB4
AY2
AW3
AY3
BA7
BB7
AV1
AW4
BC6
AY7
AY11
BA10
BB10
AW12
AY10
BA12
BB12
BA9
BB9
BC11
AY12
AU18
AR18
AP18
AM20
AM18
AV20
AM21
AP17
AR17
AP20
AT20
AU35
AV35
AT34
AP32
AV34
AV38
AU39
AV32
AT32
AR34
AU37
AP42
AP40
AP39
AR41
AR42
AN43
AM40
AU41
AU42
AP41
AN40
AG42
AG41
AG40
AL41
AL42
AF39
AE40
AM41
AM42
AF41
AF42
AC42
AC41
AC40
AD40
AD43
AA39
AA40
AE42
AE41
AB41
AB42
4
MA_DQS0
MA_DQS#0
MA_DM0
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DQS1
MA_DQS#1
MA_DM1
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DQS2
MA_DQS#2
MA_DM2
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DQS3
MA_DQS#3
MA_DM3
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DQS4
MA_DQS#4
MA_DM4
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DQS5
MA_DQS#5
MA_DM5
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DQS6
MA_DQS#6MA_DQS#6
MA_DM6
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DQS7
MA_DQS#7
MA_DM7
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
+V1.8
0.1uF/10V,X5R
0.1uF/10V,X5R
R770 80.6,1%R770 80.6,1%
C645
C645
3
3
MCH_VREF_A
T23 nsT23 ns
T49 nsT49 ns
T35 nsT35 ns
T61 nsT61 ns
R771
R771
80.6,1%
80.6,1%
RSV_TP3
RSV_TP2
SRCOMP1
SRCOMP0
BB22
BB21
BA21
AY21
BC20
AY19
AY20
BA18
BA19
BB18
BA22
BB17
BA17
AW42
BB23
AY24
BA23
AW23
AY23
AY17
BA40
AW41
BA41
AW40
BA14
AY16
BA13
BB13
AY42
AV40
AV43
AU40
AM29
AM27
AW9
AL38
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
AL39
AM2
AK18
AK23
AM3
AV9
AJ8
AJ6
AL5
U37D
U37D
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SWE_B#
SCAS_B#
SRAS_B#
SBS_B0
SBS_B1
SBS_B2
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SCLK_B0
SCLK_B#0
SCLK_B1
SCLK_B#1
SCLK_B2
SCLK_B#2
SCLK_B3
SCLK_B#3
SCLK_B4
SCLK_B#4
SCLK_B5
SCLK_B#5
RESERVED6
SMVREF1
RSV_TP[3]
RSV_TP[2]
SM_OCDCOMP_1
SM_OCDCOMP_0
SM_RCOMP1
SM_RCOMP0
LAKEPORT
LAKEPORT
SDQS_B0
SDQS_B0#
SDM_B0
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7
SDQS_B1
SDQS_B1#
SDM_B1
SDQ_B8
SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQS_B2
SDQS_B2#
SDM_B2
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQS_B3
SDQS_B3#
SDM_B3
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQS_B4
SDQS_B4#
SDM_B4
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQS_B5
SDQS_B5#
SDM_B5
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQS_B6
SDQS_B6#
SDM_B6
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQS_B7
SDQS_B7#
SDM_B7
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
2
AM8
AM6
AL11
AL6
AL8
AP8
AP9
AJ11
AL9
AM10
AP6
AV7
AR9
AW7
AU7
AV6
AV12
AM11
AR5
AR7
AR12
AR10
AV13
AT13
AP13
AM15
AM13
AV15
AM17
AN12
AR13
AP15
AT15
AU23
AR23
AP23
AM24
AM23
AV24
AM26
AP21
AR21
AP24
AT24
AT29
AV29
AR29
AU27
AN29
AR31
AM31
AP27
AR27
AP31
AU31
AP36
AM35
AR38
AP35
AP37
AN32
AL35
AR35
AU38
AM38
AM34
AG34
AG32
AJ39
AL34
AJ34
AF32
AF34
AL31
AJ32
AG35
AD32
AD36
AD38
AD39
AC32
AD34
Y32
AA32
AF35
AF37
AC33
AC35
2
1
MA_DATA[63:0] 12
MA_DQS#[7:0] 12
MA_DM[7:0] 12
MA_DQS[7:0] 12
+V1.8 11,12,30,31,33,35
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
MCH LAKEPORT PART B
MCH LAKEPORT PART B
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
MCH LAKEPORT PART B
N81
N81
N81
1
10 39Wednesday, May 20, 2009
10 39Wednesday, May 20, 2009
10 39Wednesday, May 20, 2009
A
A
A
5
+V1.5S
1 2
D D
C C
B B
A A
1 2
L18
L18
1 2
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
FB0805
FB0805
+V2.5S V_2P5_DAC_F
100ohm@100MHz,300mA
100ohm@100MHz,300mA
C671
C671
10uF/6.3V,X5R
10uF/6.3V,X5R
+V1.5S
4.7uF/10V,Y5V
4.7uF/10V,Y5V
+V1.8
0.1uF/10V,X5R
0.1uF/10V,X5R
R777 1
R777 1
R0603
L15
L15
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
FB0805
FB0805
FB35
FB35
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
1 2
C322
C322
C0805
C0805
C656
C656
R0603
R776 1
R776 1
R0603
R0603
4.7uF/10V,Y5V
4.7uF/10V,Y5V
4.7uF/10V,Y5V
4.7uF/10V,Y5V
4.7uF/10V,Y5V
4.7uF/10V,Y5V
+V1.5S
C666
C666
0.01uF/25V,Y5V
0.01uF/25V,Y5V
PCI EXPRESS FILTER
Can be changed to 0
ohm resistor
FB37
FB37
C321
C321
10uF/6.3V,X5R
10uF/6.3V,X5R
R7751R775
1
C323
C323
C0805
C0805
4.7uF/10V,Y5V
4.7uF/10V,Y5V
C657
C657
0.1uF/10V,X5R
0.1uF/10V,X5R
+V1.5S
0.1uF/10V,X5R
0.1uF/10V,X5R
4.7uF/10V,Y5V
4.7uF/10V,Y5V
5
R7741R774
1
CAPS FOR SPECIFIC CORE MCH
1uF/25V,Y5V
1uF/25V,Y5V
1uF/25V,Y5V
1uF/25V,Y5V
C664
C664
C665
C665
10uF/6.3V,X5R
10uF/6.3V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
C325
C325
C0805
C0805
VCCA_GPLL
C662
C662
VCCA_HPLL
C646
C646
0.1uF/10V,X5R
0.1uF/10V,X5R
VCCA_MPLL
C663
C663
VCCA_DPLLA
C647
C647
0.1uF/10V,X5R
0.1uF/10V,X5R
VCCA_DPLLB
C648
C648
0.1uF/10V,X5R
0.1uF/10V,X5R
C668
C668
0.01uF/25V,Y5V
0.01uF/25V,Y5V
C670
C670
0.01uF/25V,Y5V
0.01uF/25V,Y5V
C651
C651
C669
C669
0.01uF/25V,Y5V
0.01uF/25V,Y5V
V_2P5_DAC_F
C672
C672
10uF/6.3V,X5R
10uF/6.3V,X5R
C652
C652
0.1uF/10V,X5R
0.1uF/10V,X5R
C658
C658
0.1uF/10V,X5R
0.1uF/10V,X5R
VCCA_DPLLB
VCCA_MPLL
VCCA_HPLL
VCCA_DPLLA
+V2.5S
VCCA_GPLL
+V1.1S
C326
C326
C0805
C0805
4.7uF/10V,Y5V
4.7uF/10V,Y5V
+V1.8
C329
C329
C0805
C0805
4.7uF/10V,Y5V
4.7uF/10V,Y5V
MCH MEMORY DECOUPLING
C288
C288
C0805
C0805
C289
C289
C0805
C0805
ns
ns
C293
C293
C0805
C0805
ns
ns
C667
C667
0.01uF/25V,Y5V
0.01uF/25V,Y5V
10uF/6.3V,X5R
10uF/6.3V,X5R
C649
C649
0.1uF/10V,X5R
0.1uF/10V,X5R
C650
C650
C324
C324
C0805
C0805 C661
4.7uF/10V,Y5V
4.7uF/10V,Y5V
+V1.8
C327
C327
C0805
C0805
4.7uF/10V,Y5V
4.7uF/10V,Y5V
C328
C328
C0805
C0805
4.7uF/10V,Y5V
4.7uF/10V,Y5V
4
4
BB16
BB20
BB24
BB28
BB33
BB38
BB42
AV18
AV21
AV23
AV31
AV42
AW13
AW15
AW20
AW21
AW24
AW29
AW31
AW34
AW35
AY41
AY43
BC13
BC18
BC22
BC26
BC31
BC35
BC40
B19
B20
C21
C19
C18
B18
D19
B17
A18
1uF/25V,Y5V
1uF/25V,Y5V
U37F
U37F
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCADPLLB
VCCAMPLL
VCCAHPLL
VCCADPLLA
VCCA_DAC_1
VCCA_DAC_2
VCC2
VCCA_EXPPLL
VSSA_DAC
LAKEPORT
LAKEPORT
C653
C653
0.1uF/10V,X5R
0.1uF/10V,X5R
C661
1uF/25V,Y5V
1uF/25V,Y5V
C660
C660
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VCC_EXP_1
VCC_EXP_2
VCC_EXP_3
VCC_EXP_4
VCC_EXP_5
VCC_EXP_6
VCC_EXP_7
VCC_EXP_8
VCC_EXP_9
VCC_EXP_10
VCC_EXP_11
VCC_EXP_12
VCC_EXP_13
VCC_EXP_14
VCC_EXP_15
VCC_EXP_16
VCC_EXP_17
VCC_EXP_18
VCC_EXP_19
VCC_EXP_20
VCC_EXP_21
VCC_EXP_22
VCC_EXP_23
VCC_EXP_24
VCC_EXP_25
VCC_EXP_26
VCC_EXP_27
VCC_EXP_28
VCC_EXP_29
VCC_EXP_30
VCC_EXP_31
VCC_EXP_32
VCC_EXP_33
VCC_EXP_34
VCC_EXP_35
VCC_EXP_36
VCC_EXP_37
C654
C654
0.1uF/10V,X5R
0.1uF/10V,X5R
C659
C659
1uF/25V,Y5V
1uF/25V,Y5V
3
+V1.1S
A24
G23
F27
F23
E27
E26
E24
E23
N23
P23
M23
B26
B25
B24
B23
L23
K23
J23
H23
D25
D24
D23
C26
C25
C23
AA5
AA13
AC13
AC5
AC6
AD1
AD10
AD12
AD2
AD4
AD5
AD6
AD8
AE2
U13
U6
U7
U8
V10
V13
V5
V6
V7
V9
Y13
N10
N11
N12
N5
N7
N9
R10
R11
R13
R5
AE3
AE4
C655
C655
0.1uF/10V,X5R
0.1uF/10V,X5R
+V2.5S +V1.5S
+V1.5S +V1.5S
+V1.5S
R334
R334
1
1
R0402
R0402
U37G
U37G
AE20
VCC1
AE22
VCC2
AE24
VCC3
U15
VCC4
U17
VCC5
U18
VCC6
U19
VCC7
U20
VCC8
U21
VCC9
U22
VCC10
U23
VCC11
U24
VCC12
U25
VCC13
U26
VCC14
W17
VCC15
W18
VCC16
W19
VCC17
W20
VCC18
W22
VCC19
W24
VCC20
W26
VCC21
W27
VCC22
AF10
VCC23
AF11
VCC24
AF12
VCC25
AF13
VCC26
AF14
VCC27
AF15
VCC28
AF17
VCC29
AF19
VCC30
AF21
VCC31
AF23
VCC32
AF25
VCC33
AF26
VCC34
AF27
VCC35
AF29
VCC36
AF30
VCC37
AF6
VCC38
AF7
VCC39
AF8
VCC40
AF9
VCC41
V15
VCC42
V17
VCC43
V18
VCC44
V19
VCC45
V20
VCC46
V21
VCC47
V22
VCC48
V23
VCC49
V25
VCC50
V27
VCC51
Y15
VCC52
Y17
VCC53
Y18
VCC54
Y19
VCC55
Y21
VCC56
Y23
VCC57
Y25
VCC58
Y27
VCC59
AC15
VCC60
AC17
VCC61
AC18
VCC62
AC20
VCC63
AC22
VCC64
AC24
VCC65
AC26
VCC66
AC27
VCC67
AD14
VCC68
AD15
VCC69
AD17
VCC70
AD19
VCC71
AD21
VCC72
AD23
VCC73
AD25
VCC74
LAKEPORT
LAKEPORT
D41
D41
3
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124
VCC125
VCC126
VCC127
VCC128
VCC129
VCC130
VCC131
VCC132
VCC133
VCC134
VCC135
VCC136
VCC137
VCC138
VCC139
VCC140
VCC141
VCC142
VCC143
VCC144
VCC145
VCC146
VCC147
VCC148
1N5819HW-F
1N5819HW-F
12
SOD123
SOD123
AE18
AE17
AB27
AB26
AB25
AB24
AB23
AB22
AB21
AB20
AB19
AB18
AB17
AA26
AA24
AA22
AA20
AA19
AA18
AA17
AA15
AE26
AK4
AK3
AK20
AK2
AK15
AK14
AH4
AH2
AH1
R24
R23
R21
R20
R18
R17
R15
N17
AJ5
AJ20
AJ18
AJ17
AJ15
AJ14
AJ13
P21
P20
P18
P17
AG9
AG8
AG7
AG6
AG5
AG4
AG3
AG24
AG23
AG22
AG21
AG20
AG2
AG19
AG18
AG17
AG15
AG14
AG13
AG12
AG11
AG10
AD26
AE27
AK26
AK29
AK30
BB11
BB14
BB19
BB3
BB34
BB39
BB41
BB6
E12
E13
E17
E18
E20
E21
E32
AL1
AL10
AL12
AL13
AL15
AL18
AL2
AL21
AL23
AL24
AL27
AL3
AL32
AL33
AL37
AL43
AL7
G10
G13
G15
G18
G20
G21
G24
G27
G29
G31
G32
G35
G38
AT12
AT17
AT18
AT21
AT23
AT26
AT27
AT31
AV10
AV17
AV2
AV37
AU12
AU13
AU15
AU17
AU20
AU21
AU24
AU26
AU29
AU32
AU34
AU6
AU9
AA3
AA8
AA11
AA12
AA21
AA23
AA25
AA27
AA29
AA31
AD33
AD35
AD29
2
U37I
U37I
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
E3
VSS180
VSS181
E4
VSS182
E7
VSS183
E9
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
F13
VSS202
F18
VSS203
F2
VSS204
F26
VSS205
F34
VSS206
F42
VSS207
F6
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
G3
VSS218
VSS219
VSS220
VSS221
VSS222
G5
VSS223
G7
VSS224
G9
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
LAKEPORT
LAKEPORT
2
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
VSS361
VSS362
VSS363
VSS364
VSS365
AD27
AD24
AD22
AD20
AD18
AD13
AD11
AC7
AC39
AC38
AC37
AC36
AC31
AC3
AC29
AC25
AC23
AC21
AC2
AC19
AC14
AC10
T42
T2
Y9
Y6
Y5
Y42
Y39
Y37
Y35
Y31
Y29
Y26
Y24
Y22
Y20
Y2
Y14
Y12
V8
V43
V39
V38
V37
V36
V34
V29
V26
V24
V2
V14
V12
V11
AF5
AF43
AF38
AF36
AF33
AF3
AF24
AF22
AF20
AF2
AF18
AF1
W3
W25
W23
W21
U9
U5
U38
U36
U33
U31
U3
U29
U14
U12
BA42
BA4
AE23
AE21
AE19
A40
A4
A35
A31
A26
A22
A16
AB43
AB2
AA36
AA33
AD9
AD7
AD42
AD37
AA14
AE25
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
U37H
U37H
AM33
VSS1
AM36
VSS2
AM37
VSS3
AM39
VSS4
AM5
VSS5
AM7
VSS6
AM9
VSS7
C12
VSS8
C14
VSS9
C22
VSS10
C3
VSS11
C40
VSS12
C5
VSS13
C7
VSS14
AN13
VSS15
AN15
VSS16
AN17
VSS17
AN18
VSS18
AN2
VSS19
AN20
VSS20
AN21
VSS21
AN23
VSS22
AN24
VSS23
AN26
VSS24
AN27
VSS25
AN31
VSS26
AN4
VSS27
AN42
VSS28
D1
VSS29
D10
VSS30
D16
VSS31
D2
VSS32
D20
VSS33
D21
VSS34
D43
VSS35
D5
VSS36
AP10
VSS37
AP12
VSS38
AP29
VSS39
AP34
VSS40
AP38
VSS41
AP5
VSS42
AP7
VSS43
H12
VSS44
H17
VSS45
H26
VSS46
H27
VSS47
H32
VSS48
J10
VSS49
J12
VSS50
J2
VSS51
J21
VSS52
J24
VSS53
J29
VSS54
J38
VSS55
J43
VSS56
J5
VSS57
J7
VSS58
AR1
VSS59
AR15
VSS60
AR20
VSS61
AR24
VSS62
AR32
VSS63
AR37
VSS64
AR39
VSS65
AR43
VSS66
AR6
VSS67
K10
VSS68
K12
VSS69
K13
VSS70
K15
VSS71
K20
VSS72
K27
VSS73
K3
VSS74
K32
VSS75
K34
VSS76
K37
VSS77
K39
VSS78
K5
VSS79
K6
VSS80
VSS81K7VSS162
LAKEPORT
LAKEPORT
1
+V2.5S 9,34,35
+V1.8 10,12,30,31,33,35
+V1.1S 6,7,8,9,16,19,31,36
+V1.5S 8,9,19,22,23,27,32,33,35
P26
VSS82
P27
VSS83
P29
VSS84
P3
VSS85
P30
VSS86
AJ10
VSS87
AJ30
VSS88
AJ31
VSS89
AJ33
VSS90
AJ35
VSS91
AJ37
VSS92
AJ7
VSS93
N13
VSS94
N15
VSS95
N2
VSS96
N24
VSS97
N26
VSS98
N27
VSS99
N29
VSS100
N31
VSS101
N33
VSS102
N36
VSS103
N39
VSS104
N43
VSS105
N6
VSS106
N8
VSS107
R12
VSS108
R14
VSS109
R26
VSS110
R29
VSS111
R30
VSS112
R31
VSS113
R34
VSS114
R37
VSS115
R39
VSS116
R6
VSS117
R9
VSS118
AH42
VSS119
AK24
VSS120
P24
VSS121
P15
VSS122
P14
VSS123
M9
VSS124
M8
VSS125
M5
VSS126
M37
VSS127
M35
VSS128
M3
VSS129
M21
VSS130
M20
VSS131
M13
VSS132
M10
VSS133
AG39
VSS134
AG38
VSS135
AG37
VSS136
AG36
VSS137
AG33
VSS138
AG31
VSS139
AG30
VSS140
BC9
VSS141
BC4
VSS142
AY1
VSS143
B9
VSS144
B6
VSS145
B4
VSS146
B38
VSS147
B33
VSS148
B28
VSS149
B22
VSS150
B21
VSS151
B13
VSS152
B11
VSS153
AW10
VSS154
L42
VSS155
L31
VSS156
L29
VSS157
L26
VSS158
L24
VSS159
L2
VSS160
L13
VSS161
L12
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
MCH LAKEPORT PART C
MCH LAKEPORT PART C
MCH LAKEPORT PART C
N81
N81
N81
1
A
A
11 39Wednesday, May 20, 2009
11 39Wednesday, May 20, 2009
11 39Wednesday, May 20, 2009
A
5
D D
C C
Note:
+V3.3S
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C687
C687
C0402
B B
C0402
SO-DIMM0 SPD Address is 0xA0
SO-DIMM0 TS Address is 0x30
C688
C688
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
MA_A_A[13:0]10,13
MA_A_A1413
MA_A_BS#210,13
MA_A_BS#010,13
MA_A_BS#110,13
M_CS#010,13
M_CS#110,13
MA_DM[7:0]10
MA_A_WE#10,13
MA_A_CAS#10,13
MA_A_RAS#10,13
M_CKE010,13
M_CKE110,13
M_CLK_DDR110
M_CLK_DDR#110
M_CLK_DDR010
M_CLK_DDR#010
M_ODT010,13
M_ODT110,13
MA_DQS[7:0]10
SMB_DATA_S6,18,22,23
SMB_CLK_S6,18,22,23
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C689
C689
C0402
C0402
MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3
MA_DQS4
MA_DQS5
MA_DQS6
MA_DQS7
R779 10K R0402R779 10K R0402
R780 10K R0402R780 10K R0402
SM_VREF_L
close to DDR pin
MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
C690
C690
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
4
DIM1
DIM1
DDR2_SODIMM200
DDR2_SODIMM200
+V1.8
DDR200STD_5D2
DDR200STD_5D2
112
111
117
118
VDD1
VDD2
VDD3
VDD496VDD595VDD6
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16_BA2
107
BA0
106
BA1
110
CS0
115
CS1
10
DQM0
26
DQM1
52
DQM2
67
DQM3
130
DQM4
147
DQM5
170
DQM6
185
DQM7
109
WE
113
CAS
108
RAS
79
CKE0
80
CKE1
30
CK0
32
CK0
164
CK1
166
CK1
114
ODT0
119
ODT1
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
195
SDA
197
SCL
198
SA0
200
SA1
199
VDDSPD
1
VREF1
83
NC1
120
NC2
50
NC3
69
NC4
163
NCTEST
VDD781VDD882VDD9
1010 000x
VSS2
VSS3
VSS477VSS512VSS648VSS7
VSS1
47
133
183
87
103
104
187
178
VSS34
VSS35
VDD10
VDD1188VDD12
DDRII
VSS878VSS971VSS1072VSS11
VSS12
VSS13
184
121
122
196
190
155
132
144
156
VSS36
VSS379VSS3821VSS3933VSS40
VSS4134VSS42
VSS43
VSS14
VSS158VSS1618VSS1724VSS1841VSS1953VSS2042VSS2154VSS2259VSS2365VSS2460VSS2566VSS26
193
168
VSS44
VSS45
VSS462VSS473VSS4815VSS4927VSS5039VSS51
3
SO-DIMM 0
40
150
138
162
149
161
28
MA_DATA0
5
VSS54
VSS56
VSS55
VSS57
VSS52
VSS53
D0
MA_DATA1
7
D1
MA_DATA2
17
D2
MA_DATA3
19
D3
MA_DATA4
4
D4
MA_DATA5
6
D5
MA_DATA6
14
D6
MA_DATA7MA_A_A7
16
D7
MA_DATA8
23
D8
MA_DATA9
25
D9
MA_DATA10
35
D10
MA_DATA11
37
D11
MA_DATA12
20
D12
MA_DATA13
22
D13
MA_DATA14
36
D14
MA_DATA15
38
D15
MA_DATA16
43
D16
MA_DATA17
45
D17
MA_DATA18
55
D18
MA_DATA19
57
D19
MA_DATA20
44
D20
MA_DATA21
46
D21
MA_DATA22
56
D22
MA_DATA23
58
D23
MA_DATA24
61
D24
MA_DATA25
63
D25
MA_DATA26
73
D26
MA_DATA27
75
D27
MA_DATA28
62
D28
MA_DATA29
64
D29
MA_DATA30
74
D30
MA_DATA31
76
D31
MA_DATA32
123
D32
MA_DATA33
125
D33
MA_DATA34
135
D34
MA_DATA35
137
D35
MA_DATA36
124
D36
MA_DATA37
126
D37
MA_DATA38
134
D38
MA_DATA39
136
D39
MA_DATA40
141
D40
MA_DATA41
143
D41
MA_DATA42
151
D42
MA_DATA43
153
D43
MA_DATA44
140
D44
MA_DATA45
142
D45
MA_DATA46
152
D46
MA_DATA47
154
D47
MA_DATA48
157
D48
MA_DATA49
159
D49
MA_DATA50
173
D50
MA_DATA51
175
D51
MA_DATA52
158
D52
MA_DATA53
160
D53
MA_DATA54
174
D54
MA_DATA55
176
D55
MA_DATA56
179
D56
MA_DATA57
181
D57
MA_DATA58
189
D58
MA_DATA59
191
D59
MA_DATA60
180
D60
MA_DATA61
182
D61
MA_DATA62
192
D62
MA_DATA63
194
D63
MA_DQS#0
11
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
VSS27
VSS29
VSS30
VSS31
VSS32
VSS28
VSS33
GND0
127
139
145
165
171
172
128
177
201
202
GND1
MA_DQS#1
29
MA_DQS#2
49
MA_DQS#3
68
MA_DQS#4
129
MA_DQS#5
146
MA_DQS#6
167
MA_DQS#7
186
MA_DATA[63:0] 10
MA_DQS#[7:0] 10
220UF/2.5V,POSCAP
220UF/2.5V,POSCAP
2
+V1.8
12
C673
C673
1
1
C674
C674
+
+
ns
ns
CT7343_19
CT7343_19
C0402
C0402
0.1UF/25V,Y5V
0.1UF/25V,Y5V
2.2UF/10V,X7R
2.2UF/10V,X7R
ns C179
Swain 080515
+V1.8
C682
C682
C681
C681
C0402
C0402
C0805
C0805
2.2UF/10V,X7R
2.2UF/10V,X7R
0.1UF/25V,Y5V
0.1UF/25V,Y5V
Layout note:
C676
C676
C675
C675
ns
ns
C0805
C0805
C0805
C0805
2.2UF/10V,X7R
2.2UF/10V,X7R
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C683
C683
C0805
C0805
2.2UF/10V,X7R
2.2UF/10V,X7R
0.1UF/25V,Y5V
0.1UF/25V,Y5V
电容靠近
DDR slot VDD PIN
C677
C677
C0402
C0402
2.2UF/10V,X7R
2.2UF/10V,X7R
C684
C684
ns
ns
C0402
C0402
2.2UF/10V,X7R
2.2UF/10V,X7R
C678
C678
C0805
C0805
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C685
C685
ns
ns
C0805
C0805
0.1UF/25V,Y5V
0.1UF/25V,Y5V
1
+V3.3S 6,7,8,14,15,16,17,18,19,20,21,22,23,24,25,26,27,31,32,33,35,36
+V1.8 10,11,30,31,33,35
C679
C679
C680
C680
ns
ns
ns
ns
C0402
C0402
C0805
C0805
2.2UF/10V,X7R
2.2UF/10V,X7R
1, A minimum of 9 high frequency
capacitors are recommended to be
placed near each SO-DIMM of DDR2.
2, 2.2μF*5 per DIMM,0.1μF*4 per
DIMM,330μF*1 per DIMM
C686
C686
C0402
C0402
+V1.8
R769
R769
1K,1%
1K,1%
SM_VREF_L
C691
C691
R768
R768
0.1uF/10V,X5R
0.1uF/10V,X5R
1K,1%
1K,1%
A A
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
5
4
3
2
the expressed written consent of TOPSTAR
(Swain Xu)
DDR2 SODIMM0
DDR2 SODIMM0
DDR2 SODIMM0
N81
N81
N81
1
A
A
12 39Wednesday, May 20, 2009
12 39Wednesday, May 20, 2009
12 39Wednesday, May 20, 2009
A
5
4
3
2
1
+V0.9S
RN27 56x4 RA0402_8RN27 56x4 RA0402_8
1 2
D D
+V0.9S
RN32 56x4 RA0402_8RN32 56x4 RA0402_8
1 2
3 4
5 6
C C
B B
7 8
RN33 56x4 RA0402_8RN33 56x4 RA0402_8
1 2
3 4
5 6
7 8
MA_A_A[13:0]10,12
MA_A_A8
MA_A_A5
MA_A_A3 MA_A_A13
MA_A_A1
MA_A_A12
MA_A_A9
MA_A_BS#2 10,12
+V0.9S
3 4
5 6
7 8
RN29 56x4 RA0402_8RN29 56x4 RA0402_8
1 2
3 4
5 6
7 8
RN31 56x4 RA0402_8RN31 56x4 RA0402_8
1 2
3 4
5 6
7 8
R786 56 R0402R786 56 R0402
R788 56 R0402R788 56 R0402
R789 56 R0402R789 56 R0402
RN34 56
RN34 56
1 2
3 4
RN38 56
RN38 56
1 2
3 4
R790 56 R0402R790 56 R0402
RA0402_4
RA0402_4
RA0402_4
RA0402_4
MA_A_A10
MA_A_A2
MA_A_A0
MA_A_A11
MA_A_A7
MA_A_A6
MA_A_A4
MA_A_A14
MA_A_BS#0 10,12
MA_A_WE# 10,12
MA_A_CAS# 10,12
MA_A_BS#1 10,12
MA_A_RAS# 10,12
M_CKE0 10,12
M_CKE1 10,12
M_CS#1 10,12
M_ODT1 10,12
M_CS#0 10,12
M_ODT0 10,12
MA_A_A14 12
+V0.9S
每4个电阻两个
C714
C714
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C721
C721
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C715
C715
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C722
C722
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
0.1UF
C716
C716
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C723
C723
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
电容
C717
C717
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C724
C724
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
to +V0.9SLayout note:Place one cap close toevery 2 pullup resistors terminated
C718
C718
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C725
C725
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
+V0.9S 30,35
C720
C720
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C726
C726
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C719
C719
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C727
C727
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
A A
5
4
3
2
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
DDR2 TERM and Decoupling
DDR2 TERM and Decoupling
DDR2 TERM and Decoupling
N81
N81
N81
13 39Wednesday, May 20, 2009
13 39Wednesday, May 20, 2009
13 39Wednesday, May 20, 2009
1
A
A
A
5
Cross moat
place
FB12
FB12
47ohm@100MHz,500mA
47ohm@100MHz,500mA
FB0603
FB0603
C164
C164
5.6pF/50V NPO
5.6pF/50V NPO
C0402
C0402
C165
C165
5.6pF/50V NPO
5.6pF/50V NPO
C0402
C0402
C171
C171
5.6pF/50V NPO
5.6pF/50V NPO
C0402
C0402
R123 100,1%
R123 100,1%
R0402
R0402
1 2
FB13
FB13
47ohm@100MHz,500mA
47ohm@100MHz,500mA
FB0603
FB0603
1 2
FB14
FB14
47ohm@100MHz,500mA
47ohm@100MHz,500mA
FB0603
FB0603
1 2
AVS
C75
C75
10pF/50V,NPO
10pF/50V,NPO
C0402
C0402
RED9
R172
R172
150,1%
150,1%
R0402
R0402
D D
C C
150ohm
走线阻抗
GREEN9
BLUE9
电阻前
50ohm
ESDPAD_R0603
ESDPAD_R0603
EGA1-0603-V05
EGA1-0603-V05
R173
R173
150,1%
150,1%
R0402
R0402
R174
R174
150,1%
150,1%
R0402
R0402
12
D1
D1
ns
ns
R84
R84
2K,1%
2K,1%
R0402
R0402
C162
C162
5.6pF/50V NPO
5.6pF/50V NPO
C0402
C0402
C166
C166
5.6pF/50V NPO
5.6pF/50V NPO
C0402
C0402
C172
C172
5.6pF/50V NPO
5.6pF/50V NPO
C0402
C0402
HSYNC9VSYNC9
ESDPAD_R0603
ESDPAD_R0603
EGA1-0603-V05
EGA1-0603-V05
D3
D3
ns
ns
BOUT
ROUT
12
R82
R82
75,1%
75,1%
R0402
R0402
R129
R129
75,1%
75,1%
R0402
R0402
R69
R69
75,1%
75,1%
R0402
R0402
R124 100,1%
R124 100,1%
R87
R87
2K,1%
2K,1%
R0402
R0402
C81
C81
10pF/50V,NPO
10pF/50V,NPO
C0402
C0402
C85
C85
10pF/50V,NPO
10pF/50V,NPO
C0402
C0402
C78
C78
10pF/50V,NPO
10pF/50V,NPO
C0402
C0402
R0402
R0402
4
R125 100,1%
R125 100,1%
R0402
R0402
R126 100,1%
R126 100,1%
R0402
R0402
R127 100,1%
R127 100,1%
R0402
R0402
R131 100,1%
R131 100,1%
R0402
R0402
R130 100,1%
R130 100,1%
R0402
R0402
R79 100,1%
R79 100,1%
R0402
R0402
R81 100,1%
R81 100,1%
R0402
R0402
AHS
C76
C76
10pF/50V,NPO
10pF/50V,NPO
C0402
C0402
C82 0.047uF/16V,X7R
C82 0.047uF/16V,X7R
C0402
C0402
C83 0.047uF/16V,X7R
C83 0.047uF/16V,X7R
C0402
C0402
C84 0.047uF/16V,X7R
C84 0.047uF/16V,X7R
C0402
C0402
C86 0.047uF/16V,X7R
C86 0.047uF/16V,X7R
C0402
C0402
C77 0.047uF/16V,X7R
C77 0.047uF/16V,X7R
C0402
C0402
C79 0.047uF/16V,X7R
C79 0.047uF/16V,X7R
C0402
C0402
C80 0.047uF/16V,X7R
C80 0.047uF/16V,X7R
C0402
C0402
DDC_CLK9,26
DDC_DATA9,26
R+
R-
G+GOUT
G-
B+
+V3.3S
3
+V3.3S
C765
C765
1uF/10V,Y5V
SOG
B-
R10
R10
2.2K
2.2K
R0402
R0402
+V3.3S
R5
R5
2.2K
2.2K
R0402
R0402
R128
R128
1M
1M
R0402
R0402
1uF/10V,Y5V
C0603
C0603
RESET
R133
R133
4.7K
4.7K
R0402
R0402
EC_DDC_DATA9,26
EC_DDC_CLK9,26
R820 0 R0402 nsR820 0 R0402 ns
R821 0 R0402 nsR821 0 R0402 ns
XI
XO
DGND
DGNDDGND
ADC_VDDADC_VDD
B-BB+B+
G-GG+G+
SOG
R-RR+R+
DGND
ADC_REF
DDC_DATA
DDC_CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AHSAHSAHSAHSAHSAHSAHS
16
T7nsT7
ns
XIN
XOUT
AGND
REXT
ADC_GND
ADC_VDD33
BIN1BIN1+
GIN1GIN1+
SOG0
RIN1RIN1+
ADC_RN
ADC_RP
HSYNC
T6nsT6
ns
2
61
62
64
GPIO260GPIO3
GPIO463GPIO5
GPIO/PWM5
VSYNC17DDC_SDA/TX18DDC_SCL/RX19GPIO/PWM020SPI_SDO21SPI_CE22SPI_SCL23SPI_SDI
IVT_I_ADJ
AVS
R819 0 R0402R819 0 R0402
R815 0 R0402R815 0 R0402
R816 0 R0402R816 0 R0402
R817 0 R0402R817 0 R0402
PIN58
PIN56
PIN57
RESET
Core_DVCC
53
54
55
56
59
RST
GPIO1
DVDD12
GPIO/ADC057GPIO/ADC158GPIO/ADC2
GPIO/PWM3
RTD2270L
RTD2270L
24
25
PIN25
SDIN
CLKCESDOUT
PVCC
LDO_CTL
51
52
LDO_CTL
Flash_WP
Core_DVCC
PVDD33
DGND
1
+V3.3S 6,7,8,12,15,16,17,18,19,20,21,22,23,24,25,26,27,31,32,33,35,36
LVDS_VDDEN 15
BKLT+ 26,27
BKLT- 26,27
LCDSW# 26,27
VGA_LVDS_YAN0 15
VGA_LVDS_YAP0 15
U43
U43
49
50
IC_RTD2270L_64
IC_RTD2270L_64
TXO0-
TXO0+
48
VGA_LVDS_YAN1 15
47
VGA_LVDS_YAP1 15
46
VGA_LVDS_YAN2 15
45
VGA_LVDS_YAP2 15
44
VGA_LVDS_CLKAN 15
43
VGA_LVDS_CLKAP 15
42
VGA_LVDS_YAN3 15
41
VGA_LVDS_YAP3 15
40
VGA_LVDS2_YAN0 15
39
VGA_LVDS2_YAP0 15
38
VGA_LVDS2_YAN1 15
37
VGA_LVDS2_YAP1 15
36
VGA_LVDS2_YAN2 15
35
VGA_LVDS2_YAP2 15
34
VGA_LVDS2_YAN3 15
33
VGA_LVDS2_YAP3 15
VGA_LVDS_CLKAN/P ver A error, update it
许沐锌
090504
DGND32DGND31DVDD1230DGND29GPIO/PWM228GPIO/PWM127GPIO/I2C_MDL_126GPIO/I2C_MDA_1
DGND
TXO1-
TXO1+
TXO2-
TXO2+
TXOC-
TXOC+
TXO3TXO3+
TXE0-
TXE0+
TXE1-
TXE1+
TXE2-
TXE2+
TXE3-
TXE3+
CONTROL IC
+V3.3S
B B
Flash_WP
R804 0 R0402
A A
R804 0 R0402
L25
L25
1 2
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
FB0805
FB0805
L26
L26
1 2
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
FB0805
FB0805
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
600ohm@100MHz,1.5A
+V3.3S +V3.3S
ns
ns
5
C73
C73
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
C762
C762
0.1uF/10V,X5R
0.1uF/10V,X5R
L23
L23
1 2
FB0805
FB0805
L24
L24
1 2
FB0805
FB0805
C74
C74
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
R805
R805
10K
10K
R0402
R0402
R806
R806
10K
10K
R0402
R0402
ns
ns
PVCC
C763
C763
0.1uF/10V,X5R
0.1uF/10V,X5R
ADC_VDD
C761
C761
0.1uF/10V,X5R
0.1uF/10V,X5R
C764
C764
0.1uF/10V,X5R
0.1uF/10V,X5R
ADC_REF
C758
C758
0.1uF/10V,X5R
0.1uF/10V,X5R
8
VCC
7
HOLD
3
WP
VSS4SDA
Core_DVCCBJTVCC
C757
C757
0.1uF/10V,X5R
0.1uF/10V,X5R
U2
U2
SDO
CE
SCL
SERIAL FLASH
SERIAL FLASH
SO8_50_150
SO8_50_150
C759
C759
1uF/10V,Y5V
1uF/10V,Y5V
C0603
C0603
2
1
6
5
R800 22 R0402R800 22 R0402
R807 22 R0402R807 22 R0402
R808 22 R0402R808 22 R0402
R811 22 R0402R811 22 R0402
+V3.3S
+V3.3S
R810 0 R0402R810 0 R0402
R812 0 R0402R812 0 R0402
R132
R132
4.7K
4.7K
R0402
R0402
SDOUT
CE
CLK
SDIN
R67
R67
4.7K
4.7K
R0402
R0402
4
CLK
C760
C760
0.1uF/10V,X5R
0.1uF/10V,X5R
2 3
MMBT2907
MMBT2907
SOT23
SOT23
1
Q9
Q9
R809
R809
1K
1K
R0402
R0402
ns
ns
LDO_CTL
2 3
MMBT2907
MMBT2907
SOT23
SOT23
PIN25
R814 0 R0402R814 0 R0402
BJTVCC
1
Q14
Q14
POWER
C423
C423
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
C422
C422
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
DGND
12
Y7
Y7
14.318180MHz
14.318180MHz
XS2_3D3
XS2_3D3
XI
R818 22
R818 22
R0402
R0402
XO
FLASH
3
2
IVT_I_ADJ 15
LVDS_BKLTEN 15,26
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
TOPSTAR TECHNOLOGY
许沐锌
(Swain Xu)
许沐锌
(Swain Xu)
许沐锌
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
the expressed written consent of TOPSTAR
(Swain Xu)
VGA TO LVDS
VGA TO LVDS
VGA TO LVDS
N81
N81
N81
1
14 39Wednesday, May 20, 2009
14 39Wednesday, May 20, 2009
14 39Wednesday, May 20, 2009
A
A
A
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