TOPSTAR M42G Schematics

5

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1

Topstar Digital technologies Co.,LTD

D D

Board name: MotherBoard Schematic

Project name: M42

Version: VerA

Initial Date: Sep.22, 2007

02. System block & Index

03. PWR Block & Description

04. Notes & Annotations

05. Schematic Modify and History

54. CLOCK Distribution

C C

55. Power Distribution

56. Power on & off Sequence

57. ACPI Mode Switch Timings

58. Power On Sequence & Reset Map

Topstar Confidential

B B

Hardware drawing by:

Power drawing by:

Hardware check by: EMI Check by:

Power check by:

Manager Sign by:

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

A A

5

4

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2

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Lucifer Jiang
Title

Title

Title

M42G

M42G

M42G

150Tuesday, March 11, 2008

150Tuesday, March 11, 2008

150Tuesday, March 11, 2008

1

A

A

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Topstar Confidential

D D

Backlight
Connector

+VDC

TFT

+V3.3S

C C

VGA

+V5S

LVDS

R/G/B

TMDS

HDMI

PCIE mini Card

B B

PCIE mini Half-Card

NEW CARD(Type II)

Fingerprint

+V5AL

BLUE
TOOTH(V1.2)

BTM-203/CCOM

+V3.3S

+V3.3AL

ShenZhen Topstar Industry Co.,LTD

M42G SYSTEM BLOCK Ver:A

+V3.3S

PCIE 1X

USB1.1/2.0

Camera

1.3M/2.0M
MODULE

CPU
Thermal
Sensor

ASC7525

PCI-Express X16

BIOS

8Mbit

+V3.3AL

USB PORT1

+V5AL

Penryn

478 uFCPGA

+VCC_CORE,+VCCP
+VCCA1.5

CANTIGA GM

1329 FCBGA

+V3.3S,+V1.5S,
+VGFX_1_05S,
+V1.05S,+V1.8

Control
Link 0

SPI

KB Controller/EC

W83L951ADG/DG

+V3.3AL,+V3.3S,+V5AL

ICH9-M

676 PBGA

+V1.05S,+V3.3S
+V3.3AL,+V5AL
+V1.5S,+V5S
+V3.3A_RTC

LPC

FSB
667MHz/800MHz/1066MHz

DMI
x2/x4

CK505M
Clocking

CY28548
/ICS9LPRS365

DDR2 667/800

DDR2 667/800

PCIE 1X

USB1.1/2.0

AZALIA

+V3.3S,+V1.25S

DDR2 SODIMM0
667/800

+V0.9S,+V1.8,+V3.3S

DDR2 SODIMM1
667/800

+V0.9S,+V1.8,+V3.3S

POWERBTN/RJ45/LAN/USB

DAUGHTER BOARD

RTL8101E

+V3.3S,+V3.3AL,VDD3D3_LAN

SATA ODD

+V5S

S-ATA

2.5" HDD

+V5S,+V3.3S

Card Reader

ENE UB6232

+V3.3S,+V3.3AL

USB PORT

SD/MMC/MS CARD

RJ45

CONTENT

01 Title
02 System Block & Index
03 PWR Block & Description
04 Notes and Annotations
05 Schematic Modify and History
06 CK505M(CY28516&ICS9LPR365)
07 PENRYN CPU(Host BUS)(1of 2)
08 PENRYN CPU(PWR&GND)(2 of 2)
09 CANTIGA (HOST)(1 of 6)
10 CANTIGA (Graphic)(2 of 6)
11 CANTIGA (DDRII)(3 of 6)
12 CANTIGA (DMI&CLK)(4 of 6)
13 CANTIGA (VSS&NCTF)(5 of 6)
14 CANTIGA (Power)(6 of 6)
15 DDR2 SODIMM0
16 DDR2 SODIMM1
17 DDR2 Series Termination
18 DDR2 Decoupling
19 LVDS&INVERTER CONN
20 VGA&SVIDEO&DC-IN
21 HDMI
22 ICH9_M(1 of 3)
23 ICH9_M(2 of 3)
24 ICH9_M(3 of 3)
25 SATA CONN(ODD&DVD)
26 Card Reader(UB6232 USB)
27 EXPRESS CARD
28 PCIE MINI SLOT1
29 PCIE MINI SLOT2
30 LAN/POWER Connector
31 ALC662 AZALIA CODEC
32 MDC & BT & FAN & OTP
33 USB2.0 & TPM & Gsensor & LED Conn
34 KBC(W83L951ADG)
35 ADAPTER IN
36 BATTERY IN
37 +V3.3AL +V5AL
38 +V1.8/+V0.9S DDR
39 +V1.5S/+V1.05S CHIPSET
40 +V1.5AL
41 Power Good Logic/OVP
42 +VCC_CORE
43 SYSTEM/DISCHARGE
44 CHARGER
45 THROUGH HOLE/EMI
46 ACPI mode switch timings
47 Clock Distribution
48 Power ON/OFF & Reset seq
49 Power On/off Sequence
50 Power Distribution

TCM

L

R

AZALIA

LED/TouchPAD/Button/

DAUGHTER BOARD

KB Matrix

A A

5

4

Q-key/LID

DAUGHTER BOARD

ALC662

+V5S,+V3.3S

3

MiC

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Lucifer Jiang
System Block

System Block

System Block

M42G

M42G

M42G

1

A

A

250Tuesday, March 11, 2008

250Tuesday, March 11, 2008

250Tuesday, March 11, 2008

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注意:

虚线表示电源电压信号。

D D

Charge
ISL6251

Page 55

Battery

44A

+VCC_CORE

VIN

V_5

V_3

+V1.8
+V0.9S

4A

VCC_CORE
ISL6262A

Page 48,49

+V5S
+V3.3S

System Power
+V_S

Page 46

Adapter

90W

C C

VGA_CORE
TPS51117RGY

Chipset PWR
TPS51124

Page 43

Power
Switch

Page 38

Always_On
Power
TPS51120

Page 41

+VDC

5A

DDR Power
TPS51116

Page 42

+V3.3AL
+V5AL +V1.5AL

5A/5A

+VGA_CORE

+V1.5S
+V1.05S

5A/5A

10A

MOSFET
SWITCH

B B

Page 45

+V1.25S

2A

6A/2.5A

+V1.8GDDR

Platform
Logic

VR_ON

IMVP-6

CLK_ENABLE#

DPRSLPVR

IMVP6_PWRGD

Vcc_sense

ICH-M CPU-M

VR_TT#
Vcc_core

VID[6...0]
PSI#
DPRSTP#

Vss_sense

DPRSTP#

CPU_PWRGD

CLK
CHIP

PSI#

PROCHOT#

M42 POWER BLOCK Ver:A

BATT+

+V5AL

+V3.3AL

+V1.8

+V1.5S

+V1.05S

+VCC_CORE

+VGA_CORE

OVP Circuit

Page 43,52

A A

Page Name

Page Name

Page Name
Size

Size

OVP

16.5V

OVP

5.6V

5

OVP

3.6V

OVP

2.0V

4

OVP

2.0V

OVP

2.0V

3

OVP

2.0V

OVP

2.0V

2

Size

Project Name Rev

Project Name Rev

Project Name Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Lucifer Jiang

PWR Block & description

PWR Block & description

PWR Block & description

M42G

M42G

M42G

1

B

B

350Tuesday, March 11, 2008

350Tuesday, March 11, 2008

350Tuesday, March 11, 2008

B

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of

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5

A

4

3

2

1

Voltage Rails

+VDC
+VCC_CORE

+V1.5S

D D

+V1.05S
+V0.9S
+V1.8

+V3.3AL

+V3.3S
+V5AL
+V5S
+VGA_CORE

+V1.5AL

+V1.8DDR

C C

Board stack up description

PCB Layers

TOP

GND

IN1

IN2

VCC

IN3

GND

Bottom

B B

Primary DC system power supply(9V-19V)
Core voltage for processor

1.5V for CPU PLL

1.05V for FSB VTT

0.9V DDR2 Termination voltage

1.8V power rail for DDR2

3.3V always on power rail

3.3V main power rail
5V for USB Device
5V main power rail

1.15V for GPU NB8M core voltage

1.5AL for HDMI

1.8V for DDR

Trace Impedence:55ohm +/-15%(Default)

I2C SMB Address

Device

Clock Generator
SO-DIMM0
SO-DIMM1
NEW CARD
PCIE Mini CARD

Smart Battery
CPU Thermal

Sensor(ASC7525)

Power States/AC mode

Signal

S0(Full On)

S3(STM)

S4(STD)

S5(SoftOff)

Address

1101 001x
1010 000x

1001 100x I2C

SLP_S3#

HIGH

LOW

LOW OFF

LOW

BusHex

HIGH

HIGH

HIGH

LOW

SMB_ICH_S
SMB_ICH_S
SMB_ICH_S1010 010x

I2C

+V*AL

ON

ON

ON

D2
A0
A4
Variable SMB_ICH_SVariable
Variable SMB_ICH_SVariable

160001 011x
98

SLP_S4#

SLP_S5#

HIGH

HIGH ON OFF

LOW

LOW

Master

ICH9M
ICH9M
ICH9M
ICH9M

ICH9M
W83L951ADG
W83L951ADG

+V*

ON ON

ON

OFF

+V*S

OFF

OFF

OFF

Clock

ON

OFF

OFF

USB Table

USB Port#

0

1

2

3

4

5

6

7

8

9

Function Description

Express Card

RESERVED

USB Port(on Main Board)

Mini PCIE Card(WLAN & ROBSON)

Mini PCIE Card(WLAN & ROBSON)

Bluetooth

USB Port(on I/O Board)

USB CAMERA(On VGA Board)

CARD Reader

USB Port(on I/O Board)

Wake up Events

LID switch from EC
Power switch from EC

ns: Component marked "ns" is not stuff

This is a lead free project,all component must be LF

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

Lucifer Jiang

NOTE

NOTE

NOTE
M42G

M42G

M42G

450Tuesday, March 11, 2008

450Tuesday, March 11, 2008

450Tuesday, March 11, 2008

of

of

of

B

B

B

A

5

Schematic modify Item and history:

4

3

2

1

Cost Down list

2007-10-26 Ver A initial release

2007-12-28 Ver B release

1 P6 CLK C112 ns change to 18pf stuff for EMC issue
2 P7 Host clk CLK_CPU_BCLK（#） add far end diff termination as DG and intel FAE advised
3 P7 Thermal sensor7525 change to 75393
4 P8 BRACKET1_Mylarchange to bi-side sticky malyer

D D

5 P9 CPU bracket holesupport hold change to esd protection type
6 P22 IFPCD_IOVDD_FBIFPCD_IOVDD_FB add circuit for voltage leakage issue
7 P23 CameraAdd camera_on control circuit
8 P24 CRTC8 C9 C10 ns change to 22p stuff for vga emc issue
9 P25 HDMI EMCAdd common choke for HDMI emc issue
10 P27 spi bootR497 ns to stuff for boot from spi
11 P28 V1.5ALdelete for cost down
12 P32 EP_MYLAR1change as S42
13 P36 MIC1_JDMIC1_JD connect to sense B , reserved route to sense A
14 P36 Audio Jack esdD40 D41 D42 D43 change from bat54s to ESDPAD
15 P39 KBCADG change to DG
16 P39 CrystalDelete 32.768 crystal for no using
17 P39 KBC flashpull down reset# and test# for flash KBC
18 P39 "MCH_TSATN# EC_BKLT_PWM"swap these two pins for association with other cases

C C

B B

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

Lucifer Jiang

Sch Modify and history

Sch Modify and history

Sch Modify and history

M42G

M42G

M42G

1

B

B

B

of

of

of

550Tuesday, March 11, 2008

550Tuesday, March 11, 2008

550Tuesday, March 11, 2008

5

+V3.3S

+V3.3S

FB26

FB26

12

FB0805

+VDDIO_CLK

100ohm@100MHz,3A

100ohm@100MHz,3A

C343

C343
C0805

C0805

FB0805

ns

ns

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

C0805

C336

C336

C0805 ns

C0805 ns

C338

C338

C0805

C0805

C345

C345

C0805 ns

C0805 ns

C344

C344

C337

C337

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C333

C333

0.1UF/25V,Y5V

0.1UF/25V,Y5V

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C342

C342

0.1UF/25V,Y5V

0.1UF/25V,Y5V

27M_SEL

C341

C341

C339

C339

D D

10UF/6.3V,X5R

10UF/6.3V,X5R

C C

B B

100ohm@100MHz,3A

100ohm@100MHz,3A

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C340

C340

0.1UF/25V,Y5V

0.1UF/25V,Y5V

+V3.3S

R411

R411
10K

10K
ns

ns

R410

R410
10K

10K

FB27

1 2

+VDDIO_CLK

+VDDIO_CLK

+VDDIO_CLK

+VDDIO_CLK

FB0805FB27

FB0805

C348

C348

C0805

C0805

10UF/6.3V,X5R

10UF/6.3V,X5R

C122

C122

27pF/50V,NPO

27pF/50V,NPO

C121

C121

27pF/50V,NPO

27pF/50V,NPO

4

C351

C351

0.1UF/25V,Y5V

0.1UF/25V,Y5V

12

Y3

Y3

XS2

XS2

14.318180MHz

14.318180MHz

C347

C347

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C115

C115

0.1UF/25V,Y5V

0.1UF/25V,Y5V

CLK_USB48{23}

C350

C350

C0805

C0805

4.7UF/10V,Y5V

4.7UF/10V,Y5V

CLK_ICH14{23}

CLK_BSEL0

CLK_BSEL2

C346

C346

0.047uF/16V,Y5V

0.047uF/16V,Y5V

C335

C335

0.047uF/16V,Y5V

0.047uF/16V,Y5V

SATA_CLKREQ#{23}

CLK_TCMPCI{32}

CLK_591PCI{34}

CLK_debugPCI{28}

CLK_ICHPCI{23}

R164 33R164 33
R166 2.2KR166 2.2K
R172 33R172 33
R176 10KR176 10K

3

+V3.3S_CK_VDD

C349

C349

0.1UF/25V,Y5V

0.1UF/25V,Y5V
+V3.3S_CK_VDD

+V3.3S_CK_VDD

+V3.3S_CK_VDD

+V3.3S_CK_VDD

+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK

+VDDIO_CLK

SATA_CLKREQ#

R690 22 TCMR690 22 TCM

R173 22R173 22
R412 22 DebugR412 22 Debug
R171 22R171 22

R180475,1%R180475,1%

R168

R168
10K

10K

TME

27M_SEL

PCIF_ITP_EN

XTAL_IN
XTAL_OUT

CLK_BSEL1

U4

U4

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

61

VDD_REF

39

VDD_SRC

55

VDD_CPU

12

VDD_IO

20

VDD_PLL3_IO

26

VDD_SRC_IO_1

36

VDD_SRC_IO_2

45

VDD_SRC_IO_3

49

VDD_CPU_IO

1

PCI0/OE#_0/2_A

3

PCI1/OE#_1/4_A

4

PCI2/TME

5

PCI3/FSD

6

PCI4/SRC5_SEL

7

PCIF5/ITP_EN

60

XTAL_IN

59

XTAL_OUT

10

USB_48/FSA

57

FSB/TEST_MODE

62

REF0/FSC/TEST_SEL

8

VSS_PCI

11

VSS_48

15

VSS_IO

19

VSS_PLL3

52

VSS_CPU

23

VSS_SRC_1

29

VSS_SRC_2

58

VSS_REF

42

VSS_SRC3

CY28548

CY28548
TSSOP64_0D5_6D1

TSSOP64_0D5_6D1

IO_VOUT

SMB_DATA

SMB_CLK

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

CPU0

CPU0#

CPU1

CPU1#

SRC8/CPU2_ITP

SRC8#/CPU2#_ITP

SRC10

SRC10#

SRC11/OE#_10
SRC11#/OE#_9

SRC9

SRC9#

SRC7/OE#_8

SRC7#/OE#_6

SRC6

SRC6#

SRC4

SRC4#

SRC3/OE#_0/2_B

SRC3#/OE#_1/4_B

SRC2/SATA

SRC2#/SATA#

SRC1/SE1

SRC1#/SE2

SRC0/DOT96

SRC0#/DOT96#

CK_PWRGD/PWRDWN#

2

48
63

64

38
37

54
53

51
50

47
46

34
35

EXP_CLKREQ

33

MPCIE_CLKREQ

32
30

31
44

43
41

40
27

28
24

25
21

22
17

18
13

14
56

+V3.3S {7,10,12,14,15,16,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,39,41,42,43}
+V1.05S {7,8,9,12,13,14,22,24,32,39,41,42,43,45}

SMB_DATA_S {15,16,23,27,28,29}
SMB_CLK_S {15,16,23,27,28,29}

PM_STPPCI# {23}

CPU0

RN11 33

RN11 33

CPU#0
CPU1

RN9 33

RN9 33

CPU#1

RN8 33

RN8 33

RN5 33

RN5 33

RN2

RN6 33

RN6 33

RN3 33

RN3 33

RN4 33

RN4 33

RN7 33

RN7 33

RN26 33

RN26 33

RN10 33

RN10 33

1 2
3 4

1 2
3 4

1 2
3 4

3 4
1 2

3 4
1 2

1 2
3 4

1 2
3 4

3 4
1 2

3 4
1 2

3 4
1 2

3 4
1 2

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

R147 475,1%R0402 nsR147 475,1%R0402 ns
R137 475,1%R0402R137 475,1%R0402

33

33

RA0402_4RN2

RA0402_4

RA0402_4Half-MiniCard

RA0402_4Half-MiniCard

RA0402_4MINPCIE

RA0402_4MINPCIE

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

RA0402_4

PM_STPCPU# {23}
CLK_CPU_BCLK {7}

CLK_CPU_BCLK# {7}
CLK_MCH_BCLK {9}

CLK_MCH_BCLK# {9}
CLK_PCIE_ICH {23}

CLK_PCIE_ICH# {23}
CLK_PCIE_MINICARD {28}

CLK_PCIE_MINICARD# {28}
EXPCARD_CLKREQ# {27}

PCIE_CLKREQ# {12}

CLK_MCH_3GPLL {12}
CLK_MCH_3GPLL# {12}

CLK_PCIE_ROBSON {29}
CLK_PCIE_ROBSON# {29}

CLK_PCIE_GLAN {30}
CLK_PCIE_GLAN# {30}

CLK_PCIE_EXPCARD {27}
CLK_PCIE_EXPCARD# {27}

CLK_ICH_SATA {22}
CLK_ICH_SATA# {22}

DREFSSCLK {12}
DREFSSCLK# {12}

DREFCLK {12}
DREFCLK# {12}

CLK_PWRGD {23}

1

不支持

NEW CARD request

+V1.05S

+V3.3S

R408

R408
56

56
ns

+V1.05S

ns

R409

R409
1K

1K
ns

ns

R170

R170
1K

1K
ns

ns

R169

R169
1K

1K
ns

ns

R165 1KR165 1K

R167 1KR167 1K

5

MCH_BSEL0 {12}
CLK_BSEL0 {7}

MCH_BSEL1 {12}
CLK_BSEL1 {7}

CLK_BSEL2

+V1.05S

C113

+V1.05S

R179

R179
1K

1K
ns

ns

R178 1KR178 1K

R175

R175
1K

1K
ns

ns

4

C113

0.1UF/25V,Y5V

0.1UF/25V,Y5V

MCH_BSEL2 {12}
CLK_BSEL2 {7}

3

CLK_BSEL0

A A

CLK_BSEL1

SATA_CLKREQ#

EXP_CLKREQ

MPCIE_CLKREQ

TME

R181 10KR181 10K
R143 10KR143 10K
R138 10KR138 10K

+V3.3S

R177 10KR177 10K

2

CLK_ICH14
CLK_USB48

CLK_debugPCI
CLK_591PCI
CLK_ICHPCI

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

C118 10PF/50V,NPO nsC118 10PF/50V,NPO ns
C112 18pF/50V,NPO

C112 18pF/50V,NPO

C353 10PF/50V,NPO nsC353 10PF/50V,NPO ns
C119 10PF/50V,NPO nsC119 10PF/50V,NPO ns
C117 10PF/50V,NPO nsC117 10PF/50V,NPO ns

TOPSTAR TECHNOLOG

TOPSTAR TECHNOLOG

TOPSTAR TECHNOLOG

Lucifer Jiang

Lucifer Jiang

Lucifer Jiang

CK505M

CK505M

CK505M

M42G

M42G

M42G

650Tuesday, March 11, 2008

650Tuesday, March 11, 2008

650Tuesday, March 11, 2008

1

C0402

C0402

A

A

A

of

of

of

5

U10A

H_A#[35:3]{9}

D D

C C

H_ADSTB#1{9}

H_A20M#{22}
H_FERR#{22}
H_IGNNE#{22}

T20ICTPns T20ICTPns

H_STPCLK#{22}

H_INTR{22}
H_NMI{22}
H_SMI#{22}

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_ADSTB#0{9}
H_REQ#[4:0]{9}

H_A#[35:3]{9}

T9ICTPns T9ICTPns
TP2ICTPns TP2ICTPns
TP1ICTPns TP1ICTPns
T8ICTPns T8ICTPns
T19ICTPns T19ICTPns
T13ICTPns T13ICTPns
T16ICTPns T16ICTPns
T15ICTPns T15ICTPns
T11ICTPns T11ICTPns

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

R600R60
0

TP_CPU_RSVD01
TP_CPU_RSVD02
TP_CPU_RSVD03
TP_CPU_RSVD04
TP_CPU_RSVD05
TP_CPU_RSVD06
TP_CPU_RSVD07
TP_CPU_RSVD08
TP_CPU_RSVD09

J4
L5
L4
K5

M3

N2

J1
N3
P5
P2
L2
P4
P1
R1

M1

K3
H2
K2

J3
L1

Y2
U5
R3

W6

U4
Y5
U1
R4
T5
T3

W2
W5

Y4
U2
V4

W3
AA4
AB2
AA3

V1
A6

A5
C4

D5
C6
B4
A3

M4

N5
T2
V3
B2
D2

D22

D3
F6

U10A

ADDR GROUP 0 ADDR GROUP 1

ADDR GROUP 0 ADDR GROUP 1

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Penryn

Penryn

DEFER#

DRDY#
DBSY#

LOCK#

CONTROL

CONTROL

RESET#

TRDY#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

RESERVED

RESERVED

ADS#
BNR#

BPRI#

BR0#

IERR#

INIT#

RS[0]#
RS[1]#
RS[2]#

HIT#

HITM#

TDO
TMS

DBR#

T10

T10

H1
E2
G5

H5
F21
E1

F1

H_IERR#

D20
B3

H4

T17ICTP nsT17 ICTP ns

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3
G2

G6
E4

H_BPM#0

AD4

H_BPM#1

AD3

H_BPM#2

AD1

H_BPM#3

AC4

H_PRDY#

AC2

H_FREQ#

AC1

H_TCK

AC5

TCK

TDI

NC

AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

B1

H_TDI
H_TDO
H_TMS
H_TRST#
H_DBR#

VR_PROCHOT#

H_THERMDA
H_THERMDC

PM_THRMTRIP# {12,22,32}

CLK_CPU_BCLK {6}
CLK_CPU_BCLK# {6}

4

ICTP ns

ICTP ns

H_ADS# {9}
H_BNR# {9}
H_BPRI# {9}

H_DEFER# {9}
H_DRDY# {9}
H_DBSY# {9}

H_BREQ#0 {9}

H_INIT# {22}
H_LOCK# {9}
H_CPURST# {9}

H_RS#0 {9}
H_RS#1 {9}
H_RS#2 {9}
H_TRDY# {9}

H_HIT# {9}
H_HITM# {9}

ICTP nsT1ICTP ns

T1

ICTP nsT4ICTP ns

T4

ICTP nsT3ICTP ns

T3

ICTP nsT2ICTP ns

T2

ICTP nsT7ICTP ns

T7

ICTP nsT6ICTP ns

T6

+V1.05S

R65

R65
56

56
R0402

R0402

Place testpoint on
H_IERR# with a GND

0.1" away

H_DBR#

R61 1K nsR61 1K ns

H_TMS

R16 54.9,1% R0402R16 54.9,1% R0402

H_FREQ#

R15 54.9,1% R0402R15 54.9,1% R0402

H_TDI

R21 54.9,1% R0402R21 54.9,1% R0402

H_TCK

R19 54.9,1% R0402R19 54.9,1% R0402

H_TRST#

R20 54.9,1% R0402R20 54.9,1% R0402

PM_THRMTRIP# should
connect to ICH9 and
GMCH without
T-ing(No stub)

CLK_CPU_BCLK

R589

R589
100,1%

100,1%
R0402

R0402

CLK_CPU_BCLK#

ns

ns

follow DG 1.5 and intel FAE advise
By Johan 071228

+V3.3S

+V1.05S

3

H_D#[63:0]{9}

H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

CPU_TEST3

T14ICTPns T14ICTPns

CPU_TEST4

CPU_TEST5

T5ICTPns T5ICTPns

CPU_TEST6

T80ICTPns T80ICTPns

CPU_TEST7

T18ICTPns T18ICTPns

Place C30 close to
the CPU_TEST4 pin.
Make sure CPU_TEST4
routing is reference
to GND and away from
other noisy signals.

+V1.05S

R341

R341
1K,1%

1K,1%
R0402

R0402

R340

R340
2K,1%

2K,1%
R0402

R0402

R52

R52
1K

1K
R0402

R0402
ns

ns

length:<0.5 inch
width>7mil,Space>10mil

Layout Note: Z=55ohm,

0.5" max for GTLREF

C248

C248

R49

R49

C0402

C0402

1K

1K

0.1UF/10V,X7R

0.1UF/10V,X7R

R0402

R0402

ns

ns

ns

ns

H_DSTBN#0{9}
H_DSTBP#0{9}
H_DINV#0{9}

H_D#[63:0]{9}

H_DSTBN#1{9}
H_DSTBP#1{9}
H_DINV#1{9}

CLK_BSEL0{6}
CLK_BSEL1{6}
CLK_BSEL2{6}

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

AD26

AF26

2

U10B

U10B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22
F23
G25
E25
E23
K24
G24

J24

J23
H22
F26
K22
H23

J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

C23
D25
C24

AF1
A26

C3
B22
B23
C21

D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

Penryn

Penryn

DATA GRP 0

DATA GRP 0

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DATA GRP 1

DATA GRP 1

DSTBN[3]#
DSTBP[3]#

MISC

MISC

DPRSTP#

PWRGOOD

DINV[2]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPSLP#

DPWR#

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25
Y26
AA26
U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23
AE25
AF24
AC20

COMP_CPU0

R26

COMP_CPU1

U26

COMP_CPU2

AA1

COMP_CPU3

Y1
E5

B5
D24
D6
D7
AE6

PSI#

+V3.3S {6,10,12,14,15,16,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,39,41,42,43}
+V1.05S {6,8,9,12,13,14,22,24,32,39,41,42,43,45}

H_D#[63:0] {9}

H_DSTBN#/H_DSTBP# should route
as differential pair

H_DSTBN#2 {9}
H_DSTBP#2 {9}
H_DINV#2 {9}

H_D#[63:0] {9}

Layout note:
Comp0,2 connec with Zo=27.4ohm,make
trace length shorter than 0.5"
Comp1,3 connec with Zo=55ohm,make
trace length shorter than 0.5"

H_DSTBN#3 {9}
H_DSTBP#3 {9}
H_DINV#3 {9}

R343 27.4,1% R0402R343 27.4,1% R0402
R342 54.9,1% R0402R342 54.9,1% R0402
R17 27.4,1% R0402R17 27.4,1% R0402
R18 54.9,1% R0402R18 54.9,1% R0402

H_DPRSTP# {12,22,42}
H_DPSLP# {22}

H_CPUSLP# {9}
PM_PSI# {42}

1

+V1.05S

ICTP ns

ICTP ns

T12

T12

H_DPWR# {9}

Remove H_PWRGD

R38

R38

PU Resistor.

200,1%

200,1%
R0402

R0402
ns

ns

H_PWRGD {22}

B B

+V3.3S

delete for DFX
By Johan 071228

8

SCL

7

SDA

6
5

2

VDD_1

I2C_CLK
I2C_DATA
OVT_SHUTDOWN#

会用到新的支持

BI-DIRECTIONAL
PROCESSOR HOT

+V3.3S

R57

R57
10K

10K
R0402

R0402

+V1.05S

A A

R31 1K R0402R31 1K R0402

1

+V1.05S

Q4

Q4
MMBT2222A

MMBT2222A
SOT23

SOT23

R37

R37

2 3

1K

1K
R0402

R0402

5

23

Q6

Q6
MMBT2222A

MMBT2222A
1

SOT23

SOT23

EC_PROCHOT# {34}

R641KR0402R641KR0402

VR_PROCHOT# {42}

+V1.05S

4

3

MODEL

H_THERMDA

H_THERMDC

Change to 75393
By Johan 071228

的

TS

2200PF/25V,X7R

2200PF/25V,X7R
C0402

C0402

VDD_1
H_THERMDA
H_THERMDC
THERM#

C281

C281

BJT

U11

U11

1

VDD

2

D+

3

D­THERM#4GND

F75393S

F75393S

ALERT#

R347

R347
220

220
R0603

R0603

C279

C279

0.1UF/25V,Y5V

0.1UF/25V,Y5V
C0402

C0402

EC SMBUS ADD:1001 100X

I2C_CLK
I2C_DATA
OVT_SHUTDOWN#

THERM#

R350

R350

10K

10K

R0402

R0402

+V3.3S

NOTE

1.H_THERMDA/C线宽10 MILS,

然后再包地处理

2.H_THERMDA/C

C291

C291

R371

R371
10K

10K

27pF/50V,NPO

27pF/50V,NPO

R0402

R0402

C0402

C0402
ns

ns

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

.

走线远离

C290

C290
27pF/50V,NPO

27pF/50V,NPO
C0402

C0402
ns

ns

并配对走线

19V及VGA

I2C_CLK {33,34}
I2C_DATA {33,34}
OVT_SHUTDOWN# {32}

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Lucifer Jiang
PENRYN(Host Bus)

PENRYN(Host Bus)

PENRYN(Host Bus)

M42G

M42G

M42G

1

,

或高速线走线

750Tuesday, March 11, 2008

750Tuesday, March 11, 2008

750Tuesday, March 11, 2008

of

of

of

A

A

A

5

4

3

2

+VCC_CORE {41,42}
+V1.5S {14,22,24,27,28,29,31,39,41,43}
+V1.05S {6,7,9,12,13,14,22,24,32,39,41,42,43,45}

1

Demo:22uF*32 3mOhm 0.6nH
Caps

+VCC_CORE

D D

+VCC_CORE

U10C

U10C

A7

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Penryn

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9

C10
C12
C13
C15

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

C17
C18

D9

D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20

AA7
AA9

AB9

C C

B B

+VCC_CORE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

H_VID0 {42}
H_VID1 {42}
H_VID2 {42}
H_VID3 {42}
H_VID4 {42}
H_VID5 {42}
H_VID6 {42}

AF7

AE7

VCC_Sense/VSS-Sense lines
between the Penryn processor
and the VR should have a
trace width of 18 mils on
7-mil spacing, with trace
impedance of Zo=27.4 Ω.
The
VCC_Sense/VSS-Sense should
be length matched to within
25 mils.

+V1.05S

C17

C17
10uF/6.3V,X5R

10uF/6.3V,X5R
C0805

C0805

+VCCA_PROC

C272

C272

0.01uF/16V,X7R

0.01uF/16V,X7R
C0402

C0402

Place near PIN B26

+VCC_CORE

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

C21

C21

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

R338

R338
100,1%

100,1%
R0402

R0402

R339

R339
100,1%

100,1%
R0402

R0402

C269

C269

ns

ns

C0805

C0805

+VCC_CORE

C22

C22

ns

ns

C0805

C0805

+VCC_CORE

C262

C262

C0805

C0805

C33

C33
10uF/6.3V,X5R

10uF/6.3V,X5R
C0805

C0805

R345 0

R345 0
R0603

R0603

C274

C274
10uF/6.3V,X5R

10uF/6.3V,X5R
C0805

C0805

VCCSENSE {42}

VSSSENSE {42}

C270

C270

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C23

C23

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C255

C255

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

+V1.5S

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C0805

C0805

ns

ns

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C267

C267

C41

C41

C252

C252

C268

C268

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C40

C40

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C15

C15

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C0805

C0805

BRACKET

BRACKET

CPU_BRACKET

CPU_BRACKET

+V1.05S

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C34

C34

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

C266

C266

C259

C259

C24

C24

HCPU1

HCPU1

ns

ns

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C20

C20

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

C0805

C0805

C0805

C0805

C0805

C0805

C258

C258

C13

C13

C254

C254

ns

ns

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

C18

C18

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

HCPU2

HCPU2

C0805

C0805

C0805

C0805

C0805

C0805

C265

C265

C14

C14

C261

C261

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

ns

ns

C0805

C0805

C27

C27

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

BRACKET1_Mylar

BRACKET1_Mylar

Mylar

Mylar

C43

C43

10uF/6.3V,X5R

10uF/6.3V,X5R

C16

C16

10uF/6.3V,X5R

10uF/6.3V,X5R

C25

C25

ns

ns

10uF/6.3V,X5R

10uF/6.3V,X5R

change to bi-sticky mylar
By Johan 071224

HCPU3

HCPU3

C42

C42

C0805

C0805

C256

C256

C0805

C0805

C253

C253

C0805

C0805

C31

C31

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

C257

C257

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C251

C251

10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805

C260

C260

10uF/6.3V,X5R

ns

10uF/6.3V,X5R

ns

ns

ns

C0805

C0805

C19

C19

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

Change to ESD dischange point
By Johan 071224

HCPU4

HCPU4

U10D

U10D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

CPU_HOLE

CPU_HOLE

CPU_HOLE

ns

11223344556677889

A A

5

4

ns

9

3

CPU_HOLE

CPU_HOLE

11223344556677889

ns

ns

9

CPU_HOLE

CPU_HOLE

ns

11223344556677889

ns

9

Note : using ESD prtection Hole

CPU_HOLE

11223344556677889

ns

ns

9

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

Lucifer Jiang
PENRYN(POWER&GND)

PENRYN(POWER&GND)

PENRYN(POWER&GND)

M42G

M42G

M42G

1

A

A

A

of

of

of

850Tuesday, March 11, 2008

850Tuesday, March 11, 2008

850Tuesday, March 11, 2008

5

D D

+V1.05S

R391

R391
221,1%

221,1%
R0603

R0603

H_SWING

Close to the pin!

C299

C299

R384

R384

0.1UF/10V,X7R

0.1UF/10V,X7R

100,1%

100,1%

C0402

C0402

R0402

R0402

C C

H_RCOMP

Trace should be 10mil

R385

R385

24.9,1%

24.9,1%
R0402

R0402

B B

wide with 20mil
spacing!

+V1.05S

R360

R360
1K,1%

1K,1%
R0402

R0402

R361

R361
2K,1%

2K,1%
R0402

R0402

C285

C285

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

Loyout note:
Place C76 with
100mils from GMCH

H_D#[63:0]{7}

H_CPURST#{7}

H_CPUSLP#{7}

R372 0 R0402R372 0 R0402

4

U13A

AD14

AA13
AA11

AD11
AD10
AD13
AE12

AE14

AE11

M11

N12

P13

N10

Y10
Y12
Y14

W2

AA8

AA9

AE9
AA2
AD8
AA3
AD3
AD7

AF3
AC1
AE3
AC3

AE8
AG2
AD6

C12

E11

A11
B11

U13A

F2
G8

F8
E6
G2
H6
H2

F6
D4
H3
M9

J1

J2

J6
P2

L2
R2
N9

L6
M5

J3
N2
R1
N5
N6

N8

L7
M3

Y3
Y6

Y7

Y9

C5
E3

CANTIGA_1p2

CANTIGA_1p2

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

HOST

HOST

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59

H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

C286

C286

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402
ns

ns

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

3

H_A#3

A14

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20
H12

B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#[35:3] {7}

H_ADS# {7}

H_ADSTB#0 {7}

H_ADSTB#1 {7}
H_BNR# {7}
H_BPRI# {7}

H_BREQ#0 {7}
H_DEFER# {7}

H_DBSY# {7}
CLK_MCH_BCLK {6}
CLK_MCH_BCLK# {6}

H_DPWR# {7}

H_DRDY# {7}

H_HIT# {7}

H_HITM# {7}
H_LOCK# {7}

H_TRDY# {7}

H_DINV#0 {7}
H_DINV#1 {7}
H_DINV#2 {7}
H_DINV#3 {7}

H_DSTBN#0 {7}
H_DSTBN#1 {7}
H_DSTBN#2 {7}
H_DSTBN#3 {7}

H_DSTBP#0 {7}
H_DSTBP#1 {7}
H_DSTBP#2 {7}
H_DSTBP#3 {7}

H_REQ#[4:0] {7}

H_RS#0 {7}
H_RS#1 {7}
H_RS#2 {7}

Place on the middle back of the GMCH chip

2

+V1.05S

RT1

RT1
10K,1%

10K,1%
R0603

R0603
ns

ns

R109

R109

2.49K,1%

2.49K,1%
R0402

R0402
ns

ns

GMCH_TEMP {34}

ns NB ovt function for no using

1

+V1.05S {6,7,8,12,13,14,22,24,32,39,41,42,43,45}

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

Lucifer Jiang
CANTIGA(Host BUS)

CANTIGA(Host BUS)

CANTIGA(Host BUS)

M42G

M42G

M42G

1

A

A

950Tuesday, March 11, 2008

950Tuesday, March 11, 2008

950Tuesday, March 11, 2008

A

of

of

of

5

+V3.3S

D D

R627

R627

R628

R628

10K

10K

10K

10K

+V3.3S

R629

R629

R631

R631

2.2K

2.2K

2.2K

2.2K

C C

TVA_DAC
TVB_DAC
TVC_DAC

根据车

checklist

HOMY1109

靠近

MCH HOMY1109

B B

MCH_BLUE
MCH_GREEN
MCH_RED

R641 150,1%R641 150,1%
R642 150,1%R642 150,1%

R643

R643

150ohm

电阻到

走线阻抗

37.5ohm homy 1109

150ohm

电阻到

50ohm homy 1109

走线阻抗

PLACE 150 OHM
RESISTORS CLOSE TO
GMCH Homy 1109

R638 75,1%R638 75,1%
R639

R639
R640

R640

150,1%

150,1%

GMCH
VGA

LCTL_DATA
LCTL_CLK

L_DDC_DATA {19}
L_DDC_CLK {19}

75,1%

75,1%
75,1%

75,1%

口

R632

R632

2.37K,1%

2.37K,1%

1.02k demo

R6451KR645
1K

4

LVDS_BKLTCTL{19}
LVDS_BKLTEN{19}

LVDS_VDDEN{19}

LVDS_CLKAM{19}
LVDS_CLKAP{19}

LVDS_YAM0{19}

LVDS_YAM1{19}
LVDS_YAM2{19}

LVDS_YAP0{19}
LVDS_YAP1{19}
LVDS_YAP2{19}

靠近

HOMY1109

T156nsT156

ns

ns

ns

ns

ns

MCH_BLUE{20}
MCH_GREEN{20}

MCH_RED{20}

CRT_DDC_CLK{20}
CRT_DDC_DATA{20}

CRT_HSYNC{20}
CRT_VSYNC{20}

MCH

，远离高速信号

T157nsT157

T161nsT161

T158nsT158

T159nsT159

LCTL_DATA
L_DDC_CLK
L_DDC_DATA

LVDS_IBG

LVDS_VBG

TVA_DAC
TVB_DAC
TVC_DAC

R644 33 R0402R644 33 R0402
R64633 R0402R64633 R0402

靠近

MCH HOMY1109

L32
G32
M32

M33
K33

J33

M29
C44
B43
E37
E38
C41
C40
B37
A37

H47
E46
G40
A40

H48
D45

F40
B40

A41
H38
G37

J37
B42

G38

F37
K37

F25
H25
K25

H24

C31
E32

E28
G28

J28
G29
H32

J32

J29
E29

L29

U13C

U13C

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

TVA_DAC
TVB_DAC
TVC_DAC

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK

CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

CANTIGA_1p2

CANTIGA_1p2

3

+VCC_PEG {14}
+V3.3S {6,7,12,14,15,16,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,39,41,42,43}

+VCC_PEG

R630

R630

49.9,1%

T37

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6

LVDS

LVDS

TV

TV

PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3

VGA

VGA

PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PEG_COMPLCTL_CLK

靠近

49.9,1%

R634

R634
0

0
R0402

R0402

HDMI

HDMI

C496 0.1UF/10V,X7R

C496 0.1UF/10V,X7R
C495 0.1UF/10V,X7R

C495 0.1UF/10V,X7R
C497 0.1UF/10V,X7R

C497 0.1UF/10V,X7R

HDMI

HDMI

C498 0.1UF/10V,X7R

C498 0.1UF/10V,X7R

HDMI

HDMI
HDMI

HDMI
HDMI

HDMI

MCH HOMY1109

C499 0.1UF/10V,X7R

C499 0.1UF/10V,X7R
C500 0.1UF/10V,X7R

C500 0.1UF/10V,X7R
C501 0.1UF/10V,X7R

C501 0.1UF/10V,X7R

HDMI

HDMI

C502 0.1UF/10V,X7R

C502 0.1UF/10V,X7R

HDMI

HDMI
HDMI

HDMI
HDMI

HDMI

2

Place the resistor within 300 mils
(1.27 mm) of the (G)MCH.Homy 1019

R635

R635

7.5K,1%

7.5K,1%

HDMI

HDMI

IN_D2- {21}
IN_D1- {21}
IN_D0- {21}
MCH_CLK_D4- {21}

IN_D2+ {21}
IN_D1+ {21}
IN_D0+ {21}
MCH_CLK_D4+ {21}

HDMI

HDMI

+V3.3S

HDMI

HDMI

1

R633

R633
20K

20K

R636

R636
0

0
R0402

R0402
ns

ns

3

1

HDMI

HDMI

MCH_HDMI_HPD# {21}

R637

R637
100K

100K

ADD R607 hOMY 1123

Q37

Q37

2

2N7002

2N7002

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Homy

Homy

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

Homy
CANTIGA(GRAPHIC)

CANTIGA(GRAPHIC)

CANTIGA(GRAPHIC)

M42G

M42G

M42G

1

A

A

10 50Tuesday, March 11, 2008

10 50Tuesday, March 11, 2008

10 50Tuesday, March 11, 2008

A

of

of

of

5

U13D

AN38
AM38

AJ36

AJ40
AM44
AM42
AN43
AN44
AU40

AN41
AN39
AU44
AU42

AV39

AY44

BA40
BD43

AV41

AY43

BB41
BC40

AY37
BD38

AV37

AT36

AY38

BB38

AV36
AW36
BD13
AU11
BC11

BA12
AU13

AV13
BD12
BC12

AU10

BA11

AN10
AM11

AN12
AM13

AJ11

AJ12

AJ38
AJ41

AT38

BB9
BA9

AV9
BD9

AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5

AM5

AJ9
AJ8

U13D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CANTIGA_1p2

CANTIGA_1p2

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

AM37

SA_DM_0

AT41

SA_DM_1

AY41

SA_DM_2

AU39

SA_DM_3

BB12

SA_DM_4

AY6

SA_DM_5

AT7

SA_DM_6

AJ5

SA_DM_7

AJ44

SA_DQS_0

AT44

SA_DQS_1

BA43

SA_DQS_2

BC37

SA_DQS_3

AW12

SA_DQS_4

BC8

SA_DQS_5

AU8

SA_DQS_6

AM7

SA_DQS_7

AJ43

SA_DQS#_0

AT43

SA_DQS#_1

BA44

SA_DQS#_2

BD37

SA_DQS#_3

AY12

SA_DQS#_4

BD8

SA_DQS#_5

AU9

SA_DQS#_6

AM8

SA_DQS#_7

BA21

SA_MA_0

BC24

SA_MA_1

BG24

SA_MA_2

BH24

SA_MA_3

BG25

SA_MA_4

BA24

SA_MA_5

BD24

SA_MA_6

BG27

SA_MA_7

BF25

SA_MA_8

AW24

SA_MA_9

BC21

SA_MA_10

BG26

SA_MA_11

BH26

SA_MA_12

BH17

SA_MA_13

AY25

SA_MA_14

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

MA_DATA[63:0]{15}

D D

C C

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3
MA_DQS4
MA_DQS5
MA_DQS6
MA_DQS7

MA_DQS#0
MA_DQS#1
MA_DQS#2
MA_DQS#3
MA_DQS#4
MA_DQS#5
MA_DQS#6
MA_DQS#7

MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A7
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14

4

MA_A_BS#0 {15,17}
MA_A_BS#1 {15,17}
MA_A_BS#2 {15,17}

MA_A_RAS# {15,17}
MA_A_CAS# {15,17}
MA_A_WE# {15,17}

MA_DM[7:0] {15}

MA_DQS[7:0] {15}

MA_DQS#[7:0] {15}

MA_A_A[13:0] {15,17}

MA_A_A14
MB_B_A14

MA_A_A14 {15,17}
MB_B_A14 {16,17}

3

U13E

MB_DATA[63:0]{16}

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

AK47
AH46
AP47
AP46
AJ46
AJ48

AM48

AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44

BG43

BF43
BE45
BC41
BF40
BF41

BG38

BF38
BH35

BG35

BH40
BG39
BG34

BH34

BH14
BG12

BH11

BH12

BF11

BG8

BF8
BG7
BC5
BC6

AY3

AY1

BF6

BF5

BA1
BD3

AV2
AU3
AR3
AN2

AY2

AV1

AP3
AR1

AL1

AL2

AJ1
AH1
AM2
AM3
AH3

AJ3

U13E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CANTIGA_1p2

CANTIGA_1p2

2

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

AM47

SB_DM_0

AY47

SB_DM_1

BD40

SB_DM_2

BF35

SB_DM_3

BG11

SB_DM_4

BA3

SB_DM_5

AP1

SB_DM_6

AK2

SB_DM_7

AL47

SB_DQS_0

AV48

SB_DQS_1

BG41

SB_DQS_2

BG37

SB_DQS_3

BH9

SB_DQS_4

BB2

SB_DQS_5

AU1

SB_DQS_6

AN6

SB_DQS_7

AL46

SB_DQS#_0

AV47

SB_DQS#_1

BH41

SB_DQS#_2

BH37

SB_DQS#_3

BG9

SB_DQS#_4

BC2

SB_DQS#_5

AT2

SB_DQS#_6

AN5

SB_DQS#_7

AV17

SB_MA_0

BA25

SB_MA_1

BC25

SB_MA_2

AU25

SB_MA_3

AW25

SB_MA_4

BB28

SB_MA_5

AU28

SB_MA_6

AW28

SB_MA_7

AT33

SB_MA_8

BD33

SB_MA_9

BB16

SB_MA_10

AW33

SB_MA_11

AY33

SB_MA_12

BH15

SB_MA_13

AU33

SB_MA_14

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS0
MB_DQS1
MB_DQS2
MB_DQS3
MB_DQS4
MB_DQS5
MB_DQS6
MB_DQS7
MB_DQS#0
MB_DQS#1
MB_DQS#2
MB_DQS#3
MB_DQS#4
MB_DQS#5
MB_DQS#6
MB_DQS#7

MB_B_A0
MB_B_A1
MB_B_A2
MB_B_A3
MB_B_A4
MB_B_A5
MB_B_A6
MB_B_A7
MB_B_A8
MB_B_A9
MB_B_A10
MB_B_A11
MB_B_A12
MB_B_A13
MB_B_A14

MB_B_BS#0 {16,17}
MB_B_BS#1 {16,17}
MB_B_BS#2 {16,17}

MB_B_RAS# {16,17}
MB_B_CAS# {16,17}
MB_B_WE# {16,17}

MB_DM[7:0] {16}

MB_DQS[7:0] {16}

MB_DQS#[7:0] {16}

MB_B_A[13:0] {16,17}

1

B B

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

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Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

Lucifer Jiang
CANTIGA(DDRII)

CANTIGA(DDRII)

CANTIGA(DDRII)

M42G

M42G

M42G

1

A

A

11 50Tuesday, March 11, 2008

11 50Tuesday, March 11, 2008

11 50Tuesday, March 11, 2008

A

of

of

of

5

U13B

U13B

+V3.3S

D D

PM_EXTTS#0

PM_EXTTS#1

R0402

R0402

R0402

R0402

R95

R95
10K

10K

R123

R123
10K

10K

R127 0 R0402

R127 0 R0402
ns

ns

+V3.3S

R98 0 R0402

R98 0 R0402
ns

ns

DIM_EXTTS#0 {15}

DIM_EXTTS#1 {16}

RSVD1

T32ICTPns T32ICTPns
T35ICTPns T35ICTPns
T40ICTPns T40ICTPns

T43ICTPns T43ICTPns
T46ICTPns T46ICTPns
T49ICTPns T49ICTPns
T48ICTPns T48ICTPns
T47ICTPns T47ICTPns

T31ICTPns T31ICTPns

T42ICTPns T42ICTPns
T24ICTPns T24ICTPns
T33ICTPns T33ICTPns

T54ICTPns T54ICTPns

T86ICTPns T86ICTPns

T120ICTPns T120ICTPns

T123ICTPns T123ICTPns
T119ICTPns T119ICTPns
T127ICTPns T127ICTPns

RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

RSVD14
RSVD15
RSVD17

RSVD20

RSVD21
RSVD22
RSVD23
RSVD24
RSVD25

AH10
AH12
AH13

AY21

BG23

BF23

BH18

BF18

M36
N36
R33

T33

AH9

K12

T24

B31

M1

B2

VerA:reserve Pull-up and Pull-down resistor 071026

+V1.05S

R156

R156

R146

R146

R154

R154

R151

R151

1K

1K

1K

1K

1K

1K

1K

C C

B B

A A

1K
ns

ns

R150

R150
10K

10K
ns

ns

ns

ns

ns

ns

ns

ns

R161

R161

R144

R144

R155

R155

10K

10K

10K

10K

10K

10K

ns

ns

ns

ns

ns

ns

5

MCH_BSEL0{6}
MCH_BSEL1{6}
MCH_BSEL2{6}

T41ICTPns T41ICTPns
T44ICTPnsT44ICTP

ns

T25ICTPns T25ICTPns

T36ICTPns T36ICTPns

T39

T39

ICTPns

ICTPns

T34ICTPns T34ICTPns
T27ICTPnsT27ICTP

ns

T38ICTPns T38ICTPns

PM_SYNC#{23}

H_DPRSTP#{7,22,42}

PM_ICH_PWROK{23}

BUF_PLT_RST#{19,23,27,28,29,30,32,34}

PM_THRMTRIP#{7,22,32}

PM_DPRSLPVR{23,42}

ICTPns

ICTPns

T122

T122

ICTPns

ICTPns

T121

T121

ICTPns

ICTPns

T112

T112

ICTPns

ICTPns

T109

T109

ICTPns

ICTPns

T118

T118

ICTPns

ICTPns

T56

T56

ICTPns

ICTPns

T114

T114

ICTPns

ICTPns

T129

T129

ICTPns

ICTPns

T57

T57

ICTPns

ICTPns

T116

T116

ICTPns

ICTPns

T125

T125

ICTPns

ICTPns

T130

T130

ICTPns

ICTPns

T126

T126

ICTPns

ICTPns

T128

T128

ICTPns

ICTPns

T124

T124

ICTPns

ICTPns

T115

T115

ICTPns

ICTPns

T58

T58

ICTPns

ICTPns

T117

T117

ICTPns

ICTPns

T55

T55

ICTPns

ICTPns

T111

T111

ICTPns

ICTPns

T113

T113

ICTPns

ICTPns

T110

T110

ICTPns

ICTPns

T108

T108

ICTPns

ICTPns

T107

T107

ICTPns

ICTPns

T26

T26

CFG5
CFG6

CFG7
CFG9

CFG10
CFG12

CFG13

CFG16

CFG19
CFG20

R1330R0402 R1330R0402

R3680R0402 R3680R0402
PM_EXTTS#0
PM_EXTTS#1

R1580R0402 R1580R0402

R160100R0402 R160100R0402

R1300R0402 R1300R0402

TP_CN1
TP_CN2
TP_CN3
TP_CN4
TP_CN5
TP_CN6
TP_CN7
TP_CN8

TP_CN9
TP_CN10
TP_CN11
TP_CN12
TP_CN13
TP_CN14
TP_CN15
TP_CN16
TP_CN17
TP_CN18
TP_CN19
TP_CN20
TP_CN21
TP_CN22
TP_CN23
TP_CN24
TP_CN25

AL34
AK34
AN35
AM35

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21

T21
R20
M20

L21
H21
P29
R28

T28

R29

B7
N33
P32

AT40
AT11

T20

R32

BG48

BF48
BD48
BC48
BH47
BG47
BE47
BH46

BF46
BG45
BH44
BH43

BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1

F1

CANTIGA_1p2

CANTIGA_1p2

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

RSVD14
RSVD15
RSVD17

RSVD20

RSVD21
RSVD22
RSVD23
RSVD24
RSVD25

ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25

4

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

RSVD

RSVD

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_DRAMRST#
DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

ME JTAG

ME JTAG

CLK

CLK

CFG

CFG

DMI

DMI

PM

PM

GRAPHICS VID

GRAPHICS VID

MEHDA

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

NC

NC

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

MISC

4

SB_CKE_1
SA_CS#_0

SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BB36
BA17

AY16
AV16
AR13

BD17
AY17
BF15
AY13

BG22
BH21

BF28
BH28

AV42
AR36
BF17
BC36

B38
A38
E41
F41

F43
E43

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44
AF46
AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF

R185

R185

DDR2: Leave as No Connect.

499,1%

499,1%

DREFCLK {6}
DREFCLK# {6}
DREFSSCLK {6}
DREFSSCLK# {6}

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0

DMI_TXP1

DMI_TXP2

DMI_TXP3
DMI_RXN0

DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

R159 0 R0402R159 0 R0402

MCH_CLVREF

1.These signals serve as DDC signals
for iHDMI port C&B

2.SDVO_CTRLDATA&DDPC_CTRLDATA should
both be high to enable display port

R354 0 R0402R354 0 R0402

AZALIA_HDMI_BITCLK {22}
AZALIA_HDMI_RST# {22}

AZALIA_HDMI_SDOUT {22}
AZALIA_HDMI_SYNC {22}

AZALIA_SDATAIN2{22}

M_CLK_DDR0 {15}
M_CLK_DDR1 {15}
M_CLK_DDR2 {16}
M_CLK_DDR3 {16}

M_CLK_DDR#0 {15}
M_CLK_DDR#1 {15}
M_CLK_DDR#2 {16}
M_CLK_DDR#3 {16}

M_CKE0 {15,17}
M_CKE1 {15,17}
M_CKE2 {16,17}
M_CKE3 {16,17}

M_CS#0 {15,17}
M_CS#1 {15,17}
M_CS#2 {16,17}
M_CS#3 {16,17}

M_ODT0 {15,17}
M_ODT1 {15,17}
M_ODT2 {16,17}
M_ODT3 {16,17}

For DDR3:GMCH requires this pin never to be driven high
before DDR voltage has ramped to stable value. For
DDR2:connect to GND

CLK_MCH_3GPLL {6}
CLK_MCH_3GPLL# {6}

DMI_TXN0 {23}
DMI_TXN1 {23}
DMI_TXN2 {23}
DMI_TXN3 {23}

DMI_TXP0 {23}
DMI_TXP1 {23}
DMI_TXP2 {23}
DMI_TXP3 {23}

DMI_RXN0 {23}
DMI_RXN1 {23}
DMI_RXN2 {23}
DMI_RXN3 {23}

DMI_RXP0 {23}
DMI_RXP1 {23}
DMI_RXP2 {23}
DMI_RXP3 {23}

PCIE_CLKREQ#

CL_CLK0 {23}
CL_DATA0 {23}
PM_ICH_PWROK {23}
CL_RST#0 {23}

HDMI_DDC_CLK {21}
HDMI_DDC_DATA {21}
PCIE_CLKREQ# {6}

MCH_ICH_SYNC# {23}

use for the AUX2 trip point

AZALIA_HDMI_SDATAIN2

R647 33 R0402R647 33 R0402

3

+V1.8

R423

R423

R422

R422

80.6,1%

80.6,1%

20,1%

20,1%

R0603

R0603

R0603

R0603

ns

ns

R413

R413

20,1%

20,1%

80.6,1%

80.6,1%

R0603

R0603

ns

ns

+V3.3S

R122

R122
10K

10K
R0402

R0402
ns

ns

C86

C86

0.1UF/25V,Y5V

0.1UF/25V,Y5V
C0402

C0402

1.Checklist:500ohm CRB:511ohm 2.use 500ohm
resistor accord with the advice of KAM

SM_VREF_L{15,16,38}

AZALIA_HDMI_SDATAIN2

3

Loyout note:

R414

R414

Route as short as

R0603

R0603

possible

Change to ns , PU at CLK GEN
By Johan 071108

+V1.05S

R142

R142
1K,1%

1K,1%
R0402

R0402

R145

R145

49.9 1%

49.9 1%
R0402

R0402

+V1.05S

R36956R369
56

R370 330 nsR370 330 ns

PR71 0PR71 0

Close The CAP to GMCH

C153

C153

0.1UF/25V,Y5V

0.1UF/25V,Y5V

1

CFG7
(Intel ME
Crypto
Transport
Strap)

+V3.3AL

R356

R356
1K

1K
ns

ns

1

Q20

Q20
MMBT3904-F

MMBT3904-F
ns

ns

2 3

C155

C155

0.1UF/25V,Y5V

0.1UF/25V,Y5V

2

CFG5 CFG16

LOW = DMI x 2

CFG5

High =DMI x 4(Default)

LOW = Normal(Default)

CFG19

High =Lane Reversal

(DMI Lane
Reversal)

CFG19 CFG20

CFG9

LOW = Reverse Lane(default)

CFG9

High = Normal opertion

PCIe raphics
Lane

CFG6

High =The iTPM Host Interface

CFG6

is disabled(default)

(iTPM Host

Low =The iTPM Host Interface

Interface)

is enabled

Low = AMT Firmware will use TLS cipher
suite with no confidentiality (Isolators
are bypassed)
High = AMT Firmware will use TLS cipher
suite with Confidentiality {Isolators are
active (Default)}

R353

R353
1K

1K
ns

ns

MCH_TSATN# {34}

Q16

Q16
MMBT3904-F

MMBT3904-F
ns

ns

2 3

+V1.8

R225

R225
10K,1%

10K,1%
ns

ns

SM_VREF

NOTE:If the voltage regulator for

R227

R227

the system memory interface

10K,1%

10K,1%

already supplies a VREF output

ns

ns

and meets the voltage tolerance
and current requirements for
these pins, then a voltage
divider would not be needed.

CFG7

2

1

+V3.3S {6,7,10,14,15,16,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,39,41,42,43}
+V1.8 {13,14,15,16,38,41,43}
+V1.05S {6,7,8,9,13,14,22,24,32,39,41,42,43,45}
+V3.3AL {19,22,23,24,27,28,29,30,32,33,34,35,36,37,38,39,40,41,42,43}

R364

R364

2.2K

2.2K
ns

ns

+V3.3S +V3.3S

R97

R97

4.02K,1%

4.02K,1%
ns

ns

R362

R362

2.2K

2.2K
ns

ns

R128

R128

2.2K

2.2K
ns

ns

R126

R126

2.2K

2.2K
ns

ns

CFG16
(FSB Dynamic
ODT)

CFG20

LOW = Dynamic ODT
Disable
High = Dynamic ODT
Enable(default)

Low = Only Digital Display Port
(SDVO/DP/iHDMI) or PCIE or is
operational(Default)
High = Digital Display
Port(SDVO/DP/iHDMI)
and PCIE are operating
simultaneously via PEG port

Design Note:
Only one of the CFG10/CFG12/CFG13
straps can be enabled at any time

CFG10

Reference CRB 1.201a

CFG10
(PCIE Loopback
enable)

CFG12
(ALL Z)

CFG13
(XOR)

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

CFG12

R363

R363

2.2K

2.2K
ns

ns

Low =disabled(default)
High=enabled

Low =disabled(default)
High=ALL Z Mode enabled

Low =disabled(default)
High=XOR Mode enabled

SM_RCOMP_VOH

C355

C355

0.01uF/16V,X7R

0.01uF/16V,X7R
C0402

C0402

SM_RCOMP_VOL

C354

C354

0.01uF/16V,X7R

0.01uF/16V,X7R
C0402

C0402

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Lucifer Jiang
CANTIGA(DMI&CLK)

CANTIGA(DMI&CLK)

CANTIGA(DMI&CLK)

M42G

M42G

M42G

1

C359

C359

C0805

C0805

C358

C358

C0805

C0805

R135

R135

2.2K

2.2K
ns

ns

R124

R124

2.2K

2.2K
ns

ns

R96

R96

4.02K,1%

4.02K,1%
ns

ns

CFG13

1K,1%

1K,1%
R0402

R0402

2.2uF/10V,X7R

2.2uF/10V,X7R

1K,1%

1K,1%
R0402

R0402

2.2uF/10V,X7R

2.2uF/10V,X7R

12 50Tuesday, March 11, 2008

12 50Tuesday, March 11, 2008

12 50Tuesday, March 11, 2008

R418

R418

R417

R417

R132

R132

2.2K

2.2K
ns

ns

+V1.8

R419

R419

3.01K,1%

3.01K,1%
R0603

R0603

A

A

A

of

of

of

5

D D

C C

B B

AU48
AR48
AL48
BB47

AW47

AN47
AJ47
AF47
AD47
AB47

BD46
BA46
AY46
AV46
AR46

AM46

BF44
AH44
AD44
AA44

BC43
AV43
AU43

AM43

BG42
AY42
AT42
AN42
AJ42
AE42

BD41
AU41

AM41

AH41
AD41
AA41

BG40
BB40
AV40
AN40

AT39

AM39

AJ39
AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37
AJ37

BG36
BD36
AK15
AU36

N47
G47

R46
H46

U44
M44

C43

N42

U41
M41

G41

H40

N39

U38

C38

H37
C37

Y47
T47

L47

V46
P46
F46

Y44
T44
F44

J43

L42

Y41
T41

B41

E40

L39
B39

Y38
T38

J38
F38

U13I

U13I

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CANTIGA_1p2

CANTIGA_1p2

VSS

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23

BG21
AW21

AU21

AP21
AN21
AH21

AF21

AB21

BC20

BA20
AW20

AT20

AJ20
AG20

BG19
BG17

BC17
AW17

AT17

BA16
AU16

AN16

BG15
AC15

BG14

AA14
BG13

BC13

BA13

AN13

AJ13

AE13

BF12

AV12

AT12
AM12

AA12

BD11

BB11

AY11
AN11
AH11

BG10

AV10

AT10

AJ10

AE10

AA10

L12

R21
M21

G21

Y20
N20
K20
F20
C20
A20

A18

R17
M17
H17
C17

N16
K16
G16
E16

W15

A15

C14

N13
L13
G13
E13

A12

Y11
N11
G11
C11

M10

BF9
BC9
AN9
AM9
AD9

BH8

BB8

AV8

AT8

4

U13J

U13J

J21

J12

G9

B9

CANTIGA_1p2

CANTIGA_1p2

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

VSS_235
VSS_237

VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

VSS

VSS

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS NCTF

VSS NCTF

VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4

VSS_SCB_6

VSS SCB

VSS SCB

NC

NC

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354
VSS_355

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29
AJ6

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1

A3
E1

D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A47

C105

C105

C0402

C0402

ns

ns

0.1UF/10V,X7R

0.1UF/10V,X7R

3

C125

C125

CT7343_19

CT7343_19

220UF/2.5V,POSCAP

220UF/2.5V,POSCAP

C124

C124
C0805

C0805

10UF/6.3V,X5R

10UF/6.3V,X5R

C362

C362
C0805

C0805

10UF/6.3V,X5R

10UF/6.3V,X5R

C106

C106

C114

C114

C109

C109
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R
ns

ns

C0402

C0402

C0402

C0402

ns

ns

0.1UF/10V,X7R

0.1UF/10V,X7R

0.1UF/10V,X7R

0.1UF/10V,X7R

ns

ns

0.1UF/10V,X7R

0.1UF/10V,X7R

+V1.05S

CAP6_6X7_3

CAP6_6X7_3

1

1

220uF/6.3V

220uF/6.3V

+V1.05S

R153

R153
1K

1K
ns

ns

R141

R141
1K

1K
ns

ns

VerA:Reserve PU&PD resistor though it's
suggested that this two pin could be NC

+V1.8

12

ns

ns

1

1

+

+

C360

C360
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

C352

C352
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

C356

C356
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

C101

C101
C0402

C0402

ns

ns

12

C503

C503

+

+

AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AG21

AE21

AC21

AA21

AH20

AF20

AE20

AC20

AB20

AA20

AM15

AE15

AH15

AG15

AF15

AB15

AA15

AN14
AM14

AH14

AJ21

AL15
AJ15

AJ14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14
T14

U13G

U13G

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

CANTIGA_1p2

CANTIGA_1p2

2

VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22

POWER

POWER

VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30

VCC SMVCC GFX

VCC SMVCC GFX

VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

C111

C111
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

+V1.05S

C95

C95

C107

C107

C0402

C0402

C0603

C0603

0.1UF/10V,X7R

0.1UF/10V,X7R

0.22UF/10V,X7R

0.22UF/10V,X7R

C103

C103

C93

C93

C0603

C0603

C0603

C0603

0.47UF/25V,Y5V

0.47UF/25V,Y5V

0.22UF/10V,X7R

0.22UF/10V,X7R

1

+V1.8 {12,14,15,16,38,41,43}
+V1.05S {6,7,8,9,12,14,22,24,32,39,41,42,43,45}

C110

C110

C108

C108

C0603

C0603

C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

1uF/10V,X7R

1uF/10V,X7R

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

Lucifer Jiang
CANTIGA(VSS&NCTF)

CANTIGA(VSS&NCTF)

CANTIGA(VSS&NCTF)

M42G

M42G

M42G

1

A

A

13 50Tuesday, March 11, 2008

13 50Tuesday, March 11, 2008

13 50Tuesday, March 11, 2008

A

of

of

of

5

+V3.3S

+3.3S_A_CRT_DAC

0R648 R0603 0R648 R0603

C504

C504

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

R649

R649
R0603

R0603
0

0

+V1.05S_PEGPLL

0.1UF/10V,X7R

0.1UF/10V,X7R

10UF/6.3V,X5R

10UF/6.3V,X5R

0R157 R0603 0R157 R0603

10UF/6.3V,X5R

10UF/6.3V,X5R

0FB34 R0603 0FB34 R0603

0.1UF/10V,X7R

0.1UF/10V,X7R

24mA

+V1.05S_HPLL

C318

C318
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

+V1.05S_MPLL

0R400 R0603 0R400 R0603

C0402

414uA

C507

C507

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

C322

C322

C321

C321

C0402

C0402

C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

0R140 R0603 0R140 R0603

480mA~720mA

C98

C98
C0805

C0805

4.7uF/6.3V,X5R

4.7uF/6.3V,X5R

24mA~26mA

C104

C104

C102

C102

C0805

C0805

C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

C509

C509

0.022uF/16V,X7R

0.022uF/16V,X7R
C0402

C0402

C57

C57

C53

C53

C0402

C0402

C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

500uA

+V1.5S_QDAC

FB35

FB35
R0603

R0603

C484

C484

0.01uF/16V,Y5V

0.01uF/16V,Y5V
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

0.1UF/10V,X7R

0.1UF/10V,X7R

+V3.3S

C89

C89
C0805

C0805

ns

ns

R365 0 R0402

R365 0 R0402

C319

C319

C328

C328

D D

+V1.05S

50mA

FB23
300ohm@100MHz,1.5A

300ohm@100MHz,1.5A

CHANGED

C C

+V1.05S +V3.3S

D7

D7

B B

+V1.5S

R651

R651

CHANGED

A A

1 2

1N4148WS

1N4148WS
SOD323

SOD323

+V1.5S

R0402

R0402

0

0

50mA

VCC_HDA

R87 10

R87 10

+V1.05S

R0402

R0402

L3

L3

FB24
120ohm@100MHz,500mA

120ohm@100MHz,500mA

+V1.05S

+V1.05S

+V1.8

85nH

85nH

1 2

0FB9 R0603 0FB9 R0603

1 2

5

R3981R0603R3981R0603

C316

C316
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

+V3.3S

0.022uF/16V,X7R

0.022uF/16V,X7R

0.1UF/10V,X7R

0.1UF/10V,X7R

0FB22 R0603 0FB22 R0603

L1008

L1008

1

1

ns

ns

C325

C325
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

R149 0 R0805R149 0 R0805

35mA

FB0805FB23

FB0805

+V1.5S

place close to (G)MCH

C56

C56
C0402

C0402

C483

C483

C0402

C0402

139.2mA

FB0603FB24

FB0603

CHANGED

C505

C505

0.01uF/16V,X7R

0.01uF/16V,X7R

73mA

+3.3S_A_CRT_DAC_BG

C506

C506

0.01uF/16V,X7R

0.01uF/16V,X7R

64.8mA

+V1.05S_DPLLA

+V1.8

C508

C508
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

C81

C81

0.1UF/10V,X7R

0.1UF/10V,X7R
C0402

C0402

C97

C97
C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

C100

C100
C0603

C0603

ns

ns

0.1UF/10V,X7R

0.1UF/10V,X7R

64.8mA

+V1.05S_HPLL
+V1.05S_MPLL

13.2mA

414uA

+V1.05S_PEGPLL

C99

C99
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

C96

C96
C0402

C0402

24mA

50mA

AD48

AA48

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

+V1.05S_DPLLB

R139

R139
0

0
R0603

R0603

ns

ns

1uF/10V,X7R

1uF/10V,X7R

79mA

ns

ns

VCC_HDA

+V1.5S_QDAC

+V1.05S

157.2mA

C73

C73

50mA

+V1.05S_PEGPLL

C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

60.31mA

0

0

C511

C511
1uF/10V,X7R

1uF/10V,X7R
C0603

C0603
ns

ns

DG:The usage of Ferrite bead is under
investigation. A stuffing option should be
provided in case
the investigation results suggests the need of
a Ferrite bead. The CRB schematics currently
uses a Zero-Ohm resistor in place of the
Ferrite bead.

AA47

U13H

U13H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL
VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA_1p2

CANTIGA_1p2

4

+V1.05S

U13

VTT_1

T13

VTT_2

U12

VTT_3

T12

VTT_4

U11

VTT_5

T11

VTT_6

U10

VTT_7

T10

VTT_8

U9

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

PEG

PEG

DMI

DMI

VTTLF

VTTLF

+V1.05S

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15

VTT

VTT

VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_HV_1
VCC_HV_2
VCC_HV_3

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VTTLF1
VTTLF2
VTTLF3

T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

105.3mA

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

0.47UF/25V,Y5V

0.47UF/25V,Y5V

0FB36 R0603 0FB36 R0603

139.2mA

0FB37 R06030FB37 R0603

C515

C515
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

CRTPLLA PEGA SM

CRTPLLA PEGA SM

A LVDS

A LVDS

POWER

POWER

A CK

A CK

TV

TV

HDA

HDA

D TV/CRT

D TV/CRT

LVDS

LVDS

4

852mA

C83

C83
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

119.85mA~124mA

C357

C357
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

C55

C55

C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

+VCC_PEG

456mA(Only in 1.25V)

C310

C310

C313

C313

0.47UF/25V,Y5V

0.47UF/25V,Y5V

C0603

C0603

C0603

C0603

24mA

+V1.05S_DPLLA

C512

C512
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

+V1.05S_DPLLB

0R652 R0603 0R652 R0603

3

C91

C91
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R
10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.05S +V3.3S

321.35mA

+V3.3S

1782mA

0.47UF/25V,Y5V

0.47UF/25V,Y5V

C487

C487

0.1uF/10V,X5R

0.1uF/10V,X5R
C0402

C0402
C488

C488

0.1uF/10V,X5R

0.1uF/10V,X5R
C0402

C0402

C59

C59
C0402

C0402

0.1UF/10V,X7R

0.1UF/10V,X7R

C361

C361

R4201R0603R4201R0603

10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

+VCC_PEG +V1.05S

C312

C312
C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

C327

C327
C0603

C0603

1uF/10V,X7R

1uF/10V,X7R

220UF/2.5V,POSCAP

220UF/2.5V,POSCAP

C287

C287
C0603

C0603

C513

C513

0.1UF/10V,X7R

0.1UF/10V,X7R

C514

C514

0.1UF/10V,X7R

0.1UF/10V,X7R

3

C75

C75
C0805

C0805

ns

ns

ns

ns

C58

C58
C0805

C0805

10UF/6.3V,X5R

10UF/6.3V,X5R

FB28

300ohm@100MHz,1.5A

300ohm@100MHz,1.5A

C510

C510
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

C314

C314
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

C334

C334

12
CT7343_19

CT7343_19

1

1

+

+

ns

ns

C78

C78
C0805

C0805

10uF/6.3V,X5R

10uF/6.3V,X5R

1 2

C363

C363
10UF/6.3V,X5R

10UF/6.3V,X5R
C0805

C0805

+V_TXLVDS

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

C302

C302

CT4

CT4

C77

C77

2.2uF/10V,X7R

2.2uF/10V,X7R

C0805

C0805

Add for plane integrity
By Johan 071228

+V1.05S
0R105R0603 0R105R0603

+V1.8

FB0805FB28

FB0805

R379 0 R0805R379 0 R0805

C0805

C0805

R399 0 R0805R399 0 R0805

C0805

C0805

CHANGED

0R650 R06030R650 R0603

+V1.05S

+V1.8

2

+V1.05S

C87

C87
C0805

C0805

10UF/6.3V,X5R

10UF/6.3V,X5R

C80

C80
C0805

C0805

10UF/6.3V,X5R

10UF/6.3V,X5R

2

2898mA

R1360

R1360
R0402

R0402

C76

C76
C0805

C0805

10UF/6.3V,X5R

10UF/6.3V,X5R

AG34
AC34
AB34
AA34

AM33
AK33
AJ33
AG33
AF33

AE33
AC33
AA33

AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23

Y34
V34

U34

Y33

W33

V33
U33

T32

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31

VCC NCTF

VCC NCTF

VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

1

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Lucifer Jiang
CANTIGA(POWER)

CANTIGA(POWER)

CANTIGA(POWER)

M42G

M42G

M42G

1

+V3.3S {6,7,10,12,15,16,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,39,41,42,43}
+VCC_PEG {10}
+V1.8 {12,13,15,16,38,41,43}
+V1.5S {8,22,24,27,28,29,31,39,41,43}
+V1.05S {6,7,8,9,12,13,22,24,32,39,41,42,43,45}

U13F

U13F

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

VCC_35

CANTIGA_1p2

CANTIGA_1p2

VCC CORE

VCC CORE

POWER

POWER

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

+V1.05S

14 50Tuesday, March 11, 2008

14 50Tuesday, March 11, 2008

14 50Tuesday, March 11, 2008

A

A

A

of

of

of

5

D D

C C

Note:

+V3.3S

0.1UF/25V,Y5V

0.1UF/25V,Y5V
C152

C152

C0402

B B

C0402

SO-DIMM0 SPD Address is 0xA0
SO-DIMM0 TS Address is 0x30

SM_VREF_L{12,16,38}

C154

C154

2.2UF/10V,X7R

2.2UF/10V,X7R
C0805

C0805

MA_A_A[13:0]{11,17}

MA_A_A14{11,17}
MA_A_BS#2{11,17}
MA_A_BS#0{11,17}

MA_A_BS#1{11,17}

M_CS#0{12,17}
M_CS#1{12,17}

MA_DM[7:0]{11}

MA_A_WE#{11,17}
MA_A_CAS#{11,17}
MA_A_RAS#{11,17}

M_CKE0{12,17}
M_CKE1{12,17}

M_CLK_DDR0{12}
M_CLK_DDR#0{12}
M_CLK_DDR1{12}
M_CLK_DDR#1{12}

M_ODT0{12,17}
M_ODT1{12,17}

MA_DQS[7:0]{11}

SMB_DATA_S{6,16,23,27,28,29}
SMB_CLK_S{6,16,23,27,28,29}

0.1UF/25V,Y5V

0.1UF/25V,Y5V

R226 0R226 0

C166

C166
C0402

C0402

MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3
MA_DQS4
MA_DQS5
MA_DQS6
MA_DQS7

R232 10K R0402R232 10K R0402
R233 10K R0402R233 10K R0402

close to DDR pin

DIM_EXTTS#0{12}

MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6

MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

C169

C169

2.2UF/10V,X7R

2.2UF/10V,X7R
C0805

C0805

4

DIM1

DIM1
DDR2_SODIMM200

111

117

VDD1

VDD2

VDD3

1010 000x

VSS1

47

133

118

VDD496VDD595VDD6

VSS2

VSS3

183

DDR2_SODIMM200
DDR200RVS_5D2

DDR200RVS_5D2

87

103

VDD781VDD882VDD9

VSS477VSS512VSS648VSS7

184

VDD10

VSS878VSS971VSS1072VSS11

190

187

178

104

VDD1188VDD12

155

VSS36

VSS34

VSS35

VSS379VSS3821VSS3933VSS40

DDRII

VSS12

VSS13

VSS14

VSS158VSS1618VSS1724VSS1841VSS1953VSS2042VSS2154VSS2259VSS2365VSS2460VSS2566VSS26

121

122

196

193

132

144

156

168

VSS4134VSS42

VSS43

VSS44

VSS45

+V1.8

112

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

CS0

115

CS1

10

DQM0

26

DQM1

52

DQM2

67

DQM3

130

DQM4

147

DQM5

170

DQM6

185

DQM7

109

WE

113

CAS

108

RAS

79

CKE0

80

CKE1

30

CK0

32

CK0

164

CK1

166

CK1

114

ODT0

119

ODT1

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

195

SDA

197

SCL

198

SA0

200

SA1

199

VDDSPD

1

VREF1

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

VSS462VSS473VSS4815VSS4927VSS5039VSS51

VSS27

127

139

3

SO-DIMM 0

40

150

138

162

149

161

28

MA_DATA0

5

VSS54

VSS56

VSS55

VSS57

VSS52

VSS53

D0

MA_DATA1

7

D1

MA_DATA2

17

D2

MA_DATA3

19

D3

MA_DATA4

4

D4

MA_DATA5

6

D5

MA_DATA6

14

D6

MA_DATA7MA_A_A7

16

D7

MA_DATA8

23

D8

MA_DATA9

25

D9

MA_DATA10

35

D10

MA_DATA11

37

D11

MA_DATA12

20

D12

MA_DATA13

22

D13

MA_DATA14

36

D14

MA_DATA15

38

D15

MA_DATA16

43

D16

MA_DATA17

45

D17

MA_DATA18

55

D18

MA_DATA19

57

D19

MA_DATA20

44

D20

MA_DATA21

46

D21

MA_DATA22

56

D22

MA_DATA23

58

D23

MA_DATA24

61

D24

MA_DATA25

63

D25

MA_DATA26

73

D26

MA_DATA27

75

D27

MA_DATA28

62

D28

MA_DATA29

64

D29

MA_DATA30

74

D30

MA_DATA31

76

D31

MA_DATA32

123

D32

MA_DATA33

125

D33

MA_DATA34

135

D34

MA_DATA35

137

D35

MA_DATA36

124

D36

MA_DATA37

126

D37

MA_DATA38

134

D38

MA_DATA39

136

D39

MA_DATA40

141

D40

MA_DATA41

143

D41

MA_DATA42

151

D42

MA_DATA43

153

D43

MA_DATA44

140

D44

MA_DATA45

142

D45

MA_DATA46

152

D46

MA_DATA47

154

D47

MA_DATA48

157

D48

MA_DATA49

159

D49

MA_DATA50

173

D50

MA_DATA51

175

D51

MA_DATA52

158

D52

MA_DATA53

160

D53

MA_DATA54

174

D54

MA_DATA55

176

D55

MA_DATA56

179

D56

MA_DATA57

181

D57

MA_DATA58

189

D58

MA_DATA59

191

D59

MA_DATA60

180

D60

MA_DATA61

182

D61

MA_DATA62

192

D62

MA_DATA63

194

D63

MA_DQS#0

11

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

VSS29

VSS30

VSS31

VSS32

VSS28

VSS33

145

165

171

172

128

177

201

GND0

202

GND1

MA_DQS#1

29

MA_DQS#2

49

MA_DQS#3

68

MA_DQS#4

129

MA_DQS#5

146

MA_DQS#6

167

MA_DQS#7

186

MA_DATA[63:0] {11}

MA_DQS#[7:0] {11}

220UF/2.5V,POSCAP

220UF/2.5V,POSCAP

2

+V1.8

12

C179

C179

1

1

C160

C160

ns

ns

+

+

C0402

C0402

CT7343_19

CT7343_19

0.1UF/25V,Y5V

0.1UF/25V,Y5V

2.2UF/10V,X7R

2.2UF/10V,X7R

+V1.8

C172

C172

C157

C157

C0402

C0402

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

Layout note:

C173

C173

C168

C168

ns

ns

C0805

C0805

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C164

C164
C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

电容靠近

+V3.3S {6,7,10,12,14,16,19,20,21,22,23,24,25,27,28,29,30,31,32,33,34,39,41,42,43}
+V1.8 {12,13,14,16,38,41,43}

C174

C163

C163
C0402

C0402

C174
C0402

C0402

ns

ns

C156

C156
C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

0.1UF/25V,Y5V

0.1UF/25V,Y5V

C159

C159
C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

C162

C162

C158

C158

ns

ns

ns

ns

C0402

C0402

C0805

C0805

2.2UF/10V,X7R

2.2UF/10V,X7R

1, A minimum of 9 high frequency
capacitors are recommended to be
placed near each SO-DIMM of DDR2.
2, 2.2μF*5 per DIMM,0.1μF*4 per
DIMM,330μF*1 per DIMM

C161

C161
C0402

C0402

0.1UF/25V,Y5V

0.1UF/25V,Y5V

DDR slot VDD PIN

1

A A

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

TOPSTAR TECHNOLOGY

Lucifer Jiang

Lucifer Jiang

Page Name

Page Name

Page Name
Size

Size

Size

Project Name Rev

Project Name Rev

Project Name Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

Lucifer Jiang
DDR2 SODIMM0

DDR2 SODIMM0

DDR2 SODIMM0

M42G

M42G

M42G

1

A

A

15 50Tuesday, March 11, 2008

15 50Tuesday, March 11, 2008

15 50Tuesday, March 11, 2008

A

of

of

of