The TP6312 is a VFD (Vacuum Fluorescent Display)
controller/driver that is driven on a 1/4 to 1/11-duty
factor. It consists of 11 segment output lines, 6 grid
output lines, 5 segment/grid output drivelines, a
display memory, a control circuit, and a Key scan
circuit. Serial data is input to TP6312 through a
three-line serial interface. This VFD controller/driver
is ideal as a peripheral device of a single-chip
microcomputer.
Ordering Information
TP 6312
Footprint
Version
Package Type
Features
Multiple display modes (11-segment & 11-digit to
16-segment & 4-digit)
Key scanning (6 × 4 matrices)
Dimming circuit (eight steps)
High-voltage output (V
LED ports (4 chs, 20 mA max)
General-purpose input port (4 bits)
No external resistor necessary for driver outputs
(P-ch open-drain + pull-down resistor output)
Serial interface (CLK, STB, D
Package Type
Footprint
F: LQFP
S: 2.0 mm
L: 3.2 mm
– 35V max)
DD
IN
, D
OUT
)
Block Diagram
DIN
DOUT
CLK
STB
R
Key1
to
Key4
4
Serial I/F
OSC
Command decoder
Display memory
16bit x 11 word
Timing generator key
scan
Key data memory
(4x6)
Dimming circuit
1611
16-bit output latch16-bit output latch
116
Seg1
Segment driverSegment/grid driverGrid driver
5
5
Data selector
5
Seg11
Seg12/Gird11
Seg16/Gird7
Grid1
Grid6
SW1
to
SW4
4
4 bit latch
4 bit latch
1
LED
LED
VDDVSSVEE
(+5V)(0V)(-30V)
4
Version 1.1 Page 1 of 9 http://www.topro.com.tw
September 2003
Page 2
TP6312
Pin Configuration (Top View)
Grid 4
Grid 3
Grid 2
Grid 1
DD
V
LED 4
LED 3
LED 2
LED 1
VSS
OSC
44 43 42 41 40 39 38 37 36 35 34
Use all the power pins.
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
EE
Grid 6
Grid 5
33
1
SW 1
Seg15 / Grid 8
Seg16 / Grid 7
30
31
32
2
3
4
SW 2
SW 3
SW 4
V
Seg14 / Grid 9
Seg13 / Grid 10
Seg12 / Grid 11
26
27
28
29
5
6
7
8
OUT
DIN
CLK
VSS
D
Seg9
Seg10
Seg11
23
24
25
Seg8
Seg7
Seg6 / KS6
Seg5 / KS5
Seg4 / KS4
Seg3 / KS3
Seg2 / KS2
Seg1 / KS1
V
DD
KEY 4
KEY 3
12 13 14 15 16 17 18 19 20 21 22
9
10
11
STB
KEY 1
KEY 2
Pin Description
Pin No Symbol Pin Name Description
6 DIN Date input
5 D
Date output
OUT
9 STB Strobe
8 CLK Clock input
44 OSC Oscillator pin
/KS1 to
Seg
Seg
Seg
1
Seg
6
/Grid11 to
11
16
/KS6
/Grid7
High-voltage output
High-voltage output
(Segment)
High-voltage output
(Grid)
High-voltage output
(Segment/grid)
15 to 20
21 to 25 Seg7 to Seg11
37 to 32 Grid1 to Grid6
26, 28 to 31
42 to 39 LED1 to LED4 LED output CMOS output. +20 mA max.
10 to 13 Key1 to Key4 Key data input
1 to 4 SW1 to SW4 Switch input
14, 38 VDD Logic power
7, 43 VSS Logic ground Connect this pin to system GND.
27 VEE Pull-down level VDD – 35 V max
Inputs serial data at rising edge of shift clock,
starting from the lower bit.
Outputs serial data at falling edge of shift clock,
starting from the lower bit. This is N-ch open-drain
output pin.
Initializes the serial interface at rising or falling edge
to make TP6312 waiting for reception of command.
Data input after STB has fallen is processed as
command. While command data is processed,
current processing is stopped and serial interface is
initialized. While STB is high, CLK is ignored.
Reads serial data at rising edge, and outputs data at
falling edge.
Connects a resistor to this pin to determine the
oscillation frequency to this pin.
Segment output pins (Dual function as Key source).
Segment output pins.
Grid output pins.
These pins are selectable for segment or grid
driving.
Data input to these pins is latched at the end of
Version 1.1 Page 2 of 9 http://www.topro.com.tw
September 2003
Page 3
TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Functional Description
Display RAM Address and Display Mode
The display RAM stores the data transmitted from an
external device to TP6312 through the serial interface,
and is assigned addresses as follows, in units of 8
bits:
The Key matrix is of 6 × 4 configuration, as shown
below.
KEY1
KEY2
The data of each Key is stored as illustrated below,
and is read by a read command, starting from the
least significant bit.
Key
Key4Key1 Key4
1
/ KS1 Seg2 / KS2
Seg
1
Seg3 / KS3 Seg4 / KS4
Reading s eque nce
Seg5 / KS5 Seg6 / KS6
b0 b3 b4 b7
LED Port
Data is written to the LED port by a write command,
starting from the least significant bit of the port.
When a bit of this port is 0, the corresponding LED
lights; when the bit is 1, the LED goes off. The data
of bits 5 through 8 is ignored.
---- ------------b3b2b1b0
LED1
Don't care
LED2
LED3
LED4
On power application, all LEDs are unlit.
SW Data
The SW data is read by a read command, starting
from the least significant bit. Bits 5 through 8 of the
SW data are 0.
MSBLSB
0000b3b2b1b0
KEY3
KEY4
SW1
SW2
SW3
SW4
Commands
Seg1/KS1
Seg2/KS2
Seg3/KS3
Seg4/KS4
Seg5/KS5
Seg6/KS6
A command sets the display mode and status of the
VFD driver.
The first 1 byte input to TP6312 through the D
IN
pin
after the STB pin has fallen is regarded as a
command.
If STB is high while a command/data is transmitted,
serial communication is initialized, and the
transmitting command/data is invalid; however, the
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September 2003
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TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
command/data already transmitted remains valid.
(1) Display mode setting command
This command initializes TP6312 and selects the
number of segments and number of grids (1/4 to 1/11duty, 11 segments to 16 segments).
On power application, the 11-digit, 11-segment mode
is selected.
On power application, the normal operation mode and
address increment mode set.
(3) Address setting command
This command sets an address of the display
memory.
MSBLSB
11----b4b3b2b1b0
One cycle of Key scanning consists of two frames,
and data of 6 × 4 matrices is stored in RAM.
Serial Communication Format
Reception (command/data write)
STB
DIN
CLK
b0b1b2……b6b7
If d a ta i s cintiguous
……
Address (00H-15H)
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September 2003
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TP6312
Transmission (data read)
STB
DIN
CLK
DOUT
b0 b1 b2 b3b5b4b6 b7
12345678123456
Data r ea di ng comma nd i s s e t.Data reading starts.
t
WAIT
b0 b1 b2 b3b5b4
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Because the D
pin, be sure to connect an external pull-up resistor to
this pin (1kΩ to 10 kΩ).
*: When data is read, a wait time (t
necessary from the rising of the eighth clock that has
set the command till the falling of the first clock that
has read the data.
pin is an N-ch open-drain output
OUT
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
Parameter Symbol Ratings Unit
Logic Supply Voltage VDD -0.5 to + 7.0 V
Driver Supply Voltage VEE VDD +0.5 to VDD -40 V
Logic Input Voltage Vi1 -0.5 to VDD +0.5 V
VFD Driver Output Voltage Vo2 VEE –0.5 to VDD +0.5V
LED Driver Output Current Io1 +25 mA
= VFD driver dissipation + RL dissipation + LED driver dissipation + dynamic power
MAX
consumption.
Where segment current = 3 mA, grid current = 15mA, and LED current = 20 mA,
VFD driver dissipation = number of segments x 6 + number of grids/(number of grids + 1) x 30(mW)
R
dissipation ≒ (VDD-VEE)2/50 x (segment+1) (mW)
L
LED driver dissipation = number of LEDs x 20(mW)
Dynamic power consumption = V
x 5(mW)
DD
Electrical Characteristics (Ta = -20°C to +70°C, V
Parameter Symbol Min Typ.Max. Unit Test Conditions
High-Level Output Voltage V
Low-Level Output Voltage V
Low-Level Output Voltage V
High-Level Output Current I
High-Level Output Current I
Driver Leakage Current I
Output Pull-Down Resistor RL 50 100 150
Input Current Ii
High-Level Input Voltage VIH 0.6 V
Low-Level Input Voltage VIL 0.3 V
Hysteresis Voltage VH 0.35 V CLK, DIN, STB
Dynamic Current ConsumptionI
0.9 V
OH1
OL1
OL2
-3
OH21
-15
OH22
-10
OLEAK
5 mA Under no load, display off
DDdyn
-40 (grid)
-15 (segment)
DD
DD
DD
DD
V LED1 – LED4, I
DD
V
mA
℃
℃
V
V
= 4.5V to 5.5V, VS = 0V, V
1 V LED1 – LED4, I
0.4 V D
mA VO = VDD –2V, Seg1 to Seg11
mA
µA
kΩ
±1 µA
DD
V
OUT
= VDD –2V,Grid1 to Grid6,
V
O
Seg
/Seg 11 to Seg16/Seg 7
12
VO = VDD - 35V, Drive off
VI = VDD or VSS
WAIT)
= V
EE
OH1
= 20 mA
OL1
, I
= 4 mA
OL2
Drive output
of 1µs is
- 35V)
DD
= -1 mA
Version 1.1 Page 5 of 9 http://www.topro.com.tw
September 2003
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TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Switching Characteristics (Ta = -20°C to +70°C, VDD = 4.5V to 5.5V, VEE = -30V)
Parameter Symbol Min Typ.Max. Unit Test Conditions
Oscillation Frequency f
Propagation Delay Time
Rise Time
350 500 650 kHz
OSC
t
300 ns
PLZ
t
100 ns
PZL
t
2
TZH1
0.5
t
TZH2
µs
µs
R = 56kΩ
CLK ⇒ DOUT
CL = 15pF,RL = 10kΩ
Seg1 to Seg11
CL = 300
Grid1 to Grid6
PF
Seg12/Grid11
Seg16/Grid7
Fall Time t
Maximum Clock Frequency f
120
THZ
1 MHz Duty = 50%
max
µs
CL = 300 pF, Segn, Gridn
Input Capacitance C1 15 pF
Timing Conditions (Ta = -20°C to +70°C, Vdd = 4.5V to 5.5V)
Parameter Symbol Min Typ.Max. Unit Test Conditions
Clock Pulse Width PWCLK 400 ns
Strobe Pulse Width PW STB 1
Data Setup Time t
Data Hold Time t
Clock-Strobe Time t
Wait Time t
100 ns
SETUP
100 ns
HOLD
1
CLK-STB
1
WAIT
µs
µs
µs
CLK ↑→ STB ↑
CLK ↑→ CLK ↓
to
Switching Characteristic Waveform
PW
CLK
PW
t
SETUP
t
hold
CLK
PW
STB
t
CLK-STB
t
PZL
t
PZL
t
THZ
90%
10%
t
THZ
Version 1.1 Page 6 of 9 http://www.topro.com.tw
September 2003
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TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Application
Updating display memory by incrementing address
STB
CLK
DIN
Command1
Command2
Command3
Data 1
Command1: sets display mode
Command2: sets data
Command3: sets address
Data 1 to n: transfers display data (22 bytes max.)
Command4: controls display
……
……
Data n
Comma n d 4
Updating specific address
STB
CLK
DIN
Command1: sets data
Command2: sets address
Data: display data
Command1
Command2
Data
Command2
Data
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September 2003