Toppoly TD141THCA1 Specification
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TD141THCA1
Tentative Ver.: 0.00
TFT LCD Specification
Model Name: TD141THCA1
Customer Signature
Date
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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NO. Item Page
Cover Sheet 1
Table of Contents 2
Record of Revision 3
1 Features 4
2 General Specifications 4
3 Input / Output Terminals 5
4 Absolute Maximum Ratings 6
5 Electrical Characteristics 6
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TD141THCA1
Table of Contents
6 Timing Chart 9
7 Optical Characteristics 13
8 Reliability 17
9 Handling Cautions 18
10 Mechanical Drawing 19
11 Packing Drawing 21
12
Module & Carton Label Drawing & Definition
Appendix1 EDID
22
24
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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Rev Issued Date Description
0.00 Oct. 26, 2005 New Create
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TD141THCA1
Record of Revision
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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1. FEATURES
This module is a color active matrix LCD module that uses LTPS (Low Temperature Poly Silicon) TFT
(Thin Film Transistor). This module is composed of a color TFT-LCD panel, a driver circuit and a
backlight unit. The resolution of a 14.1” contains 1280 x 800 pixels and can display up to 262,144
colors.
(1) 14.1” WXGA (1280 x 800 pixels) display size for notebook PC
(2) LTPS TFT technology
(3) High contrast ratio, high aperture ratio and high-brightness
(4) LVDS interface system
(5) Onboard EDID chip
(6) Low power consumption.
(7) Thin and light weight
(8) RoHS compliant
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TD141THCA1
2. GENERAL SPECIFICATIONS
Item Description Unit
Display Size 14.1” Diagonal inch
Aspect Ratio 16 : 10
Active Area 303.4 (H) x 189.6 (V) mm
Number of Dots 1280 (H) x RGB x 800 (V) dot
Pixel Pitch 0.237 (H) x 0.237 (V) mm
Color Arrangement R, G, B Vertical Stripe
Outline Dimension (typ.) 319.5 (H) x 205.5 (V) x 5.1 (T) mm
Weight (typ.) 415 g
Display Mode Normally White
Surface Treatment Glare + 3H Hard coating
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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3. INPUT/OUTPUT TERMINALS
3.1 TFT LCD Panel
Recommend Connector Type JAE FI-XB30S-HF10 or Compatible
TD141THCA1
Matching Connector Type
FPC : FI-X30M or Compatible
WIRE : FI-X30H or Compatible
Pin No Symbol Function Polarity Remark
1 VSS Ground
2 VDD Power supply +3.3 v
3 VDD Power supply +3.3 v
4V
EDID
DDC 3.3V power
5 NC Reserved for supplier test point
6 Clk
7 DATA
EDID
EDID
DDC Clock
DDC Data
8 Rin0- -LVDS differential data input (R0~R5, G0) Negative
1CH
9 Rin0+ +LVDS differential data input (R0~R5, G0) Positive
10 VSS Ground
11 Rin1- -LVDS differential data input (G1~G5, B0~B1) Negative
1CH
12 Rin1+ +LVDS differential data input (G1~G5, B0~B1) Positive
13 VSS Ground
14 Rin2- -LVDS differential data input (B2~B5, DE, Hsync, Vsync) Negative
1CH
15 Rin2+ +LVDS differential data input (B2~B5, DE, Hsync, Vsync) Positive
16 VSS Ground
17 Clk IN- -LVDS differential clock input (Clock input) Negative
1CH
18 Clk IN+ +LVDS differential clock input (Clock input) Positive
19 VSS Ground
20 No connect
21 No connect
22 VSS Ground
23 N.C No connect
24 N.C No connect
25 VSS Ground
26 N.C No connect
27 N.C No connect
28 VSS Ground
29 N.C No connect
30 N.C No connect
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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3.2 Light Source
Light Source Type: CCFL Back Light
Recommend Connector Type：JST BHSR – 02VS - 1
Pin NO. Symbol Color Function
1VHPink High Voltage
2VLWhite Low Voltage
4. ABSOLUTE MAXIMUM RATINGS
Item Symbol MIN MAX Unit Remark
Power Supply Voltage Vcc Vss-0.3 4.0 V
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TD141THCA1
GND =0V
Logic Input Voltage Vin Vss-0.3
Lamp Current I
Lamp Frequency F
L
L
2.0 7.0
50 80 KHz
Operating Temperature Topr 0 +50
Storage Temperature Tstg -25 +60
Vss+0.3
（
）
V
rms
mA
℃
℃
Storage Humidity Hstg 10 90 %RH Note 4-1
Note 4-1: Maximum wet – bulb temperature at 39
or less.（Ta＞40
℃
No condensation
℃）
5. ELECTRICAL CHARACTERISTICS
5.1 TFT LCD Module
Item Symbol MIN TYP MAX Unit Remark
Voltage of power supply V
Differential Input
Threshold Voltage
Rush Current I
V
HIH
V
HIL
RUSH
V
I
DD
HIH
V
HIL
RUSH
3.0 3.3 3.6 V
-- -- 100 mV
V
-100 -- -- mV
-- -- 1.5 A Note 5.1
Ta=25
= +1.2V
CM
℃
Vsync Frequency f
Hsync Frequency f
Main Frequency f
V
H
DCLK
40 60 -- Hz
31.9 47.8 -- KHz
68 71 85 MHz
White -- 280 -- mA Note 5.2
Current of Power Supply
Mosaic -- 335 -- mA Note 5.2
Black -- 397 -- mA Note 5.2
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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Note 5-1: Refer to the following power-on condition
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TD141THCA1
VDD rising time is 470 us
0.9V
DD
GND
0.1VDD
470us
Note 5-2: Power are measure as following test condition: fV=60 Hz, f
Current
Driving TFT LCD Module Block Diagram
1-CH LVDS INTERFACE
EDID Chip
Timing
Controller
DC to DC
Level
Shifter
Gamma
Reference
Common
Circuit
3.3V
=71 MHz, VDD =3.3V, DC
DCLK
PCB
LTPS WXGA Panel
4 ea 350 Pin
DRIVER With
TCP
PACKAGE
LVDS
DC POWER
SIGNAL LINE
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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5.2 Driving Backlight
The backlight system is an edge – lighting type with a single CCFL (Cold Cathode Fluorescent Tube)
The characteristics of a single lamp are shown in the following tables.
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TD141THCA1
Ta=25
℃
Item Symbol MIN TYP MAX Unit Remark
Lamp Current I
Lamp Voltage V
Power Consumption P
Frequency F
L
L
L
L
3.0 6.0 6.5 mArms Note 5-1
I
576 680 704 Vrms
L
＝
6mA
-- 4.08 -- W Note 5-2
50 60 80 kHz Note 5-3
Operating Life time Hr 15,000 -- -- Hour Note 5-4
Lamp starting voltage Vs -- --
1160（25
1450（0
℃）
Vrms Note 5-5
℃）
Note) The performance of backlight, for example life time or brightness are deep influence by the
characteristic of the inverter. So all the parameters of inverter should be designed carefully. And
should not to produce too much leakage current from high-voltage output of the inverter.
The Inverter should be designed with the characteristic of lamp. Please make sure that a poor
lighting cause by the mismatch of the backlight and inverter never occur.
Note 5-1: Lamp current is measured with a high frequency current meter as show below.
High Voltage：(Pink)
LCD
Module
1
Low Voltage：(White)
2
Inverter
A
Switching Frequency：(50~80)KHz
Note 5-2: W＝I
Note 5-3: Lamp frequency may produce interference with horizontal synchronous frequency and this
may cause line flow on the display. Therefore lamp frequency shall be detached from the
horizontal synchronous frequency and its harmonics as far as possible in order to avoid
interference.
Note 5-4: Operating Life time is defined as lamp which are continue to operate under the condition
Ta=25℃ and I
brightness.
(TYP)× VL(TYP)
L
6mArms until the brightness is decreased to the 50% or lower than the initial
＝
L
Note 5-5: Above this value should be applied to the lamp for more than 1 second to startup, otherwise
the lamp may not be turned on.
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
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6. TIMING CHART
6.1 1CH LVDS Channel Interface Data Mapping Diagram
(n-1)th cycle Present (n)th cycle (n+1)thcycle
ORXCLK+
ORXCLK-
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TD141THCA1
ORX0(+/-)
ORX1(+/-)
OEX2(+/-)
OR1 OR0 OG0 OR5 OR4 OR3 OR2 OR1 OR0 OG0
OG2 OG1 OB1 OB0 OG5 OG4 OG3 OG2 OG1 OB1
OB3 OB2 DE Vsync Hsync OB5 OB4 OB3 OB2 DE
Note1: R/G/B [5] are the MSBs and R/G/B[0] are LSBs
6.2 Pixel Format in Display
1 1280
Line 1
R G B R G B R G B R G B
Active
TD141THCA1
R G B R G B R G B R G B
Line 800
The information contained herein is the exclusive property of toppoly Optoelectronics corporation, and shall not be
distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly Optoelectronics
corporation.
Area
Edge
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