This manual is the latest at the time of printing, and does not
include the modification which ma
the constant improvement of product.
be made after the printing, b
Page 2
CAUTION:
RISK OF ELECTRIC
SHOCK DO NOT OPEN.
1
Use of controls, adjustments or procedures other than those specified herein may result in
hazardous radiation exposure.
CAUTION:TO REDUCETHE RISKOF
CAUTION
The lighting flash with arrowhead symbol, with an equilateral triangle is intended to
alert the user to the presence of uninsulatedvoltage within the product s
enclosure that may be of sufficient magnitude to constitute a risk of electric shock to
the person.
The exclamation point within an equilateral triangle is intended to alert the user to the
presence of important operating and maintenance (servicing) instructions in the
literature accompanying the appliance.
ELECTRICAL SHOCK, DO NOT REMOVE
COVER (OR BACK). NO USER SERVICEABLE
PARTS INSIDE.REFER SER VICINGTO
QUALIFIED SERVICE PERSONNEL.
dangerous
WARNING: TO REDUCE RISK OF FIRE OR ELECTRIC SHOCK, DO NOT
EXPOSE THIS APPLIANCE TO RAIN OR MOISTURE.
2
Page 3
IMPORTANT SAFETY INSTRUCTIONS
CAUTION:
Read all of these instructions. Save these instructions for later use . Follow all Warnings and
Instructions marked on the audio equipment.
1. Read Instructions-All the safety and operating instructions should be read before the product is operated.
2. Retain Instructions- The safety and operating instructions should be retained for future reference.
3. Heed Warnings- All warnings on the product and in the operating instructions should be adhered to.
4. Follow Instructions- All operating and use instructions should be followed.
FOR YOUR PERSONAL SAFETY
1.When the power cord or plug is damaged or frayed, unplug this television set from the wall outlet and refer servicing to
qualified service personnel.
2.Do not overload wall outlets and extension cords as this can result in fire or electric shock.
3.Do not allow anything to rest on or roll over the power cord, and do not place the TV where power cord is subject to
traffic or abuse. This may result in a shock or fire hazard.
4.Do not attempt to service this television set yourself as opening or removing covers may expose you to dangerous
voltage or other hazards. Refer all servicing to qualified service personnel.
5.Never push objects of any kind into this television set through cabinet slots as they may touch dangerous voltage
points or short out parts that could result in a fire or electric shock. Never spill liquid of any kind on the television set.
6.If the television set has been dropped or the cabinet has been damaged, unplug this television set from the wall outlet
and refer servicing to qualified service personnel.
7.If liquid has been spilled into the television set, unplug this television set from the wall outlet and refer servicing to
qualified service personnel.
8.Do not subject your television set to impact of any kind. Be particularly careful not to damage the picture tube surface.
9.Unplug this television set from the wall outlet before cleaning. Do not use liquid cleaners or aerosol cleaners. Use a
damp cloth for cleaning.
10.1. Do not place this television set on an unstable cart, stand, or table. The television set may fall, causing serious injury
to a child or an adult, and serious damage to the appliance. Use only with a cart or stand recommended by the
manufacturer, or sold with the television set. Wall or shelf mounting should follow the manufacturer s instructions, and
should use a mounting kit approved by the manufacturer.
10.2. An appliance and cart combination should be moved with care. Quick stops, excessive force, and uneven surfaces
may cause the appliance and cart combination to overturn.
3
Page 4
PROTECTION AND LOCATION OF YOUR SET
11.Do not use this television set near water ... for example, near a bathtub, washbowl, kitchen sink, or laundry tub, in a
wet basement, or near a swimming pool, etc.
Never expose the set to rain or water. If the set has been exposed to rain or water, unplug the set from the wall
outlet and refer servicing to qualified service personnel.
12. Choose a place where light (artificial or sunlight) does not shine directly on the screen.
13. Avoid dusty places, since piling up of dust inside TV chassis may cause failure of the set when high humidity persists.
14. The set has slots, or openings in the cabinet for ventilation purposes, to provide reliable operation of the receiver, to
protect it from overheating. These openings must not be blocked or covered.
Never cover the slots or openings with cloth or other material.
Never block the bottom ventilation slots of the set by placing it on a bed, sofa, rug, etc.
Never place the set near or over a radiator or heat register.
Never place the set inenclosure, unless proper ventilation is provided.
a built-in
PROTECTION AND LOCATION OF YOUR SET
15.1. If an outside antenna is connected to the television set, be sure the antenna system is grounded so as to provide some
protection against voltage surges and built up static charges, Section 810 of the National Electrical Code, NFPA No.
70-1975, provides information with respect to proper grounding of the mast and supporting structure, grounding of the
lead-in wire to an antenna discharge unit, size of grounding conductors, location of antenna discharge unit, connection
to grounding electrode, and requirements for the grounding electrode.
EXAMPLE OF ANTENNA GROUNDING AS PER NATIONAL ELECTRICAL CODE INSTRUCTIONS
EXAMPLE OF ANTENNA GROUNDING AS PER
NATIONAL ELECTRICAL CODE
ANTENNA
LEAD- IN WIRE
GROUND CLAMP
ANTENNA DISCHARGE
UNIT (NEC SECTION
810-20)
GROUNDING
ELECTRIC SERVICE
EQUIPMENT
NEC-NATIONAL ELECTRICAL CODE
15.2. Note to CATV system installer : (Only for the television set with CATV reception)
This reminder is provided to call the CATV systemattention to Article 820-40 of the NEC that provides
installer s
guidelines for proper grounding and, in particular, specifies that the cable ground shall be connected to the grounding
system of the building, as close to the point of cable entry as practical.
16.An outside antenna system should not be located in the vicinity of overhead power lines or other electric lights or power
circuits, or where it can fall into such power lines or circuits. When installing an outside antenna system, extreme care
should be taken to keep from touching such power lines or circuits as contact with them might be fatal.
CONDUCTORS
(NEC SECTION810-21)
GROUND CLAMPS
POWER SERVICE GROUNDING
ELECTRODE SYSTEM
(NEC ART 250. PART H)
17.For added protection for this television set during a lightning storm, or when it is left unattended and unused for long
periods of time, unplug it from the wall outlet and disconnect the antenna. This will prevent damage due to lightning
and power-line surges.
4
Page 5
OPERATION OF YOUR SET
18.
This television set should be operated only from the type of power source indicated on the marking label.If you are not
sure of the type of power supply at your home, consult your television dealer or local power company. For television
sets designed to operate from battery power, refer to the operating instructions.
19.If the television set does not operate normally by following the operating instructions, unplug this television set from the
wall outlet and refer servicing to qualified service personnel. Adjust only those controls that are covered in the operating
instructions as improper adjustment of other controls may result in damage and will often require extensive work by a
qualified technician to restore the television set to normal operation.
20.When going on a holiday : If your television set is to remain unused for a period of time, for instance, when you go on
a holiday, turn the television setand unplug the television set from the wall outlet.
off
IF THE SET DOES NOT OPERATE PROPERLY
21. If you are unable to restorenormal operation by followingthe detailed procedure in your operating instructions,
do not attempt any further adjustment. Unplug the set and call your dealer or service technician.
22. Whenever the television set is damaged or fails, or a distinct change in performance indicates a need for
service, unplug the set and have it checked by a professional service technician.
23. It is normal for some TV sets to make occasional snapping or popping sounds, particularly when being
turned on or off. If the snapping or popping is continuous or frequent, unplug the set and consult your
dealer or service technician.
FOR SERVICE AND MODIFICATION
24. Do not use attachments not recommended by the television set manufacturer as they may cause hazards.
25. When replacement parts are required, be sure the service technician has used replacement parts specified
by the manufacturer that have the same characteristics as the original part. Unauthorized substitutions
may result in fire, electric shock, or other hazards.
26. Upon completion of any service or repairs to the television set, ask the service technician to perform
routine safety checks to determine that the television is in safe operating condition.
compensative)
Film mode / reverse 3:2 pull downyes / yes
Format control (Pin8/WSS)Yes/Yes
16/9 autoformat (black bars canceller)no
Zoom type : 4/3 formatYes
Zoom type : 14/9 Zoomno
Zoom type : 16/9 ZoomYes
Zoom type : 16/9 Zoom up/downNo/No
VideoSound
Zoom type : CineramaYes
Zoom type : 16/9FormatYes
Colour preset (Cool/Normal/Warm/Favourite)Cool/Normal/Warm
Contrast expend (low/medium/high)high
Picture Reseton factory menu
Backlight Adjuston factory menu
Picture Autoadjustment (PC mode)Yes
Picture presets : Standard / Film / Studio / Sport /
Personal / Game / Video Camera
Music Power (Watt)2*15W
RMS Power (Watt)2*8W
Graphic EqualizerYes
Treble, Bass, Balance, Volume, Mute Control-/-/ Yes/Yes/Yes
Sound presets (My
Loudspeakers built in (T/M/B)-/2/DPS/DPS+StandardBG/DK/I/LL`
linerar/motion adaptive/motion
compensative
Standard / Film / Studio / Sport / Personal
normal/personal/rock/pop/live/dance/techn
o/classic/soft
NICAM,German Stereo,Virtual surround
Page 8
Color System (PAL/SECAM/NTSC)PAL/SECAM/NTSC(AV)
prog
)
g
DVBT (yes/no)Yes
Video standard NTSC 3.58 / 4.43 (AV)Yes
HD capability
Compatible video format if DVD/USB:
DviX/VCD/SVCD/JPEG/AVI/MPEG2/WMV- HD/SD
Compatible audio format if DVD/USB:
MP3/WMA/AAC/MPEG1/…
PC capability (up to maximum format)1280*1024 60Hz
Playable Discs (CD/CD-R(RW)/CD-
Decoding capabilityUser convenience
ROM/DVD+R/+RW/-R/-RW)
Card reader format compatibility-
IB languages
DVD player (No/slot/tray)No
Program Numbers (example: 99+3AV)99+1AV+2SCART
Number of buttons on cabinet (Power; Vol+/-; Pr+/-,
Menu )
Main switch button (yes/no)No
ClockYes
Sleep timerYes
wake-up timerYes
Calendar / GamesYes/Parent Control - Channel lock (Input code for certain
channel)
Parent Control - Child lock (set the lock of the
keyboard, only the RCU can control the TV)
Parent Control - Kid pass (preset the ontime,
channel for each day of the week)
Parent Control - Channel lock (For digital
transmission and DVD program, to filter some
CINCH audio in / out (No volumpe control on Audio
out/can be jack 3,5mm)
CINCH video in / out1(side)/S-video in / out-/Component Video Input (YCrCb/YPrPb)1
Component Audio Input (YCrCb/YPrPb)Share with the VGA Audio input
VGA in / Audio L/R in / Jack audio in 3.5mm1/1/HDMI2
DVI-HDCPShare with HDMI
Audio input for DVI – HDCPShare with Audio VGA
CINCH subwoofer out / Coaxial out (SP-DIF)-/Headphone connector (mm)1 (side)
RS232 (Y/N)Card ReadersUSB slot (NO/1.1/2)-
Connectors (if possible, please indicate the position)Accessories included
DVBC-I (common interface)yes
1(side)/1
External power converterRemote control referenceRCT 311TV1G
Carton (English/French/Spanish)yes(English)
Batteriesyes
IByes
Product registration Cardno
AC power cordsyes
Audio Cord (Jack 3.5mm)no
VGA Cordno
WallmountNo
Antenna Cableno
Size (W x H x D, with stand) in mm1058X765X270
Size (W x H x D, without stand) in mm1058X711X116
Package Size (W x H x D, with stand) in mm1214*364*889
Data
Page 10
Net Weight in kg27.5
l
Gross Weight in Kg33
Power supply220V50Hz
Genera
Power consumption working / standby / Annual240W/ 1W /Wallmount VESA compatible (standard reference)VESA compatible
Adaptor for VESA wallmount compatibility
(accessory ref)
Desktop Stand (included/optionnal + ref/NO)yes
Panel Tilt (Fowards/Backwards/Rotation)no
Swivel function desktop stand (yes/no) + motorized?no
Docking station (yes/no)no
Floor Stand (included/optionnal + ref/NO)no
Glass shield (yes/no)no
Finish on FrontGES704S as moulded (high glossy black)
Finish on sideRBK60TH(A8252) as moulded (black)
Finish on backRBK60TH(A8252) as moulded (black)
ID specification reference (file name)Graphic specification reference (file name)Finish on standTransparent
number of colors on carton box1
Brand logoThomson Inlet
Other logoFull HD/DVB on front
Design / Mechanical
Screen StikersExternal AC/DC Power with DC power cord (yes/no)
Handle (yes/no)no
LCD42/37M61NF21 is designed for Europe, using 37/42 inch Full HD
panel. The main chip is MTK8206. Support 1x RF in, 0.5x SCART, 1XSCART,
1xYPbPr, 1xVGA, 1xside AV include YC input, 2xHDMI,1x headphone out,
1xDVB-T input. The detail please refer the SyRS˅
1
Main board alignment
For Analog part
Before power on, please check and make sure the output of U20ˈU21ˈ
U22ˈU23,U24ˈU30ˈU31 are not shorted to grand.
Supply 5v to P504 and test the output of U20, the normal is 3.3V+/-5%, the
U21 output should be 1.8V+/-5%
Download the SW to the main chip, please see the chapter of how to
download
Check all the function of the all others board on the test tool
For PCMCIA interface
Digital module servicing and debug hints.
Mainly point:
1. Check PCB and each section power supply: 12V, 5V, 1.2V,1.8V ,3.3V.
2. Switch on the power, then measure the signal of output port of video and
audio.
If no output, check the following point:
1) video output of CPU section.
2) 4Mhz clock of the tuner output
3) Output of chip 74AHC1GU04( position U24 of schematic). 4Mhz clock
signal
to CUP(PNX8314).
4) Signal of SDRAM and flash chip when working .
5) Audio DAC ( component’s position U6 of schematic.
By contraries, enter the menu’s manual research item, and set appointed
channel number, check the signal indicator on TV screen.
3. Normal there is a signal level display on the menu.
If no displaying for the signal state indicated information, check the
following point:
1) 4Mhz clock signal of the tuner output,
2) Output of chip 74AHC1GU04(component’s position U23 of
schematic).
3) Else channel decoder schematic section.
4. When it display the signal state indicated information, Press “ok’ button,
and research program. It will not play the program if not get the program
enter the sub-menu and press MENU key to return the main-menu
4ǃBalance Adjust
Adjust the temperature in CMP, VGA, AV. Please make sure the picture
mode is set to “Stand”, the “PictureÆ Black expand” on the user Menu is set to
“OFF”. “OtherÆFlesh Tone & Adaptive Luma Control ” on the factory Menu is
set to “OFF”. After Alignment, all the item will change to “ON”
ADC Adjust
A. For CMP input, the test signal is 576i/50Hz, 100%, 8 steps colour bar.
Select the “BalanceÆRGB Calibrate” on the factory Menu, then press ”Æ”.,
ADC adjust is finished after “OK” is displayed
B. For VGA input, the test signal is 1024h768/60Hzˈwhite/black grid.
Select the “BalanceÆRGB Calibrate” on the factory Menu, then press ”Æ”.,
ADC adjust is finished after “OK” is displayed
1
VGA :
For VGA input, the test signal is 1024h768/60Hzˈ16 steps gray bar. Set
the “BalanceÆ Tone” on factory menu to “Normal”:
AǃFor the third step form the white bar, Adjust the value of White RǃWhite
GǃWhite B, until the color temperature is x=280f5ˈy=290f5ˈY > 220nit
BǃFor the second step form the black bar, Adjust the value of Gray Rǃ
Gray GǃGray B, until the color temperature is x=280f5ˈy=290f5ˈY < 25nit
Cǃrepeat A&B, until all is ok
DǃAdjust the value of Black level
2˅ˊAV
For AV3 input, the test signal is PALˈ8 steps gray bar. Set the “BalanceÆ
Tone” on factory menu to “Normal”:
AǃFor the third step form the white bar, Adjust the value of White RǃWhite
GǃWhite B, until the color temperature is x=280f5ˈy=290f5ˈY > 220nit
BǃFor the second step form the black bar, Adjust the value of Gray Rǃ
Gray GǃGray B, until the color temperature is x=280f5ˈy=290f5ˈY < 25nit
Cǃrepeat A&B, until all is ok
DǃAdjust the value of Black level
3˅ˊCMP
For CMP input, the test signal is 576i/50Hzˈ16 steps gray bar. Set the
AǃFor the third step form the white bar, Adjust the value of White RǃWhite
GǃWhite B, until the color temperature is x=280f5ˈy=290f5ˈY > 220nit
BǃFor the second step form the black bar, Adjust the value of Gray Rǃ
Gray GǃGray B, until the color temperature is x=280f5ˈy=290f5ˈY < 25nit
Cǃrepeat A&B, until all is ok
DǃAdjust the value of Black level
4). Adjust the value of Black level
Measurements are using ‘SCALBRI2.UPA’ patterns with -1% to 10% video
level bars.
12%
10%
8%
6%
4%
2%
video level (%)
0%
-2%
time
Basic video signal is following:
Change the Black level to make sure the value is 0-3%.
5ǃFactory Menu definition˖
1˅ˊ System
Item Sub-item
Power Mode Remember˖Remember the state of
Factory Key OFF˖Factory Key is invalidation
Tuner AGC 12
Key Board On˖the keypad board is locked, only
LOGO Select the POWER ON LOGO
Pattern Come from IC MT8201. It is used for
Back Light Peak White Alignment
Reset Reset EEPROM data, and load the
Source TV(channel 1)
Picture Preset Standard
Black expand ON
Tone Normal
USE
R
MEN
U
Noise reduction Low
Volume 30
Sound type Automatic
Virtual Surrond OFF
Auto Volume OFF
Sound effect OFF
FACTTORY-KEY OFF
FACT
TOR
Y
MEN
POWER ON OFF
Flesh Tone ON
Adaptive Luma
Control.
U
ON
7ˊAnalog board software update
Solution 1˖
Prepare MTKTOOL UPDATE, update board, serial line.
(1)ǃConnect PC, update board, and J3 on the main board with serial line
(2)ǃProvide the STB +5V for main board
(3)ǃOpen “MtkTool.exe” in MTK TOOL program, and set the parameter as
below picture
(4)ǃPress “Browse” for selecting the SW.
(5)ǃPress “Upgrade” to download the SW. It will be OK when it show “100%”
(6)ǃAfter downloading SW, it will be long time for Initializing EEPROM.
Solution 2˖
Preparative is same with above.
Set SYSTEM->FactoryKey on factory MENU to OFF. Connect the device
as below picture.
Update the SW follow solution1- (3), (4), (5), (6)
Page 19
4.IC Brief Instruction
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
1. Features description
MT8206
format up to HDTV. It includes 3D comb filter TV decoder to retrieve the best image from
popular composite signals. Embedded HDTV/VGA decoders enable the high quality video
reproduction. 24/16/8 bits digital port may accept all kinds of external digital input video source.
New 3
video into progressive non-flicking video. 2D Graphic engine generates high quality UI
interface. Advanced full function color processing with fully 10-bit path provides high quality
video contents. Independent two Flexible scalars provide wide adoption to various LCD panels
for two of different video sources at the same time. Its on-chip audio processor decodes
analog signals from tuner with lip sync control, delivering high quality post-processed sound
effect to customers. On-chip microprocessor reduces the system BOM and shortens the
schedule of UI design by high level C program. MT8206 is a cost-effective and high
performance HDTV-ready solution to LCD TV product.
is a highly integrated single chip for LCD TV supporting video input and output
rd
generation advanced motion adaptive de-interlacer converts accordingly the interlace
FEATURE List
Analog front end
1 set of high resolution ADC with corresponding PGAs adopting to 0.5V~2V input dedicated for TV/AV/SV input signals
3 high speed ADCs dedicated for VGA/HDTV input signals up to 160MHz
All 8-bit programmable gain pre-amplifiers
Embedded Schmitt trigger and deglitch circuits on Hsync/Vsync/SOG/SOY inputs
Video Input
Embedded input Multiplexers without external switch including
10 for TV/AV/S-video input pins available for any possible combination
3 sets for VGA/Component/Scart/D-connector with differential input pairs
1 24/16/8 bit digital port for ITU601/656/RGB video format
1 additional 8 bit digital port for ITU656 video format
All the input sources can be flexibly routed to Main/PIP internally
Sync Processor
Two enhance sync processors for all timing detection supporting Macrovision detection
Enhanced measuring mechanism for VGA auto adjustment
Decoder
TVD
Single 3
Automatic TV standard detection supporting NTSC, NTSC-4.43, PAL (B, G, D, H, M, N, I, Nc), PAL (Nc), PAL, SECAM
Enhanced 3
rd
generation TV decoder
rd
generation NTSC/PAL Motion Adaptive 3D comb filter
June, 2006
Page 20
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Supporting HDTV 480i/480p/576i/576p/720p/1080i input
Smart detection on Scart function for European region
Smart detection on D-connector for Japan region
Supporting SCART RGB inputs mixed with composite signal by adjustable horizontal delay
VGA
Supporting various VGA input timings up to SXGA (1280x1024@75Hz).
Supporting Separate/Composite/SOG sync types
Digital port
1 digital port supporting DVI 24-bit RGB or CCIR-656/601 digital video input format
1 additional 8 bit digital port for ITU656 video format
VBI
Dual VBI decoders for the application of V-Chip/Closed-Caption/XDS/ Teletext/WSS/VPS
Supporting external VBI decoder by YPbPr input
VBI decoder up to 1000 pages Teletext.
Video Processor
Noise Reduction
All Video input source with motion adaptive 3D noise reduction
Color Management
Fully 10-bit processing to enhance the video quality
Advanced flesh tone and multiple-color enhancement. (For skin, sky, and grass…)
Gamma/anti-Gamma correction
Advanced Color Transient Improvement (CTI)
Saturation/hue adjustment
Contrast/Brightness/Sharpness Management
Sharpness and DLTI/DCTI
Brightness and contrast adjustment
Black level extender
Adaptive Luma/Chroma management
Automatic detect film or video source
3:2/2:2 pull down source detection
Main/PIP 2 independent de-interlacing processor
Scaling
rd
3
generation high resolution arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X
Advanced linear and non-linear Panorama scaling.
Picture-in-Picture (PIP)
Picture-Out-Picture (POP)
Display
Advanced dithering processing for LCD display with 6/8/10 bit output
10bit gamma correction
Supporting alpha blending for Video and two OSD planes
Frame rate conversion
Seamless performance comparing demonstration function
MT8206
June, 2006
Page 21
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Support Left/Right video processing comparing function without additional resources (DRAM…) for customers’
demonstration
All the video functions (De-interlace/3D comb/NR/Flesh tone/CTI) can be included
Video Output
Programmable output timing for 1080p panel.
Dual-channel 6/8-bit LVDS, single channel 6/8/10-bit LVDS
Supporting video output mirror and upside down
1 CVBS bypass output of CVBS/S-video(mixed) input
Audio Features
Supporting BTSC/EIAJ/A2/NICAM decode
Stereo demodulation, SAP demodulation
Mode selection (Main/SAP/Stereo)
Equalizer
Sub-woofer/Bass enhancement
MTK proprietary 3D surround processing (Virtual surround)
Audio and video lip synchronization
Supporting Reverberation
MT8206
Audio Input/Output
Decode audio AF from Tuner
1 set of audio L/R digital line in (MT8206 is Master)
7.1-channel slave digital line in
Supporting total 12-channels including full 7.1-channels digital output, 2- channel bypass and 2-channel headphone
output.
Embedded 3 internal audio DACs
Supporting 1 Tuner audio decoder and 1 digital input and both output for SCART1/2 output application
2D-Graphic/OSD processor
Embedded two backend RGB domain OSD planes and one YUV domain OSD plane. To support Main/PIP
Teletext/Close-caption functions together with setup menu
Supporting alpha blending among these two planes and video
Supporting Text/Bitmap decoder
Supporting line/rectangle/gradient fill
Supporting bitblt
Supporting color Key function
Supporting Clip Mask
65535/256/16/4/2-color bitmap format OSD,
Automatic vertical scrolling of OSD image
Supporting OSD mirror and upside down
Host Micro controller
Turbo 8032 micro controller
Built-in internal 373 and 8-bit programmable lower address port
2048-bytes on-chip RAM
June, 2006
Page 22
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Up to 4M bytes FLASH-programming interface
Supporting 5/3.3-Volt. FLASH interface
Supporting power-down mode
Supporting additional serial interface
IR control serial input
Supporting 2 RS232 interface for external source communication
Supporting single interface directly supporting SD/MS/MMC memory card
Supporting 2 PWM output
Programmable GPIO setting for complex external device control
DRAM Controller
Supporting up to 32M-byte SDR/DDR DRAM
Supporting 2x16 bit SDR/DDR bus interfaces
Build in a DRAM interface programmable clock to optimize the DRAM performance
Programmable DRAM access cycle and refresh cycle timings
Supporting 3.3/2.5-Volt SDR/DDR Interface
DRAM Usage
For features of 8206, Dual 8Mx16 DDR are used.
It is recommended to use dual 8Mx16 DDR (32MB) for following basic features.
MT8206
Function Full Screen PIP/POP
3D-Comb Y
MDDi Up to 1080i MDDi
Scale mode Normal/Full Normal/Full
VGA timing Up to
1280x1024@75Hz
Panel 1080P
z For PIP/POP mode, 1280x1024 should be under 60Hz.
z Case lists are evaluated when Dram clock = 169 MHz,DDRx2.
Flash Usage
Flash is used to store FW code, fonts, bitmaps, big tables for VGA, Video, Gamma..
In our demo system, we can support 2-4 languages within 1MB flash.
For single country, we need around 20KB to store font data.
For more bitmaps, we need more flash space to store them.
When POP mode, Main=AV, Sub=1080I, only one of HD MDDi and Comb
can be enable.
(for POP)Case i: Main=AV(with 3D Comb), Sub=1080i(Bob mode)
(for POP)Case ii: Main=1080i(Bob mode), Sub=AV(with 3D Comb)
(for POP)Case iii: Main=AV(without 3D Comb), Sub=1080i(HD MDDi)
(for POP)Case iv: Main=1080i(HD MDDi), Sub= AV(without 3D Comb)
When PIP mode, there is no constraint in 3D-Comb and MDDi.
Up to 1280x1024x60Hz
2Mbytes is recommended to build a general TV model.
Outline
June, 2006
Page 23
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
3. BLOCK DIAGRAM
CVBS / SV
(x8)
(Customer)
External
YPbPr
(x2)
Switches
VGA
Digital
Control Signal (GPIO, …)
LVDS
DAC
Analog Front End
ADC
ADC
3D TVD
HDTVD
ADC
VGAD
ADC
Digital Path
LVDS Tx
Gamma
Dithering
Merge
MUX
8032
Main Path
MDDi
PIP Path
MDDi
OSD
Color
Color
DSP
DS
DRAM
DS
US
US
June, 2006
Page 25
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
4. MT8206 PIN DESCRIPTION
4.1GENERAL PIN LIST:
Item Symbol Pin # TypeDescription
DIGITAL
Power/Ground (41)
1 DVDD33A D5, H4 I 3.3V power (necessary when power saving)
2 DVDD33 AA4, AC17, AC20 I 3.3V power for all the 3.3V I/O pins
2 DVSS33 L11, N12, R15, T16 I 3.3V ground
3 DVDD25 AC5, AC6, AC7, AD5, AD6, I 2.5V power for DDR (for 16/32 bit DDR)
DVDD25OPT AC14, AC15, AD15 I 2.5V power for DDR (for 32 bit DDR), 3.3V power for GPIO
DVSS25 N11, P11, R11, T11, R13,
T13, T14
5 DVDD18A K3, K4 I 1.8 V power (necessary when power saving)
DVDD18 U3, U4, AC8, AC9, AC22,
AC23
6 DVSS18 L12, M11, M12, P12, R12,
R14, R16, T12, T15
I 2.5V ground for DDR (for 16/32 bit DDR)
I 1.8 V power for internal digital part
I 1.8 V ground
RS232 (2)
1 RXD M3 I RS232 received data, 2mA
2 TXD M4 O RS232 transmitted data, 2mA
Serial interface (6)
1 SCL AA2 O
2 SDA AA1 I/O
3 SCL0 U23 I/O
4 SDA0 V23 I/O
5 SCL1 AB24 I/O
6 SDA1 AB23 I/O
Digital Audio Interface (8)
1) GPIO, 2mA
2) Clock of master serial interface, 2mA
1) GPIO, 2mA
2) Data of master serial interface, 2mA
1) Clock of slave0 serial interface, 2mA
2) GPIO
3) RS232 RXD
1) Data of slave0 serial interface, 2mA
2) GPIO
3) RS232 TXD
1) Clock of slave1 serial interface, 2mA
2) GPIO
1) Data of slave1 serial interface, 2mA
2) GPIO
1 AOMCLK M1 O Audio out master clock, 2~16mA, SR(optional), SMT
2 AOLRCK N3 O Audio out left-right clock, 4mA, SR, SMT
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Item Symbol Pin # TypeDescription
3 AOBCK N1 O Audio out bit clock, 2~16mA, SR(optional), PD(optional), SMT
MT8206
4 AOSDATA0 P1 O
5 AOSDATA1 P2 O
6 AOSDATA2 P3 O
7 AOSDATA3 P4 O
8 LIN N4 I Audio line in
Microcontroller and Flash Interface (38)
1 HIGHA0 G2 I/O
2 HIGHA1 F3 I/O
3 HIGHA2 F4 I/O
4 HIGHA3 E1 I/O
5 HIGHA4 E2 I/O
6 HIGHA5 E3 I/O
7 HIGHA6 E4 I/O
8 HIGHA7 D1 I/O
9 AD7 C4 I/O
10 AD6 B1 I/O
11 AD5 B2 I/O
12 AD4 A2 I/O
13 AD3 B3 I/O
14 AD2 A3 I/O
15 AD1 B4 I/O
1) GPIO (default, input in initial state)
2) Audio out data line 0, 4mA, SR, PD(optional), SMT
1) GPIO (default, input in initial state)
2) Audio out data line 1, 4mA, SR, PD(optional), SMT
1) GPIO (default, input in initial state)
2) Audio out data line 2, 4mA, SR, PD(optional), SMT
1) GPIO (default, input in initial state)
2) Audio out data line 3, 4mA, SR, PD(optional), SMT
Microcontroller address 8, 2~16 mA, PU, works in stand-by
mode
Microcontroller address 9, 2~16 mA, PU, works in stand-by
mode
Microcontroller address 10, 2~16 mA, PU, works in stand-by
mode
Microcontroller address 11, 2~16 mA, PU, works in stand-by
mode
Microcontroller address 12, 2~16 mA, PU, works in stand-by
mode
Microcontroller address 13, 2~16 mA, PU, works in stand-by
mode
Microcontroller address 14, 2~16 mA, PU, works in stand-by
mode
Microcontroller address 15, 2~16 mA, PU, works in stand-by
mode
Microcontroller address/data 7, 2~16 mA, SR, works in
stand-by mode
Microcontroller address/data 6, 2~16 mA, SR, works in
stand-by mode
Microcontroller address/data 5, 2~16 mA, SR, works in
stand-by mode
Microcontroller address/data 4, 2~16 mA, SR, works in
stand-by mode
Microcontroller address/data 3, 2~16 mA, SR, works in
stand-by mode
Microcontroller address/data 2, 2~16 mA, SR, works in
stand-by mode
Microcontroller address/data 1, 2~16 mA, SR, works in
stand-by mode
16 AD0 A4 I/O
17 IOA0 C2 I/O
18 IOA1 C1 I/O
June, 2006
Microcontroller address/data 0, 2~16 mA, SR, works in
stand-by mode
Microcontroller address 0 / IO, 2mA, SR, PU, works in
stand-by mode
Microcontroller address 1 / IO, 2mA, SR, PU, works in
stand-by mode
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Æ
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Item Symbol Pin # TypeDescription
19 IOA2 D4 I/O
20 IOA3 D3 I/O
21 IOA4 G1 I/O
22 IOA5 H3 I/O
23 IOA6 H2 I/O
24 IOA7 H1 I/O
25 A16 D2 I/O
26 A17 C3 I/O
27 IOA18 G3 I/O
28 IOA19 G4 I/O
29 IOA20 F2 I/O
30 IOA21 F1 I/O
31 IOALE J1 I/O
32 IOOE# B5 I/O
33 IOWR# J2 I/O
34 IOCS# A5 I/O
35 UWR# K1 I/O
36 URD# K2 I/O
37 UP3_4 L3 I/O
38 INT0# L1 I/O
DIGITAL MISC (5)
1 PRST_ L2 I
Microcontroller address 2 / IO, 2mA, SR, PU, works in
stand-by mode
Microcontroller address 3 / IO, 2mA, SR, PU, works in
stand-by mode
Microcontroller address 4 / IO, 2mA, SR, PU, works in
stand-by mode
Microcontroller address 5 / IO, 2mA, SR, PU, works in
stand-by mode
Microcontroller address 6 / IO, 2mA, SR, PU, works in
stand-by mode
Microcontroller address 7 / IO, 2mA, SR, PU, works in
stand-by mode
6 AVDD_VFE0 J23 power 3.3v CVBS video front end power
7 AV3 E26 I
8 AV2 E25 I
9 AV1 D25 I
10 AV0 D26 I
11 AVSS_VAD0 G23 GND CVBE ADC ground
12 REFP F24 I/O
13 REFN G24 I/O
14 AVDD_VAD0 F23 power 3.3v CVBS ADC power
AV6 input (input range: 0.5V~1.5V)
AV4 input (input range: 0.5V~1.5V)
AV 3 input (input range: 0.5V~1.5V)
AV 2 input (input range: 0.5V~1.5V)
AV 1 input (input range: 0.5V~1.5V)
AV0 input (input range: 0.5V~1.5V)
Positive CVBS ADC Voltage Reference
The function changed to SY2
Negative CVBS ADC Voltage Reference
The function changed to SC2
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Item Symbol Pin # TypeDescription
Audio FE (6)
1 AADCVDD E24 Power 3.3v Audio front end power
2 MPX1 B26 I Audio Frequency input0
3 MPX2 C26 I Audio Frequency input1
4 AADCVSS D24 GND Audio front end ground
5 TN2 C25 I/Onegative Audio ADC reference pin
MT8206
6 TP2 B25 I/O
1 ADACVDD C24 Power 3.3v Audio front end power
2 ACENT B24 I/O
3 AVICM A24 Audio DAC input common voltage
4 AL A25 I/O
5 AR A26 I/O
6 ADACVSS D23 GND Video ADC Voltage Reference N0
1) positive Audio ADC reference pin
2) bypass CVBS video output pin
Audio DAC (6)
1) Audio DAC output
2) I2S , ASDATA2
3) GPIO
1) Audio DAC output
2) I2S , ASDATA0
3) GPIO
1) Audio DAC output
2) I2S , ASDATA1
3) GPIO
4.2 NOTICES ABOUT GPIOS:
There are considerably various I/O pins provided by MT8206EG, but some of them are shared by
other function, here we notice some conditions when you use.
When GPIO have to active in power saving mode
1. GPIOs in Stand by mode means UP30, UP31, UP34 and UP35 can be used.
2. Servo ADs can be also used when power saving mode
3. GPIOs which are sharing with servo AD can be also used when power saving mode.
GPIO use DE pin
DE pin is also use for trapping when VGA download have to use. So DE pin should be used carefully.
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MT8206
When you use DE as GPIO, it is highly recommended that DE can not pull high.
BLOCK DIAGRAM
4.3
(see Next Page)
June, 2006
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MT8206
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
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June, 2006
Page 42
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
5. Video Configuration
CVBS/SV Input Switch, S-first Function
We have 8 CVBS/SV input pins for arbitrary order of customers’ demand. Because there is only 1 TV decoder in MT8206G,
there is only one set (CVBS or SV) through the input pins. However, we can support S-first function without any external
circuits.
CVBS Bypass Output
The pin “TP2 “ can only output the CVBS signal of the chosen input but SV input.
INTERNAL VIDEO SWITCH
Main Path
CVBS / S video (Total
Source
CVBS / S video
(Total 8 input pins)
PIP
path
z Above table is the PIP/POP table if we do not use any extern input switch.
z If video goes through DVI port, then PIP/POP case will not be limited to AD numbers.
Digital Input Pin Swap Selection
YPbPr
RGB
Digital port (DVI /
HDMI / CCIR656 /
CCIR601)
8 input pins)
YPbPr RGB
X
For layout conveniently, 8206 can flexibly swap input pin:
1. If VI0~VI23 configure as 24-bits R/G/B or CB/Y/CR mode -->
8206 can do B/R or CB/CR bus swap or MSB/LSB swap.
Digital port (DVI / HDMI
/ CCIR 656 / CCIR601)
X
2. If VI8~VI23 configure as 16-bits CBCR/Y mode -->
8206 can do B/R or CB/CR bus swap or MSB/LSB swap
3. If VI16~VI23 or VI8~VI15 configure as 8-bits mode -->
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
8206 can do VI16~VI23/VI16~VI23 two bus swap or MSB/LSB swap.
4. We have second port dedicated for 8-bit ITU656 digital video format.
Clock Spread Spectrum
1. Up-down 2 directions spread spectrum
2. SS frequency: 10Hz~100Hz
3. SS percentage: 0%~5%, 8 bits resolution.
4. Output clock and DRAM clock all available.
6. Audio Configuration
Digital Audio Input Pin Configuration
* Note that there are different input pin configurations for MT8206G on master and slave clock modes.
Master Mode
Description
Data input LIN HDMISD0
Master clock AOMCLK HDMIMCLK
L/R clock AOLRCK HDMILRLK
Bit clock AOBCK HDMIBCLK
Extension Data input 1 HDMISD1 HDMISD1
Extension Data input 2 HDMISD2 HDMISD2
Extension Data input 3 HDMISD3 HDMISD3
Digital Audio Output Mapping Rule
Item Symbol Pin # IO Description: Output Type
1 AOSDATA0 O Audio out data 0: Speaker / AV_LR / Bypass Out
(MT8206G is Master clock
mode)
(MT8206G is Slave clock mode)
Slave Mode
2 AOSDATA1 O Audio out data 1: Speaker / AV_LR / Headphone
3 AOSDATA2 O Audio out data 2: Center(L) / Subwoofer(R)
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Item Symbol Pin # IO Description: Output Type
4 AOSDATA3 O Audio out data 3: Speaker / AV_LR / Bypass Out / 5.1ch_LS_RS
5 AOSDATA4 I/O Audio out data 4: 7.1ch_LC_RC
6 AOSDATA5 I/O Audio out data 5: Headphone / Bypass Out
MT8206
Analog Audio Output Mapping Rule
Item Symbol Pin # IO Description: Output Type
1 AL O Left of AOSDATA0
2 AR O Right of AOSDATA0
3 CENT O Left or Right of AOSDATA2
7. Power Saving Mode
Only DVDD33A, DVDD18A, XTALVDD, and PLLVDD1/2/3 power supplied. At this mode, there are 7
GPIO pins(UP3_0, UP3_1, UP3_4, UP3_5, GPIO19, IOA20, IOA21), IR, microprocessor and 5
Servo ADC pins (also can be GPIO) working normally. The MT8206G only need 16mA at this mode,
and whole system is approximate 0.8W according to internal measurement.
If you want to support power saving mode,please also remomber to use proper GPIOs which can be
active when powe saving mode.(Please see 4.2 NOTICES about GPIOs)
p.s.System is based on PCB m1v2 + mt8206B E2 IC and Ver1845 F/W,different system may result in a bit viriation in power
comsuption
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
DDR / SDR Interface
The DDR / SDR interface of MT8206G can support varied kinds of DRAM. The ROW bit number is no more than 12; the
column number is 8, 9, or 10bit; and the bank bit is 1/2 bits (2 or 4 banks).
The following is the DRAM support list:
SizeDRAMFW/PCB
128MX2 DDR 8MX16X2Support
128MDDR 8MX16X1Support
128M
128MX2
128M
128M
64MX2
64M
64M
16MX2
16M
DDR 4MX32X1Support but not ready
SDR 8MX16X2Support
SDR 8MX16X1Support
SDR 4MX32X1Support but not ready
SDR 4MX16X2Support
SDR 4MX16X1Support
SDR 2MX32X1Support but not ready
SDR 1MX16X2Support
SDR 1MX16X1 Support
The compatible DRAM types are –5 or –6, and the maximum speed is 175MHz (for ESMT –5 and MOSEL –5).
9. Layout Guide
9.1 PCB LAY E R
Board Stack up
Outer Layer 0.5 oz
P.P
FR 4
Inner Layer 1.0 oz
Fig. 1-1PCB Stackup – 4 Layers
The outer layers of the PCB were designated to the mainly signal routings by default, and
normally were chosen to have the 0.5 oz Cu foil with plated 0.5 oz copper, and the inner layers
was designated to be 1.0 oz at the PCB manufacturing step.
H
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MT8206
Refer to the Fig. 1-1 above. The dielectrics between conductors were as the isolators,
which were used to separate the conductors. By the microstrip line architecture of system
memory signals, the target impedance was desired to have 55 +/- 10%. Please refer to the
table 1 below for your PCB design and recommendation. The default design was 6-mil trace
width with 4.5 mil high dielectrics.
Table 1-1. 4 Layer PCB Stack up Configurations
PCB Parameter
H (mil)
Target Impedance (
)
Tolerance
Trace Width
(mil)
5 4 55 10 %
6 4.5
8 7 55 10 %
55 10 %
9.2 DDR/SDR DRAM LAY O U T GUIDE
System DDR Memory Solution Space
Refer to the diagrams below to the topologies of the DDR signals, and the actual
dimension specifications were listed of the tables.
¾DDR Signal Topology – 1
V
TT
Rt
Rs
C
AB
Fig. 1-2 Signal Topology -1
Table 1-2. Signal Topology –1
June, 2006
DDR
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Signal DQ DQS
MT8206
Trace (mil)
A
B
C
Trace Length (inch)
A+B
Rs ( )
Rt ( )
Width6 6
Spacing
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
2*W or Above 2*W or Above
0.2 0.2
2 2
0.2 0.2
1.2 1.2
0.1 0.1
0.5 0.5
0.4 0.4
3 3
47 47
75 75
Note
1. Keep the difference of the trace length of the same data signal groups within about
200 mils as possible.
2. Keep the difference of the data signal groups within 500 mils as possible (The
longest signal trace to the shortest signal trace).
3. Placing the damping resistor close to the controller IC
4. Placing the termination resistor close to the memory as possible.
5. Put an integrated plane as the return path to the signals beneath the data signals.
6. When the signal needs to change layers and the reference paths beneath the
signal are not continued. Placing the bypass capacitors nearing to the vias where
are the points to change layers and connecting the capacitors to the different
reference paths.
¾DDR Signal Topology – 2
V
TT
Rt
C
D
DDR
MT8202
Rs
AB
E
Fig. 1-3 Signal Topology -2
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Table 1-3. Signal Topology –2
CAS# RAS# WE#
Signal DQM RA / BA
CS#
MT8206
Trace (mil)
B
C
D E
Trace Length (inch)
A+B+D(o
r E)
A
Rs ( )
Rt ( )
Width
Spacing
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
6 6 6
2*W or Above 2*W or Above 2*W or Above
0.2 0.2 0.2
1 1.2 1.2
0.2 0.2 0.2
1 1 1
0.1 0.1 0.1
0.5 0.5 0.5
0.2 0.2 0.2
1.4 1.2 1.2
0.6 0.6 0.6
2.8 3.2 3.2
22 22 22
75 75 75
Note
1. Keep the difference of the branches’ length DE of the dual loads signal within 100
mils.
2. Put the termination resistor close to the crossing point of the branches.
3. Reversing more spacing to the periodic signal as clock if signal was critical and there
weren’t the guard traces.
4. Put an integrated plane as the return path to the signals beneath the address
command signals.
5. When the signal need to change layers, and the reference paths beneath the signal
are not continued, placing the bypass capacitors nearing to the vias where are the
points to change layers and connecting the capacitors to the different reference
paths.
6.If the DQM Signal used as the dual load topology shown above of Fig. 1-3. Treating
the DQM signal topology as the table 1-3 of signal topology – 2.
¾DDR Signal Topology – 3
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
C
Rs
AB
DDRMT8202
D
Fig. 1-4 Signal Topology -3
Table 1-4. Signal Topology –3
CLK#
Signal
CLK
CKE
Trace (mil)
Trace Length (inch)
A
B
C D
A+B+C(or D)
Rs ( )
Width
Spacing
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
6 6
20 2*W or Above
0.2 0.2
1.2 1.2
0.2 0.2
1 1
0.2 0.2
1.2 1.2
0.6 0.6
2.6 3.2
22 22
Note
1. The length difference of the CD shall be within 200mils.
2. The trace length difference of CLKCLK# shall be as short as possible.
3. Keep the trace difference between CLK pair to DQS signals as small as possible.
4. Keep the trace difference between CLK pair to RA / Command signals as small as
possible.
System SDR Memory Solution Space
Refer to the diagrams below to the topologies of the SDR signals, and the actual
dimension specifications were listed of the tables. By the experiments, the target impedance of
the SDR signal was designed to be 55 +- 10, and which was same as the DDR signals
illustrated above. Refer to the Fig. 1-1 and table. 1-1 for the board stackup.
¾SDR Signal Topology
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
Rs
Top. 1
Top. 2
MT8202
Table 1-5. Signal Topology – SDR
DQ CLK DQM RA/Command
Signal
A
Trace
B
Length
C
(Inch)
D
Rs ( )
Top. 1 Top. 2 Top. 2 Top. 2
Min. Max. Min. Max. Min. Max. Min. Max.
0.2 1.3 0.2 1 0.2 1.6 0.2 1
0.2 2.4 0.2 1 0.2 1 0.2 1
0.2 1.6 0.2 1.6 0.2 1.6
0.2 1.6 0.2 1.6 0.2 1.6
47 22 22 22
AB
Rs
C
AB
D
System Memory
(SDR)
Fig. 1-4 Signal Topologies
A+B+C (D)
0.4 2.7 1.2 3.2 1 3.2 0.6 3
Note
1. Keep the length of the branches as the same length (C = D), or within 0.2 inches as
possible.
2. Keep the maximum difference of the signal length within 300mil of the same group to meet
the minimum timing skew requirement.
3. It was suggested to keep the spacing between the nearby signals above 2 times of the
trace width as possible.
9.3. LVDS SIGNAL PCB LAYO U T GUIDELINE
For the other applications of the high-speed signal PCB design, below illustrated the
topologies and constraints of the LVDS or other differential signals that were achieved to the
electrical requirements. Also refer to the form to the detail recommendations.
Multi-Layer PCB Design
By the default multi-layers PCB architecture, the inner layers were assigned to be the
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
reference plane to the signals. For the signal integrity issues, the integrate plane would held to
hold a good signal qualities when signal were proceeding on the signal traces. Refer to the Fig.
2-1 Fig. 2-2 below shown the stack up and the topology of the differential signals of the
4-layer PCB where the signals were routed of the outer layers.
¾Signals without Guard Traces
Fig. 2-1 LVDS Signal Topology – 4 Layers
Table 2-1.
Variable Nominal (mil) Tolerance Min. (mil) Max. (mil)
Trace High (H)
Trace Width (W)
Spacing (S)
Single Ended Trace
Impedance
Differential Trace
Impedance
Reference Plane
4.5 (2116)
5+ / - 1 mil 4 6
8 (mil) + / - 1 mil 9 7
5661.6 52.6
98109 89.9
Ground Ground Ground Ground
¾Signals with Guard Traces
The other application was used the coplanar ground copper and surrounded the signals to achieve the noise shielding
purpose. Fig. 2-2 below shows the signal topology.
Fig. 2-2 Differential Signal with Guard Trace
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Table 2-2.
Variable Nominal (mil) Tolerance Min. (mil) Max. (mil)
MT8206
Trace High (H)
Trace Width (W)
Spacing (S)
Spacing to GND(Sg)
Single Ended Trace
Impedance
Differential Trace
Impedance
Reference Plane
Note:
¾ Keeping the spacing to the other signals as far as possible.
¾ Keeping the spacing to different ground planes (Sp) more than 30 mils as possible as the Fig. 2-3.
4.5 (2116)
5+ / - 1 mil 4 6
8 (mil) + / - 1 mil 9 7
8 (mil) + / - 1 mil 9 7
5560 50.5
97107 87
Ground Ground Ground Ground
Fig. 2-3 Cross-Section of Plane Designated
June, 2006
Page 54
g
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
10. IC AC/DC Specification and Timing Chart
10.1 RESET T IMING C HART AND POWER SEQUENCE
The Reset pin works is active low mode, and we have to keep the reset rising edge after crystal oscillating stable at least 5
clocks.
3.3V
1.8V
Crystal clock
Unstable
Reset
5 clocks
stable
Low
SB33A
ASB18A
Hi
h
June, 2006
Page 55
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
REQUIRED POWER ON SEQUENCE-1
The following chart shows Power-On sequence of 82-series IC’s. Both 5VSB and DV18A must be supplied when chip is
powered on. DV18A could not be off since booted-up and only turned off by firmware after initialization done. The minimum
duration to keep DV18A alive depends on how firmware initiates chip.
REQUIRED POWER ON SEQUENCE-2
MT8206
Standby power (SB18V)
Digital main power (DV18A)
Td
Chip reset signal (RESET)
>300ms
Note 1 : Td < 20ms, this will dependent on LDO type and C value on DV18A
Note 2 : this timing is safe to power
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
10.2
DC CHARACTERISTICS MEASUREMENT VALUE
Absolute Maximum Ratings
SYMBOL PARAMETER RATING UNITS
VDD18 1.8V Power Supply
VDD2 2.5V Power Supply
VDD3 3.3V Power Supply
VIN3 Input Voltage of 3.3V I/O with 5V Tolerance
VOUT3 Output Voltage
Ta Ambient Temperature
-0.3~2.0
-0.3~2.75
-0.3~3.6
-0.3~5.25 V
-0.3 ~ VDD3+0.3 V
0 to 70
Test Conditions
SYMBOL PARAMETER #1 #2 #3 #4 #5 UNITS
VDD18
VDD2
VDD3
VIN3
Topr
1.8V Power Supply
2.5V Power Supply
3.3V Power Supply
Input Voltage of 3.3V
I/O with 5V Tolerance
Operation
Temperature
1.6~2.0 1.6~2.0 1.6~2.0 1.6~2.0 1.6~2.0
2.25~2.752.25~2.752.25~2.752.25~2.752.25~2.75
3.0~3.6 3.0~3.6 3.0~3.6 3.0~3.6 3.0~3.6
0~5.25 0~5.25 0~5.25 0~5.25 0~5.25
25 25 25 25 25 °C
V
V
V
°C
V
V
V
V
General DC Characteristic (Not for DDR Pins)
SYMBOL PARAMETER CONDITIONS#1 #2 #3 #4 #5 UNITS
IIL Input low current
IIH Input high current
IOZ
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
Tri-state leakage
current
No pull-up or
down
No pull-up or
down
| = 2mA0.25 0.26 0.24 0.25 0.26 V
|I
OL
| = 2mA3.12 3.13 3.13 3.14 3.11 V
|I
OH
d500d500d500d500d500
d500d500d500d500d500
d1d1d1d1d1
1.12 1.14 1.14 1.15 1.16 V
1.68 1.69 1.76 1.76 1.74 V
DC characteristics for DDR Pins
SYMBOL PARAMETER CONDITIONS#1 #2 #3 #4 #5 UNITS
VIL Input Lower Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
|I
|I
| = 2mA
OL
| = 2mA2.21 2.19 2.18 2.23 2.21 V
OH
1.13 1.12 1.12 1.12 1.13
1.30 1.30 1.30 1.30 1.31
0.24 0.26 0.28 0.24 0.24
nA
nA
uA
V
V
V
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
10.3 ADC CHARACTERISTICS
TV high resolution Video ADC Characteristics
Symbol Parameter Conditions MinTypMax Units
VIDEO ADC CHARACTERISTICS
ENOB Effective number of bits 8.58.8Bits
SNR Signal to noise ratio 5255dB
DNL Differential nonlinearity 0.70.8 LSB
INL Integral nonlinearity
VIN Input voltage range 2 Vpp
VCM Input common mode voltage 1.5V
Conversion Rate 54MHz
2.02.5 LSB
HDTV high frequency Video ADC Characteristics
Symbol Parameter Conditions MinTypMax Units
VIDEO ADC CHARACTERISTICS
ENOB Effective number of bits 6.46.6Bits
SNR Signal to noise ratio 4245dB
DNL Differential nonlinearity 0.60.8 LSB
INL Integral nonlinearity
VIN Input voltage range 1 Vpp
VCM Input common mode voltage 0.75V
Conversion Rate 208MHz
1.01.3 LSB
Audio ADC Characteristics
Symbol Parameter Conditions MinTypMax Units
AUDIO ADC CHARACTERISTICS
ENOB Effective number of bits
SNR Signal to noise ratio
Conversion Rate 27MHz
DNL Differential nonlinearity
INL Integral nonlinearity
VIN Input voltage range
June, 2006
8.58.8
5255
0.70.8
2.02.5
2
Bits
dB
LSB
LSB
Vpp
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
VCM Input common mode voltage
10.4 LVDS Electrical Specifications
Symbol Parameter Conditions MinTypMax Units
LVD S DRIVER DC CHARACTERISTICS
Vod Differential Output Voltage 200350400 mV
vod
Vos Output Common Mode Voltage 1.241.251.27 V
Vos
Ios Output Short Circuit Current
Ioz Output TRI-STATE Current PD=1,Vout=0V or Vcc 3 uA
LVD S DRIVER AC CHARACTERISTICS
Change in Vod between
Complimentary Output States
Change in Vos between
Complimentary Output States
RL=100
Vout=0V, RL=100
1.5
25 mV
50mV
3 4 mA
V
Tpix Pixel Clock Rate in Period 9.274.07 ns
TpixH Tpix in High Time T-0.6T T+0.6 ns
TpixL Tpix in Low Time T-0.6T T+0.6 ns
DOrt Data Output Rise Time 500600 ps
DOft Data Output Fall Time 500600 ps
FDO Output Data Rate
RL=100
92.5 756 MHz
10.5 AUDIO DAC CHARACTERISTICS
Symbol Parameter MinTyp Max Units
Supplies
ADACVDDAudio DAC power supply voltage 3.0 3.3 3.6 V
ADACGND Audio DAC Ground 0 V
I
Audio DAC power supply current (stereo) 4.5 9 12 mA
ADACVDD
VCM Audio DAC common mode reference 1.5 1.65 1.8 V
General
Fs Sampling Frequency 32 48 192 kHz
OSR Oversampling Ratio 32 64 128
Interpolation filter characteristics for normal sped mode
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT8206
Pass band ripple, 0 .. 0.4535F
0.03 dB
s
Stop band, >0.5465Fs -62 dB
Dynamic Range, 0 .. 0.4535Fs 108 dB
Stereo DAC
V
Output swing level:
out
0.9 1.0 1.1 V
P
Digital i/p level =0 dBFS , ADACVDD =3.3V
= 1.0 * ADACVDD / 3.3)
(V
out
VCM Common mode output voltage 1/2(ADCVDD-
V
ADACGND)
Ro Output impedance @ 1kHz 50 100
RL_
Minimum resister load 5 k
min
CL_
Maximum capacitor load 20 pF
max
S/(THD+N) S/(THD+N) @ 0 dBFS;
= 1kHz; Fs = 48kHz, A-weighted
f
in
THD+N @ -60 dBFS (THD+N) @ -60 dBFS ;
76 79 dBr(A)
-19 -19.7dBr(A)
fin = 1kHz; Fs = 48kHz, A-weighted
DR Dynamic Range 76 79.3 dBr(A)
SNR Signal to noise ratio; A-weighted 93 95 dBr(A)
Channel Separation Close-talk of Left and Right Channel 85 dB
10.6 CVBS BYPASS CHARACTERISTICS (AV OUT)
Description Min Typ Max Unit
Vout Output swing level 1.9 V
DP Differential phase 2 5
DG Differential gain 2 5 %
o
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
11. Power consumption
MT8206
Mode Current: mA Power
consumption: mW
MT8206 digital power
1
2
SB33A (up)
SB18A (up)
8.78 28.97
6.82 12.27
3 DV33A 6.23 20.56
4 DV18A 523.00 941.40
5 DV25A 16.09 40.30
6 SDV25A 19.18 47.95
MT8206 analog power
1
2
XTALVDD
ADCVDD
1.45 2.61
6.14 20.26
3 LVDD,AB,C 67.74 223.54
4 AADCVDD 51.89 171.23
TOTAL IC
TOTAL IC without DACVDD
5 ADACVDD 13.34 44.02
6 DACVDD(2.0V) 78.96 157.90
7 PLLVDD1,2 25.93 46.67
8 VPLVDD1 2.12 3.81
9 VPLVDD2 3.78 12.47
10 AVDD_VFE0 38.03 125.50
11 AVDD_VAD0 44.11 145.56
12 AVDD_VFE1 29.09 52.36
13 AVDD_VAD1 81.30 146.34
2243.72mW
2085.82mW
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
12. 388 Pin BGA Package Dimension
MT8206
MT8206AG/BD-L FOR MT8206AG/BD (LEAD FREE VERSION)
1. MT8206AG for basic function that uses MTK surround and MTK vocal audio effect.
2. MT8206AAG for embedded SRS WOW surround.
3. MT8206ABG for embedded SRS TruSurround-XT surround.
June, 2006
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PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE