Thomson 30LCD120S4 Schematic

SERVICE MANUAL
DOCUMENTATION TECHNIQUE
TECHNISCHE DOKUMENTATION
DOCUMENTAZIONE TECNICA
DOCUMENTACION TECNICA

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WARNING : Before servicing this chassis please read the safety recommendations.

ATTENTION : Avant toute intervention sur ce châssis, lire les recommandations de sécurité.

ACHTUNG : Vor jedem Eingriff auf diesem Chassis, die Sicherheitsvorschriften lesen.

ATTENZIONE : Prima di intervenire sullo chassis, leggere le norme di sicurezza.

IMPORTANTE : Antes de cualquier intervención, leer las recomendaciones de seguridad.

Code : 358 597 20 - 0305 / 6M - LCD12B - 27”, 30”, 32” Print.

LCD12B

27”, 30”, 32”

TV

Indicates critical safety components, and identical components should be used for replacement. Only then can the

operational safety be garanteed.

Le remplacement des éléments de sécurité (repérés avec le symbole ) par des composants non homologués selon la
Norme CEI 65 entraine la non-conformité de l'appareil. Dans ce cas, la responsabilité du fabricant n'est plus engagée.

Wenn Sicherheitsteile (mit dem Symbol gekennzeichnet) nicht durch Original - Ersatzteile ersetzt werden, erlischt die
Haftung des Herstellers.

La sostituzione dei componenti di sicurezza (evidenziati con il segno ) con componenti non omologati secondo la
norma CEI 65 comporta la non conformitá dell'apparecchio. In tal caso è "esclusa la responsabilità " del costruttore.

La sustitución de elementos de seguridad (marcados con el simbolo ) por componentes no homologados segun la
norma CEI 65, provoca la no conformidad del aparato. En ese caso, el fabricante cesa de ser responsable.

MEASUREMENT CONDITIONS - CONDITIONS DE MESURES - MESSBEDINGUNGEN

CONDIZIONI DI MISURA - CONDICIONES DE MEDIDAS

RICEVITORE :

In UHF, livello d'entrata 1 mV, monoscopio barre :

- PAL, norma G. bianco 100%.
Via SCART, livello d'entrata 1 Vpp, monoscopio barre :
Colore, Contrasto, Luminositá media, Suono minimo.

Programma selezionato PR 01.
Tensioni continue rilevate rispetto alla massa con un voltmetro digitale.

RECEIVER :
On UHF,input level : 1 mV, bar test pattern :

- PAL, I standard, 100% white.
Via the scart socket, input level : 1 Vpp, bar test pattern :
Colour, contrast and brightness at mid-position, sound at minimum.

Programme selected : PR 01.
DC voltages measured between the point and earth using a digital

voltmeter.

EMPFÄNGER :
Bei UHF Eingangspegel 1 mV, Farbbalken :

- PAL, Norm G, Weiss 100%.
Über die Scartbuchse : Eingangspegel 1 Vss, Farbbalken :
Farbe, Kontrast, Helligkeit in der Mitte des Bereichs, Ton auf Minimum.

Zugeordnetes Programm PR 01.
Gleichspannungen mit einem digitalen Voltmeter zur Masse gemessen.

RECEPTEUR :
En UHF, niveau d'entrée 1 mV mire de barres

- SECAM, Norm L, Blanc 100%.
Par la prise Péritélévision, niveau d'entrée 1 Vcc, mire de barres .
Couleur, contraste, lumière à mi-course, son minimum.

Programme affecté PR 01.
Tensions continues relevées par rapport à la masse avec un

voltmètre numérique.

RECEPTOR :
En UHF, nivel de entrada 1 mV, mira de barras :

- PAL, norma G, blanco 100%.
Por la toma Peritelevision, nivel de entrada 1 Vpp mira de barra.
Color, Contraste, luz a mitad de carrera, Sonido minimo.

Programa afectado PR 01.
Tensiones continuas marcadas en relacion a la masa con un voltimetro digital.

MAIN

FRANÇAIS ESPAÑOLDEUTSCHENGLISH ITALIANO

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21

NC

21

17

19

15

13

20

18

16

14
12

11

9

10

8

7

5
3

1

6
4

2

NC

AUDIO "R"

AUDIO "R"

AUDIO "L"

NOTE :

... etc. identifies each

pcb module.

AUDIO "D"

AUDIO "D"

AUDIO "G"

AUDIO

"BLEU"

AUDIO "G" MONO

"BLEU"

COMMUT. LENTE

"VERT"

"VERT"

"ROUGE"

COMMUT. RAPIDE

COMMUT. RAPIDE

VIDEO

VIDEO SYNCHRO

BLINDAGE PRISE

AUDIO "R"

AUDIO "R"

AUDIO "L"

AUDIO

"BLAU"

AUDIO "L" MONO

"BLAU"

AV

UMSCHALTUNG

"GRÜN"

"GRÜN"

"ROT"

AUSTASTUNG

AUSTASTUNG

VIDEO

VIDEO ODER

SYNCHRO

ABSCHIRMUNG
DES STECKERS

AUDIO "D"

AUDIO "D"

AUDIO "I"

AUDIO

"AZUL"

AUDIO "I" MONO

AZUL

"CONMUTACION

LENTA"

"VERDE"

"VERDE"

"ROJA"

"CONMUTACION

RAPIDA"

"CONMUTACION

RAPIDA"

VIDEO

VIDEO O SINCRO

BLINDAJE

DEL ENCHUFE

AUDIO "D"

AUDIO "D"

AUDIO "S"

AUDIO

"BLU"

AUDIO "S" MONO

BLU

"COMMUTAZIONE

LENTA"

"VERDE"

"VERDE"

"ROSSO"

"COMMUTAZIONE

RAPIDA"

"COMMUTAZIONE

RAPIDA"

VIDEO

VIDEO O SINCRO

INVOLUCRO METAL-

LICO DELLA PRESA

AUDIO "L" MONO

"BLUE"

"GREEN"

AV LINK AV LINK AV LINK AV LINK AV LINK

"GREEN"

"RED"

"ROUGE" "ROT" "ROJA""ROSSO""RED"

SLOW SWITCH

FAST SWITCH

VIDEO

VIDEO VIDEO VIDEOVIDEOVIDEO

PLUG SCREEN

BOX

VIDEO OR "SYNC"

FAST SWITCH

AUDIO

"BLUE"

: OUTPUT - SORTIE - AUSGANG - USCITA - SALIDA •

: EARTH - MASSE - MASSE - MASSA - MASA

MAIN

NOTE :

... etc. repères des

platines constituant l'appareil.

MAIN

NOTA :

... etc. marcas de las

placas que constituyen el
aparato.

MAIN

NOTA :

... ecc. sigla delle

piastre dell' apparecchio.

MAIN

HINWEIS :

... usw. Kennzeichnung
der Platinen, aus denen das
Gerät zusammengesetzt ist.

: INPUT - ENTRÉE - EINGANG - ENTRATA - ENTRADA •

Do not disconnect modules when they are energized!
Repairs on power supply section are to be carried out only with isolating transformer.

Ne pas retirer les modules lorsqu' ils sont sous tension. N'effectuer les travaux de maintenance sur la partie reliée
au secteur (Switch Mode) qu'au travers d'un transformateur d'isolement.

Module nicht bei eingeschaltetem Gerät entfernen!
Servicearbeiten am Netzteil nur unter Verwendung eines Regeltrenntrafos durchführen.

Non scollegare le piastre quando sono alimentate!
Per le riparazioni sulla sezione alimentatore, utilizzare un trasformatore isolatore.

No desconectar los módulos cuando están activados. Las reparaciones en la sección de alimentación de energía
deben ser ejecutadas solamente con un transformador de separación.

LCD12B

First issue 03 / 05 3

INFORMATION - INFORMATIONS - INFORMATIONEN

INFORMAZIONE - INFORMACIONES

Chassis group table

1 - The electronic chassis configuration (modules) and schematic diagram page numbers.
2 - The chassis configuration.

Le tableau ci-dessous regroupe :
1 - L’environnement électronique de chaque chassis (modules) et le numéro de page où il est décrit.
2 - La désignation des chassis

Die nachstehendeTabelle umfaßt:
1 - Die elektronischen Baugruppen (Module) der Chassis varianten und die Seiten auf der sie beschrieben werden
2 - Die Chassisbezeichnung

La tabella qui di seguito contiene:
1 - l’ambiente elettronico di ogni telaio (moduli) e il numero di pagina nella quale è descritto.
2 - La descrizione dei telai

El cuadro siguiente agrupa:
1 - El entorno electrónico de cada chasis (módulos) y el número de página donde está descrito.
2 - La designación de los chasis

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Reference Information Block Service FCB KDB Inverter DC/DC Audio Earphone Main Video

Diagram Mode - - Power

Supply -- Board Board

27LCD120S4 34 to 6 7 to 12 13 to 14 - 15 to 20 - 21 to 22 - 23 to 44 45 to 58
30LCD120S4 34 to 6 7 to 12 13 to 14 - 15 to 20 - 21 to 22 - 23 to 44 45 to 58
32LCD120S4 34 to 6 7 to 12 13 to 14 - 15 to 20 - 21 to 22 - 23 to 44 45 to 58

Chassis LCD12B

LCD12B

4 First issue 03 / 05

BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD
SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES

Scart

Block Diagram

Board

5 pin 16 pin

PFC/DC+DC Board

10 pin

10 pin

12 pin

12 pin

(Invertert)

LCD Panel

30 pin

30 pin

AC

Input

14 pin

14 pin

Teltext

Module

Tuner

Audio

Processor

50 pin FFC

50 pin EFC

20 Pin

SDA555XFL

Tuner

Video Mux.

MSP3412G

SCART1 SCART2

CXA2161R

S-

Video

Video

Composite

Input

L/R Audio

5 pin

Audio Board

4 pin

6 pin

THC63LVDM83A

6 pin 16 pin

LVDS

Scaller

PW166B

Flash

Keypad/IR

5 pin

PW1230

De-Interlace

AFE

Main Board

Interface

12 pin

AD9883

DVI

Receiver

Video

Decoder

VPC3230D

BA7657F

Analog Mux.

HDCP

Sil169

DDC

UART

DDC

Component L/R

PC

DVI-I

DVI

Audio input

Y CbCr

PhoneJack

Audio Input

Audio

12 pin

5 pin

Keypad Board

10 pin

10 pin

LCD12B

First issue 03 / 05 5

BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI
ESQUEMA DE BLOQUES

SCART 1

Video Output

SCART 2

Video Output

MM1234+

ADG779

FL

SDA555X

VPC3230D

To Panel

Y

V

U

4

2

2

LVDS

signal

THC6 3L

VDM83 A

RGB 888

PW166B

Pixelworks

Tuner

Video Signal Flow

2

A

X

C

SCART 2

1

6

1

SCART 1

R

Video

Composite

S-Video

AD9883

BA7657F

Y

Cr

Pr/

Cb

Pb/

PC

Sil169

Differetial Sigal RGB 888

DVI-D

LCD12B

6 First issue 03 / 05

BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI -
ESQUEMA DE BLOQUES

Output

PhoneJack

L/R Output

EarPhone

SCART 2 Audi o L/R Output

SCART 1 Audi o L/R Output

TDA2822D

TDA7490

FROM TUNER AUDIO

MSP3412G

SCART 2

Audio Signal Flow

Component Audio

Input

Audio L/R

Composite

CXA7002R

SCART 1

DVI

AUDIO

Tuner

74HC4053D

Input

PC Phone-Jack

LCD12B

First issue 03 / 05 7

Service Mode Operation Manual

Model support: 15” 20” and 20” bi-sonic
Service Mode

1. Press the “menu” button, and then the screen display will
appear “Overview” OSD, below as Figure Overview OSD.
Then press the “info” button and ”1”, ”0”and ”3” buttons
step by step to enter Service Mode. And Figure
Service mode will appear on the screen display.

Mode Service

1.Presser la touche “Menu” l’ecran de selection ci-dessus apparait
Presser la touche “Info”, la touche “1” puis les touches “0” et “3” pour
acceder au “Mode Service”

Anleitung Service Mode

Für Modelle: 15“, 20“ und 20“ bi-sonic
Service Mode

1. Drücken sie die „MENU“ – Taste. Es erscheint das „Übersicht“
–Menü (siehe Abbildung 1). Drücken sie dann nacheinander die Tasten
„INFO“, „1“, „0“, und „3“. Die erste Seite des Service-Modes wird
angezeigt (siehe Abbildung 2).

Manuale Procedura Service Mode

Modelli: 15” 20” e 20” bi-colonna
Service Mode

1. Premere il tasto “menu” per far visualizzare il menu “Sommario”,
vedi pagina OSD.
Poi premere sequenzialmente i tasti “info” , “1”, “0” e “3” per entrare in
Service mode. Il menu di Service mode verrà visualizzata sullo schermo.
Per cambiare pagina premere il tasto “Menu”.
Menu Sommario

Manual de operación del Modo Servicio

Para modelos de : 15”, 20” y 20” bi-columna
Modo Servicio

1. Pulsar la tecla “menú”, en la pantalla se mostrará
el menú “OVERVIEW (ÍNDICE)”, como se muestra en
la figura MENU OVERVIEW (ÍNDICE).
A continuación, pulsar las teclas “info”, ”1”, ”0” y ”3” una tras otra
para entrar en Modo Servicio y se mostrará
la primera página del Modo Servicio en la pantalla.

Overview

Preferences

Installation

Sound

Picture

Figure Overview OSD

SERVICE MODE - MODE SERVICE - SERVICE-MODE - MODO SERVICIO

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➠

- “Change“ value

- Réglage de la valeur

- Wert “änden“

- “Cambiare“ valore

- “Cambiar“ valor

NAVIGATION INSIDE THE SERVICE MODE - DEPLACEMENT DANS LE MODE SERVICE

SUCHE IN SERVICE MODE - OPZIONI NEL SERVICE MODE - BUSQUEDA EN MODO SERVICIO

➠

REMOTE CONTROL - TELECOMMANDE - FERNBEDIENUNG

TELECOMANDO - MANDO A DISTANCIA

Naviagation up

Naviagation down

VALUE

VALUE

>

<

- Press "Menu" button

- Appuyer sur la touche "Menu"

- Taste "Menu"

- Premere " Menu"

- Pulse "Menu"

Changing page - Changement de page

Seitenwechsel - Cambiare Pagina - Cambio de página

Choosing a setting from the menu / setting e value

Choix d'un réglage dans un menu / Réglage d'une valeur

Wahl einer einstellung in einem menü / Einstellung eines wertes

Scegliere una Regolazione dal Menu / Selezione di un valore

Eleccion de un Ajuste en un menu / Ajuste de un valor

Color temp P-N P-C V-CV-NP-W

Red Drive - 123 -

Green Drive

Blue Drive

Red Offset

Green Offset

Blue Offset

Reset To Default

Calibration...

Auto Turn on on off

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Tuner 1D

+

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- 123 -

+

- 123 -

+

- 123 -

- 123 -

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Eu 20L0BI

Ver 09171I

Color temp P-N P-C V-CV-NP-W

Red Drive - 123 -

Green Drive

Blue Drive

Red Offset

Green Offset

Blue Offset

Reset To Default

Calibration...

Auto Turn on on off

-

-

-

-

-

-

Tuner 1D

+

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- 123 -

+

- 123 -

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190247

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LCD12B

8 First issue 03 / 05

1. Color Temp: P-N means “Normal” on YpbPr, V-N means “Normal” on
Video mode. Each item decide different gamma curve.

2. Red drive, Green drive and blue drive means gamma RGB gain.
Control by scaler

3. Red offset, Green offset and blue offset means gamma RGB offset.
Control by scaler

4. Reset To Default: press OK will load all default value on User OSD

5. Calibration: press this botton guide to calibrate A/D converter white

and black level on PC input. Also guide to calibrate A/D converter PbPr
offset on YpbPr input.

6. MV enable: (30") designer debug tool revision
( this is information only )

1. Color Temp: Temperature des couleurs.

P-N correspond à un reglage “Normal” /YpPr
V-N correspond à un reglage “normal” / mode vidéo

chaque item permet de règler la courbe de gamma.

2. Red drive, Green drive and blue drive: green drive et Bleu drive
correspond aux reglages de gain
du gamma RVB ( controlé par le scaler).

3. Red offset, green offset et blue offset: correspond aux réglage
d’offset du gamma RVB ( controlé par le scaler ).

4. Reset To Default: Appuyer sur “OK”.

Charger les valeurs par defaut sur le menu OSD.

5. Calibration: Appuyer sur “OK” pour valider.

Etalonne les niveaux blanc et noir du convertisseur A/D de l’ entrée PC
Etalonne egalement les offset Pb/Pr du convertisseur A/D sur l’ entrée
Ypb Pr.

6. MV enable: Port Vidéo Chip 323 ( Seulement Utilisé pour le
debuggage en conception ). Si vous quittez le menu usine, la fonction
n'existe plus.

1. Color Temp: P-W steht für „Warm im YPbPr-Mode, P-N steht für
„Neutral“ bei YPbPr-Mode, P-C steht für „Kalt“ im YPbPr,-Mode, V-W
steht für „Warm“ im Video-Mode, V-N steht für „Neutral“ im Video-Mode,
V-C steht für „Kalt“ im Video-Mode. Alle Modi haben unterschiedliche
Gamma-Kennlinien.

2. Red Drive, Green Drive und Blue Drive: Einstellung der RGB­Verstärkung

3. Red Offset, Green Offset und Blue Offset: Einstellung des RGB­Offsets

4. Reset to Default: Durch Drücken der “OK”-Taste werden die
Benutzerdaten gelöscht und die Defaultwerte geladen.

5. Calibration: Kalibrieren der Schwarz- und Weißpegel des AD­Wandlers des PC-Eingangs.

6. MV enable: (30") Chip 323 Video-Port (Nur für Entwicklungszwecke,
hat keine Funktion sobald der Produktionsmode verlassen wird.)

1. Color Temp: P-N significa “Normale” in funzione YPbPr, V-N significa
“Normale” in funzione Video. Ogni selezione determina una differente
curva di risposta.

2. Red Drive, Green Drive e Blue Drive significa guadagno gamma
RGB. Controllato da una scala.

3. Red Offset, Green Offset e Blue Offset significa Offset gamma RGB.
Controllato da una scala.

4. Reset To Default: premendo OK verranno caricati tutti i valori di
Default nel Menu Utente.

5. Calibration: premere questo tasto guida per calibrare il livello Bianco
/Nero del convertitore A/D dell’ingresso PC. Calibra anche l’offset del
convertitore A/D PbPr dell’ingresso YpbPr.

6. MV enable: (30")Porta video chip 232 ( Sviluppato per la ricerca
guasti in fabbrica; questa funzione, al di fluori del menu di fabbricca, non
è attiva)

1. Color Temp: P-N significa “Normal” en modo YpbPr, V-N significa
“Normal” en modo Video. Cada elemento tiene una curva de gamma
distinta.

2. Red drive, Green drive y Blue drive ajustan la ganancia de la gamma
RGB.

3. Red offset, Green offset y Blue offset ajustan el offset de la gamma
RGB.

4. Reset To Default: Al pulsar OK se cargarán todos los valores por
defecto del menú de usuario

5. Calibration: Pulsando este botón ayuda a calibrar el convertidor A/D
de nivel de blanco y negro
para la entrada de PC. También sirve para calibrar el offset del
convertidor A/D PbPr en la entrada YpbPr.

6. MV enable: (30") puerto de vídeo c.i. 323 (uso solamente por el
diseñador, si se deja el menú de fábrica, no funciona mas)

Color temp P-N P-C V-CV-NV-WP-W

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Red Drive - 128 -

Green Drive

Blue Drive

Red Offset

Green Offset

Blue Offset

Reset To Default

Calibration...

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11:45:04

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LCD12B
First issue 03 / 05 9

7. OSD position: OSD position selection.

8. Burn in mode: For development only. Value change is not

recommended.

9. Burn in time Adjust: For development only. Value change is not
recommended.

10. Video int Gain: this slider bar used to align brightness spec of Video
mode. Larger value bring to brighter. Control by Video decoder VPC3230

11. YPbPr: For development only. Value change is not recommended.

12. Colour: adjust color saturation. Same funct ion on User OSD.

Control by Video decoder VPC3230.

13. Tuner Set V-Level: not used

14. Tuner Get V-Level: not used.

15. Set First Installation: “Enable” means TV will pop-up installation

OSD at next power-on.

16. Tuner Set Factory Programs: not used.

17. Fan test: For development only. Value change is not recommended
17-1. Enter PW1230 Adjustment page: Deinterlacer parameters control.

For development only. Value change is not recommended.

7. OSD position: Selection de la position OSD.

8. Burn in mode: Réglage usine, ne pas modifier.

9. Burn in time Adjust: Réglage usine, ne pas modifier.

10. Video int Gain: Réglage de la lumière en mode vidéo.

Contrôle par le décodeur vidéo VP¨C 3230.
La position élevèe du curseur augmente la lumière.

11. YPbPr: Réglage usine, ne pas modifier.

12. Colour: Régle la saturation de la couleur.

13. Tuner Set V-Level:Pas utilisé.

14. Tuner Get V-Level: Pas utilisé.

15. Set First Installation: Signifie que la TV à la prochaine mise sous

tension affichera le menu d’ installation.

16. Tuner Set Factory Programs: Pas utilisé.

17. Fan test: Réglage usine, ne pas modifier.
17-1. Enter PW1230 Adjustment page: Ne pas modifier. Réglage usine

Contrôle les parametres “ Deinterlacer”.

8. OSD Position: Wahl der Menü-Position auf dem Bildschirm

9. Burn in mode: Eine Änderung dieser Grundeinstellung ist nicht

empfehlenswert.

10. Burn in time Adjust: Eine Änderung dieser Grundeinstellung ist
nicht empfehlenswert.

11. Video Int Gain: Helligkeitsvoreinsteller für den Video-Mode.
Steuerung über den Videodecoder VPC3230.
XX. YPbPr: Eine Änderung dieser Grundeinstellung ist nicht
empfehlenswert.

12. Colour: Einstellung der Farbsättigung; gleiche Funktion wie die
Benutzersteuerung. Steuerung über den Videodecoder VPC3230.

13. Tuner Set V-Level: nicht benutzt

14. Tuner Get V-Level: nicht benutzt

15. Set First Installation: „Enable“ lässt beim nächsten Einschalten des

Gerätes nach einer Netztrennung das Installationsmenü erscheinen.

16. Tuner Set Factory Programs: nicht benutzt.

17. Fan test: Eine Änderung dieser Grundeinstellung ist nicht

empfehlenswert.
17-1. Enter PW1230 Adjustment Page: Abgleich der Parameter des
Deinterlacers. Eine Änderung dieser Grundeinstellungen ist nicht
empfehlenswert.

7. OSD position: Selezione posizione OSD.

8. Burn in mode: Utilizzato per la fabbrica. Si consiglia di non cambiare

valore.

9. Burn in time Adjust: Utilizzato per la fabbrica. Si consiglia di non
cambiare valore.

10. Video int Gain: Regola il livello di luminosità in funzione Video. Più
alto è il valore più l’immagine è luminosa. Controllo tramite il Decoder
Video VPC3230.

11. YPbPr: Utilizzato per la fabbrica. Si consiglia di non cambiare valore.

12. Colour: Regola la saturazione del colore. Stessa funzione del Menu

utente. Controllo tramite Video Decoder VPC3230.

13. Tuner Set V-Level: Non utilizzato.

14. Tuner Get V-level: Non utilizzato.

15. Set First Installation: “Enable” significa abilitazione, all’accensione,

del menu di prima installazione.

16. Tuner Set factory Programs: Non utilizzato.

17. Fan test: Utilizzato per la fabbrica. Si consiglia di non cambiare

valore.
17-1. Enter PW Adjustment page: Controllo parametric Deinterlacer.
Utilizzato in fabbrica. Si consiglia di non cambiare valore.

a7. OSD position: Selecciona la posición del OSD.

8. Burn in mode: No se recomienda cambiar este valor

9. Burn in time Adjust: No se recomienda cambiar este valor

10. Video int Gain: Esta barra deslizante se utiliza para ajustar las

especificaciones del brillo en el modo Video. Cuanto mayor sea el valor,
más brillante. Control por el descodificador de Video VPC3230

11. YPbPr: No se recomienda cambiar este valor

12. Colour: ajusta la saturación del color. Es la misma función que el

menú de usuario. Control por el descodificador de Video VPC3230.

13. Tuner Set V-Level: no utilizado.

14. Tuner Get V-Level: no utilizado.

15. Set First Installation: “Enable” significa que la próxima vez que se

conecte el TV aparecerá el menú de primera instalación.

16. Tuner Set Factory Programs: no utilizado.

17. Fan test: No se recomienda cambiar este valor
17-1. Enter PW1230 Adjustment page: control de los parámetros de

Deinterlacer. No se recomienda cambiar este valor.

OSD Position

Burn in mode On 0:00Off

96

0

180

53

8

YPbPr Int Gain

Burn in time adjust

Colour

Video Int Gain

PW 1280 Brighness

Set First INstallation NotEnabled...

Tuner Set Factory Programs

Fan test

EN
FR

DE

ES

IT

LCD12B

10 First issue 03 / 05

18. PW Gamma: gamma curve selection. “Automatic” means pick-up

proper gamma curve automatically when user choose Normal, Warm and
Cool. Value change is not recommended.

19. Scale Mode: screen ratio selection.

21. HV Lock Sensitivity: Tuner HV sync sensitivity. Value change is not

recommended. Fake programme be detected or Real programme be
skipped.

22. Color Delay: Color timing delay which only impact on Video mode. For
development only. Value change is not recommended

23. Audio gain: not used.

24. Pb offset: adjust Pb offset on YpbPr input.

25. Pr offset: adjust Pr offset on YpbPr input.

These 2(25,26) Functions above could be automatically done by
“Calibration” page1.

18. PW Gamma: Selection de la courbe de gamma “Automatic”
correspont à l’optention de la courbe de gamma appropriée quand
l’utilisateur choisit la position froide, neutre, chaude ou le rendu des
couleurs est meilleur.
il est deconseillé de sélectionner la position “value Change”.

19. Scale Mode: Selection format d’ecran.

21. HV Lock Sensitivity: Sensibilité de la Synch. HV tuner.

Il est imperatif de ne pas modifier sa valeur.
Le tuner détectera les mauvais progrmmes ou passera les programmes
corréctes.

22. Color Delay: Réglage du “délai” couleur en mode vidéo.
Réglage usine, ne pas modifier.

23. Audio gain: Non utilisé.

24. Pb offset: Réglage de l’offset Pb sur l’ entrée Ypb Pr.

25. Pr offset: Réglage de l’offset Pr sur l’entée Ypb Pr.

Ces 2 réglages ( 25, 26 ) sont automatiquement effectues par
“calibration” de la page 1 du mode service.

18. PW Gamma: Auswahl der Gamma-Kennlinie: Bei Einstellung
„Automatic“ wird automatisch die jeweilige Kennlinie gewählt, wenn der
Benutzer zwischen Warm, Neutral oder Kalt umschaltet. Eine Änderung
dieser Grundeinstellung ist nicht empfehlenswert.

19. Scale Mode: Wahl des Bildformates

21. HV Lock Sensitivity: Empfindlichkeit des Synchrondetektors im

Tuner. Eine Änderung dieser Grundeinstellung ist nicht empfehlenswert,
da sonst der Sendersuchlauf falsche Ergebnisse liefern könnte.

22. Color Delay: Einstellung Farbversatz. Eine Änderung dieser
Grundeinstellung ist nicht empfehlenswert.

23 Audio Gain: nicht benutzt

24. Pb Offset: Einstellung des Pb Offsets bei YPbPr.

25. Pr Offset: Einstellung des Pr Offsets bei YPbPr.

Zu 26 und26: Der Abgleich dieser Funktionen kann automatisch mit der

Funktion „Calibration“ auf der Service-Mode Seite 1 durchgeführt werden.

18. PW Gamma: Selezione curva gamma. In “Automatic” viene
selezionata automaticamente la curva gamma ideale, in base alla scelta
utente Calda, Fredda o Neutra, nella funzione Tonalità . Si consiglia di
non cambiare valore.

19. Scale Mode: Selezione Rapporto schermo.

21. HV Lock Sensitivity: Sensibilità Sync HV Tuner. Si consiglia di non

cambiare valore. Livello soglia per saltare eventuali emittenti con segnale
debole.

22. Color Delay: Regola il ritardo colore rispetto al segnale video.
Utilizzato per la fabbrica. Si consiglia di non cambiare valore.

23. Audio Gain: Non utilizzato.

24. Pb offset: Regola l’offset Pb sul segnale YpbPr in ingresso.

25. Pr offset: Regola l’offset Pr sul segnale YpbPr in ingresso.

Le regolazioni menzionate nei punti 25 e 26 possono essere eseguite
automaticamente come indicato nella riga “Calibration” di pagina 1.

18. PW Gamma: Selección de la curva de gamma. “Automatic” quiere
decir que recuperará automáticamente la curva ideal de gamma cuando
el usuario seleccione Normal, Cálido o Frío. No se recomienda cambiar
este valor.

19. Scale Mode: selecciona la relación de pantalla.

21. HV Lock Sensitivity: Sensibilidad de los sincronismos HV del

sintonizador para la búsqueda de emisoras. No se aconseja cambiar este
valor. Los canales reales pueden ser ignorados o los falsos
memorizados.

22. Color Delay: Retardo del color en modo Video. No se recomienda
cambiar este valor

23. Audio gain: no utilizado.

24. Pb offset: ajuste del offset de Pb en la entrada YpbPr.

25. Pr offset: ajuste del offset de Pr en la entrada YpbPr.

Estas 2 funciones anteriores (25,26) serán hechas automáticamente en

“Calibration” de la página 1.

Pw Gamma Automatic

CineramaScale Mode

25

58

-

-

+

+

3

-+

5+

60

-+

Color Delay

Audio Gain

7

-+

Audio Delay

HVLock Sensitivity

Pb Offset

Pr Offset NotEnabled...

Nonlinear Scale...

SW Deinterlace Field Inverse...

VClipPct

EN

FR

DE

ES

IT

VOffsetPct

VStretchPct

HClipPct

HOffsetPct

HStretchPct

-+

-+

-+

-+

-

-

+

+

- 1074 -

- 998 -

- 1000 -

- 1030 -

- 1000 -

- 1300 -

GEOMETRY

V-Amplitude

VClipPct

4/3

16/9

V-Position

VOffsetPct

16/9

V-Linearity

VStretchPct

4/3

16/9

GEOMETRY
H-Amplitude

HClipPct

4/3

16/9

H-Position
HOffsetPct

16/9

H-Linearity

HStretchPct

4/3

16/9

LCD12B

First issue 03 / 05 11

26. Auto Adjustment: auto adjustment new timing(position ,phase…etc).

Only active on PC mode.

27. Default Language: set default language. Same function on User
OSD.

28. RGB filter: sharpness filter of PC port of scaler. Impact on PC and
YpbPr input

29. Video filter: sharpness filter of Video of scaler. Impact on TV Video
and YcbCr.

30. Monitor Sync: force to “On”. So that Video format can auto
detection.

31.VPC Brightness Reset: For development only. Value change is not
recommended.

32. Reset All Nvram: press “OK” will reset all parameters on service
mode, including color temp settings, brightness setting….etc.

33. Test Pattern: display test-pattern which generate by scaler. Only
active on PC source.

34. H.Position: adjust horizontal position while PC source in

35. V.Position: adjust Vertical position while PC source in

26.Auto Adjustment: Actif seulement en mode PC. Auto réglage des

nouveaux parametres de temps ( Position, phase..).

27. Default Language: Selectionne la langue par défaut. Même fonction
que le réglage utilisateur.

28. RGB filter: Filtre Contour RGB du Port PC.

29. Video filter: filtre contour Vidéo. Agit sur les entrées TV Vidéo et

Ye bCr.

30. Monitor Sync: Forcé à ON Auto détection du format Vidéo.

31.VPC Brightness Reset: Réglage usine, ne pas modifier.

32. Reset All Nvram: Appui sur “OK”.

Reset De tous les parametres du “MODE SERVICE” incluant la
tempèrature de couleur, Contour... etc.

33. Test Pattern: Affichage de la mire interne. Actif seulement en mode
PC

34. H.Position: Réglage Horizontal en mode PC.

35. V.Position: Réglage Vertical en mode PC.

26. Auto Adjustment: Automatischer Abgleich von Timing, Lage, Phase

usw. im PC-Mode

27. Default Language: Auswahl der Menüsprache; gleiche Funktion wie
die Benutzersteuerung.

28. RGB Filter: Abgleich des Schärfefilters des Scalers für PC-Mode und
YPbPr.

29. Video Filter: Abgleich des Schärfefilters des Scalers für den
Video-Mode.

30. Monitor Sync: Sollte immer auf „On“ stehen damit das Videoformat
automatisch erkannt wird.

31.VPC Brightness Reset: Eine Änderung dieser Grundeinstellung ist
nicht empfehlenswert.

32. Reset All Nvram: Drücken der „OK“-Taste setzt alle Parameter im
Service-Mode ( auch Farbtemparatur, Helligkeit usw.) zurück.

33. Test Pattern: Zeigt ein vom Scaler erzeugtes Testmuster auf dem
Bildschirm. Nur im PC-Mode.

34. H.Position: Horizontallage für PC-Eingang.

35. V.Position: Vertikallage für PC-Eingang.

26. Auto Adjustment: Auto regolazione nuove temporizzazioni

( posizione, fase ... etc). Attivo solo in funzione PC.

27. Default language: Seleziona la lingua. Stessa funzione del Menu
Utente.

28. RGB Filter: Definizione filtro del demoltiplicatore (scaler) della porta
PC. Influisce sugli ingressi PC e YpbPr.

29. Video Filter: Definizione filtro del demoltiplicatore del segnale Video.
Influisce sui segnali TV Video e YcbCr.

30. Monitor Sync: Forzato su “On”. In questo modo può essere rilevato
automaticamente il Formato Video.

31.VPC Brightness Reset: Utilizzato per la fabbrica. Si consiglia di non
cambiare valore.

32. Reset All Nvram: Premendo “OK” verranno resettati tutti I
parametri del Service Mode, inclusi regolazione Temp. Colore,
Regolazione Luminosità, ... ecc.).

33. Test Pattern: Attivazione serie di segnali test. Attivo solo con
ingresso PC.

34. H. Position: Regola la posizione Orizzontale in ingresso PC.

35. V. Position: Regola la posizione Verticale in ingresso PC.

26. Auto Adjustment: Autoajuste de nuevo timing (posición, fase…etc).

Sólo activo en modo PC.

27. Default Language: selecciona el idioma por defecto. Hace la misma
función que el menú "Usuario".

28. RGB filter: filtro de nitidez. Válido para las entradas de PC e YpbPr.

29. Video filter: filtro de nitidez. Válido para las entradas de TV, Video e

YcbCr.

30. Monitor Sync: forzado a “On”. El formato de video puede ser
autodetectado.

31.VPC Brightness Reset: No se recomienda cambiar este valor

32. Reset All Nvram: pulsando “OK” se borrarán todos los parámetros

del Modo Servicio, incluyendo los ajustes de temperatura de color,

ajustes de brillo y contraste....., etc.

33. Test Pattern: muestra unas cartas de ajuste generadas
internamente. Activo solamente en modo PC.

34. H. Position: ajusta la posición horizontal sobre la entrada PC.

35. V. Position: ajusta la posición Vertical sobre la entrada PC.

Auto Adjustment

Page4 on service mode

EN

FR

DE

ES

IT

Default Langage English

RGB Filter

Video Filter VID_320T_5.PWF

Monitor Sync On Off

VPC Brightness Reset Temp: 51.0 C

Reset All Nvram...

Test Pattern...

H.position

V.position

-

-

Fan1: ORPM

Fan2: ORPM

+

100+

25

LCD12B

12 First issue 03 / 05

36. Life Time: The left item means the time added by stand by + TV on

The right item display the time of TV-on only.

37. Project Code: as title

38. Panel Resolution: as title

39. NvRam Ver. Display EEPROM data veriosn.

40. HXV Res / Hfreq: timing information. Resolution and H clock

41. HXV Total: timing information.

42. Mode Num: timing information. Sequence of Timing chart.

43. DCLK: timing information. Data clock

These (41,42,43,and 44) items above are for development check only.

44.SDK: Designer debug tool revision ( this is information only )

45. Factory save: save factory parameters.

36. Life Time:

-Indication de gauche:

indique le temps fonctionnement total du TV: On+ Stand by.

-Indication de droite:

Indique le temps de fonctionnement du TV en On seulement.

37. Project Code: Info code.

38. Panel Resolution: Resolution du panneau d’écran.

39. NvRam Ver. Version EEPROM.

40. HXV Res / Hfreq: Information de temps resolution et Horloge H.

41. HXV Total: Information de temps.

42. Mode Num: Information de temps

43. DCLK: Information de temps.Data clock.

Ces 4 lignes d’information sont utilisées en développement.

44.SDK: Version de l'outil de debuggage.

45. Factory save: Sauvegarde les paramétres usine.

Seite 5 des Service-Modes

36. Life Time: Betriebsstundenzähler, links: Summe Standby-Zeit und
TV-Ein, rechts: nur TV-Ein-Zeit.

37. Project Code:

38. Panel Resolution: Auflösung der LCD-Panels

39. NvRam Ver. : Version EEPROM-Daten

40. HXV Res / HFreq:Timing-Information (Auflösung und H-Clock)

41. HXV Total: Timing Information

42. Mode Num Timing Information

43. DCLK: Timing Information Data Clock

44.SDK: Version des Entwicklungsdebugtools (nur zur Information).

45. Factory Save: Daten des Service-Modes speichern.

36. Life Time: Il contatore a sinistra indica il tempo totale di

funzionamento in Stand By + apparecchio acceso. Il contatore a destra
indica il tempo totale di funzionamento ad apparecchio acceso (ON).

37. Project code: Codice progetto.

38. Panel Resolution: Risoluzione pannello.

39. NvRam Ver: Versione EEPROM.

40. HXV res / Hfreq: Informazione timing. Risoluzione e Clock H.

41. HXV Total: Informazioni timing.

42. Mode Num: Informazioni Timing. Sequenza carta tempi.

43. DCLK: Informazioni Timing. Clock Data.

I valori menzionati nei punti 41, 42 43 e 44 sono solo per la fabbrica

44.SDK:

45. Factory save: Parametri memorizzati in fabbrica.

36. Life Time: Los números de la izquierda muestran la suma de las

horas en stand-by + TV encendido. Los de la derecha indican sólo las
horas de TV encendido.

37. Project Code: informativo

38. Panel Resolution: informativo

39. NvRam Ver. Indica la versión de la EEPROM.

40. HXV Res / Hfreq: información de timing. Resolución y frecuencia H.

41. HXV Total: información de timing.

42. Mode Num: información de timing.

43. DCLK: información de timing. Frecuencia del reloj.

Estas 4 funciones anteriores (41,42,43,y 44) son informativas. Sólo son
para comprobación.

44.SDK: Herramienta para la revisión de los defectos de diseño (sólo
para información)

45. Factory save: memoriza los valores de fábrica.

Life Time 00009:30 00005:05

Page5 on service mode

EN

FR

DE

ES

IT

Project Code EU27L04B
Panel Resolution 1280 X 720
NvRam Ver. 15 / 94
HXV Res / HFreq 649 X 546 15,68 KHz

HXV Total 864 X 625
Mode Num 64

DCLK 81 MHz
SDK 2.2 SPB Release Build: Sept 9 2004 17:46:49

TUNER: 09Factory Save...

14

LCD12B

First issue 03 / 05 13

KEYBOARD SCHEMATIC DIAGRAM - SCHEMA DES CIRCUITS COMMANDES - SCHALTBILD BEDIENTEIL - SCHEMA DEI CIRCUITI TASTIERA - ESQUEMA DE LOS CIRCUITOS MANDOS

Optical Points

OP

OP2 OP4 OP6OP3 OP7OP5OP1

OP

OP OP

OP

OP

OP

J2=> J8 Main board

EAR_MUTE

TP 1

5

TP 2

J2

12V

4
3
2
1

G1 G2

TP 3
TP 4
TP 5

A udio_R

Audio_L

V5S

J3=> J2 IR board

TP 6

10

10

10

9

9

9

8

8

8

7

7

7

6

6

6

5

5

5

4

4

4

3

3

3

2

2

2

1

1

1

G1 G2

G1 G2

TP 7
TP 8
TP 9
TP 10
TP 11
TP 12
TP 13
TP 14
TP 15

KP D0
KP D1
KP D2
KP D3
KP D4
KP D5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

16V

R1 0

51.1KF

+

16V

C4

+

10U

C9

10U

R2

10K

13

SW6

245

H1

HO LE-V 8

H2

HOL E-V8

R1 1

51.1KF

13

245

IR BOARD

R8
1K

SW5

J3=> J6 Main board

123456789

1234567891011

IR

V5S

TP13

10

TP14

9

9
8
7
6
5
4
3
2
1

TP15

8

TP16

7

TP17

6

TP18

5

TP19

4

TP20

3
2
1

J2

20L1033010

J2

G1G2

G2

10

G1

J2=> J3 KeyPad board

R7
1K

C1 2

+

100U
16V

13

SW4

245

12V

C1 3

+

100U
16V

R1

10K

13

SW3

245

TP 10

KP D5

TP 9

TP 8

KP D4

KP D3

2N3906

101112

TP 3

TP 7

TP 5

TP 6

TP 2

TP 4

KP D2

KP D0

KP D1

R9

1K

Q1

C1

5

1

00U

16V

13

SW2

245

J3

12

IR Sensor P/N :05.04856.010 for the USA

IR Sensor P/N :05.04833.010 for the EU

TP 1

L2L4L3

TDA2 822D

V5S

2

13

GREEN/RED

12

+

C1

4.7U

25V

5.1K

R3

U1

+

C1
100U
16V

7

8

6

5

6

33 0

VOUT
GND
VCC

R2

R4

33 0

R1

V5S

2

1

3

4

V5S

RG

4

LE D1

1
2
3

330

+

-

+

-

+

13

SW1

245

TSOP4856

100U

100U

U1

R1 2

4.7

C6

0.1U
25V K

R5

39

R1 3

4.7

C7

0.1U
25V K

C1 0

C1 1

+

16V

+

16V

KEYPAD BOARD

KB

1N4148

Q3
2N3904

12V

R1 4
47K

D7

12

+

C1
1000P

C2

R3
10K

R4
10K

1000P

C3
100 0P

D3

TZMC 5V 1

D6

TZMC 5V 1

R6

39

D1

TZMC 5V 1

D4

TZMC 5V 1

D2

TZMC 11

D5

TZMC1 1

C1 4
100U
16V

7
6
1

2
4
5

3

1

J1

7
6
1

2
4
5

3

2210165091

32

R1 5
10K

Q2
2N3 904

2

2

3

3

4

4

5

5

1

1

H1
HOLE -V8

6

6

7

7

8

8

9

9

2

2

3

3

4

4

5

5

1

1

H2
HOLE -V 8

6

6

7

7

8

8

9

9

Optical Points

OP2 OP4

OP

OP8 OP14OP11
OP

OP

OP

OP

OP10
OP

OP5OP1

OP

OP

OP12OP9
OP

OP6OP3 OP7
OP

OP13
OP

OP

OPOP

15

LCD12B

16 First issue 03 / 05

POWER SUPPLY INTERFACE - INTERFACE ALIMENTATION - NETZTEIL - ALIMENTAZIONE - INTERFAZ ALIMENTACIÓN

SCHEMATIC DIAGRAM - SCHEMA DE PRINCIPE - SCHALTBILD - SCHEMA - ESQUEMA

PFC BOARD

EMI BOARD

AC-

EMI Board

AC+

AC-

AC+

CY6201

CY6202

L6201

115uH

L6202

115uH

VCC1

8
3
2

6

ZD6201

27V

C6201
1uF

VCC
MULT
COMP

GND

C6203

47uF

IC651

L6561

C6205

1uFC6206

R6205

200K

ZCD

GD

CS

INV

R6209

5
7

4
1

C6210

0.1uF

R6206

22K

R6207

22

D6203

1N4148

R6201A

332K

C6204

0.01uF

R6201B

332K

R6201C

332K

R6201D

332K

R6203

11K

C6209

0.1uF

R6204
475K

R6202A
590K

R6202B

590K

1

BD6201
GBJ8J

4

3

2

R6202C
590K

C6208

0.01uF

L6203

450uH

R6208

20K

C6207
470p

D6201

SF10A60U

Q6201
20N60C 3

R6212

0.15R/5W

R6211

46.4K

Q6202
2N7002

D6202

MUR460

R6212A

590K

R6212B

590K

R6212C

590K

R6212D

590K

R6213

9.09K

SCK15056

R6212E

590K

C6202

R6212F

590K

R6212G

590K

R6212H

590K

1uF

PFC BOARD

TR6201

t

C6211

100uF/450V

C6212
100uF/450V

B+

PGND

Mainsvoltage
50HZ / 60HZ

F6101

CN6101

3P

1
2
3

T4A/250V

EMI BOARD

VZ6101

471

L6101

3Ts

L6102

3Ts

L6103

1.1mH

CY6101

1000p

CY6102
1000p

R6101A
270K

R6101B

270K

R6101C

270K

CX6101

0.47uF
L6104

24mH

CX6102

0.68uF
L6105

1.1mH

AC+

AC-

AC+

AC-

PFC Board

18

LCD12B

First issue 03 / 05 17

POWER SUPPLY INTERFACE - INTERFACE ALIMENTATION - NETZTEIL - ALIMENTAZIONE - INTERFAZ ALIMENTACIÓN

SCHEMATIC DIAGRAM - SCHEMA DE PRINCIPE - SCHALTBILD - SCHEMA - ESQUEMA

R7302

C7301

INVERTER POWER BOARD

47

R7301

47

1000p

C7302

1000p

POWE

D7301

B+

To PFC Board
Audio Power Board

R6316

1.1K

R6317

R6325

Q6304

D6310

P-ON
Audio Power Board

VCC1

Q6305

PMBS3906

R6323
47K

D6311
1N4148

P-ON

R6309
100K

1N4148

R6322

47K

R6315

11K

C6308

2200p

D6309

C6314
100uF

C6301

0.01uF/500V

C6312

4.7uF

R6314
100K

C6313

4.7uF

VCC

D6307
1N4148

D6308

1N4148

R6320

7.5K

R6321

1.5K

Q6303
PMBS3904

VCC

8

4

C6307

0.1uF

Q6307

PMBS3904

2

3

R6301
68K/2W

Q6302
MPSA44

R6308

D6303
1N4148

C6311

150uF

7

VCC

V REF

U6301

UC3843A

RT/CT

COM B GND

1

R6313

10K

C6306
1500p

R6318

5.1K

R6319

1.2K

U6303
LM431

1

392K

VC

2

6

I SEN

U6302

PC123F1

4

R6307

392K

C6315

0.1uF

OUT

5

3

R6326

1.1K

R6303
392K

R6304
392K

R6305
392K

R6306
392K

D6304
1N4148

R631010R6311

3

C6305
100p

Q7301

PMBS3904

VC

R7312

12

VF

330

C6302
3300p

ZD6301

24V

R6327

1K

C6304
1000p

R7311
10

20K

C7311

0.1uF

G

D6301
ES1D

C6310
47uF

ZD7301

30V

R6302
68K

D6302
ES1D

Q6301
STW11NB80

R6312

0.27R/2W

V-INVERTER

U7302

PQ1CY1032Z

1

VI
ON/OFF GND FB

5

R7320

5.1K

C7320

0.1uF

3

C6303

T6301

PQ3220

1

2

3

5

VO

4

CY6301

1500p

2

D7304A

RB060L

7

94

D7302

D7303

D7304B
RB060L

FMX-22SL

FMX-22SL

FMX-22SL

L7301

150uH

C7303A

470uF

R7321

3.3K

R7322

1.1K

C7303B

470uF

C7305
470uF

C7305

C7309

0.1uF

R7308

10K

C7303C

470uF

1.2K

C7310

0.1uF

5VS

EGND

G

8

1

V-INVERTER

C7303D

470uF

R7303

22.1K

C7306
1000p

7

VCC

VRIN

VREF

CSEN

2

R7309

1.2K

R7310
100

R7313

15mohm

R7304

1K

6

OUT

CRREF

3

5

CRIN

GND

4

VF

C7307

R7306

5.1K

U7301
TSM101A

G

7-Sep-2004

C7304

0.1uF

C7308

0.1uF

R7307
75

LCD-ON

LCD-BRI

EGND

V-INVERTER

V-INVERTER

CN701

12
11
10
9
8
7
6
5
4
3
2
1

CN702

10
9
8
7
6
5
4
3
2
1

19

LCD12B

20 First issue 03 / 05

POWER SUPPLY INTERFACE - INTERFACE ALIMENTATION - NETZTEIL - ALIMENTAZIONE - INTERFAZ ALIMENTACIÓN

SCHEMATIC DIAGRAM - SCHEMA DE PRINCIPE - SCHALTBILD - SCHEMA - ESQUEMA

AUDIO POWER BOARD

C7401

POWE

B+

To PFC Board

R6403
10K

R6402

D6407

1K

1N4148

Q6403

PMBS3904

Q6402
PMBS3906

R6413
10K

R6414

10K

C6414

4.7uF

C6411

0.1uF

C6401

0.01uF/500V

VCC

ZD6401

R6410
100K

C6415

4.7uF

6.2V

Q6404

D6406
1N4148

PMBS3904

R6404

2.2K

D6405

1N4148

C6413

4.7uF

7

VCC OUT

8

V REF

R6411

11K

4

RT/CT

COMP FB GND

1

C6410
2200p

U6401

UC3843A

R6412

10K

C6409

0.022uF

C6412
100uF

2

C6404

0.1uF

R6406

4.7

6

3

I SEN

C6408

U6404
PC123F1

220p

1

2

3

2

5

R6415

5.1K
34

R6416

1K

R6407

22

R7413

U7402
LM431

R7410

330

10K

1

D6404
1N4148

R6408

1K

C6407
1000p

C7415

0.1uF

12V

C6402
3300p

R6417
22K

R7411

11K

R7412

2.87K

5

R401
68K

4

D6402
UF4007

38

1

Q6401

2SK3264-01

R6409

0.47R/2W

C6403
68p

2

P-ON

12

U6403
PC123F1

34

R7314

1K

T6401
ER28

CY6401

1500p

5VS

10

9

7

6

POWER-ON

R7317

10K

R7401

47

R7401A

47

D7401

10CTQ150S

D7402

R7402

47

R7402A

47

D7403

10CTQ150S

R7403

47

R7403A

47

C7402

1000p

1000p

10CTQ150S

C7403

C7404

1000p

1000p

C7405

C7406

1000p

1000p

12V

12V +16V

ZD7302
18V

D7305
1N4148

R7318

10K

C7407
470uF

1

ZD7303
24V

D7306
1N4148

L7401

2.7uH

C7408
470uF

L7402

2.7uH

C7410
470uF

C7412
470uF

L7403

2.7uH

U7401

PQ1CY1032Z

VI

ON/OFF GND FB

5

R7409

5.1K

C7416

0.1uF

3

C7411
1000uF

C7413
1000uF

4

C7409
820uF

VO

2

R7404

4.7K

R7405

4.7K

R7406

4.7K

L7403

3.5mm

D7404

RB060L

12V

+16V

-16V

POWE R-ON

CN703=>J2

L7404

45uH

D7405

RB060L

12V

5VS

5V

LCD-ON

LCD-BRI

5
4
3
2
1

R7407

3.4K

R7408

1.1K

CN704=>J12

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

Power Board

5V

C7414
470uF

EGND

Main Board

Q7302
PMBS3904

C7312

0.1uF

R7316

10K

Q7303
PMBS3904

R7315

10K

C7313
10uF

22

LCD12B

First issue 03 / 05 21

AUDIO CHANNEL SCHEMATIC DIAGRAM - SCHEMA DES CIRCUITS AUDIO - SCHALTBILD MEHRKANAL AUDIO - SCHEMA DEI CIRCUITI AUDIO - ESQUEMA DE LOS CIRCUITOS AUDIO

AUDIO BOARD

AUDI

J1=>J9 Main board

J2=>CN703 Audio
power board

1. Resistor values are in ohm, K = 1,000 ohm, M = 1,1000 000 ohm

NOTES:

2. All resistors are SMD 0603 5% exept where otherwise indicated

3. All capacitors are SMD 0603 5% exept where otherwise indicated

4. Represents PCB common ground

U1
TDA7490L

G-2-5

PWM-STAGE 1

CN705

PWM-STAGE 2

AUDIO BOARD

23

LCD12B

24 First issue 03 / 05

(DIGITAL BOARD 1/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

+5VS

MAIN BOARD

MAIN

TP 2

TP10

GSDA

TP 5

GSCL

TP 9

11

12

13

14

15

TP13 6

1617

J1

D-Sub15

BAV99

DN 2

K

J

BAV99

A

TZMC5 V1

K

DN 1

BAV99

6
1
7
2
8
3
9
4
10
5

TP 7

PC_5V

R1

TP 1

G1

TP 3

B1

TP 6

R6
75

R7
75

R1 47

R2 47

R4 47

R8
75

D26
27V

D27

27V

C4

47P
50V J

C5

47P
50V J

TZMC5 V1

A

C6

47P
50V J

J

BAV99

DN 3

DN 4

K

J

A

K

J

AUDIO PC INPUT

A

RED_PR_IN

GREEN_YP_IN

BLUE_PB_IN

J2

7

7

6

6

1

1

2

2

4

4

5

5

3

3

[P27/28]

[P27/28]

[P27/28]

TP 4

TP 8

TP13 7

L1

L2

220 OHM

220 OHM

C7

1000P J

C8

1000P J

D1

TZMC5 V1

12

12

D3

TZMC5 V1

12

12

R9

O PEN

1K

1K

AUD_PC_L

AUD_PC_R

R10

O PEN

[P.25/26]

[P.25/26]

R3

R5

D2

TZMC5 V1

D4

TZMC5 V1

TZMC5 V1

D30

R11
R12

TZMC5 V1

D31

4.7K

G SCL

G SDA

1K
1K

R15

4.7K

Screw Holes

+5VS

12

PC_5V

12

R16

D9

D10
1N4148

1N4148

8

7

6

5

VC C

WP

SC L

SD A

AT24C02A

U2

GND

D5

TZMC5 V1

D7

TP14 2
TP14 3

1

A0

2

A1

3

A2

4

C1 40.1U K

D6

D8

C1 0 0.1U K

C1 20.1U K

C1 1 0.1U K

TZMC5 V1

C1 30.1U K

R13 47
R14 47

U1

1

C1+

2

V+

3

C1-

4

C2+

5

C2-

6

V-

7

T2OUT

8

R2IN

SP232ECN

RGB_VS
RGB_HS

C9 0.1U K

16

VCC

15

GND

14

T1OUT

13

R1IN

12

R1OUT

11

T1IN

10

T2IN

9

R2OUT

+5VS

[P27/28]
[P27/28]

UART_R X

UA RT_T X

RX
TX D

RX
TX D

[P.29/30]
[P.29/30]

Optical Points

OP 1
OP

OP 8
OP

MAIN BOARD

OP 2
OP

OP 9
OP

OP 3
OP

OP10
OP

OP 4
OP

OP11
OP

OP 5
OP

OP12
OP

OP 6
OP

OP13
OP

OP 7
OP

OP14
OP

OP15
OP

OP16
OP

5

4

3

2

H1

HOLE-V8

1

9

8

7

6

5

4

3

2

H2

HOLE-V 8

1

9

8

7

6

5

4

3

2

H3

HOLE-V 8

1

9

8

7

6

H4

HOLE-V8

1

5

4

3

2

9

8

7

6

H6

HOLE-V8

1

5

4

3

2

9

8

7

6

H8

HOLE-V8

1

5

4

3

2

9

8

7

6

26

LCD12B

First issue 05 / 04 25

(DIGITAL BOARD 2/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

Main BOARD

MAIN

31

J3

31
17

9

1

1

9

10

11

12

13

14

15

16

C3

C1

C5

C4

C2

OPEN

[P.25/26]

DVI_SCL_3V

[P.25/26]

DVI_SDA_3V

2

3

4

5

6

7

8

TP 23 3

17
2
10
18
3
11
19
4
12
20
5
13
21
6
14
22
7
15
23
8
16
24

25
27
29
30
26
28

J4

2210018551

OPEN

18

19

20

21

22

23

24

C5_

32

32

12

DN5
O PEN

R35
OPEN

2

TP 23 1

TP 23 2

J

12

1

OPEN

D33

2

OPEN

Q3

K

DN6

J

O PEN

A

J

1

Q1

3

3

OPEN

3

OPEN

L32

L33

OPEN

K

J

A

TP 11
TP 12
TP 13
TP 14
TP 15
TP 16

TP 17
TP 18

TP 19

TP 20

TP 21

D32

OPEN

+3V_DDV I +5V_EDI D

R39

OPEN

4

334

2

112

DVI AUDIO input

+3V_DDV I

+5VS

OPEN

C1 8
O PEN

C3 8
OPEN

+3V_DDV I

[P.25/26]]

C1 6

O PEN

C1 9
O PEN

C232

0.1U K

5

3

12

13

IDCK+
IDCK -

9

16

U 37C

74HC 4053

876

11

16

U37A

74HC 4053

876

C2 0
O PEN

D2 +
D2­D1 +
D1­D0 +
D0-

4

14

R186

10K

Q21

2N3906

32

1

R188

1K

Q22

2N3904

R191

OPEN

R192

OPEN

10K

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

R190

R21

R23

R24

R25

10K

QO2
QO3
QO4
QO5
QO6
QO7
OVCC
OGND
QO8
QO9
QO10
QO11
QO12
QO13
QO14
QO15
VCC
GND
QO16
QO17
QO18
QO19
QO20
QO21
QO22

R187

U3

C1 5
O PEN

K

A

K

A

DN7
O PEN

DN 13
O PEN

Q2

OPEN

R31

K

J

A

+5VS

K

J

A

1

2

1

Q4

3

R26

OPEN

R27

R33

2

OPEN

OPEN

OPEN

OPEN

DN8
O PEN

DN 14
O PEN

K

J

A

ZD1
O PEN

ZD2
O PEN

ZD3
O PEN

ZD4
O PEN

DN9
O PEN

HO T_ PLUG

DVI _SCL

DVI _SDA

AUD _DVI_L

AUD_DVI_R

J

K

DN 10
O PEN

A

L4

12

+

C2 1
22U
OPEN

R40
OPEN

[P.25/26]

[P.25/26]

D2­D1­D0­D2 +
D1 +
D0 +
IDCK+
IDCK -

OPEN

R41
OPEN

[P.25/26]

C2 2
OPEN

8

7

6

5

[P.25/26]

[P.23/24]

[P.25/26]

[P.23/24]

12

D17 O PEN

12

D18 O PEN

VD3 3

L5

AV DD

L34

ADP WR

L35

+5V_EDI D

U4

A0

VCC

A1

WP

A2

SCL

GND

SDA

O PEN

AUD _DVI_L

A UD_PC_ L

AUD_DVI_R

AUD_PC _R

L3

OPEN

C2 7
OPEN

C3 2
OPEN

GFBK

DVI_C K

G PEN

GVS

GHSS OG

C2 8

C3 5

OPEN

OPE N

C3 3
OPEN

2

+3V_PDV I

12

+

C4 0
47U

C4 1
OPE N

OPEN

C3 6
OPEN

R22

C1 7
O PEN

C3 7
OPEN

[P.29/30]

TP 13 8

[P.29/30]

[P.29/30]

[P.29/30]

[P.29/30]

+5V_EDI D+5VS

+3V_DDV I

OPEN

C2 6

C2 5

OPEN

OPEN

+3V_ADVI

OPEN

C3 0

C3 1

OPEN

OPEN

U6

OPEN

C3 9
OPEN

3

VIN

LD1117-3. 3

VOUT

GND

1

OPEN

1

2

3

4

C171

1U K

C172

1U K

C173

1U K

C174

1U K

C2 4
O PEN

+9V

+9V

R170
27K

R171

R172
47K

R173

+9V

R178
27K

R179

R180
47K

R181

Q17
2N3904

100

+9V

1K

R174
27K

R175

100

R176
47K

R177

Q19

100

2N3904

+9V

1K

R182
27K

100

R183

R184
47K

R185

C231

Q18
2N3904

1K

1K

10U
16V

+

12

Q20
2N3904

R17 O PEN

R19 O PEN

OPEN

OPEN

OPEN

OPEN

49

48

47DE46

45

44

43

42

QO150QO0

OGND76QO2377OVCC78AGND79RX2+80RX2-81AVCC82AGND83AVCC84RX1+85RX1-86AGND87AVCC88AGND89RX0+90RX0-91AGND92RXC+93RXC-94AVCC95EXT_RES S96PVCC97PGND98RESERVED99SCL

+9V

HSYNC

VSYNC

OGND

ODCK

OVCC

AV_SE L

LOW

HIGH

R189

PC_AUDIO_SEL

1K

AU D_PC_DVI_L

AUD_PC_ DVI_ R

R18

R20

41

40

39

CTL3

OCK_INV

HS_DJTR

SII169

OPEN

OUTPUT

DVI

PC

[P.33/34]

OPEN

OPEN

38

VCC

GND

QE2337QE2236QE2135QE2034QE1933QE1832QE1731QE16

[P .35/36]

[P .35/36]

R36
OPEN

+3V_ADVI

OPEN

[P.29/30]

[P.29/30]

[P.33/34]
[P.33/34]

+3V_DDV I

12

[P.25/26]

GRE[0. .7]

GGE [0..7]

GBE [0..7]

[P.29/30]

SII169 _RSTZ

[P.33/34]

DVI_SDA_3V

[P.25/26]

OPEN

OPEN

OPEN

4
3
2
1
4
3
2
1

4
3
2
1
4
3
2
1

4
3
2
1
4
3
2
1

GRE7
GRE6
GRE5
GRE4
GRE3
GRE2
GRE1
GRE0

GGE7
GGE6
GGE5
GGE4
GGE3
GGE2
GGE1
GGE0

GBE7
GBE6
GBE5
GBE4
GBE3
GBE2
GBE1
GBE0

DVI _PDO
DV I_SCDT

+3V_DDVI

R34

D23 O PEN

R38
OPEN

DVI_SCL_3V

5

RN1

6
7

OPEN

8
5

RN2

6
7

OPEN

8

5

RN3

6
7

OPEN

8
5

RN4

R29

6
7
8

5
6
7
8
5
6
7
8

OPEN

R32

R28

R30

OPEN

OPEN

RN5

OPEN
RN6

OPEN

C2 3

30

29

28

26

QE1527QE14

OVCC

OGND

100

R37
OPEN

R43
OPEN

QE13
QE12
QE11
QE10

QE9
QE8

OGND

OVCC

QE7
QE6
QE5
QE4
QE3
QE2
QE1

QE0
PDOZ
SCDT

STAG_OUT

VCC

GND
PIXS
SDA

PDZ

RESETZ

+3V_ADVI

R42 O PEN

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3V_PDVI

+3V_DDV I

+3V_DDV I

Main BOARD

27

LCD12B

28 First issue 03 / 05

(DIGITAL BOARD 3/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

R4 5

Main BOARD

MAIN

[P.39/40]

[P.39/40]

AD PW R_ON

COMP _CRPR

COM P_ CY PY

CO MP _CBPB

RE D_PR_IN

GR EEN_ YP _IN

BLUE_PB_ IN

R195

AV DD

[P.39/40]

[P.23/24]

[P.23/24]

[P.23/24]

R164 470K
C216 470P

50V K

C217 0.01U K

+

C21810U16V

C219 0.01U K

+

C22010U16V

C221 0.01U K

+

C22210U16V

C223 0.01U K

+

C22410U16V

C225 0.01U K

+

C22610U16V

C227 0.01U K

+

C22810U16V

12

12

12

12

12

12

+5VS

U3 2

1

RIN_ 1

2

HDdetect

3

GIN_ 1

4

GND

5

BIN_ 1

6

GND

7

RIN_ 2

8

GND

9

GIN_ 2

10

GND

11

BIN_ 2

12

VIN_ 1

BA7657 F

TWO_OPTION

L37

+5VS ADP WR

R194
OPEN

OPEN

C233
OPEN

C7 8

C7 9

0.1U K

0.1U K

Z220
Q24

SI4431D Y-T1

3
2
16

1

R196
OPEN

C8 1

C8 0

0.1U K

0.1U K

(OPEN)

4

32

Q25

OPEN

C8 2

0.1U K

8
7

5

C8 3

0.1U K

L31

HIN_ 1
HIN_ 2
HD_ O

R_out

VCC

G_out

CON_IN

CON_ O

CTL

B_out

VD_out

VIN_ 2

RG B_VS
RG B_HS

TW O_OPTION

LOW
HIGH

L8

L10

L11

C8 4

0.1U K

C8 5

0.1U K

R4 4

0

R47 47
R49 47

Z220

R165

C229

C230
1U K

0.01U K

68K

C5 30.22U K

C5 60.22U K
C5 8 1000 P J

C6 10.22U K

R5 1
R5 2

GCOAS T

50V

0
0

C6 4

0.1U K

BA IN

GA IN
SOG IN

RA IN

GVR EF

[P.29/30]

24
23
22
21
20
19
18
17
16
15
14
13

[P.29/30]

SCL _CP U

[P.29/30]

SDA_ CP U

C4 7

0.1U K

GVM ID

40

GND

41

GND

42

VD

43

BAIN

44

GND

45

VD

46

VD

47

GND

48

GAIN

49

SOGIN

50

GND

51

VD

52

VD

53

GND

54

RAIN

55

A0

56

SCL

57

SDA

58

REF BYPASS

59

VD

60

GND

GND61VD62GND63VSOUT64SOGOUT65HSOUT66DATACK67GND68VD D69R770R671R572R473R374R275R176R077VD D78VD D79GND

OUTPUT
PC
Y Pr Pb

LD1117-3.

Z220

Z220

Z220

C8 6

0.1U K

C7 4

0.1U K

C3 4

0.1U K

C8 7

0.1U K

C7 6

0.1U K

U1 4

3

VOUT

VIN

GND

3

1

U5

3

VOUT

VIN

GND

LD1117-3. 3

1

U1 5

3

VOUT

VIN

GND

LD1117-3. 3

1

VD3 3 PV DD

C8 9

0.1U K

2

2

2

C9 0

0.1U K

AV DD

VD3 3

PV DD

12

+

12

+

12

+

C9 1

0.1U K

C7 5
47U

16V

C2 9
47U

16V

C8 8
47U

16V

C9 2

0.1U K

[P.33/34]

C9 3

0.1U K

Main BOARD

MV_EN

C9 4

0.1U K

C9 5

0.1U K

1
2
3

OE
A
GND

C9 6

0.1U K

U1 2

VCC

74LVC1 G126

VD33

5

4

Y

OPEN

PV DD VD3 3AV DD

31

32

35

36

37

38VD39

FILT33PVD34PVD

GND

GND

CLAMP

MIDSCV

VSYN C

U9
AD9 883KST-110

I2C Addr: 0x98

ADS OG

GBLKSPL

29

30

HSYN C

C6 9

0.1U K

28

COAST

A DCK

1
2

3
9

10
11

GND

VD33

1A
1B

1R
2A

2B
2R

25VD26VD27

16

8

[P.29/30]

23

VD D22VD D

GND24GND

U1 1

CX1

VC C

RCX1

1Q
1Q

2Q
2Q

CX2

RCX2

GND

74LV123PW

R46

C4 2.039U

3.3K

C4 3 3900P

50V K

21

GND

20

GND

19

B0

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

11

VDD

10

GND

9

G0

8

G1

7

G2

6

G3

5

G4

4

G5

3

G6

2

G7

1

GND

80

R163
L30

30 OHM

C210
O PEN

14
15

12

13
4

5

12

12
6

7

0

C7 0
220P
50V J

D2 4

1N4148

D2 5

1N4148
C7 3
220P
50V J

16V K

R6 2

R6 7

Trac e and
Components
Close IC

PV DD

AD BE0
AD BE1
AD BE2
AD BE3
AD BE4
AD BE5
AD BE6
AD BE7

AD GE 0
AD GE 1
AD GE 2
AD GE 3
AD GE 4
AD GE 5
AD GE 6
AD GE 7

C211

O PEN

VD3 3

33K

360

R6 3

R6 4

1K

VD3 3

221K F

A DHS
ADVS

AD RE 0
AD RE 1
AD RE 2
AD RE 3
AD RE 4
AD RE 5
AD RE 6
AD RE 7

R6 1
1K

1
2
3
4
1
2
3
4

1
2
3
4
1
2
3
4

1
2
3
4
1
2
3
4

RN7

RN8

RN9

RN 10

47

RN 11

RN 12

DVI_CK

12

+

817263

CN7

OPEN

GBE0

8

GBE1

7

47

GBE2

6

GBE3

5

GBE4

8

GBE5

7

47

GBE6

6

GBE7

5

GGE0

8

GGE1

7

47

GGE2

6

GGE3

5

GGE4

8

GGE5

7

GGE6

6

GGE7

5

CN9

OPEN

OPEN

GRE0

8

GRE1

7

47

GRE2

6

GRE3

5

GRE4

8

GRE5

7

47

GRE6

6

GRE7

5

R59 4 7
R60 4 7

[P.33/34]

C7 1

R6 6

1U

47K

50V

CN 11

GAF EO E

63

54

817263

817263

54

54

81

72

54

817263

R5 8
L7

C6 7
OPEN

U1 3

1

OE

2

A

3

GND

74LVC1 G126

72

63

0

30 OHM

C6 5
O PEN

VCC

Y

54

CN8
OPEN

CN 10
OPEN

81

54

CN 12
OPEN

C6 6

O PEN

GFBK
GVS

C6 8
OPEN

VD3 3

5

R6 5

4

GB E[0..7]

GGE [0..7]

GRE[0. .7]

GCL K

[P.29/30]
[P.29/30]

47

[P.29/30]

[P.29/30]

[P.29/30]

[P.29/30]

GHSS OG

C7 2

O PEN

[P.29/30]

30

LCD12B

First issue 03 / 05 29

(DIGITAL BOARD 4/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

TP24

[P.25/26-27/28]

[P.25/26-27/28]
[P.25/26]
[P.25/26-27/28]
[P.25/26-27/28]

[P.25/26-27/28]

G RE[0. .7]

[P.25/26-27/28]

GGE[0..7]

[P.25/26-27/28]

GBE[0..7]

B12

VCC1

PW166B-1 0T

C10

VCC2C3VCC3

GND 1

A12

B11

GND 2

GFBK

GCLK

GPEN

GVS

GHSSOG

GRE0
GRE1
GRE2
GRE3
GRE4
GRE5
GRE6
GRE7

GGE 0
GGE 1
GGE 2
GGE 3
GGE 4
GGE 5
GGE 6
GGE 7

GBE0
GBE1
GBE2
GBE3
GBE4
GBE5
GBE6
GBE7

R82 27

C14

C11

G1 8

VCC5

VCC4

VCC6G3VCC7

GND 3D4GND 4D7GND 5

GND 6

D10

D14

Main BOARD

H19

GCLK

G2 0

GPENSOG

J17

GV S

G1 9

GH S

M20

GRE0

N19

GRE1

N18

GRE2

N17

GRE3

N20

GRE4

P20

GRE5

P19

GRE6

R20

GRE7

F18

GGE 0

E19

GGE 1

E20

GGE 2

J18

GGE 3

H20

GGE 4

J19

GGE 5

J20

GGE 6

K19

GGE 7

D16

GBE0

A18

GBE1

C1 7

GBE2

B18

GBE3

A19

GBE4

B19

GBE5

A20

GBE6

D18

GBE7

K20

GRO0

L17

GRO1

L18

GRO2

L19

GRO3

L20

GRO4

M18

GRO5

M17

GRO6

M19

GRO7

E17

GGO0

C1 9

GGO1

B20

GGO2

C2 0

GGO3

E18

GGO4

F17

GGO5

D19

GGO6

D20

GGO7

B15

GBO0

A16

GBO1

C1 5

GBO2

D15

GBO3

B16

GBO4

A17

GBO5

C1 6

GBO6

B17

GBO7

K18

L3

P18

V11

V14

Y14

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

U16E

GND 7

GND 8G4GND 9

GND1 0K4GND1 1

GND1 2L4GND1 3

K17

D17

G1 7

VCPU33 V3PVCPU25 V25P

L14 Z22 0

V7

VCC14

Power and Ground

GND1 4

GND1 5U4GND1 6U7GND1 7U9GND1 8

T19

P17

MAIN

GFBK
GREF

GBLKSPL

GCOAST

U16A

PW166B-1 0T
Graphics Port

C18

U20

V12

VDD1C7VDD2

VDD3K3VDD4

VDD5V9VDD6

GND1 9

GND2 0

GND2 1

U11

U12

U14

U17

[P.43/44]
[P.43/44]

[P.43/44]
[P.43/44]
[P.43/44]
[P.43/44]

[P.43/44]

V18

VDD7

VDD8V3VDD9

GND2 2W4GND2 3W6GND2 4

W14

H17
H18
F19
F20

Y6

W17

TP25

[P.33/34]

TP27

VGU[0..7]

VBV[0..7]

Y17

VDD1 0

GND2 5

GBLKSPL

GCOAST

[P.25/26]
[P.25/26]
[P.39/40]
[P.39/40]
[P.43/44]
[P.43/44]
[P.35/36]
[P.35/36]

VCLK
VPEN
VVS

VH S
VFI EL D

U18

1

NC

2

VSS

3

NC

V6300L

[P.25/26-27/28]
[P.25/26-27/28]

SDA_CPU
SCL_CPU
TT_SDA
TT_SCL
DI_SDA
DI_SCL
PW R_ON
LCD_B R

D12
C1 3
A14

B14
A15

VGU0
VGU1
VGU2
VGU3
VGU4
VGU5
VGU6
VGU7

VBV0
VBV1
VBV2

B10

VBV3

A10

VBV4

D11

VBV5

A11

VBV6

C1 2

VBV7

B13

SCL
SDA

+5VS

5

4

R87 470

RESET

C128

0.1U K

[P.33/34]

VD D

RE S

V33VCPU33

R723.3 K

R713.3 K

R2123.3 K

R74 10 K
C101

2.2U K
16V

VCLK
VPEN
VVS

VHS
VFIELD

D8

VY 0

C8

VY 1

B7

VY 2

A7

VY 3

B8

VY 4

D9

VY 5

C9

VY 6

A8

VY 7

B9

VUV0

A9

VUV1
VUV2
VUV3
VUV4
VUV5
VUV6
VUV7

V33

R832.2 K

PW166B-1 0T

Video Po rt

R842.2 K

SW 1

3

45

R88
1K

U16B

VCPU33

RESET

R68 O PEN

Y1

C99

18P J

[P.1]
[P.1]

R2133.3 K

IRRCVR_3V

X607

[P.33/34]

R198 3.3 K

V33

14.318 MHZ

RX

TX D

X608

R73 10 K

R199 3.3 K

VRY[0..7]

[P.43/44]

VCPU33

R75
R76 O PEN
R77 4.7 K

R78 4.7 K

NO TE: Upon reset, the on-board A/D
and video decoder will be tri-stated.

C1

0.1U K
U33

VCPU33

1

2

8

VC C

7

SCL1

6

SDA1

5

EN

PCA9515DP

PW R_O N

SCL_5V

SDA_5V

SCL0

SDA0

GN D

1

NC

2
3
4

VC C

R852.2 K

C100
18P J

R70 470

4.7 K

R210 0
R211 0

VCPU33

R862.2 K

8
7
6
5

TP28

SDA_CPU
SCL_CPU

VR Y0
VR Y1
VR Y2
VR Y3
VR Y4
VR Y5
VR Y6
VR Y7

TP33
TP35

TP36

C2

0.1U K

U34

VC C
SCL1

SCL0

SDA1

SDA0

EN

PCA9515D P

PW R_O N

RX D
TX D

PW M_BR

TMS
TC K

TD O

NC

GN D

E3

RESET

W13

MCKEXT

Y13

DCKEXT

P3

XTALI

P4

XTALO

C1

RXD

D3

TXD

E4

IRRCVR 0

D2

IRRCVR 1

C2

PORTA0

B1

PORTA1

B2

PORTA2

A1

PORTA3

C4

PORTA4

D5

PORTA5

B3

PORTA6

A2

PORTA7

A3

PORTB0

C5

PORTB1

D6

PORTB2

B4

PORTB3

A4

PORTB4

C6

PORTB5

B5

PORTB6

A5

PORTB7

D13

CPUTM S

A6

CPUTC K

W3

CPUTD O

A13

MODE0

U5

MODE1

B6

MODE2

R81 O PEN
R80 0
R79 O PEN

0.1U K

SCL_CPU
SDA_CPU

1

SCL_CPU

2

SDA_CPU

3
4

PW166B-1 0T

VCPU33

C102

12

MAIN BOARD

+

U16D

Misc

C116
100U
16V

ROMOE

ROMWE

RAMOE

RAMWE

EXTIN T

SCL_CPU
SDA_CPU

VCPU25

A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

D10
D11
D12
D13
D14
D15

RD

WR

BHEN

CS0
CS1

NMI

8
7
6
5

C117

0.1U K

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

VC C
WP
SC L
SD A

AT 24C32

P1
P2
N3
N4
R1
R2
T1
T2
R3
U1
U2
R4
T3
V1
W1
V2
T4
U3
Y1
W2

F4
F3
E1
F2
F1
G2
G1
H1
H4
H3
H2
J1
J2
J4
J3
K1

M3
M4
N2
M1
L2
L1
K2
M2
N1

E2

D1

R197 O PEN

TP26

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

RD n

WR n

TP32

TP34
CS0n
CS1n

U17

NC
NC
NC

GND

[P.29/30]
[P.29/30]

C113

0.1U K

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

1
2
3
4

C114

0.1U K

TP29
TP30
TP31

ROMOEn
ROMWEn

CS0n
CS1n

NMI

VV S

V3P

C118

0.1U K

A[1..19]

[P.33/34]

D[0..15]

[P.33/34]

[P.33/34]
[P.33/34]

[P.33/34]
[P.33/34]

[P.33/34]

[P.43/44]

C103

0.1U K

0.1U K

C119

0.1U K

PW166B-10T

Display Port

C104

U16C

C105

0.1U K

C120

0.1U K

DCLK

DCKEXT

DRE0
DRE1
DRE2
DRE3
DRE4
DRE5
DRE6
DRE7

DGE 0
DGE 1
DGE 2
DGE 3
DGE 4
DGE 5
DGE 6
DGE 7

DBE0
DBE1
DBE2
DBE3
DBE4
DBE5
DBE6
DBE7

DRO0
DRO1
DRO2
DRO3
DRO4
DRO5
DRO6
DRO7

DGO0
DGO1
DGO2
DGO3
DGO4
DGO5
DGO6
DGO7

DBO0
DBO1
DBO2
DBO3
DBO4
DBO5
DBO6
DBO7

C106

0.1U K

C121

0.1U K

DV S

DH S
DE N

W12
V13
U13
Y13
Y15

R19
T20
R18
R17
T18
U19
T17
V20

U18
V19
W20
W19
Y20
V17
U16
W18

Y19
Y18
V16
U15
Y16
V15
W16
W15

Y12
W11
Y11
U10
V10
W10
Y10
W9

Y9
W8
V8
U8
Y8
Y7
W7
Y5

V6
U6
W5
Y4
V5
Y3
V4
Y2

C107

0.1U K

C122

0.1U K

C97

22P J

DC LK R

C123

0.1U K

DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7

DG 0
DG 1
DG 2
DG 3
DG 4
DG 5
DG 6
DG 7

DB 0
DB 1
DB 2
DB 3
DB 4
DB 5
DB 6
DB 7

C108

0.1U K

R69

30 OHM

RVS
RHS

C109

0.1U K

C124

0.1U K

RDE

DCLK

C110

0.1U K

C125

0.1U K

C98

22P J

DR[0..7]

DG[0..7]

DB[0..7]

C111

0.1U K

C126

0.1U K

DCLK

RV S

RHS

RDE

C127

0.1UK

[P.31/32]
[P.31/32]

[P.31/32]
[P.31/32]

[P.31/32]

[P.31/32]

[P.31/32]

C112

0.1U K

31

LCD12B

32 First issue 05 / 04

(DIGITAL BOARD 5/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

[P.29/30]
[P.29/30]
[P.29/30]
[P.29/30]

[P.29/30]

DR[0..7]

[P.29/30]

DG[0..7]

[P.29/30]

DCLK
RV S
RH S
RD E

DB[0..7]

R89 47
R90 47
R91 47

DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7

DG0
DG1
DG2
DG3
DG4
DG5
DG6
DG7

C129

O PEN

DR2
DR0
DR6
DR3
DR4
DR1
DR5
DG0

DG6
DR7
DG1
DG5
DG2
DG3
DG7
DG4

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

O PEN

RN13

5
6
7
8
5
6
7
8

RN14

5
6
7
8
5
6
7
8

5
6
7
8
5
6
7
8

C130

47

47

RN15

RN16

RN17

RN18

DCLK
DVS
DHS
DEN

C131

O PEN

81

72

63

54

CN13

4
3
2
1
4
3
2
1

CN14

81

72

63

81

72

CN15

47

4
3
2
1
4
3
2
1

47

CN16

81

72

81

72

47

CN17

4
3
2
1
4
3
2
1

47

CN18

81

72

OPEN

DRLV2
DRLV0
DRLV6
DRLV3
DRLV4
DRLV1
DRLV5
DGLV 0

OPEN

54

63

54

OPEN

DGLV 6
DRLV7
DGLV 1
DGLV 5
DGLV 2
DGLV 3
DGLV 7
DGLV 4

OPEN

63

54

63

54

OPEN

DBLV 0
DBLV 1
DBLV 2
DBLV 3
DBLV 4
DBLV 5
DBLV 6
DBLV 7

OPEN

63

54

TP37
TP38

Main BOARD

V33

DRLV7

C 132

0.1U K
DRLV5

DGLV 0

DGLV 1

C 133

0.1U K

R92
O PEN

R93
10K

C 138

0.1U K

DGLV 2

DGLV 6

DGLV 7

DGLV 3

DGLV 4

DGLV 5

DBLV 0

DBLV 6

DBLV 7

DBLV 1

DBLV 2

DBLV 3

DBLV 4

DBLV 5

DHS

DVS

V33

V33

V33

MAIN

U19

1

VC C

2

TXIN5

3

TXIN6

4

TXIN7

5

GND

6

TXIN8

7

TXIN9

8

TXIN10

9

VC C

10

TXIN11

11

TXIN12

12

TXIN13

13

GND

14

TXIN14

15

TXIN15

16

TXIN16

17

VC C

18

TXIN17

19

TXIN18

20

TXIN19

21

GND

22

TXIN20

23

TXIN21

24

TXIN22

25

TXIN23

26

VC C

27

TXIN24

28

TXIN25

T.L.

T HC63LVDM83A

TXIN4

TXIN3

TXIN2

GND

TXIN1

TXIN0

TXIN27

LVDS GND

TXOUT0-

TXOUT0+

TXOUT1-

TXOUT1+

LVDS VCC

LVDS GND

TXOUT2-

TXOUT2+

TXCLK OUT-

TXCLK OUT+

TXOUT3-

TXOUT3+

LVDS GND

PLL GND

PLL VCC

PLL GND

PWR DWM

TXCLK IN

TXIN26

GND

TP14 0

J5

G1

RXIN3+

TP39

RX IN3-

TP40

RXCLKIN +

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

D RLV4

D RLV3

D RLV2

D RLV1

D RLV0

D RLV6

RX IN0-

RXIN0+

RX IN1-

RXIN1+

RX IN2-

RXIN2+

RXCLKIN -

RXCLKIN +

RX IN3-

RXIN3+

DCLK

DEN

C 134

0.1U K

C 137

0.1U K

VC C

12

+

12

+

L15

Z22 0

C 135
22U

C 136
22U

L16

Z22 0

16V

L17

Z22 0

16V

TP41

RXCLKIN -

TP42

RXIN2+

TP43

RX IN2-

TP44

RXIN1+

TP45

RX IN1-

TP46

RXIN0+

TP47

RX IN0-

TP48

TP49

V33

FOR CMO 27" , 30" LCD CONNECTOR

V33

LVDS_EN

[P.29/30]

MA IN BOARD

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29

20D2010215

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2

2

G1

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

G2

G2

34

LCD12B

First issue 03 / 05 33

(DIGITAL BOARD 6/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

Main BOARD

MAIN

[P.29/30]
[P.29/30]
[P.29/30]

[P.29/30]

D[0..15]

A[1..19]

ROMOEn
ROM WEn
RESET

VCPU33

R95 O PEN

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

R135

OPEN

R94

0

FW Pn

R107

3.3 K

R108

3.3 K

[P.29/30]

A2
A4
A6

A9
A11

A12

A17
A19

[P.29/30]

ROMOEn ROM WEn

D15
D14

D5

D4

D3
D2
D9

D8

[P.29/30]

RESET

U20
AT 49BV8192A(T)

26

CE

28

OE

11

WE

12

RP

14

WP

47

BYTE

25

A0

24

A1

23

A2

22

A3

21

A4

20

A5

19

A6

18

A7

8

A8

7

A9

6

A10

5

A11

4

A12

3

A13

2

A14

1

A15

48

A16

17

A17

16

A18

9

A19

FCEn

J7

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 31

20L1023060

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32

VPP

13

VCC

37

29

D1

31

D2

33

D3

35

D4

38

D5

40

D6

42

D7

44

D8

30

D9

32

D10

34

D11

36

D12

39

D13

41

D14

43

D15

45

D16

46

GND

27

GND

VCPU33VCPU33

[P.29/30]

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

A1
A3
A5
A7
A8
A10

A13A14
A15
A16
A18

NM I

[P.29/30]

C S1n

VCPU33

D7
D6
D13
D12

D11
D10

D1
D0

R130

10 K

D0
D1
D2
D3
D4
D5
D6
D7

R98
1K

+

VCPU33

C139

0.1U K

[P.33/34]

[P.33/34]

[P.29/30]

U23

3
4
7

8
13
14
17
18

11

1

C144
10U

16V

D1
D2
D3
D4
D5
D6
D7
D8

CL K

CL R

VCPU33

VC C

GND

10

LED1_SEL

LED2_SEL

D10
D11
D12
D13
D14
D15

20

Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8

74LVC273

3

2N 3904
2N 3906

D0
D1
D2
D3
D4
D5
D6
D7

D8
D9

C143

0.1U K

2
5
6
9
12
15
16
19

R128 0

21

C140

0.1U K

18
16
14
12

9
7
5
3

C141

0.1U K

18
16
14
12

9
7
5
3

+5VS

R99

1K

R 105

1K

VCPU33

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

GN D

74AHC244

10

VCPU33

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

GN D

74AHC244

10

ADPW R_ON
DVI_PDO
MV_EN
SII169_RST Z
GAFEOE
SCART_FB_EN
MU TE
AUDIO_RESET

R96

10 K

+5VS

R117

3.3 K

C S1n

L18 Z22 0

R109 1K

R110 1K

R 131 10 K

81

72

R 103

R111 1K

SCART 1_MODE 1
INPUT_DET

DVI _SCDT
SCART 1_MODE 2

SCART 2_MODE 1
SCART 2_MODE 2

D8
D9
D10
D11
D12
D13
D14
D15

12

470

R112 1K

R113 1K

U24

3
4
7

8
13
14
17
18

11

1

C 145

+

10U
16V

CN1 9

O PEN

63

54

R 104

10 K

R114 1K

R115 1K

81

[P.39/40]
[P.39/40]
[P.25/26]
[P.39/40]
[P.39/40]
[P.39/40]

VCPU33

0.1U K
C 142

20

Q1
Q2

VCC

Q3
Q4
Q5
Q6
Q7
Q8

GN D

74LVC273

10

2
5
6
9
12
15
16
19

D1
D2
D3
D4
D5
D6
D7
D8

CL K

CL R

IRRCVR_3V

72

63

R123 0
R124 0
R125 0
R126 0
R127 0
R129 0

[P.29/30]

81

54

CN2 0

22P

TP61

72

63

54

LED1_SEL
LED2_SEL
VIDEO_RESET
DECOE
TWO_OPTIO

LCD_O N

PC_AUDIO_SEL

LVDS_EN

KPD 0KPD0
KPD 1
KPD 2
KPD 3
KPD 4
KPD 5
KPD 6

CN21

22P

[P.33/34]
[P.33/34]
[P.41/42,43/44]
[P.41/42]
[P.27/28]
[P.35/36]
[P.25/26]
[P.31/32]

TP50
TP51
TP52
TP53
TP54
TP55
TP56
TP57
TP58
TP59

TP60

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

J6

Q1 3

2N3906

32

1

R97
1K

+5VS

32

Q1 5

1

2N3904

R 101

10 K

20

U21

2

1A1

4

1A2

VCC

6

1A3

8

1A4

11

2A1

13

2A2

15

2A3

17

2A4

1

1G

19

2G

20

U22

2

1A1

4

1A2

VC C

6

1A3

8

1A4

11

2A1

13

2A2

15

2A3

17

2A4

1

1G

19

2G

R100

10 K

KPD1
KPD2
KPD3
KPD4
KPD5
KPD6

C S0n

R116

3.3 K

R 119 0
R 120 0
R 121 0
R 122 0

2N3906

1

R106

10 K

C S0n

CS0n

Q1 4

32

1

R 102
1K

32

Q1 6
2N3904

KPD[0. .6]

[P.29/30]

R 118
O PEN

[P.29/30]

[P.27/28]
[P.25/26]
[P.27/28]
[P.25/26]
[P.27/28]
[P.39/40]
[P.35/36]
[P.39/40]

[P.29/30]

VCPU33

MAIN BOARD

35

LCD12B

36 First issue 03 / 05

(DIGITAL BOARD 7/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

+12V

Main BOARD

R133
10K

Q9
2N3904

[P.33/34]
[P.39/40]
[P.39/40]

MU TE
A UDIO_L_OU T

AUDIO_R_OUT

EARPHONE_MUT E

220 OHM

L22

L23

220 OHM

TP64

TP68
TP71

TP74

C 147
OPEN

TP66

J9

1
2
3
4
5
6

+12V

L24

Z22 0

MAIN

J8
20D0045105

5
4
3
2
1

G1 G2

TP63
TP65
TP67
TP70
TP73

L19

220 OHM

L21

220 OHM

C 234 560P J

C 235 560P J

EAR_MUT E

AUDIO_R_EAR

AUDI O _L_EAR

[P.39/40]

[P.39/40]

R48

47K

R 132
10K

TO KEYPAD BOARD

C146

O PEN

EMI Solution

J12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

TP77

TP78

TP79

TP80

TP81

TP82
TP83

TO POWER BOARD

+12V +5VS VC C

PW R_ON

LCD_O N
LCD_B R

[P.6]

[P.6]
[P.6]

+12V

+5VS

C150

0.33U Z

C 156

0.1U K

C 160

0.1U K

TO AUDIO BOARD

R 136
681F

+9 V

+

VPU3 3

+

VPU2 5

+

C 149
47U

16V

C 155
47U

16V

C 159
47U

16V

C 151

0.1U K

C 157

0.1U K

C 161

0.1U K

L26

Z22 0

L13

Z22 0

VCPU33

VCPU25

U25

1

VI

U27

3

VIN

1

U28

3

VIN

1

VO

GN D

2

7809ABD2T

VOUT

GN D

LD1117-3.3

VOUT

GND

LM317M

3

2

2

MAIN BOARD

VCC

C 164

0.1U K

R137
681F

U29

3

VIN

VOUT

GN D

1

LD1117-3.3

12

C162

+

10U
16V

2

V33

C 163

+

47U

16V

C 165

0.1U K

38

LCD12B

First issue 03 / 05 37

(DIGITAL BOARD 8/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

Main BOARD

MAIN

[P.37/38]

VCC +5V_FAN

+12V +12V_FAN

[P.37/38]

+5V_FA N

C48

0.1U K

U36

1

VDD

C50

10PJ

TP69

2

AR

3

A

4

BR

5

B

6

CR

7

C

8

VSS

CD 4049UBCM

J10

1
2
3

CLOCK_FAN

R167

2M

R168

10 M

Y2

25.6KH Z

C49

10P J

L27

Z22 0

L28

Z22 0

TP72 J17

FANSPIN 1 FANSPIN2

TP14 1

NC
FR

F
NC
ER

E

DR

D

[P.37/38]

J11

OPEN

123

TP24 4

0
0

10K

+5V_FA N

14
12

11

6

1

10

9

CLOCK_FAN

U35

SMBCLK
SMBDATA

ALERT

RESET

OUT1

FG1

CLK

G768B

MAIN BOARD

C52

0.1U K

[P.37/38]

VCC
VCC

DXP1

DXN

DXP2

OUT2

FG2
GND
GND

C51

0.1U K

15
2

3

4

5

16
13
7
8

Q6

2SB772S

1
2
3

+12V_FAN

+

R151

C3
47U

25V

4.7K

2N3904

R 152

4.7K

Q5

R 150

R 153

2.2K

[P.29/30]
[P.29/30]

2.2K

[P.37/38]

R149

2.2K

SCL_5V
S DA_5V

FANSPIN1

+5V_FA N

R 147
R 148

R 146

+5V_FA N

R 154

10K

D28

TZMC5V1

16
15
14
13
12
11
10
9

+12V_FAN1 +12V_FAN2

+12V_FAN2+12V_FAN1

TP24 6

TP24 7

TP24 5

R 134 O PEN

+5V_FA N

R161
10K

D29
TZMC5V1

C4 5
2200P J

C46
0

R159

R158

2.2K

FANSPIN2

2.2K

TP76

Q1 0
2N3906

[P.37/38]

R 139
O PEN

R162

R166

4.7K

Q7
2N3904

R160

2.2K

4.7K

TP24 3

+12V_FAN

2SB772S
Q8

+

C44
47U

25V

L25
Z22 0

39

LCD12B

40 First issue 03 / 05

(DIGITAL BOARD 9/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

Main BOARD

TP50 2

MAIN

J501

5

5

3

3

1

1

2210018571

3

1

6

4

2

J502

3

1

2210018551

TP50 1

6

TP50 3

4

TP50 4

2

TP50 7

4

4

2

2

TP52 6

L501

1000 OHM

L502

1000 OHM

L503

1000 OHM

C501

O PEN

C502

O PEN

R515

1K

R533

1K

R501

75

R510

75

R514

75

R516
22 K

R539
22 K

VCC

K

DN501

BAV99

A

VCC

K

DN502

BAV99

A

VCC

K

DN503

BAV99

ZD501
TZMC5V1

12

12

ZD502
TZMC5V1

ZD503
TZMC5V1

12
12

ZD504
TZMC5V1

K

A

J

J

DN504
BAV99

A UD_CO MP_L

A UD_COMP_R

R 502 0

J

R 506 0

J

A

COMP_CYPY

COMP_CBPB

[P.27/28-39/40]

[P.27/28-39/40]

C OMP_CRPR

[P.27/28-39/40]

[P.39/40]

[P.39/40]

SCART1_S WI TC H

SCART2_S WI TC H

R505 10 K

0V~4.85V

R 512 10 KR 511 0

0V~4.85V

TP50 5

TP50 6

TP50 8

R 507

6.8 K

R 513

6.8 K

L504 Z22 0

L505 Z22 0

L506 Z22 0

+5VS

R 503

4.3 K

3.49V

R 508
10 K

8.6-12V

0-3.5V

R 504
10 K

1.40V

R 509

3.9 K

Mode1

1

0

00

+12V

+9 V

VCC

3
2

5
6

10

9

12
13

Mode2

1

13.5-8.6V

IN1+
IN1-

IN2+
IN2-

IN3+
IN3-

IN4+
IN4-

4

U 501

V+

OUT 1

OUT 2

OUT 3

OUT 4

GND

LMV324M

11

scart 4:3

scart 16:9

Prev. status

1

SCART 1_MODE 1

7

SCART 1_MODE 2

8

SCART 2_MODE 1

14

SCART 2_MODE 2

[P.33/34]

[P.33/34]

[P.33/34]

[P.33/34]

[P.33/34]

[P.39/40]

[P.29/30]
[P.29/30]
[P.39/40]
[P.41/42]
[P.33/34]

[P.39/40]

SCL_5V

SCART2_S WI TC H

TT_SC L

SVVS

INPUT_DET

MAIN BOARD

TP510
TP512
TP514
TP516
TP518
TP520

50

50

48

48

46

46

44

44

42

42

40

40

38

38

36

36

34

34

32

32

30

30

28

28

26

26

24

24

22

22

20

20

18

18

16

16

14

14

12

12

10

10

8

8

6

6

4

4

2

2

49

49

47

47

45

45

43

43

41

41

39

39

37

37

35

35

33

33

31

31

29

29

27

27

25

25

23

23

21

21

19

19

17

17

15

15

13

13

11

11

9

9

7

7

5

5

3

3

1

1

TP50 9
TP51 1
TP51 3
TP51 5
TP51 7
TP51 9
TP52 1
TP52 2
TP52 3
TP52 4
TP52 5
TP52 7
TP52 8
TP52 9
TP53 0
TP53 1
TP53 2
TP53 3
TP53 4
TP53 5
TP53 6

A UDIO_RESET
S DA_5V
TT_SDA

SCART1_SWITCH

SVHS
SCART_FB_EN

SCAR T_TT_BLNK
SCART_TEXT_B
SCART_TEXT_G
SCAR T_TEXT_R
OUT _S_C
OUT_S_Y
CVBS_VD

AUD_PC_DVI_L
AUD_PC_DVI_R
AUD_COM P_ L
A UD_COMP_R

A UDIO_L_OUT
AUDIO_R_OUT
A UDI O_L_EAR
AUDIO_R_EAR

[P.29/30]
[P.29/30]
[P.39/40]
[P.41/42]
[P.33/34]
[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]
[P.25/26]
[P.25/26]
[P.39/40]
[P.39/40]
[P.35/36]
[P.35/36]

20L2055050

J503

[P.35/36]
[P.35/36]

42

LCD12B

First issue 03 / 05 41

(DIGITAL BOARD 10/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

VCC_A

VCC_A VCC_A

C 504

10U Z

UV 7

C 505

0.1U K

C 506

1500P J

R 545 47
R 546
R 547 47
R 548 O PEN

RN501
47

5
6
7
8

5
6
7
8

V33D

RN502
47

C 507
390P K

47

4
3
2
1

4
3
2
1

DUV 0
DUV 1
DUV 2
DUV 3

DUV 4
DUV 5
DUV 6
DUV 7

C 508

1500P J

PIN76

SVVS
SVH S
SVPEN
VFI ELD

DUV[0..7]

[P.43/44]
[P.43/44]
[P.43/44]
[P.29/30]

[P.43/44]

Main BOARD

MAIN

VCC

C 509

0.1U K

U 502

3

VIN

LD1117-3. 3

1

VOUT

GND

PIN5 9 P IN69

C503

0.1U K

V33D

2

C514

0.1U K

PIN4 5

C515

0.1U K

C5180.047U K

C 519

10U
16V

C 516

3.3P C

Y501

20.25M HZ

C 517

3.3P C

V33D V33D

UV 0

UV 3

UV 1

UV 2

UV 4

UV 5

UV 6

PIN2 9

C 513

0.1U K

PIN3 6

C 510

+

47U

16V

C511

0.1U K

PIN1 0

C512

0.1U K

[P.39/40]

[P.39/40]

[P.39/40]

[P.39/40]

[P.39/40]

[P.39/40]

[P.39/40]

OUT _S_C

OUT_S_Y

C VBS_VD

SCART_TT _BLN K

SCART_TEXT_B

SCART_TEXT_G

SCART _TEXT_R

VCC VCC_A

C 540

+

47U
16V

C 544

0.1U K

L511

Z22 0

R554 75

R555

75

L507 3.3N H

L508 3.3N H

L509 3.3N H

L510 3.3N H

C 526 330P J

[P.39/40]

C 545

+

22U
16V

[P.39/40]

R 551 75

R559 75

R560 75

R561 75

R562 75

COMP_CBPB

COMP_CYPY

R549
75

R550 75

C 522 330P J

C 524 0.68U K

C 525 0.68U K

R 558

TP538

O PEN

C 532 O PEN

C 534 150P J

C 536 150P J

C 538 150P J

R565 75 C542 0.22U K

R 568 75

C520

330P J

C 521 0.68U K

TP537

C 523 0.68U KR552 75

C52710U 16V

+

C 528 0.047U K

C 533 0.22U K

C 535 0.22U K

C 537 0.22U K

C 547

330P J

C 548 0.22U K

C 549

330P J

VCC_A

65

GNDF

66

VRT

67

I2CSEL

68

ISGND

69

VSUPF

70

VOUT

71

CIN

72

VIN1

73

VIN2

74

VIN3

75

VIN4

76

VSUPAI

77

GNDAI

78

VREF

79

FB1IN

80

AISGND

VPC323XD

VINB1

VING1

VI NR1

64

62

61

60

59

N.C

ASGF

B1/CB1IN1G1/Y1IN2R1/CR1IN

CLK5

XTAL263XTAL1

B2/CB2IN4G2/Y2IN5R2/CR2IN6ASGF7N.C/FFRSTWIN

3

58VS57

56

55

54

53

52

VSTBY

FPDAT/VSYA

AVO

INTLC

MSY/HS

FSY/HC/HSYA

51C050C149C248C347

GNDSYY

VSUPSY

46

GNDC

U5 03

VPC3230D

I2C : 0X8E

VSUPCAP9VSUPD10GNDD11GNDCAP12SCL13SDA14RESQ15TEST16VGAV17YCOEQ18FFIE19FFWE20FFRSTW21FFRE22FFOE23CLK20

8

R563
O PEN

C539

0.22UK
C543

1500P J

C546
390P K

R566 100
R567 100

45C444C543C642C741

VSUPC

SDA

VSUPY

GNDY

GNDLLC

VSUPLLC

LLC1
LLC2

VSUPPA

GNDPAA

24

R 564 100

C 541

100PK

[P.29/30]

Y0
Y1
Y2
Y3

Y4
Y5
Y6
Y7

Y1

39

Y2

38

Y3

37

36

35

Y4

34

Y5

33

Y6

32

Y7

31

30

29

28

27

26

25

Y0

40

DECOE

RN503 47

5
6
7
8

RN504 47

5
6
7
8

R 556 0
R 557 O PEN

Y/C Output

L

Disable
Enable

H

VIDEO_RESET

C 529

1500P J

[P.33/34]

4
3
2
1

4
3
2
1

DY 0
DY 1
DY 2
DY 3

DY 4
DY 5
DY 6
DY 7

C530

0.1U K

Q501

R569

1K

2N3904

VC C

R 571

10 K

DY[0..7]

SVCLK

C 531

22PJ

1K

R 570

[P.43/44]

[P.43/44]

DECOE

[P.33/34]

[P.39/40]

C OMP_CRPR

R572 75

C 550 0.22U K

C 551

330P J

MAIN BOARD

43

LCD12B

44 First issue 03 / 05

(DIGITAL BOARD 11/11)

MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL

Main BOARD

MAIN

[P.41/42]

DY[0..7]

[P.41/42]

DUV[0..7]

[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]
[P.41/42]

SVHS
SVVS
SVCLK
SVCLK
SVPEN
SVVS
SVHS

C 579

0.1U K

DY 0
DY 1
DY 2
DY 3
DY 4
DY 5
DY 6
DY 7

DUV0
DUV1
DUV2
DUV3
DUV4
DUV5
DUV6
DUV7

1
2
3
4
6
7
8
9

15
16
17
18
20
21
22
23

30
31
32
33
35
36
37
38

11
12
13
25
26
27
28

70
71
72
73
75
76
78
79

81
82
83
84
86
87
88
89

91
92
94
95
97
98
99

100

66
67
68

C 580

0.1U K

U504A

VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7

VG 0
VG 1
VG 2
VG 3
VG 4
VG 5
VG 6
VG 7

VR 0
VR 1
VR 2
VR 3
VR 4
VR 5
VR 6
VR 7

SVH S
SVVS
SVCLK
PVCLK
CREF
PVVS
PVH S

DGB 0
DGB 1
DGB 2
DGB 3
DGB 4
DGB 5
DGB 6
DGB 7

DGG0
DGG1
DGG2
DGG3
DGG4
DGG5
DGG6
DGG7

DGR 0
DGR 1
DGR 2
DGR 3
DGR 4
DGR 5
DGR 6
DGR 7

DGH S
DGV S
DGCLK

VREFOUT

PW 1230

C 581

0.1U K

DCLK

DEN G
DEN B
DEN R

AD G

VREFIN

RSET

COMP

MV E

CGMS

TESTCLK

DB 0
DB 1
DB 2
DB 3
DB 4
DB 5
DB 6
DB 7

DG0
DG1
DG2
DG3
DG4
DG5
DG6
DG7

DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7

DV S
DH S
DE N

AD R

AD B

C 582

0.1U K

VDBU0

110

VDBU1

111

VDBU2

113

VDBU3

114

VDBU4

116

VDBU5

117

VDBU6

118

VDBU7

119

VDG Y0

121

VDG Y1

122

VDG Y2

124

VDG Y3

125

VDG Y4

127

VDG Y5

128

VDG Y6

129

VDG Y7

130

VDRV0

132

VDRV1

133

VDRV2

135

VDRV3

136

VDRV4

138

VDRV5

139

VDRV6

141

VDRV7

142

YC LK

102

YV S

103

YH S

104

YE N

145
106
107

Y PEN

108

156
153
150

161
162

R 589

159

C 553 0.01U K

160

C554 10U

R 591

201

R 592

146
144

C583

0.1U K

4

RN505

3
2
1
4

RN506

3
2
1

4

RN507

3
2
1
4

RN508

3
2
1

4

RN509

3
2
1
4

RN511

3
2
1

R579
R581
R583
TP53 9
TP54 0
R586

TP54 1
TP54 2
TP54 3

C 552 0.01U K

270

12

+

TP54 4

C 584

0.1U K

43

VDDQ

VSSQ

6

3

VDDQ9VDDQ

VSSQ

VSSQ

46

12

C 560

0.1U K

C 568

0.1U K

27

VDD

VSSQ

52

2

P3P3V

1

14

VDD

VSS

41

28

VDD

NC/RFU

12

+

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VSS54VSS

NC

RA MD14

51

RA MD13

50

RA MD12

48

RA MD11

47

RA MD10

45

RAMD 9

44

RAMD 8

42

RAMD 7

13

RAMD 6

11

RAMD 5

10

RAMD 4

8

RAMD 3

7

RAMD 2

5

RAMD 1

4

RAMD 0

2

40
36

HY57V641620HGT-6

RA MD15

53

4M*16 SDRAM

C 561

0.1U K

R 594
681F

C 576
10U

16V

P2P5V

12

+

C 562

0.1U K

C571
47U

16V

P3P3V

C573

0.1U K

C563

0.1U K

[P.29/30]

VGU0

5

VGU1

6

VGU2

7

16V

8
5
6
7
8

5
6
7
8
5
6
7
8

5
6
7
8
5
6
7
8

L512

47
47
47

47

AVD3 3

P3P3V

VGU3
VGU4
VGU5
VGU6
VGU7

VR Y0
VR Y1
VR Y2
VR Y3
VR Y4
VR Y5
VR Y6
VR Y7

VBV0
VBV1
VBV2
VBV3
VBV4
VBV5
VBV6
VBV7

70 OHM

47

47

47

47

47

47

0
0

VGU[0. .7]

[P.29/30]

VRY[0..7]

[P.29/30]

VBV[0..7]

[P.29/30]

VCLK

[P.29/30]

VVS
VH S

[P.29/30]

DECOE

[P.33/34]

VPEN

[P.29/30]

112
134
187
219
251

105
115
126
137
147
171
189
193
202
212
222
228
233
240
246
253

196
198

148
164
167

152
155
158

U504B

19

Vss

49

Vss

77

Vss
Vss
Vss
Vss
Vss
Vss

10

PVss

24

PVss

39

PVss

46

PVss

57

PVss

65

PVss

74

PVss

85

PVss

96

PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss
PVss

DPAVss
DPDVss

59

MPDVss

61

MPAVss

ADDVss
ADAVss
ADGVss

AVS33B
AVS33G
AVS33R

DPAVdd
DPDVdd

MPDVdd
MPAVdd

ADDVdd
ADAVdd

ADGVdd

AVD33B

AVD33G

AVD33R

PW 1230

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd
PVdd

5
34
93
123
140
175
205
235

14
29
42
54
64
69
80
90
101
109
120
131
143
165
180
200
208
216
224
230
237
243
249
256

197
199

58
60

149
163
166

151
154
157

A VDD2

A VDD1

AVD2 5

AVD3 3

P2P5V

P3P3V

[P.29/30]
[P.29/30]

[P.29/30]

[P.29/30]

RCLK

R 573

R 574

SCL
SDA

DI_SCL
DI_SDA

RAMA 0
RAMA 1
RAMA 2
RAMA 3
RAMA 4
RAMA 5
RAMA 6
RAMA 7
RAMA 8
RAMA 9
RAMA10
RAMA11
RAMA12
RAMA13

0

0

P3P3V

R576
R577
R578
R580
R582

R584
R585

R587
R588

R596
R597

Y502 10M HZ

R590

C555

18P J

Option: PW1230 output RGB format

C585

0.1U K

P2P5V

C586

0.1U K

VDBU0
VDBU1
VDBU2
VDBU3
VDBU4
VDBU5
VDBU6
VDBU7

VDG Y0
VDG Y1
VDG Y2
VDG Y3
VDG Y4
VDG Y5
VDG Y6
VDG Y7

VDRV0
VDRV1
VDRV2
VDRV3
VDRV4
VDRV5
VDRV6
VDRV7

1
2
3
4
1
2
3
4

1
2
3
4
1
2
3
4

1
2
3
4
1
2
3
4

O PEN

RN512

O PEN

RN513

O PEN

RN514

O PEN

RN515

O PEN

RN516

O PEN

RN517

VBV0

8

VBV1

7

VBV2

6

VBV3

5

VBV4

8

VBV5

7

VBV6

6

VBV7

5

VGU0

8

VGU1

7

VGU2

6

VGU3

5

VGU4

8

VGU5

7

VGU6

6

VGU7

5

VR Y0

8

VR Y1

7

VR Y2

6

VR Y3

5

VR Y4

8

VR Y5

7

VR Y6

6

VR Y7

5

VBV[0..7]

VGU[0. .7]

VRY[0..7]

P2P5V

P3P3V

[P.33/34]

L514

Z22 0

L515

Z22 0

VIDEO_RESET

C 564

+

22U

16V

C 569

0.1U K

C566

0.1U K

R 593

C 567

0.01U K

C 570

0.01U K

213
210
207
204
203
206
209
211
214
217
215
220
221
218

223

229

O PEN
O PEN

2M

AVD2 5

AVD3 3

10K
10K
10K
10K
10K

0
0

0
0

C 556

18P J

0

U 504C

MA 0
MA 1
MA 2
MA 3
MA 4
MA 5
MA 6
MA 7
MA 8
MA 9
MA10
MA11
MA12
MA13

MCLKFB

MCL K

DI_RESET

P2P5V

PW 1230

MD 0
MD 1
MD 2
MD 3
MD 4
MD 5
MD 6
MD 7
MD 8

MD 9
MD1 0
MD1 1
MD1 2
MD1 3
MD1 4
MD1 5

mRASn
mCASn

mWE n

L516

Z22 0

L517

Z22 0

255
252
248
245
242
239
236
232
231
234
238
241
244
247
250
254

225
226
227

U 504D

48

TD O

50

TC K

51

TD I

52

TM S

53

TRSTN

43

I2CA1

44

I2CA2

45

SC L

47

SD A

40

XTALI

41

XTALO

56

TEST

55

RESETn

I2C : 0X64

C577

4
3
2
1

PW 1230

C574

0.1U K

0.1U K

RAMD 0
RAMD 1
RAMD 2
RAMD 3
RAMD 4
RAMD 5
RAMD 6
RAMD 7
RAMD 8

RAMD 9
RA MD10
RA MD11
RA MD12
RA MD13
RA MD14
RA MD15

RN510

47

MCUA 0
MCUA 1
MCUA 2
MCUA 3
MCUA 4
MCUA 5
MCUA 6
MCUA 7

MCUD0
MCUD1
MCUD2
MCUD3
MCUD4
MCUD5
MCUD6
MCUD7

MCUCS

MCUWR

MCUCMD

MCURDY

RRASn

5

RCASn

6
7
8

168
169
170
172
173
174
176
177

178
179
181
182
183
184
185
186

190
191
192
188

C 575

0.01UK

C 578

0.01U K

RW En

A VDD2

A VDD1

P3P3V

V33D

VC C

MAIN BOARD

RRASn
RCASn
RW En

C 557

0.1U K

RAMA11
RAMA10
RAMA 9
RAMA 8
RAMA 7
RAMA 6
RAMA 5
RAMA 4
RAMA 3
RAMA 2
RAMA 1
RAMA 0
RAMA12
RAMA13

R 575

R CLK

P3P3V

L513

Z22 0

1K

C 558

0.1U K

C 572

0.1U K

35
22
34
33
32
31
30
29
26
25
24
23
20
21

19
38
37

18
17
16

39
15

P3P3V

3

12

+

U 506

VIN

U 505

A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1

CS
CL K
CK E

RA S
CA S
WE

UDQM
LDQM

C 559

0.1U K

C 565
10U

16V

49

VDDQ

VOUT

GN D

LM317M
1

R 595
681F

C 587

0.1U K

C 588

0.1U K

C 589

0.1U K

C 590

0.1U K

C591

0.1U K

C 592

0.1U K

C593

0.1U K

C594

0.1U K

C 595

0.1U K

C596

0.1U K

C597

0.1U K

C 598

0.1U K

C 599

0.1U K

C600

0.1U K

C601

0.1U K

C602

0.1U K

C 603

0.1U K

C 604

0.1U K

C 605

0.1U K

C 606

0.1U K

C 607

0.1U K

P3P3V

C 608

0.1U K

C 609

0.1U K

C 610

0.1U K

46

LCD12B

First issue 03 / 05 45

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( CONNECTOR BOARD 1/7)

CONNECTOR BOARD

AV

1

2

Bottom View

Bottom View

G1

G2

G3

3

4

1

2

TP 1

5

6

3

4

AUDIO MONITOR OUTPUT

J1

CVBS_IN

5

5

6

3

3

4

1

1

2

2210018561

J2

TP 6

S1

J4

7

7

6

6

1

1

2

2

4

4

5

5

3

3

L4

1000 OHM

TP22

TP23

TP24

S1

L5 220 OHM

L6 220 OHM

TP 2

6

TP 3

4

TP 4

2

C1

O PEN

3

Y

1

.

.

C

C3

1000P J

G1

2

4

G1

[P.51/52]

INPUT_DET

C2

O PEN

C4

1000P J

R1 1K

R2 1K

TP 5

TP 7

D5

TZMC5 V1

D7

TZMC5 V1

TP 8

1000 OHM

L1

R3
22 K

TZMC5V1

L2

1000 OHM

L3

1000 OHM

D6

TZMC5 V1

D8

TZMC5 V1

D1

R4

22 K

TZMC5 V1

12

12

D3

R6

DN 2

75

BAV99

R7

75

S-VIDEO IS INDEPENDENT

R8 0

R9 0

J

R10
1 00K

R5

75

DN 1

BAV99

A

K

R11
1 00K

DN4
BAV99

D2

TZMC5 V1

12

12

TZMC5V1

D4

VC C

K

J

A

A

DN 3
BAV99

VCC

K

J

A

VC C

J

K

AUDIO_L_LINE

AUDIO_R_LINE

CONNECTOR BOARD

S_Y

S_C

[P.55/56]

[P.55/56]

[P.51/52]

[P.51/52]

[P.55/56]

[P.51/52]

[P.51/52]

SCART2_LOUT

SCART2_ROUT

SCART2_S_C

CVBS_AV

AUD_CVBS_L

AUD_CVBS_ R

+9 V VC C

[P.51/52]

[P.51/52]

[P.51/52]

TP 9

TP11

TP12

TP14

TP16

TP18

TP20

J3

12

34

56

78

910

11 12

13 14

15 16

17 18

19 20

TP13

TP15

TP17

TP19

TP21

TP10

AUD_SCART2_L

AU D_SCART2_R

SCART 2_VD_OUT

SCART2_SWITCHSCART2_S_Y

[P.55/56][P.55/56]

[P.55/56]

[P.51/52]

[P.45/46]

47

LCD12B

48 First issue 03 / 05

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( CONNECTOR BOARD 2/7)

CONNECTOR BOARD

[P.47/48]

SCART1_ROUT

SCART1_LOUT

[P.47/48]

2

D9

TZMC5 V1

D1 4TZMC5 V1

[P.47/48]

SCART1_ROU T

SCART1_LOUT

[P.47/48]

+9 V

TP39

1

TP42

3
5
7

9
11
13

Top View (ST)

R13 0

R14 0

D1 0TZMC5 V1

D1 5TZMC5 V1

J6

2060201207

AV

R17

1 00K

[P.47/48]

[P.47/48]

[P.47/48]

C16
O PEN

2
4
6
8
10
12
14

R18

1 00K

1000P J

SCART1_BLUE_IN

SC ART1_GREEN_IN

SCAR T1 _RED_IN

R40 470

R45 470

C17

O PEN

TP40
TP41

R55 100
R57 100

TP43

R59 0TP44

TP46

R62 0

SCL_TV

TP48

SDA_TV

TP49

214

C7

L9

1000 OHM

C8

1000PJ

DN7
BAV99

A

C18
O PEN

TU NER_DET
TU NER_AC K

TP25

TP27

TP30

TP33

TP35

TP37

J

C19

O PEN

L13

11

13

15

17

19

21

VC C

K

1

3

5

7

9

TP45
TP47

J5

(SCART1)

REVERSE

+9 V

AUD_TV_R
AUD_T V_L

1000 OHM

2

TP28

4

6

8

CLK_OUT

10

DATA_OUT

12

14

16

18

20

L11 Z22 0

[P.51/52]
[P.51/52]

SCL_5V

S DA_5V

TP26

R21 0

TP29

R23 0

TP31

R25 0

TP36

R29 0

TP38

R41 560

C15

+

10U
16V

[P.51/52]

[P.51/52]

TP32

TP34

1

D1 8TZMC5 V1

SCART1_CVBS_IN

SCART1_VIDEO_OUT

R53
470

R60 100

2N3906
Q7

S CART1_AR_IN

SCART1_AL_IN

SCART1_SWITCH

D13

12.4_ TO_ 14.1V

SCART1_BLNK

R30

75

[P.51/52]

[P.47/48]

C14

+

10U
16V

[P.47/48]

[P.47/48]

[P.47/48]

[P.45/46]

C12

0.1U K

+9 V

R51

22

Q6
2N3904

R65

1K

CONNECTOR BOARD

SCART1_CVBS_IN

[P.53/54]

VC C

R38
68 K

R46
68 K

R50 1K

[P.47/48]

12

C21

+

10U
16V

R63 68

SCART1_AL_I N

[P.47/48]

S CART1_AR_IN

[P.47/48]

[P.47/48]

R42

1

100

S CART1_VIDEO_OUT

[P.47/48]

L7 1000 OHM

R24 1K

R26 1K

SCART1_BLUE_IN

32

Q4
2N3904

SCART1_GREEN_IN

SCART1_RED_IN

R19

75

R27

22 K

R47 0

[P.47/48]

+

C6 10 U 16V

R28

22 K

1000 OHM

L8

CVBS_TV

1000 OHM

L10

1000 OHM

L12

VC C

J

D11 TZMC5V1

D16 TZMC5V1

R34

75

[P.51/52]

R43

75

R58

75

K

DN5

BAV99

A

C10 10U 16V

C13 10U 16V

C22 10U 16V

C5

0.1U K

D12 TZMC5V1

D17 TZMC5V1

+

+

+

DN8

BAV99

VC C

J

J

J

VC C

VC C

VC C

R12
68 K

R20
68 K

K

A

K

A

K

A

R15
100

R22 1K

DN6

C9

BAV99

0.1U K

C11

0.1U K

DN9

C20

BAV99

0.1U K

AUD_SCART1_L

AU D_SCART1_R

VC C

R31
68 K

R33
68 K

R36 1K

VC C

R37
68 K

R44
68 K

VC C

R52
68 K

R54 100

R56
68 K

Q1
2N3904

R32 100

R39

100

R49

1K

R64 1K

R16 47

[P.51/52]

[P.51/52]

R4 8 47

R6 1 47

Q2
2N3904

Q3
2N3904

Q5
2N3904

R35
47

SCART1_CVBS

[P.47/48]

S CART1_BLUE

[P.45/46]

SCART1_GREEN

[P.45/46]

SCART1_RE D

[P.45/46]

13

1

LCD12B
First issue 03 / 05 49

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG
ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( CONNECTOR BOARD 3/7)

SCART BOARD

SCART2_ROUT

SCART2_LOUT

SCART2_S_C_IN

AV

R6 0

R7 0

2

D3

TZMC5V1

TZMC5V1D8

D4

TZMC5V1

TP1

TP3

D9

TP6

TZMC5V1

TP9

TP11

TP13

11

13

15

17

19

21

J1

1

3

5

7

9

R9

100K

(SCART2)

REVERSE

R10

100K

1000P J

2

4

6

8

10

12

14

16

18

20

C3

1000P J

TP2

TP4

TP5

TP7

CLK_OUT2

DATA_OUT2

TP12

TP14

C4

R12 0

R14 0

R15 0

TP8

TP10

SCART2_S_Y_IN

SCART2_AR_IN

SCART2_AL_IN

SCART2_SWITCH

D7

12.4 to 14.1V

L3

Sc rew Holes

5

4

3

2

H1

HOLE-V8

1000 OH M

1

9

8

7

6

DN3

VCC

BAV99

SCART2_VD_OUT

5

4

3

2

H2

HOLE-V8

1

9

8

7

6

Optical Points

OP1
OP

OP5OPOP6
OP

OP2OPOP3
OP

OP7
OP

OP4
OP

OP8
OP

SCART BOARD 30" 32"

LCD12B

50 First issue 03 / 05

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG
ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( CONNECTOR BOARD 4/7)

SCART BOARD

SCART2_AL_IN

SCART2_AR_IN

AV

R11 1K

R13 1K

R16

22K

R17

22K

SCART2_S_C_IN

D1 TZMC5V1

D5 TZMC5V1

1000 OH M

L2

D2 TZMC5V1

D6 TZMC5V1

DN2

BAV99

R18

75

DN4

BAV99

AUD_SCART2_L

AUD_SCART2_R

VCC

2

3

1

SCART2_S_C

VCC

2

3

SCART2_LOUT

SCART2_ROUT

SCART2_S_Y

SCART2_S_C

+9V

SCART2_S_Y_IN

TP93

TP95

TP97

TP99

TP101

TP104

TP103

SCART BOARD 30" 323

1000 OH M

L4

12

34

56

78

910

1112

1314

1516

1718

1920

J2

TP94

TP96

TP98

TP100

TP102

TP105

1

SCART2_S_Y

R19

75

AUD_SCART2_L

AUD_SCART2_R

SCART2_VD_OUT

SCART2_SWITCH

SCART2_DET

VCC

R27
0

52

LCD12B

First issue 03 / 05 51

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( CONNECTOR BOARD 5/7)

CONNECTOR BOARD

AV

[P.45/46]

[P.45/46]

CVBS_AV

SCART2_S_Y

C2 52.2U Z

C2 42.2U Z

[P.47/48]

[P.45/46]

CVBS_T V

SCART 2_S_C

C2 62.2U Z

C2 72.2U Z

[P.45/46]

[P.45/46]

S_Y

S_ C

C2 82.2U Z

C2 92.2U Z

C30

0.1U K

+5V_PI

+5V_PI

TT_CVBS_VD

[P.53/54]

R66 75

R67

O PEN

R68

O PEN

R69

0

+9 V

Q8
O PEN

R70
O PEN

R71

C23
O PEN

CVBS_VD

[P.51/52]

+5V_PI

[P.45/46]

[P.47/48]

SCART2_S_Y

S CART1_CVBS

+12V

C48

0.1U K

+12V +12V_PI

0

Z22

L18

R72 68 K

7809ABD2T

1

VI

C33 2.2U Z

C34 2.2U Z

U2

VO

GN D

2

C51

+

10U

16V

C3 1 0 .1U K

+5V_PI

+9 V

3

C52

0.1U K

48

56

1

2

3

4

5

6

7

8

9

10

11

12

13

14

+12V_PI

C49

+

47U

16V

C53

0.1U K

VIN12

VIN13

SYNC_ID

VIN11

VIN10

VIN7

VIN4

VIN2

GND_DIG

TV_FBLK

FBLK_IN1

FNC_TV

FBLK_IN2

FNC_VCR

+5V_DIG

+12V_DIG

15

C5 0

0.1U K

53

54

55

VIN6

VIN8

VIN9

LIN316RIN317AUD_BIAS18LIN219RIN2

12

C4 10.1U K

C4 00.1U K

C4 222 U16 V

+

L

A UD_CVBS_

A UD_CVBS_R

[P.45/46]

[P.45/46]

50

51

52

VIN1

VIN3

VIN5

U1

CXA2161R

-5V_GNDA

20

21

C4 40.1U K

C4 30.1U K

49

+5V_VID

VID_BIAS

LIN122RIN1

23

C4 50.1U K

C4 60.1U K

AUD_SCART 1_L

AUD_SCART 1_R

[P.47/48]

[P.47/48]

47

VOUT1

+5/+12V_VCCA

24

+12V_P I

VC C +5V_PI

46

VOUT2

VOUT345VOUT4

LTV25RTV

26

C39 10U 16V

C47 10U 16V

L19 Z22 0

44

43

+5V_VOUT

INTERUPT

PHONO_R

PHONO_L

LOUT1

27

28

+

+

RIN4

VOUT5

GND_VID

VOUT6

VOUT7

TRAP

SCL

SDA

LOGIC

MONO

LIN4

ROUT1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

AUD_MUX_R

AUD_MUX_L

C54

+

10U

16V

C37 0.1U K

C38 0.1U K

[P.55/56]

[P.55/56]

R78 1K

R80 10 K

R81 10 K

R83 75

R89 0

R90 0

C55

0.1U K

L14 10 0U

+5V_PI

+5V_PI

SCART 2_VD_OUT

SCL_5V

SDA_5V

AUD_TV_R

AUD_T V_L

C56

0.1U K

C35 12P J

[P.45/46]

[P.51/52]

[P.51/52]

[P.47/48]

[P.47/48]

[P.51/52-55/56]
[P.53/54]
[P.45/46]
[P.53/54]
[P.45/46]

C57

0.1U K

SCL_5V

SCART2_SWITC H

TT_SCL TT_SDA

TT_VS

INPUT_DET

R73 75

R74

O PEN

R82 75

R84

O PEN

O PEN

+9 V

Q9

R76

0

R86

0

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

O PEN

R77
O PEN

R79

O PEN

+9 V

Q1 0
O PEN

R87
O PEN

R88

O PEN

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

R75

O PEN

R85

O PEN

J7

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

C32
O PEN

C36
O PEN

L15 Z22 0

L16 Z22 0

L17 Z22 0

AUDIO_RESET
S DA_5V

SCART1_SWITC H

TT_HS
SCART_FB_EN

SCAR T_TT_BLNK

SCART_TEXT_B
SCART_TEXT_G
SCART _TEXT_R

OUT _S_C

OUT_S_Y

C VBS_VD
A UD_PC_L
AUD_PC_ R
AUD_COM P_L
AU D_COMP_R

AUDIO_L_OUT

AUDIO_R_OUT
AUDI O _L_EAR
AUDIO_R_EAR

OUT _S_C

OUT_S_Y

[P.51/52]

[P.51/52]

+12V

+9 V

VCC

[P.53/54-55/56]
[P.51/52-55/56]
[P.53/54]
[P.47/48]
[P.53/54]
[P.53/54]
[P.53/54]
[P.53/54]
[P.53/54]
[P.53/54]
[P.51/52]
[P.51/52]
[P.51/52]
[P.55/56]
[P.55/56]
[P.55/56]
[P.55/56]
[P.55/56]
[P.55/56]
[P.55/56]

CONNECTOR BOARD

[P.55/56]

53

LCD12B

54 First issue 03 / 05

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( CONNECTOR BOARD 6/7)

CONNECTOR BOARD

AV

(Bypass Group Delay

Circuit for TMM tuner)

C6 3 O PEN

C66

TT_CVBS_VD

[P.51/52]

[P.47/48]

+

22U
16V

SCART1_BLNK

R9 80

R9 5OPEN

R9 60

R9 40

+3.3VDAC

U3

1
2
3

+9 V

R115

470

R 107
560

C6 4 O PEN

Q1 1

2N3904

R114 0

R 106

6.8 K

R 1081.3 K

R 112

3.3 K

NC
NC
NC
GND4SD A

AT 24 C02

[P.51/52]

R117

[P.51/52]

OPEN

VC C

WP

SC L

[P.51/52]
[P.51/52]

VC C

C69

O PEN

R 130
470

R131 100

R133 10 K

VC C

R134

10 K

2N3906
Q1 7

Q1 8
2N3904

8
7
6
5

TT_HS
TT_VS

TT_SCL
TT_SDA

VC C

C58

0.1U K

EE _SCL

EE _SDA

Q1 6
2N3904

R132
75

R99

4.7 K

C65

0.1U K

R116 0
R118 0

R122 0
R124 0

TT_BLNK

ADG77 9truthtable

+2.5V +2.5V

R100

4.7

K

0.1

C59

U K

C60

0.1U K

IN Dout

0 S1

1 S2

SCART _BK

R 135

470

SEL

+3 .3VDAC +3 .3VDAC+2 .5VDAC +2 .5VDAC

U4

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD 2.5
VSS
VDD 3.3
CVBS
VDDA 2.5
VSSA
P2.0
P2.1
P2.2
P2.3
HS/SSC
VS
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5

SDA555x FL

BLANK/COR

VDDA 2.5

P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0

VDD 3.3

VSS

VDD 2.5

VSSA
XTAL1
XTAL2

RST-

P4.3
P4.2

VDD 3.3

VSS
P3.7
P3.6

52
51
50
49
48
47
46
45
44
43
42
41
40

B

39

G

38

R

37
36
35
34
33
32
31
30
29
28
27

I2C : 0X60

VCC

C75

2

U6

4

S1

Dout

6

S2

1

IN

ADG7

79

VD D

GND

0.1U K

5

3

SCA RT_TT_BLN

K

[P.51/52]

TT_ RST n

R123

0

R128OPEN

C61

0.1U K

+3.3V

R 125

12

O PEN

+

C62

0.1U K

LCB

INFO
LIST
I2C _E N
RGB _G AIN

TT_ FSB
BLUE
GREEN

RED

C70
10U
16V

AUDIO_RESET

R9 7OPEN

R101 OPEN
R102 0
R103 OPEN
R104 0
R105 OPEN

Y1 6M HZ

C67
33P J

C68

33PJ

+3 .3VDAC

TT_FSB

R 109

220

R119

O PEN

BLU E

GREEN

RED

C72

0.1U K

[P.53/54]

U5

3

VIN

LD1117-3.3

Q1 2
2N3904

R 121

330

VOUT

GN D

1

R110
680

2N3906

Q13

2

R111
680

2N3906
Q1 4

C71

+

47U

+3.3V

2N3906

16V

R 113
680

R 120 47

R 126 10

R 127 10

R 129 10

Q1 5

+3 .3VDAC +3.3VVC C

C73

0.1U K

L20

BEAD

TT_BLNK

TE XT_B

TE XT_G

TE XT _R

[P.53/54]

[P.53/54]

[P.53/54]

[P.53/54]

C74

+

10U

16V

[P.51/52]

SCART_FB_E N

[P.47/48]

[P.53/54]

[P.47/48]

[P.53/54]

[P.47/48]

[P.53/54]

R 137 0

SCART1_BLUE

TEXT_B

SCART1_GREEN

TEXT_G

SCART1_RED

TEXT_R

Q1 9

2N3904

R140
150

R147
1K

R139 0

R 148
1K

Q2 0

2N3904

R 141 O PEN

R 142 10 K

R 143 O PEN

R 144 10 K

R 145 O PEN

R 146 10 K

R 149
1K

TT_FSB

C831U Z

C871U Z

C881U Z

C891U Z

C901U Z

C911U Z

SEL

SEL

SEL

16

12
11
14

2

1

7
8
9

U8

SW 1
IN1A
IN1B
SW 2
IN2A
IN2B
SW 3
IN3A
IN3B

MM1234

OUT 1

OUT 2

OUT 3

GND1

4

15

13

VC C

GND3

GND2

10

VC C

C81

0.1U K

3

5

6

MM1234 truth table

SW RGBout

0 RGB A in

1 RGB B in

C82

+

10U

16V

SCART_TEXT_B

SCART_TEXT_G

SCART _TEXT_

[P.51/52]

[P.51/52]

R

[P.51/52]

U7

3

C78

0.1U K

+3 .3VDAC

PIN11 PIN3 0 P IN44

C84

0.1U K

VIN

1

VOUT

GND

LM317M

R138
681F

C85

0.1U K

2

+

C86

0.1U K

R 136
681F

C80
10U

+2.5VDA C +2.5VVC C

+

16V

L21

C76
47U

16V

CONNECTOR BOARD

BEAD

C79

0.1U K

C77

+

10U

16V

56

LCD12B

First issue 03 / 05 55

VIDEO SIGNAL PROCESSING - TRAITEMENT VIDEO - VIDEO SIGNALVERARBEITUNG - ELABORAZIONE VIDEO - TRATAMIENTO VIDEO

( CONNECTOR BOARD 7/7)

CONNECTOR BOARD

AV

AUDIO_RE SET

[P.51/52]

AUDIO_ R_EAR

[P.51/52]

[P.51/52]

[P.51/52]

[P.51/52]

A UDIO_L_EAR

AU DIO_R_OUT

AUDIO_L_O UT

[P.51/52]

[P.51/52]

C 128

330P J

D19

1N4148

C 133

330P J

SCL_5V

SD A_5V

VCC

R169

10K

R164

4.7K

+ C125

22U
16V

C135 10U 16V

C137 10U 16V

R170

10K

NOTE:I 2C ADDRESS SELECT

C111

1.5N M

C101

OPEN

C112

220P Z

R165 47 0

R166 47 0

R151

OPEN

C102

OPEN

R150 10

R154 10 0

R155 10 0

VCC

L23
Z220

C110

+

100U
16V

C1261U Z

C1321U Z

+

+

12

C113

470P K

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

C9 2

3.3P C

Y2

18.432M HZ

R152

62

ADR_SEL

C1381000P J

60

61

D_CTR_I/O_1

D_CTR_I/O_0

C1391000P J

R153

4.7K

C1401000P J

TP 50

TP 51

57NC58NC59

AUD_CL_OUT

U9

MSP4421K

C1421000P J

C1411000P J

55

56

54

TP

XTAL_IN

XTAL_OUT

4.7K

63NC64

I2C_CLK

I2C_SDA

I2S_SL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

DVSUP

DVSS

I2S_DA_IN2

NC

NC

NC

RESETQ

DACA_R

STANDBYQ

DACA_L18VREF219DACM_R20DACM_L21DACM_C22DACM_SUB23DACM_S24SC2_OUT_R25SC2_OUT_L26VREF127SC1_OUT_R28SC1_OUT_L29CAPL_A30AHVSUP31CAPL_M

C9 3

3.3P C

53

TESTEN

R167 22 0

R168 22 0

R171 22 0

R172 22 0

51

ANA_IN -

C9 4

56P J

C9 8

56P J

50

52

ANA1_IN+

ANA2_IN+

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

SC2_IN_R

SC2_IN_L

SC3_IN_R

SC3_IN_L

SC4_IN_R

SC4_IN_L

32

C134 10U 16V

C136 10U 16V

C9 9

56P J

AVSUP

AVSS

ASG1

ASG2

ASG4

AGNDC

AHVSS

+

+

C145 10U 16V

C146 10U 16V

C143 10U 16V

C144 10U 16V

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

+

+

+

+

+C95

100U
16V

C103

0.1U K

C124 0.1U K

+

C127 3.3U 35V

C129

C130

1.5N M

470P K

VCC

C9 6

470P K

L22
Z220

C9 7

1.5N M

+ C100

10U
16V

C104 330 N Z

C105 330 N Z

C106 330 N Z

C107 330 N Z

C108 330 N Z

C109 330 N Z

C114 330 N Z

C115 330 N Z

+ C131

470U 25V
<Spec >

AU DIO_L_LIN E

AUDIO_R _LINE

SCART 2_LOUT

SCART2_R OU T

L25

Z220

C116

330P J

[P.45/46]

[P.45/46]

[P.45/46]

[P.45/46]

C117

330P J

D20

1N4148

C118

330P J

C119

330P J

+9V

C120

330P J

C121

330P J

C122

330P J

R156 47 0

R157 47 0

R158 47 0

R159 47 0

R160 47 0

R161 47 0

R162 47 0

R163 47 0

C123

330P J

AUD _MUX _R

AUD_MU X_L

AUD_PC_R

A UD_PC_L

AUD_COMP_R

AUD_COMP_L

AUD_SCART2_R

AUD_SCART2_L

[P.53/54]

[P.53/54]

[P.51/52]

[P.51/52]

[P.51/52]

[P.51/52]

[P.45/46]

[P.45/46]

L24

Z220

S crew Holes

5

4

3

2

H1

HO LE-V 8

1

9

8

7

6

5

4

3

2

H2

HO LE-V 8

1

9

8

7

6

5

4

3

2

H3

HO LE-V 8

1

9

8

7

6

5

4

3

2

H4

HO LE-V 8

1

9

8

7

6

Optical Points

OP1
OP

OP8
OP

OP3
OP

OP10
OP

OP4
OP

OP11
OP

OP5
OP

OP12
OP

OP6
OP

OP13
OP

OP7
OP

OP14
OP

OP15
OP

OP16
OP

OP2
OP

OP9
OP

CONNECTOR BOARD

57

LCD12B

58 First issue 03 / 05

TUNER SCHEMATIC DIAGRAM - SCHEMA TUNER - SCHALTBILD TUNER - SCHEMA DELLA SINTONIZZATORE - ESQUEMA SINTONIZADOR

TUNER BOARD
Power in

+5V

C4

10uF

R1

10K

D

+5V

L2

12

12

POWER COIL 100UH

R52 NC
R53 NC

SC-OUT-R
SC-OUT-L

+9V

UHF

+5V

C3

0.1uF

D

1,2

SDA1

1,2

SCL1

Y1

12MHz

C7

20pF

DD

R16 4.7K
R17 4.7K
R18 4.7K
R19 4.7K
R37 4.7K

BEAD 70ohm

L3

2012

R51

0

C8

20pF

+9V

R50

0

D2 SM4001

R22 4R7 ,1W,2512

C72

+

10uF

D

7

RST

8

VDD

9

P6.3/AD3

10

VSS

11

X2

12

X1

13

ISDA/P3.4/T0

14

ISCL/P3.5/T1

15

STOUT/P4.2

16

P6.2

17

P1.0

D

SCL
SDA
SCL1 1,2
SDA1 1,2
RST 2

VDD

+

C12
470uF

J1

1
3
5
7

9
11
13 14

CON14AP

RST

2
4
6
8
10
12

6

NC

P1.1

18

IRIN

2

4

5

NC

VDD3

P1.2

P3.2/INT0

19

C15

0.1uF

1

3

2

DA0/P5.0

DA1/P5.1

P1.3

P1.4

212022

VSYNC 1

HSYNC 1

42

43

44

P5.3

VSYNC

HSYNC

DA2/P5.2

P1.5

P1.6

P1.7

P6.1/AD1

2324252627

VSYNC

U2
LM78L05

TV_COMP_OUT 1
AUDIO_R 2
AUDIO_L 2

IRIN
SCL
SDA

40

41

P5.5

P5.4

DA6/P5.6

P6.0/AD0

SDA

28

SDA

1

GND

2

R26

0

P4.1
P4.0

P6.7
P6.6
P6.5
P6.4

DA8
DA9

DA7

SCL

D

OUTIN

U1

39
38
37
36
35
34
33
32
31
30
29

MTV312M

31

C11
100uF

SCL11,2

SDA11,2

U7

L1 1mH

180pF

R58 100

FB1

inductor 10uH

+5V

+

C17 1uF

1

AGC

AS

SCL

SDA

+5V-T

+5V-T

+33V

FM-SW

SIF/AS

GND

VIDEO

FM-IF

+5V-IF

C20

0.1uF

D

2

3

C2

0.1uF

A

C16

100pF

A

C80 0.1uF

R5 10K

SIF 2

A

R24

130K

AA

R11

100K

A

A

C5

22P

C48

C9 47uF

HSYNC1

VSYNC1

R10

10K

4

5

6

7

9

12

13

14

15

16

17

18

R2 22
R3 22

C6

22P

A

D1

1N4148

22nF

A

R20 510

R4

NC

R8

NC

R15 0

U3

1

H_OSC

2

HD

3

SYNCOUT

45

VD GND

BA7046

+5V

TV_AUDIO 2

C10

0.1uF

A

+5V

NC

Q1

NC

AA

R23 470K

C55 22nF

D3

BZV55B33V

A

C21

A

P_COMP

VCC

VIN

SCL1
SDA1

8

7

6

FM ANT IN

SCL

AUDIO O/P

FE6234

+5V

+

0.1uF

6

5

1

2

3

D

C13

U4

SCL

SDA

A0

A1

A2

AT24C08

+5V

FB2

inductor 10uH

8

VCC

7

WP

4

VSS

C1

100uF

+5V

C27

0.1uF

1,2
1,2

TV_COMP_OUT 1

C75

100uF

A

C56

C59

6.8nF

A

R44

470K

A

C64

4.7nF

C14

0.1uF

A

R60 NC

+5V

C58

1nF

A

R6

10K

+5V

2N3906

C57

47uF

A

R43 470

R59

470

Q4

A

R7

150

Q3

BC847

A

TV_VIDEO 1

TV_VIDEO

C19

C65

1uF

R25

10K

+

1uF

+5V

R9

22

A

C18

2200P

AA

TUNER BOARD

60

LCD12B

First issue 03 / 05 59

TUNER SCHEMATIC DIAGRAM - SCHEMA TUNER - SCHALTBILD TUNER - SCHEMA DELLA SINTONIZZATORE - ESQUEMA SINTONIZADOR

TV TUNER BOARD--(PAL)
Sound Processor

UHF

Y2

AUDIO_ R

SIF

R57

100K

C2 2 1 0uF

A

+

AUD_ R

DIP

18.432MHz

C2 3

3.3pF

VCCSI F

R42

R38

12K

470

BPF 7

3

Q2

BC848B

C5 0

1nF

BPF 1

R39

330

U9

1

2

3

4

A

C5 1

BPF2 BPF3 BPF5

910pF

L8
1uH
1008

A

OUTA

VC C

INA-

OUTB

INB-

INA+

GN D

INB+

LM358

C5 3

860pF

C5 2

3.9nF

+8VOP

8

7

6

5

BPF4

L9
1uH
1008

AAAA

C25 10uF

+

AUD_L

C5 4

10nF

R40

3.9K

AUDIO_ L

R56

100K

A

SOT 23

1

2

BPF6

R41
100

SCL 11,2

SDA11,2

VCCAUDIOD

C3 6

C3 5

+

RST

1.5nF

10uF

D

D

RESET #

VDD +8VOP

C6 1

C6 0

+

10uF

0.1uF

AA

C3 8

C3 7

220pF

470pF

DD

AUD_ R

AUD_L

B6

BEAD 70ohm

B7

BEAD 70ohm

C26 56pF

U6

1

I2C-CL

2

I2C-DA

3

I2S-CL

4

I2S-WS

5

I2S-DA-OUT

6

I2S-DA-IN1

7

ADR-DA

8

ADR-WS

9

ADR-CL

10

DVSUP

11

DVSS

12

D

I2S-DA-IN2

13

NC

14

NC

15

NC

16

RESETQQ

DACMR

DACML

VCCAUDIOAH

C6 3

C6 2

+

0.1uF

10uF

MSPX2

A

ANAIN1

ANAIN-

C28 56pF

A

D

64

NC

DACA-R

171819202122232425262728293031

A

C4 7
1nF

A

ADR-SEL

STANDBYQ

D-CTR-I/O1

D-CTR-I/O0

DACA-LL

VREF2

DACM-R

DACM-LLNCDACM-SUBNCSC2-OUT-R

C4 9

1nF

NC

NC

AUD-CL-OUT

MSP3415G
PLQFP64

TP

MSPX1

TESTEN

XTAL_IN

XTAL_OUT

SC2-OUT-L

VREF1

SC1-OUT-R

A

ANA-IN-

ANA-IN1+

ANA-IN2+

SC1-OUT-L

CAPL-A

AHVSUP

CAPL A

495051525354555657585960616263

AVSUP

CAPL-M

32

R54 NC

R55 NC

AVSS
MONO-IN
VREFTOP
SC1-IN-R
SC1-IN-L

SC2-IN-R
SC2-IN-L

SC3-IN-R
SC3-IN-L

SC4-IN-R
SC4-IN-L

AGNDCC

AHVSS

CAPLM

C45 10uF

C2 4

3.3pF

A

C2 9

C30

470pF

1.5nF

A

A

48
47
46
45
44
43

ASG

42
41
40

ASG

39
38
37

ASG

36
35
34
33

C4 1

+

+

10uF

+

C6 9 NC

+

C7 0 NC

AGNDC

A

C4 2
470pF

A

MONOI N
VREFTO P

0.1uF

A

SC-OUT-L

SC-OUT-R

C4 0

C4 3

1.5nF

A

VCCAUDIOA

C3 1

+

10uF

A

TV_AUDI O

C32 330n F

C34

0.1uF

C3 9

+

3.3uF

A

VCCAUDIOA H

C4 4

+

10uF

A

C33

+

10uF

AA

L5

2.7uH
L7

2.7uH
L10

BEAD 70ohm

VCCAUDIOA+5V

VCCAUDIOD

VCCSI F

61

LCD12B

62 First issue 03 / 05

INTEGRATED CIRCUITS BLOCK DIAGRAM

INTEGRATED CIRCUITS BLOCK DIAGRAM

VYUV

(15:0)

GRGB
(47:0)

VVS
VHS

GVS
GHS

PortBPortA

I/O Ports PWM

YUV

to

R G B

YPbPr

to

R G B

Sync

Decoder

And Timer

IRRCVR(1:0)

IR

Decoder

Video

Port Pixel

Processing

16-Bit

Microprocessor

Processor

Memory

Interface

A

(19:0)D(15:0)CS(1:0) NMIEXTINT RxDTxDJTAG Debugger

Processor ROM

RAM Interface

On-

Screen

Display

OSD

SDRAM

Frame

Graphic

Port Pixel

Processing

Buffer

Memory

Controller

Image
Scaler

Color

Matrix

OSD

and

Gain

UCLKMCLK DCLK

Auto Image

Optimisation

Clock

Generator

PW166/B Image Processor
Internal Block Diagram

GREF GFBK XI*MCKEXT, DCKEXT,XO*

PLL Control

(XI*,XO* for PW166B Only)

Watchdog

Timers

Color

LooKup

Tables

Interrupt

Controller

UART

Microprocessor BUS

Color

Space

Expander

Display

Timing

Generator

DRGB
(23:0)

DRGB
(23:0)

DVS,DHS
DEN,DCLK

SDA55XX

WDT

Capture Control

PWM

Port Logic

P { 0 to 04}

UART

SFRs

ADC

Interface

Peripheral

BUS

Interface

CLOCK &

Sync

System

RAM

256x8

Memory

Extension

STACK
128x8

Counter 0

Counter 1

A { 16 to A20 }

Memory

Extension / Unit

CORE

Interrupt

Contoller

A { 0 to 15 }

D { 0 to 7 }

ALE

PSENRDWR

PROGRAM ROM

Analog / MUX

ADC

128K x8

ADC

Slicer

Acquisition

Acquisition Interface

BUS

Arbiter

RAM / ROM Interface

Display Logic

DISPLAY GENERATOR

Display

REGs

DAC's

RG B

CLUT

FIFO

XRAM

SRAM

16K x8bit

Caracter

ROM

16K x8bit

H

V

BLANK / COR

Premary

Video Port

ITU-R BT 601

Secondary

Video Port

ITU-R BT 6656

Digital

Graphic Port

24-Bit

Two-Wire

Interface

Input Unit

Motion

Detection

&

Video

Noise

Reduction

Unit

Down

Scaler

Proramming Unit

PW1230

Interna Block Diagram

Previous

Video

I-Channel

P-Channel

Memory Unit

Film-Mode

Detection
(3:2&2:2)

Premary

Picture

(l/P)

I-Channel

Display Unit

Deinterlacer

P-Channel

R G B

Color

Lut

Video

Enhancement

CSC

Blue

Screen

VSync/
HSync
Timing

Up

Scaler

DACs

Display

Timing

Y U V

Digital
Output
Timing

Analog
Output

Digital
Output
Data

CI

VIN1
VIN2

VIN3

VIN4

VOUT

RGB/

YCrCb

FB

RGB/

YCrCb

71

N

72

Analog

Front-end

Adaptive

Comb

Filter

74

75

AGC

2 x ADC

NTSC

PAL

70

Y/G

1..3

79

4..6

Analog

Component

Front-End

4 x ADC

Processing

U/B

Matrix

Contrast

V/R

Saturation

Brightness

FB FB

R

G

B

HSYNC

CO AST

CLAMP

FILT

SCL

SD A

Tint

54

AI

N

48

AIN

43

AIN

30

29

38

33

56

57

55

A

0

Color

Decoder

NTSC

PAL

SECAM

Saturation

Tint

VPC3230

Y

Cr

Cb

AD9883A

CLAMP

CLAMP

CLAMP

PROCESSING

AND CLOCK

GENERATIO N

SERIAL REGISTER

POWER MANAGEMENT

SYNC

AND

Cr

Cb

Y

Mixer

A/D

A/D

A/D

8

8

8

REF

AD9883A

Y

2D Scaler

PIP

Cr

Panorama

Mode

Peacking

Contrast

Cb

Brightness

2

I

Clock
Gen.

62 63

70...77

R

2...9

G

12...19

B

37

MIDSCV

67

DTACK

66

HSOUT

64

VSOUT

65

SOGOU

58

REF
BYP

C Bus

OUTA

OUTA

OUTA

T

ASS

13,14

2

I

C Bus20.25 MHz

Output

Formatter

ITU-R 656
ITU-R 601

Memory

Control

Sync

+

Clock

Generation

31...34

37...40

41...44

47...5073

18

19...23

27,28

56

57

54

Y OUT

CrCb
OUT

YCOE

FIFO
CNTL

LL Clock

H Sync

V Sync

AVO

The description and characteristics given here are of informative significance only, and non committal. To keep up the high quality of our products, we reserve the right to
make any changes or improvement without previous notice. • Les descriptions et caractéristiques figurant sur ce document sont données à titre d'information et non
d'engagement. En effet, soucieux de la qualité de nos produits, nous nous réservons le droit d'effectuer, sans préavis, toute modification ou amélioration. • Die
Beschreibungen und Daten in dieser Anleitung dienen nur zur Information und sind nicht bindend. Um die Qualität unserer Produkte ständig zu verbessern, behalten wir uns
das Recht auf Änderungen vor. • Le descrizioni e le caratteristiche date su questo documento sono fornite a semplice titolo informativo e senza impegno. Ci riserviamo il
diritto di eseguire, senza preavviso, qualsiasi modifica o miglioramento. • Las descripciones y características que figuran en este documento se dan a título de información y
no de compromiso. En efecto, en bien de la calidad de nuestros productos, nos reservamos el derecho de efectuar, sin previo aviso, cualquier modificación o mejora.

Thomson multimedia Sales Europe - S.A. au capital de 115 273 710 - Siège : 46, quai Alphonse Le Gallo 92100 Boulogne France - RCS Nanterre B 322 019 464

Thomson multimedia
Sales France

46, quai Alphonse Le Gallo
92648 Boulogne cedex
Te l.

: 01 41 86 60 00

Internet : www.thomson-network.com

Thomson Sales UK Limited

Bath Road
West Drayton
Middlesex UB7 0DB (England)

Thomson multimedia
Sales Italy S.p.A.

Via Leonardo da Vinci,43
20090 Trezzano sul naviglio (Milano)
Te l.

: (02) 48 414 111

Thomson multimedia
Scandinavia AB

Florettgatan 29 C
S-25467 Helsingborg (Sweden)
Te l.

: 042 25 75 00

Thomson multimedia
Switzerland

Seewenweg 5
CH-4153 Reinach
Te l.

: (61) 716 96 60

Thomson
Consumer Electronics Poland

ul.Gen.L. Okulickiego 7/9
05-500 Piaseczno (Varsovie)
Te l.

: (22) 757 10 80

Thomson multimedia
Hungary KFT

Lajos u. 78. II.em.
H-1036 Budapest
Te l.

: 00 36 14 5334/80

Thomson multimedia
Czech s.r.o.

ul. Dopravaku - dum Genius 1
Dolni Chabry
CZ - 18400 Prague 8
Te l.

: (2) 688 67 70

Thomson multimedia
Sales Germany GmbH & Co oHG

Karl-Wiechert-Allee 74
30625 Hannover

Thomson multimedia
Sales Spain

Avenida Isla Graciosa, 1
Edificio Áncora
Parque Empresarial La Marina
28700 San Sebastián de los Reyes (Madrid)
Tel. : [phone]

Thomson multimedia
Sales Portugal

Avenida da Boavista, 3521
4106 Porto
Tel. : [phone]

This technical documentation is for use by maintenance technicians only
Documentation technique exclusivement destinée aux professionnels de la maintenance
Diese Angaben und Hinweise sind ausschließlich für den Service des Fachhändlers bestimmt
Documentazione tecnica destinata esclusivamente ai tecnici dell'assistenza
Documentación técnica destinada exclusivamente a los profesionales de mantenimiento